| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/config/sh/ |
| H A D | elf.h | 60 #define SUBTARGET_ASM_ISA_SPEC "\ macro
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| H A D | sh.h | 392 #define SUBTARGET_ASM_ISA_SPEC "" macro
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| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/gcc/config/sh/ |
| H A D | elf.h | 60 #define SUBTARGET_ASM_ISA_SPEC "\ macro
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| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc9/gcc-9.4.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/sh/ |
| H A D | sh.h | 248 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
251 #define SUBTARGET_ASM_ISA_SPEC \ macro
255 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/sh/ |
| H A D | sh.h | 248 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
251 #define SUBTARGET_ASM_ISA_SPEC \ macro
255 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc10/gcc-10.3.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc8/gcc-8.5.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc11/gcc-11.2.0/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/sh/ |
| H A D | sh.h | 250 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" macro
253 #define SUBTARGET_ASM_ISA_SPEC \ macro
257 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/sh/ |
| H A D | sh.h | 296 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
299 #define SUBTARGET_ASM_ISA_SPEC \ macro
303 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gnat_util/gcc-6-20180516/gcc/config/sh/ |
| H A D | sh.h | 308 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
311 #define SUBTARGET_ASM_ISA_SPEC \ macro
315 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc48/gcc-4.8.5/gcc/config/sh/ |
| H A D | sh.h | 296 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
299 #define SUBTARGET_ASM_ISA_SPEC \ macro
303 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/sh/ |
| H A D | sh.h | 296 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
299 #define SUBTARGET_ASM_ISA_SPEC \ macro
303 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/sh/ |
| H A D | sh.h | 308 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
311 #define SUBTARGET_ASM_ISA_SPEC \ macro
315 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/config/sh/ |
| H A D | sh.h | 402 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" macro
405 #define SUBTARGET_ASM_ISA_SPEC \ macro
409 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC macro
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