1 /* $NetBSD: svga_reg.h,v 1.3 2021/12/18 23:45:45 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 4 /********************************************************** 5 * Copyright 1998-2015 VMware, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person 8 * obtaining a copy of this software and associated documentation 9 * files (the "Software"), to deal in the Software without 10 * restriction, including without limitation the rights to use, copy, 11 * modify, merge, publish, distribute, sublicense, and/or sell copies 12 * of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be 16 * included in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 21 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 22 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 23 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25 * SOFTWARE. 26 * 27 **********************************************************/ 28 29 /* 30 * svga_reg.h -- 31 * 32 * Virtual hardware definitions for the VMware SVGA II device. 33 */ 34 35 #ifndef _SVGA_REG_H_ 36 #define _SVGA_REG_H_ 37 #include <linux/pci_ids.h> 38 39 #define INCLUDE_ALLOW_MODULE 40 #define INCLUDE_ALLOW_USERLEVEL 41 42 #define INCLUDE_ALLOW_VMCORE 43 #include "includeCheck.h" 44 45 #include "svga_types.h" 46 47 /* 48 * SVGA_REG_ENABLE bit definitions. 49 */ 50 typedef enum { 51 SVGA_REG_ENABLE_DISABLE = 0, 52 SVGA_REG_ENABLE_ENABLE = (1 << 0), 53 SVGA_REG_ENABLE_HIDE = (1 << 1), 54 } SvgaRegEnable; 55 56 typedef uint32 SVGAMobId; 57 58 /* 59 * Arbitrary and meaningless limits. Please ignore these when writing 60 * new drivers. 61 */ 62 #define SVGA_MAX_WIDTH 2560 63 #define SVGA_MAX_HEIGHT 1600 64 65 66 #define SVGA_MAX_BITS_PER_PIXEL 32 67 #define SVGA_MAX_DEPTH 24 68 #define SVGA_MAX_DISPLAYS 10 69 #define SVGA_MAX_SCREEN_SIZE 8192 70 #define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS) 71 72 73 /* 74 * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned 75 * cursor bypass mode. This is still supported, but no new guest 76 * drivers should use it. 77 */ 78 #define SVGA_CURSOR_ON_HIDE 0x0 79 #define SVGA_CURSOR_ON_SHOW 0x1 80 81 /* 82 * Remove the cursor from the framebuffer 83 * because we need to see what's under it 84 */ 85 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 86 87 /* Put the cursor back in the framebuffer so the user can see it */ 88 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 89 90 /* 91 * The maximum framebuffer size that can traced for guests unless the 92 * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case 93 * the full framebuffer can be traced independent of this limit. 94 */ 95 #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 96 97 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 98 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) 99 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) 100 101 #define SVGA_MAGIC 0x900000UL 102 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) 103 104 /* Version 2 let the address of the frame buffer be unsigned on Win32 */ 105 #define SVGA_VERSION_2 2 106 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) 107 108 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so 109 PALETTE_BASE has moved */ 110 #define SVGA_VERSION_1 1 111 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) 112 113 /* Version 0 is the initial version */ 114 #define SVGA_VERSION_0 0 115 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) 116 117 /* 118 * "Invalid" value for all SVGA IDs. 119 * (Version ID, screen object ID, surface ID...) 120 */ 121 #define SVGA_ID_INVALID 0xFFFFFFFF 122 123 /* Port offsets, relative to BAR0 */ 124 #define SVGA_INDEX_PORT 0x0 125 #define SVGA_VALUE_PORT 0x1 126 #define SVGA_BIOS_PORT 0x2 127 #define SVGA_IRQSTATUS_PORT 0x8 128 129 /* 130 * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. 131 * 132 * Interrupts are only supported when the 133 * SVGA_CAP_IRQMASK capability is present. 134 */ 135 #define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */ 136 #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ 137 #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ 138 #define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */ 139 #define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */ 140 141 /* 142 * Registers 143 */ 144 145 enum { 146 SVGA_REG_ID = 0, 147 SVGA_REG_ENABLE = 1, 148 SVGA_REG_WIDTH = 2, 149 SVGA_REG_HEIGHT = 3, 150 SVGA_REG_MAX_WIDTH = 4, 151 SVGA_REG_MAX_HEIGHT = 5, 152 SVGA_REG_DEPTH = 6, 153 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ 154 SVGA_REG_PSEUDOCOLOR = 8, 155 SVGA_REG_RED_MASK = 9, 156 SVGA_REG_GREEN_MASK = 10, 157 SVGA_REG_BLUE_MASK = 11, 158 SVGA_REG_BYTES_PER_LINE = 12, 159 SVGA_REG_FB_START = 13, /* (Deprecated) */ 160 SVGA_REG_FB_OFFSET = 14, 161 SVGA_REG_VRAM_SIZE = 15, 162 SVGA_REG_FB_SIZE = 16, 163 164 /* ID 0 implementation only had the above registers, then the palette */ 165 SVGA_REG_ID_0_TOP = 17, 166 167 SVGA_REG_CAPABILITIES = 17, 168 SVGA_REG_MEM_START = 18, /* (Deprecated) */ 169 SVGA_REG_MEM_SIZE = 19, 170 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ 171 SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ 172 SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ 173 SVGA_REG_GUEST_ID = 23, /* (Deprecated) */ 174 SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ 175 SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ 176 SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ 177 SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ 178 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ 179 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ 180 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ 181 SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ 182 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ 183 SVGA_REG_IRQMASK = 33, /* Interrupt mask */ 184 185 /* Legacy multi-monitor support */ 186 SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ 187 SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ 188 SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ 189 SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ 190 SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ 191 SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ 192 SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ 193 194 /* See "Guest memory regions" below. */ 195 SVGA_REG_GMR_ID = 41, 196 SVGA_REG_GMR_DESCRIPTOR = 42, 197 SVGA_REG_GMR_MAX_IDS = 43, 198 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, 199 200 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ 201 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ 202 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 203 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */ 204 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */ 205 206 /* 207 * Max primary memory. 208 * See SVGA_CAP_NO_BB_RESTRICTION. 209 */ 210 SVGA_REG_MAX_PRIMARY_MEM = 50, 211 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, 212 213 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */ 214 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 215 SVGA_REG_CMD_PREPEND_LOW = 53, 216 SVGA_REG_CMD_PREPEND_HIGH = 54, 217 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55, 218 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56, 219 SVGA_REG_MOB_MAX_SIZE = 57, 220 SVGA_REG_BLANK_SCREEN_TARGETS = 58, 221 SVGA_REG_CAP2 = 59, 222 SVGA_REG_DEVEL_CAP = 60, 223 SVGA_REG_TOP = 61, /* Must be 1 more than the last register */ 224 225 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 226 /* Next 768 (== 256*3) registers exist for colormap */ 227 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS 228 /* Base of scratch registers */ 229 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: 230 First 4 are reserved for VESA BIOS Extension; any remaining are for 231 the use of the current SVGA driver. */ 232 }; 233 234 /* 235 * Guest memory regions (GMRs): 236 * 237 * This is a new memory mapping feature available in SVGA devices 238 * which have the SVGA_CAP_GMR bit set. Previously, there were two 239 * fixed memory regions available with which to share data between the 240 * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs 241 * are our name for an extensible way of providing arbitrary DMA 242 * buffers for use between the driver and the SVGA device. They are a 243 * new alternative to framebuffer memory, usable for both 2D and 3D 244 * graphics operations. 245 * 246 * Since GMR mapping must be done synchronously with guest CPU 247 * execution, we use a new pair of SVGA registers: 248 * 249 * SVGA_REG_GMR_ID -- 250 * 251 * Read/write. 252 * This register holds the 32-bit ID (a small positive integer) 253 * of a GMR to create, delete, or redefine. Writing this register 254 * has no side-effects. 255 * 256 * SVGA_REG_GMR_DESCRIPTOR -- 257 * 258 * Write-only. 259 * Writing this register will create, delete, or redefine the GMR 260 * specified by the above ID register. If this register is zero, 261 * the GMR is deleted. Any pointers into this GMR (including those 262 * currently being processed by FIFO commands) will be 263 * synchronously invalidated. 264 * 265 * If this register is nonzero, it must be the physical page 266 * number (PPN) of a data structure which describes the physical 267 * layout of the memory region this GMR should describe. The 268 * descriptor structure will be read synchronously by the SVGA 269 * device when this register is written. The descriptor need not 270 * remain allocated for the lifetime of the GMR. 271 * 272 * The guest driver should write SVGA_REG_GMR_ID first, then 273 * SVGA_REG_GMR_DESCRIPTOR. 274 * 275 * SVGA_REG_GMR_MAX_IDS -- 276 * 277 * Read-only. 278 * The SVGA device may choose to support a maximum number of 279 * user-defined GMR IDs. This register holds the number of supported 280 * IDs. (The maximum supported ID plus 1) 281 * 282 * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- 283 * 284 * Read-only. 285 * The SVGA device may choose to put a limit on the total number 286 * of SVGAGuestMemDescriptor structures it will read when defining 287 * a single GMR. 288 * 289 * The descriptor structure is an array of SVGAGuestMemDescriptor 290 * structures. Each structure may do one of three things: 291 * 292 * - Terminate the GMR descriptor list. 293 * (ppn==0, numPages==0) 294 * 295 * - Add a PPN or range of PPNs to the GMR's virtual address space. 296 * (ppn != 0, numPages != 0) 297 * 298 * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to 299 * support multi-page GMR descriptor tables without forcing the 300 * driver to allocate physically contiguous memory. 301 * (ppn != 0, numPages == 0) 302 * 303 * Note that each physical page of SVGAGuestMemDescriptor structures 304 * can describe at least 2MB of guest memory. If the driver needs to 305 * use more than one page of descriptor structures, it must use one of 306 * its SVGAGuestMemDescriptors to point to an additional page. The 307 * device will never automatically cross a page boundary. 308 * 309 * Once the driver has described a GMR, it is immediately available 310 * for use via any FIFO command that uses an SVGAGuestPtr structure. 311 * These pointers include a GMR identifier plus an offset into that 312 * GMR. 313 * 314 * The driver must check the SVGA_CAP_GMR bit before using the GMR 315 * registers. 316 */ 317 318 /* 319 * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer 320 * memory as well. In the future, these IDs could even be used to 321 * allow legacy memory regions to be redefined by the guest as GMRs. 322 * 323 * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA 324 * is being phased out. Please try to use user-defined GMRs whenever 325 * possible. 326 */ 327 #define SVGA_GMR_NULL ((uint32) -1) 328 #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */ 329 330 typedef 331 #include "vmware_pack_begin.h" 332 struct SVGAGuestMemDescriptor { 333 uint32 ppn; 334 uint32 numPages; 335 } 336 #include "vmware_pack_end.h" 337 SVGAGuestMemDescriptor; 338 339 typedef 340 #include "vmware_pack_begin.h" 341 struct SVGAGuestPtr { 342 uint32 gmrId; 343 uint32 offset; 344 } 345 #include "vmware_pack_end.h" 346 SVGAGuestPtr; 347 348 /* 349 * Register based command buffers -- 350 * 351 * Provide an SVGA device interface that allows the guest to submit 352 * command buffers to the SVGA device through an SVGA device register. 353 * The metadata for each command buffer is contained in the 354 * SVGACBHeader structure along with the return status codes. 355 * 356 * The SVGA device supports command buffers if 357 * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The 358 * fifo must be enabled for command buffers to be submitted. 359 * 360 * Command buffers are submitted when the guest writing the 64 byte 361 * aligned physical address into the SVGA_REG_COMMAND_LOW and 362 * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32 363 * bits of the physical address. SVGA_REG_COMMAND_LOW contains the 364 * lower 32 bits of the physical address, since the command buffer 365 * headers are required to be 64 byte aligned the lower 6 bits are 366 * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW 367 * submits the command buffer to the device and queues it for 368 * execution. The SVGA device supports at least 369 * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued 370 * per context and if that limit is reached the device will write the 371 * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command 372 * buffer header synchronously and not raise any IRQs. 373 * 374 * It is invalid to submit a command buffer without a valid physical 375 * address and results are undefined. 376 * 377 * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE 378 * will be supported. If a larger command buffer is submitted results 379 * are unspecified and the device will either complete the command 380 * buffer or return an error. 381 * 382 * The device guarantees that any individual command in a command 383 * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is 384 * enough to fit a 64x64 color-cursor definition. If the command is 385 * too large the device is allowed to process the command or return an 386 * error. 387 * 388 * The device context is a special SVGACBContext that allows for 389 * synchronous register like accesses with the flexibility of 390 * commands. There is a different command set defined by 391 * SVGADeviceContextCmdId. The commands in each command buffer is not 392 * allowed to straddle physical pages. 393 * 394 * The offset field which is available starting with the 395 * SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the 396 * start of command processing into the buffer. If an error is 397 * encountered the errorOffset will still be relative to the specific 398 * PA, not biased by the offset. When the command buffer is finished 399 * the guest should not read the offset field as there is no guarantee 400 * what it will set to. 401 * 402 * When the SVGA_CAP_HP_CMD_QUEUE cap bit is set a new command queue 403 * SVGA_CB_CONTEXT_1 is available. Commands submitted to this queue 404 * will be executed as quickly as possible by the SVGA device 405 * potentially before already queued commands on SVGA_CB_CONTEXT_0. 406 * The SVGA device guarantees that any command buffers submitted to 407 * SVGA_CB_CONTEXT_0 will be executed after any _already_ submitted 408 * command buffers to SVGA_CB_CONTEXT_1. 409 */ 410 411 #define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */ 412 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32 413 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */ 414 415 #define SVGA_CB_CONTEXT_MASK 0x3f 416 typedef enum { 417 SVGA_CB_CONTEXT_DEVICE = 0x3f, 418 SVGA_CB_CONTEXT_0 = 0x0, 419 SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */ 420 SVGA_CB_CONTEXT_MAX = 0x2, 421 SVGA_CB_CONTEXT_HP_MAX = 0x2, 422 } SVGACBContext; 423 424 425 typedef enum { 426 /* 427 * The guest is supposed to write SVGA_CB_STATUS_NONE to the status 428 * field before submitting the command buffer header, the host will 429 * change the value when it is done with the command buffer. 430 */ 431 SVGA_CB_STATUS_NONE = 0, 432 433 /* 434 * Written by the host when a command buffer completes successfully. 435 * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless 436 * the SVGA_CB_FLAG_NO_IRQ flag is set. 437 */ 438 SVGA_CB_STATUS_COMPLETED = 1, 439 440 /* 441 * Written by the host synchronously with the command buffer 442 * submission to indicate the command buffer was not submitted. No 443 * IRQ is raised. 444 */ 445 SVGA_CB_STATUS_QUEUE_FULL = 2, 446 447 /* 448 * Written by the host when an error was detected parsing a command 449 * in the command buffer, errorOffset is written to contain the 450 * offset to the first byte of the failing command. The device 451 * raises the IRQ with both SVGA_IRQFLAG_ERROR and 452 * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been 453 * processed. 454 */ 455 SVGA_CB_STATUS_COMMAND_ERROR = 3, 456 457 /* 458 * Written by the host if there is an error parsing the command 459 * buffer header. The device raises the IRQ with both 460 * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device 461 * did not processes any of the command buffer. 462 */ 463 SVGA_CB_STATUS_CB_HEADER_ERROR = 4, 464 465 /* 466 * Written by the host if the guest requested the host to preempt 467 * the command buffer. The device will not raise any IRQs and the 468 * command buffer was not processed. 469 */ 470 SVGA_CB_STATUS_PREEMPTED = 5, 471 472 /* 473 * Written by the host synchronously with the command buffer 474 * submission to indicate the the command buffer was not submitted 475 * due to an error. No IRQ is raised. 476 */ 477 SVGA_CB_STATUS_SUBMISSION_ERROR = 6, 478 479 /* 480 * Written by the host when the host finished a 481 * SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer 482 * queue. The offset of the first byte not processed is stored in 483 * the errorOffset field of the command buffer header. All guest 484 * visible side effects of commands till that point are guaranteed 485 * to be finished before this is written. The 486 * SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the 487 * SVGA_CB_FLAG_NO_IRQ is not set. 488 */ 489 SVGA_CB_STATUS_PARTIAL_COMPLETE = 7, 490 } SVGACBStatus; 491 492 typedef enum { 493 SVGA_CB_FLAG_NONE = 0, 494 SVGA_CB_FLAG_NO_IRQ = 1 << 0, 495 SVGA_CB_FLAG_DX_CONTEXT = 1 << 1, 496 SVGA_CB_FLAG_MOB = 1 << 2, 497 } SVGACBFlags; 498 499 typedef 500 #include "vmware_pack_begin.h" 501 struct { 502 volatile SVGACBStatus status; /* Modified by device. */ 503 volatile uint32 errorOffset; /* Modified by device. */ 504 uint64 id; 505 SVGACBFlags flags; 506 uint32 length; 507 union { 508 PA pa; 509 struct { 510 SVGAMobId mobid; 511 uint32 mobOffset; 512 } mob; 513 } ptr; 514 uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise, 515 * modified by device. 516 */ 517 uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */ 518 uint32 mustBeZero[6]; 519 } 520 #include "vmware_pack_end.h" 521 SVGACBHeader; 522 523 typedef enum { 524 SVGA_DC_CMD_NOP = 0, 525 SVGA_DC_CMD_START_STOP_CONTEXT = 1, 526 SVGA_DC_CMD_PREEMPT = 2, 527 SVGA_DC_CMD_START_QUEUE = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */ 528 SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */ 529 SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */ 530 SVGA_DC_CMD_MAX = 6, 531 } SVGADeviceContextCmdId; 532 533 /* 534 * Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1. 535 */ 536 537 typedef struct SVGADCCmdStartStop { 538 uint32 enable; 539 SVGACBContext context; /* Must be zero */ 540 } SVGADCCmdStartStop; 541 542 /* 543 * SVGADCCmdPreempt -- 544 * 545 * This command allows the guest to request that all command buffers 546 * on SVGA_CB_CONTEXT_0 be preempted that can be. After execution 547 * of this command all command buffers that were preempted will 548 * already have SVGA_CB_STATUS_PREEMPTED written into the status 549 * field. The device might still be processing a command buffer, 550 * assuming execution of it started before the preemption request was 551 * received. Specifying the ignoreIDZero flag to TRUE will cause the 552 * device to not preempt command buffers with the id field in the 553 * command buffer header set to zero. 554 */ 555 556 typedef struct SVGADCCmdPreempt { 557 SVGACBContext context; /* Must be zero */ 558 uint32 ignoreIDZero; 559 } SVGADCCmdPreempt; 560 561 /* 562 * Starts the requested command buffer processing queue. Valid only 563 * if the SVGA_CAP_HP_CMD_QUEUE cap is set. 564 * 565 * For a command queue to be considered runnable it must be enabled 566 * and any corresponding higher priority queues must also be enabled. 567 * For example in order for command buffers to be processed on 568 * SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must 569 * be enabled. But for commands to be runnable on SVGA_CB_CONTEXT_1 570 * only that queue must be enabled. 571 */ 572 573 typedef struct SVGADCCmdStartQueue { 574 SVGACBContext context; 575 } SVGADCCmdStartQueue; 576 577 /* 578 * Requests the SVGA device to stop processing the requested command 579 * buffer queue as soon as possible. The guest knows the stop has 580 * completed when one of the following happens. 581 * 582 * 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned 583 * 2) A command buffer error is encountered with would stop the queue 584 * regardless of the async stop request. 585 * 3) All command buffers that have been submitted complete successfully. 586 * 4) The stop completes synchronously if no command buffers are 587 * active on the queue when it is issued. 588 * 589 * If the command queue is not in a runnable state there is no 590 * guarentee this async stop will finish. For instance if the high 591 * priority queue is not enabled and a stop is requested on the low 592 * priority queue, the high priority queue must be reenabled to 593 * guarantee that the async stop will finish. 594 * 595 * This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used 596 * to implement mid command buffer preemption. 597 * 598 * Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set. 599 */ 600 601 typedef struct SVGADCCmdAsyncStopQueue { 602 SVGACBContext context; 603 } SVGADCCmdAsyncStopQueue; 604 605 /* 606 * Requests the SVGA device to throw away any full command buffers on 607 * the requested command queue that have not been started. For a 608 * driver to know which command buffers were thrown away a driver 609 * should only issue this command when the queue is stopped, for 610 * whatever reason. 611 */ 612 613 typedef struct SVGADCCmdEmptyQueue { 614 SVGACBContext context; 615 } SVGADCCmdEmptyQueue; 616 617 618 /* 619 * SVGAGMRImageFormat -- 620 * 621 * This is a packed representation of the source 2D image format 622 * for a GMR-to-screen blit. Currently it is defined as an encoding 623 * of the screen's color depth and bits-per-pixel, however, 16 bits 624 * are reserved for future use to identify other encodings (such as 625 * RGBA or higher-precision images). 626 * 627 * Currently supported formats: 628 * 629 * bpp depth Format Name 630 * --- ----- ----------- 631 * 32 24 32-bit BGRX 632 * 24 24 24-bit BGR 633 * 16 16 RGB 5-6-5 634 * 16 15 RGB 5-5-5 635 * 636 */ 637 638 typedef struct SVGAGMRImageFormat { 639 union { 640 struct { 641 uint32 bitsPerPixel : 8; 642 uint32 colorDepth : 8; 643 uint32 reserved : 16; /* Must be zero */ 644 }; 645 646 uint32 value; 647 }; 648 } SVGAGMRImageFormat; 649 650 typedef 651 #include "vmware_pack_begin.h" 652 struct SVGAGuestImage { 653 SVGAGuestPtr ptr; 654 655 /* 656 * A note on interpretation of pitch: This value of pitch is the 657 * number of bytes between vertically adjacent image 658 * blocks. Normally this is the number of bytes between the first 659 * pixel of two adjacent scanlines. With compressed textures, 660 * however, this may represent the number of bytes between 661 * compression blocks rather than between rows of pixels. 662 * 663 * XXX: Compressed textures currently must be tightly packed in guest memory. 664 * 665 * If the image is 1-dimensional, pitch is ignored. 666 * 667 * If 'pitch' is zero, the SVGA3D device calculates a pitch value 668 * assuming each row of blocks is tightly packed. 669 */ 670 uint32 pitch; 671 } 672 #include "vmware_pack_end.h" 673 SVGAGuestImage; 674 675 /* 676 * SVGAColorBGRX -- 677 * 678 * A 24-bit color format (BGRX), which does not depend on the 679 * format of the legacy guest framebuffer (GFB) or the current 680 * GMRFB state. 681 */ 682 683 typedef struct SVGAColorBGRX { 684 union { 685 struct { 686 uint32 b : 8; 687 uint32 g : 8; 688 uint32 r : 8; 689 uint32 x : 8; /* Unused */ 690 }; 691 692 uint32 value; 693 }; 694 } SVGAColorBGRX; 695 696 697 /* 698 * SVGASignedRect -- 699 * SVGASignedPoint -- 700 * 701 * Signed rectangle and point primitives. These are used by the new 702 * 2D primitives for drawing to Screen Objects, which can occupy a 703 * signed virtual coordinate space. 704 * 705 * SVGASignedRect specifies a half-open interval: the (left, top) 706 * pixel is part of the rectangle, but the (right, bottom) pixel is 707 * not. 708 */ 709 710 typedef 711 #include "vmware_pack_begin.h" 712 struct { 713 int32 left; 714 int32 top; 715 int32 right; 716 int32 bottom; 717 } 718 #include "vmware_pack_end.h" 719 SVGASignedRect; 720 721 typedef 722 #include "vmware_pack_begin.h" 723 struct { 724 int32 x; 725 int32 y; 726 } 727 #include "vmware_pack_end.h" 728 SVGASignedPoint; 729 730 731 /* 732 * SVGA Device Capabilities 733 * 734 * Note the holes in the bitfield. Missing bits have been deprecated, 735 * and must not be reused. Those capabilities will never be reported 736 * by new versions of the SVGA device. 737 * 738 * XXX: Add longer descriptions for each capability, including a list 739 * of the new features that each capability provides. 740 * 741 * SVGA_CAP_IRQMASK -- 742 * Provides device interrupts. Adds device register SVGA_REG_IRQMASK 743 * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to 744 * set/clear pending interrupts. 745 * 746 * SVGA_CAP_GMR -- 747 * Provides synchronous mapping of guest memory regions (GMR). 748 * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR, 749 * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH. 750 * 751 * SVGA_CAP_TRACES -- 752 * Allows framebuffer trace-based updates even when FIFO is enabled. 753 * Adds device register SVGA_REG_TRACES. 754 * 755 * SVGA_CAP_GMR2 -- 756 * Provides asynchronous commands to define and remap guest memory 757 * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and 758 * SVGA_REG_MEMORY_SIZE. 759 * 760 * SVGA_CAP_SCREEN_OBJECT_2 -- 761 * Allow screen object support, and require backing stores from the 762 * guest for each screen object. 763 * 764 * SVGA_CAP_COMMAND_BUFFERS -- 765 * Enable register based command buffer submission. 766 * 767 * SVGA_CAP_DEAD1 -- 768 * This cap was incorrectly used by old drivers and should not be 769 * reused. 770 * 771 * SVGA_CAP_CMD_BUFFERS_2 -- 772 * Enable support for the prepend command buffer submision 773 * registers. SVGA_REG_CMD_PREPEND_LOW and 774 * SVGA_REG_CMD_PREPEND_HIGH. 775 * 776 * SVGA_CAP_GBOBJECTS -- 777 * Enable guest-backed objects and surfaces. 778 * 779 * SVGA_CAP_DX -- 780 * Enable support for DX commands, and command buffers in a mob. 781 * 782 * SVGA_CAP_HP_CMD_QUEUE -- 783 * Enable support for the high priority command queue, and the 784 * ScreenCopy command. 785 * 786 * SVGA_CAP_NO_BB_RESTRICTION -- 787 * Allow ScreenTargets to be defined without regard to the 32-bpp 788 * bounding-box memory restrictions. ie: 789 * 790 * The summed memory usage of all screens (assuming they were defined as 791 * 32-bpp) must always be less than the value of the 792 * SVGA_REG_MAX_PRIMARY_MEM register. 793 * 794 * If this cap is not present, the 32-bpp bounding box around all screens 795 * must additionally be under the value of the SVGA_REG_MAX_PRIMARY_MEM 796 * register. 797 * 798 * If the cap is present, the bounding box restriction is lifted (and only 799 * the screen-sum limit applies). 800 * 801 * (Note that this is a slight lie... there is still a sanity limit on any 802 * dimension of the topology to be less than SVGA_SCREEN_ROOT_LIMIT, even 803 * when SVGA_CAP_NO_BB_RESTRICTION is present, but that should be 804 * large enough to express any possible topology without holes between 805 * monitors.) 806 * 807 * SVGA_CAP_CAP2_REGISTER -- 808 * If this cap is present, the SVGA_REG_CAP2 register is supported. 809 */ 810 811 #define SVGA_CAP_NONE 0x00000000 812 #define SVGA_CAP_RECT_COPY 0x00000002 813 #define SVGA_CAP_CURSOR 0x00000020 814 #define SVGA_CAP_CURSOR_BYPASS 0x00000040 815 #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 816 #define SVGA_CAP_8BIT_EMULATION 0x00000100 817 #define SVGA_CAP_ALPHA_CURSOR 0x00000200 818 #define SVGA_CAP_3D 0x00004000 819 #define SVGA_CAP_EXTENDED_FIFO 0x00008000 820 #define SVGA_CAP_MULTIMON 0x00010000 821 #define SVGA_CAP_PITCHLOCK 0x00020000 822 #define SVGA_CAP_IRQMASK 0x00040000 823 #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 824 #define SVGA_CAP_GMR 0x00100000 825 #define SVGA_CAP_TRACES 0x00200000 826 #define SVGA_CAP_GMR2 0x00400000 827 #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 828 #define SVGA_CAP_COMMAND_BUFFERS 0x01000000 829 #define SVGA_CAP_DEAD1 0x02000000 830 #define SVGA_CAP_CMD_BUFFERS_2 0x04000000 831 #define SVGA_CAP_GBOBJECTS 0x08000000 832 #define SVGA_CAP_DX 0x10000000 833 #define SVGA_CAP_HP_CMD_QUEUE 0x20000000 834 #define SVGA_CAP_NO_BB_RESTRICTION 0x40000000 835 #define SVGA_CAP_CAP2_REGISTER 0x80000000 836 837 /* 838 * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits. 839 * 840 * SVGA_CAP2_GROW_OTABLE -- 841 * Allow the GrowOTable/DXGrowCOTable commands. 842 * 843 * SVGA_CAP2_INTRA_SURFACE_COPY -- 844 * Allow the IntraSurfaceCopy command. 845 * 846 * SVGA_CAP2_DX2 -- 847 * Allow the DefineGBSurface_v3, WholeSurfaceCopy. 848 * 849 * SVGA_CAP2_RESERVED -- 850 * Reserve the last bit for extending the SVGA capabilities to some 851 * future mechanisms. 852 */ 853 #define SVGA_CAP2_NONE 0x00000000 854 #define SVGA_CAP2_GROW_OTABLE 0x00000001 855 #define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002 856 #define SVGA_CAP2_DX2 0x00000004 857 #define SVGA_CAP2_RESERVED 0x80000000 858 859 860 /* 861 * The Guest can optionally read some SVGA device capabilities through 862 * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before 863 * the SVGA device is initialized. The type of capability the guest 864 * is requesting from the SVGABackdoorCapType enum should be placed in 865 * the upper 16 bits of the backdoor command id (ECX). On success the 866 * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to 867 * the requested capability. If the command is not supported then EBX 868 * will be left unchanged and EAX will be set to -1. Because it is 869 * possible that -1 is the value of the requested cap the correct way 870 * to check if the command was successful is to check if EBX was changed 871 * to BDOOR_MAGIC making sure to initialize the register to something 872 * else first. 873 */ 874 875 typedef enum { 876 SVGABackdoorCapDeviceCaps = 0, 877 SVGABackdoorCapFifoCaps = 1, 878 SVGABackdoorCap3dHWVersion = 2, 879 SVGABackdoorCapDeviceCaps2 = 3, 880 SVGABackdoorCapMax = 4, 881 } SVGABackdoorCapType; 882 883 884 /* 885 * FIFO register indices. 886 * 887 * The FIFO is a chunk of device memory mapped into guest physmem. It 888 * is always treated as 32-bit words. 889 * 890 * The guest driver gets to decide how to partition it between 891 * - FIFO registers (there are always at least 4, specifying where the 892 * following data area is and how much data it contains; there may be 893 * more registers following these, depending on the FIFO protocol 894 * version in use) 895 * - FIFO data, written by the guest and slurped out by the VMX. 896 * These indices are 32-bit word offsets into the FIFO. 897 */ 898 899 enum { 900 /* 901 * Block 1 (basic registers): The originally defined FIFO registers. 902 * These exist and are valid for all versions of the FIFO protocol. 903 */ 904 905 SVGA_FIFO_MIN = 0, 906 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ 907 SVGA_FIFO_NEXT_CMD, 908 SVGA_FIFO_STOP, 909 910 /* 911 * Block 2 (extended registers): Mandatory registers for the extended 912 * FIFO. These exist if the SVGA caps register includes 913 * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their 914 * associated capability bit is enabled. 915 * 916 * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied 917 * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. 918 * This means that the guest has to test individually (in most cases 919 * using FIFO caps) for the presence of registers after this; the VMX 920 * can define "extended FIFO" to mean whatever it wants, and currently 921 * won't enable it unless there's room for that set and much more. 922 */ 923 924 SVGA_FIFO_CAPABILITIES = 4, 925 SVGA_FIFO_FLAGS, 926 /* Valid with SVGA_FIFO_CAP_FENCE: */ 927 SVGA_FIFO_FENCE, 928 929 /* 930 * Block 3a (optional extended registers): Additional registers for the 931 * extended FIFO, whose presence isn't actually implied by 932 * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to 933 * leave room for them. 934 * 935 * These in block 3a, the VMX currently considers mandatory for the 936 * extended FIFO. 937 */ 938 939 /* Valid if exists (i.e. if extended FIFO enabled): */ 940 SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ 941 /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */ 942 SVGA_FIFO_PITCHLOCK, 943 944 /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */ 945 SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ 946 SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ 947 SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ 948 SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ 949 SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ 950 951 /* Valid with SVGA_FIFO_CAP_RESERVE: */ 952 SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ 953 954 /* 955 * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2: 956 * 957 * By default this is SVGA_ID_INVALID, to indicate that the cursor 958 * coordinates are specified relative to the virtual root. If this 959 * is set to a specific screen ID, cursor position is reinterpreted 960 * as a signed offset relative to that screen's origin. 961 */ 962 SVGA_FIFO_CURSOR_SCREEN_ID, 963 964 /* 965 * Valid with SVGA_FIFO_CAP_DEAD 966 * 967 * An arbitrary value written by the host, drivers should not use it. 968 */ 969 SVGA_FIFO_DEAD, 970 971 /* 972 * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED: 973 * 974 * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h) 975 * on platforms that can enforce graphics resource limits. 976 */ 977 SVGA_FIFO_3D_HWVERSION_REVISED, 978 979 /* 980 * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new 981 * registers, but this must be done carefully and with judicious use of 982 * capability bits, since comparisons based on SVGA_FIFO_MIN aren't 983 * enough to tell you whether the register exists: we've shipped drivers 984 * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of 985 * the earlier ones. The actual order of introduction was: 986 * - PITCHLOCK 987 * - 3D_CAPS 988 * - CURSOR_* (cursor bypass 3) 989 * - RESERVED 990 * So, code that wants to know whether it can use any of the 991 * aforementioned registers, or anything else added after PITCHLOCK and 992 * before 3D_CAPS, needs to reason about something other than 993 * SVGA_FIFO_MIN. 994 */ 995 996 /* 997 * 3D caps block space; valid with 3D hardware version >= 998 * SVGA3D_HWVERSION_WS6_B1. 999 */ 1000 SVGA_FIFO_3D_CAPS = 32, 1001 SVGA_FIFO_3D_CAPS_LAST = 32 + 255, 1002 1003 /* 1004 * End of VMX's current definition of "extended-FIFO registers". 1005 * Registers before here are always enabled/disabled as a block; either 1006 * the extended FIFO is enabled and includes all preceding registers, or 1007 * it's disabled entirely. 1008 * 1009 * Block 3b (truly optional extended registers): Additional registers for 1010 * the extended FIFO, which the VMX already knows how to enable and 1011 * disable with correct granularity. 1012 * 1013 * Registers after here exist if and only if the guest SVGA driver 1014 * sets SVGA_FIFO_MIN high enough to leave room for them. 1015 */ 1016 1017 /* Valid if register exists: */ 1018 SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ 1019 SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */ 1020 SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ 1021 1022 /* 1023 * Always keep this last. This defines the maximum number of 1024 * registers we know about. At power-on, this value is placed in 1025 * the SVGA_REG_MEM_REGS register, and we expect the guest driver 1026 * to allocate this much space in FIFO memory for registers. 1027 */ 1028 SVGA_FIFO_NUM_REGS 1029 }; 1030 1031 1032 /* 1033 * Definition of registers included in extended FIFO support. 1034 * 1035 * The guest SVGA driver gets to allocate the FIFO between registers 1036 * and data. It must always allocate at least 4 registers, but old 1037 * drivers stopped there. 1038 * 1039 * The VMX will enable extended FIFO support if and only if the guest 1040 * left enough room for all registers defined as part of the mandatory 1041 * set for the extended FIFO. 1042 * 1043 * Note that the guest drivers typically allocate the FIFO only at 1044 * initialization time, not at mode switches, so it's likely that the 1045 * number of FIFO registers won't change without a reboot. 1046 * 1047 * All registers less than this value are guaranteed to be present if 1048 * svgaUser->fifo.extended is set. Any later registers must be tested 1049 * individually for compatibility at each use (in the VMX). 1050 * 1051 * This value is used only by the VMX, so it can change without 1052 * affecting driver compatibility; keep it that way? 1053 */ 1054 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) 1055 1056 1057 /* 1058 * FIFO Synchronization Registers 1059 * 1060 * This explains the relationship between the various FIFO 1061 * sync-related registers in IOSpace and in FIFO space. 1062 * 1063 * SVGA_REG_SYNC -- 1064 * 1065 * The SYNC register can be used in two different ways by the guest: 1066 * 1067 * 1. If the guest wishes to fully sync (drain) the FIFO, 1068 * it will write once to SYNC then poll on the BUSY 1069 * register. The FIFO is sync'ed once BUSY is zero. 1070 * 1071 * 2. If the guest wants to asynchronously wake up the host, 1072 * it will write once to SYNC without polling on BUSY. 1073 * Ideally it will do this after some new commands have 1074 * been placed in the FIFO, and after reading a zero 1075 * from SVGA_FIFO_BUSY. 1076 * 1077 * (1) is the original behaviour that SYNC was designed to 1078 * support. Originally, a write to SYNC would implicitly 1079 * trigger a read from BUSY. This causes us to synchronously 1080 * process the FIFO. 1081 * 1082 * This behaviour has since been changed so that writing SYNC 1083 * will *not* implicitly cause a read from BUSY. Instead, it 1084 * makes a channel call which asynchronously wakes up the MKS 1085 * thread. 1086 * 1087 * New guests can use this new behaviour to implement (2) 1088 * efficiently. This lets guests get the host's attention 1089 * without waiting for the MKS to poll, which gives us much 1090 * better CPU utilization on SMP hosts and on UP hosts while 1091 * we're blocked on the host GPU. 1092 * 1093 * Old guests shouldn't notice the behaviour change. SYNC was 1094 * never guaranteed to process the entire FIFO, since it was 1095 * bounded to a particular number of CPU cycles. Old guests will 1096 * still loop on the BUSY register until the FIFO is empty. 1097 * 1098 * Writing to SYNC currently has the following side-effects: 1099 * 1100 * - Sets SVGA_REG_BUSY to TRUE (in the monitor) 1101 * - Asynchronously wakes up the MKS thread for FIFO processing 1102 * - The value written to SYNC is recorded as a "reason", for 1103 * stats purposes. 1104 * 1105 * If SVGA_FIFO_BUSY is available, drivers are advised to only 1106 * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set 1107 * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will 1108 * eventually set SVGA_FIFO_BUSY on its own, but this approach 1109 * lets the driver avoid sending multiple asynchronous wakeup 1110 * messages to the MKS thread. 1111 * 1112 * SVGA_REG_BUSY -- 1113 * 1114 * This register is set to TRUE when SVGA_REG_SYNC is written, 1115 * and it reads as FALSE when the FIFO has been completely 1116 * drained. 1117 * 1118 * Every read from this register causes us to synchronously 1119 * process FIFO commands. There is no guarantee as to how many 1120 * commands each read will process. 1121 * 1122 * CPU time spent processing FIFO commands will be billed to 1123 * the guest. 1124 * 1125 * New drivers should avoid using this register unless they 1126 * need to guarantee that the FIFO is completely drained. It 1127 * is overkill for performing a sync-to-fence. Older drivers 1128 * will use this register for any type of synchronization. 1129 * 1130 * SVGA_FIFO_BUSY -- 1131 * 1132 * This register is a fast way for the guest driver to check 1133 * whether the FIFO is already being processed. It reads and 1134 * writes at normal RAM speeds, with no monitor intervention. 1135 * 1136 * If this register reads as TRUE, the host is guaranteeing that 1137 * any new commands written into the FIFO will be noticed before 1138 * the MKS goes back to sleep. 1139 * 1140 * If this register reads as FALSE, no such guarantee can be 1141 * made. 1142 * 1143 * The guest should use this register to quickly determine 1144 * whether or not it needs to wake up the host. If the guest 1145 * just wrote a command or group of commands that it would like 1146 * the host to begin processing, it should: 1147 * 1148 * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further 1149 * action is necessary. 1150 * 1151 * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest 1152 * code that we've already sent a SYNC to the host and we 1153 * don't need to send a duplicate. 1154 * 1155 * 3. Write a reason to SVGA_REG_SYNC. This will send an 1156 * asynchronous wakeup to the MKS thread. 1157 */ 1158 1159 1160 /* 1161 * FIFO Capabilities 1162 * 1163 * Fence -- Fence register and command are supported 1164 * Accel Front -- Front buffer only commands are supported 1165 * Pitch Lock -- Pitch lock register is supported 1166 * Video -- SVGA Video overlay units are supported 1167 * Escape -- Escape command is supported 1168 * 1169 * XXX: Add longer descriptions for each capability, including a list 1170 * of the new features that each capability provides. 1171 * 1172 * SVGA_FIFO_CAP_SCREEN_OBJECT -- 1173 * 1174 * Provides dynamic multi-screen rendering, for improved Unity and 1175 * multi-monitor modes. With Screen Object, the guest can 1176 * dynamically create and destroy 'screens', which can represent 1177 * Unity windows or virtual monitors. Screen Object also provides 1178 * strong guarantees that DMA operations happen only when 1179 * guest-initiated. Screen Object deprecates the BAR1 guest 1180 * framebuffer (GFB) and all commands that work only with the GFB. 1181 * 1182 * New registers: 1183 * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID 1184 * 1185 * New 2D commands: 1186 * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, 1187 * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY 1188 * 1189 * New 3D commands: 1190 * BLIT_SURFACE_TO_SCREEN 1191 * 1192 * New guarantees: 1193 * 1194 * - The host will not read or write guest memory, including the GFB, 1195 * except when explicitly initiated by a DMA command. 1196 * 1197 * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, 1198 * is guaranteed to complete before any subsequent FENCEs. 1199 * 1200 * - All legacy commands which affect a Screen (UPDATE, PRESENT, 1201 * PRESENT_READBACK) as well as new Screen blit commands will 1202 * all behave consistently as blits, and memory will be read 1203 * or written in FIFO order. 1204 * 1205 * For example, if you PRESENT from one SVGA3D surface to multiple 1206 * places on the screen, the data copied will always be from the 1207 * SVGA3D surface at the time the PRESENT was issued in the FIFO. 1208 * This was not necessarily true on devices without Screen Object. 1209 * 1210 * This means that on devices that support Screen Object, the 1211 * PRESENT_READBACK command should not be necessary unless you 1212 * actually want to read back the results of 3D rendering into 1213 * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB 1214 * command provides a strict superset of functionality.) 1215 * 1216 * - When a screen is resized, either using Screen Object commands or 1217 * legacy multimon registers, its contents are preserved. 1218 * 1219 * SVGA_FIFO_CAP_GMR2 -- 1220 * 1221 * Provides new commands to define and remap guest memory regions (GMR). 1222 * 1223 * New 2D commands: 1224 * DEFINE_GMR2, REMAP_GMR2. 1225 * 1226 * SVGA_FIFO_CAP_3D_HWVERSION_REVISED -- 1227 * 1228 * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists. 1229 * This register may replace SVGA_FIFO_3D_HWVERSION on platforms 1230 * that enforce graphics resource limits. This allows the platform 1231 * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest 1232 * drivers that do not limit their resources. 1233 * 1234 * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators 1235 * are codependent (and thus we use a single capability bit). 1236 * 1237 * SVGA_FIFO_CAP_SCREEN_OBJECT_2 -- 1238 * 1239 * Modifies the DEFINE_SCREEN command to include a guest provided 1240 * backing store in GMR memory and the bytesPerLine for the backing 1241 * store. This capability requires the use of a backing store when 1242 * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT 1243 * is present then backing stores are optional. 1244 * 1245 * SVGA_FIFO_CAP_DEAD -- 1246 * 1247 * Drivers should not use this cap bit. This cap bit can not be 1248 * reused since some hosts already expose it. 1249 */ 1250 1251 #define SVGA_FIFO_CAP_NONE 0 1252 #define SVGA_FIFO_CAP_FENCE (1<<0) 1253 #define SVGA_FIFO_CAP_ACCELFRONT (1<<1) 1254 #define SVGA_FIFO_CAP_PITCHLOCK (1<<2) 1255 #define SVGA_FIFO_CAP_VIDEO (1<<3) 1256 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) 1257 #define SVGA_FIFO_CAP_ESCAPE (1<<5) 1258 #define SVGA_FIFO_CAP_RESERVE (1<<6) 1259 #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) 1260 #define SVGA_FIFO_CAP_GMR2 (1<<8) 1261 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2 1262 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9) 1263 #define SVGA_FIFO_CAP_DEAD (1<<10) 1264 1265 1266 /* 1267 * FIFO Flags 1268 * 1269 * Accel Front -- Driver should use front buffer only commands 1270 */ 1271 1272 #define SVGA_FIFO_FLAG_NONE 0 1273 #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0) 1274 #define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */ 1275 1276 /* 1277 * FIFO reservation sentinel value 1278 */ 1279 1280 #define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff 1281 1282 1283 /* 1284 * Video overlay support 1285 */ 1286 1287 #define SVGA_NUM_OVERLAY_UNITS 32 1288 1289 1290 /* 1291 * Video capabilities that the guest is currently using 1292 */ 1293 1294 #define SVGA_VIDEO_FLAG_COLORKEY 0x0001 1295 1296 1297 /* 1298 * Offsets for the video overlay registers 1299 */ 1300 1301 enum { 1302 SVGA_VIDEO_ENABLED = 0, 1303 SVGA_VIDEO_FLAGS, 1304 SVGA_VIDEO_DATA_OFFSET, 1305 SVGA_VIDEO_FORMAT, 1306 SVGA_VIDEO_COLORKEY, 1307 SVGA_VIDEO_SIZE, /* Deprecated */ 1308 SVGA_VIDEO_WIDTH, 1309 SVGA_VIDEO_HEIGHT, 1310 SVGA_VIDEO_SRC_X, 1311 SVGA_VIDEO_SRC_Y, 1312 SVGA_VIDEO_SRC_WIDTH, 1313 SVGA_VIDEO_SRC_HEIGHT, 1314 SVGA_VIDEO_DST_X, /* Signed int32 */ 1315 SVGA_VIDEO_DST_Y, /* Signed int32 */ 1316 SVGA_VIDEO_DST_WIDTH, 1317 SVGA_VIDEO_DST_HEIGHT, 1318 SVGA_VIDEO_PITCH_1, 1319 SVGA_VIDEO_PITCH_2, 1320 SVGA_VIDEO_PITCH_3, 1321 SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */ 1322 SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */ 1323 /* (SVGA_ID_INVALID) */ 1324 SVGA_VIDEO_NUM_REGS 1325 }; 1326 1327 1328 /* 1329 * SVGA Overlay Units 1330 * 1331 * width and height relate to the entire source video frame. 1332 * srcX, srcY, srcWidth and srcHeight represent subset of the source 1333 * video frame to be displayed. 1334 */ 1335 1336 typedef 1337 #include "vmware_pack_begin.h" 1338 struct SVGAOverlayUnit { 1339 uint32 enabled; 1340 uint32 flags; 1341 uint32 dataOffset; 1342 uint32 format; 1343 uint32 colorKey; 1344 uint32 size; 1345 uint32 width; 1346 uint32 height; 1347 uint32 srcX; 1348 uint32 srcY; 1349 uint32 srcWidth; 1350 uint32 srcHeight; 1351 int32 dstX; 1352 int32 dstY; 1353 uint32 dstWidth; 1354 uint32 dstHeight; 1355 uint32 pitches[3]; 1356 uint32 dataGMRId; 1357 uint32 dstScreenId; 1358 } 1359 #include "vmware_pack_end.h" 1360 SVGAOverlayUnit; 1361 1362 1363 /* 1364 * Guest display topology 1365 * 1366 * XXX: This structure is not part of the SVGA device's interface, and 1367 * doesn't really belong here. 1368 */ 1369 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1) 1370 1371 typedef struct SVGADisplayTopology { 1372 uint16 displayId; 1373 uint16 isPrimary; 1374 uint32 width; 1375 uint32 height; 1376 uint32 positionX; 1377 uint32 positionY; 1378 } SVGADisplayTopology; 1379 1380 1381 /* 1382 * SVGAScreenObject -- 1383 * 1384 * This is a new way to represent a guest's multi-monitor screen or 1385 * Unity window. Screen objects are only supported if the 1386 * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. 1387 * 1388 * If Screen Objects are supported, they can be used to fully 1389 * replace the functionality provided by the framebuffer registers 1390 * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. 1391 * 1392 * The screen object is a struct with guaranteed binary 1393 * compatibility. New flags can be added, and the struct may grow, 1394 * but existing fields must retain their meaning. 1395 * 1396 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of 1397 * a SVGAGuestPtr that is used to back the screen contents. This 1398 * memory must come from the GFB. The guest is not allowed to 1399 * access the memory and doing so will have undefined results. The 1400 * backing store is required to be page aligned and the size is 1401 * padded to the next page boundry. The number of pages is: 1402 * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE 1403 * 1404 * The pitch in the backingStore is required to be at least large 1405 * enough to hold a 32bbp scanline. It is recommended that the 1406 * driver pad bytesPerLine for a potential performance win. 1407 * 1408 * The cloneCount field is treated as a hint from the guest that 1409 * the user wants this display to be cloned, countCount times. A 1410 * value of zero means no cloning should happen. 1411 */ 1412 1413 #define SVGA_SCREEN_MUST_BE_SET (1 << 0) 1414 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */ 1415 #define SVGA_SCREEN_IS_PRIMARY (1 << 1) 1416 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) 1417 1418 /* 1419 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is 1420 * deactivated the base layer is defined to lose all contents and 1421 * become black. When a screen is deactivated the backing store is 1422 * optional. When set backingPtr and bytesPerLine will be ignored. 1423 */ 1424 #define SVGA_SCREEN_DEACTIVATE (1 << 3) 1425 1426 /* 1427 * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set 1428 * the screen contents will be outputted as all black to the user 1429 * though the base layer contents is preserved. The screen base layer 1430 * can still be read and written to like normal though the no visible 1431 * effect will be seen by the user. When the flag is changed the 1432 * screen will be blanked or redrawn to the current contents as needed 1433 * without any extra commands from the driver. This flag only has an 1434 * effect when the screen is not deactivated. 1435 */ 1436 #define SVGA_SCREEN_BLANKING (1 << 4) 1437 1438 typedef 1439 #include "vmware_pack_begin.h" 1440 struct { 1441 uint32 structSize; /* sizeof(SVGAScreenObject) */ 1442 uint32 id; 1443 uint32 flags; 1444 struct { 1445 uint32 width; 1446 uint32 height; 1447 } size; 1448 struct { 1449 int32 x; 1450 int32 y; 1451 } root; 1452 1453 /* 1454 * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional 1455 * with SVGA_FIFO_CAP_SCREEN_OBJECT. 1456 */ 1457 SVGAGuestImage backingStore; 1458 1459 /* 1460 * The cloneCount field is treated as a hint from the guest that 1461 * the user wants this display to be cloned, cloneCount times. 1462 * 1463 * A value of zero means no cloning should happen. 1464 */ 1465 uint32 cloneCount; 1466 } 1467 #include "vmware_pack_end.h" 1468 SVGAScreenObject; 1469 1470 1471 /* 1472 * Commands in the command FIFO: 1473 * 1474 * Command IDs defined below are used for the traditional 2D FIFO 1475 * communication (not all commands are available for all versions of the 1476 * SVGA FIFO protocol). 1477 * 1478 * Note the holes in the command ID numbers: These commands have been 1479 * deprecated, and the old IDs must not be reused. 1480 * 1481 * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D 1482 * protocol. 1483 * 1484 * Each command's parameters are described by the comments and 1485 * structs below. 1486 */ 1487 1488 typedef enum { 1489 SVGA_CMD_INVALID_CMD = 0, 1490 SVGA_CMD_UPDATE = 1, 1491 SVGA_CMD_RECT_COPY = 3, 1492 SVGA_CMD_RECT_ROP_COPY = 14, 1493 SVGA_CMD_DEFINE_CURSOR = 19, 1494 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, 1495 SVGA_CMD_UPDATE_VERBOSE = 25, 1496 SVGA_CMD_FRONT_ROP_FILL = 29, 1497 SVGA_CMD_FENCE = 30, 1498 SVGA_CMD_ESCAPE = 33, 1499 SVGA_CMD_DEFINE_SCREEN = 34, 1500 SVGA_CMD_DESTROY_SCREEN = 35, 1501 SVGA_CMD_DEFINE_GMRFB = 36, 1502 SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, 1503 SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, 1504 SVGA_CMD_ANNOTATION_FILL = 39, 1505 SVGA_CMD_ANNOTATION_COPY = 40, 1506 SVGA_CMD_DEFINE_GMR2 = 41, 1507 SVGA_CMD_REMAP_GMR2 = 42, 1508 SVGA_CMD_DEAD = 43, 1509 SVGA_CMD_DEAD_2 = 44, 1510 SVGA_CMD_NOP = 45, 1511 SVGA_CMD_NOP_ERROR = 46, 1512 SVGA_CMD_MAX 1513 } SVGAFifoCmdId; 1514 1515 #define SVGA_CMD_MAX_DATASIZE (256 * 1024) 1516 #define SVGA_CMD_MAX_ARGS 64 1517 1518 1519 /* 1520 * SVGA_CMD_UPDATE -- 1521 * 1522 * This is a DMA transfer which copies from the Guest Framebuffer 1523 * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which 1524 * intersect with the provided virtual rectangle. 1525 * 1526 * This command does not support using arbitrary guest memory as a 1527 * data source- it only works with the pre-defined GFB memory. 1528 * This command also does not support signed virtual coordinates. 1529 * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with 1530 * negative root x/y coordinates, the negative portion of those 1531 * screens will not be reachable by this command. 1532 * 1533 * This command is not necessary when using framebuffer 1534 * traces. Traces are automatically enabled if the SVGA FIFO is 1535 * disabled, and you may explicitly enable/disable traces using 1536 * SVGA_REG_TRACES. With traces enabled, any write to the GFB will 1537 * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. 1538 * 1539 * Traces and SVGA_CMD_UPDATE are the only supported ways to render 1540 * pseudocolor screen updates. The newer Screen Object commands 1541 * only support true color formats. 1542 * 1543 * Availability: 1544 * Always available. 1545 */ 1546 1547 typedef 1548 #include "vmware_pack_begin.h" 1549 struct { 1550 uint32 x; 1551 uint32 y; 1552 uint32 width; 1553 uint32 height; 1554 } 1555 #include "vmware_pack_end.h" 1556 SVGAFifoCmdUpdate; 1557 1558 1559 /* 1560 * SVGA_CMD_RECT_COPY -- 1561 * 1562 * Perform a rectangular DMA transfer from one area of the GFB to 1563 * another, and copy the result to any screens which intersect it. 1564 * 1565 * Availability: 1566 * SVGA_CAP_RECT_COPY 1567 */ 1568 1569 typedef 1570 #include "vmware_pack_begin.h" 1571 struct { 1572 uint32 srcX; 1573 uint32 srcY; 1574 uint32 destX; 1575 uint32 destY; 1576 uint32 width; 1577 uint32 height; 1578 } 1579 #include "vmware_pack_end.h" 1580 SVGAFifoCmdRectCopy; 1581 1582 1583 /* 1584 * SVGA_CMD_RECT_ROP_COPY -- 1585 * 1586 * Perform a rectangular DMA transfer from one area of the GFB to 1587 * another, and copy the result to any screens which intersect it. 1588 * The value of ROP may only be SVGA_ROP_COPY, and this command is 1589 * only supported for backwards compatibility reasons. 1590 * 1591 * Availability: 1592 * SVGA_CAP_RECT_COPY 1593 */ 1594 1595 typedef 1596 #include "vmware_pack_begin.h" 1597 struct { 1598 uint32 srcX; 1599 uint32 srcY; 1600 uint32 destX; 1601 uint32 destY; 1602 uint32 width; 1603 uint32 height; 1604 uint32 rop; 1605 } 1606 #include "vmware_pack_end.h" 1607 SVGAFifoCmdRectRopCopy; 1608 1609 1610 /* 1611 * SVGA_CMD_DEFINE_CURSOR -- 1612 * 1613 * Provide a new cursor image, as an AND/XOR mask. 1614 * 1615 * The recommended way to position the cursor overlay is by using 1616 * the SVGA_FIFO_CURSOR_* registers, supported by the 1617 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1618 * 1619 * Availability: 1620 * SVGA_CAP_CURSOR 1621 */ 1622 1623 typedef 1624 #include "vmware_pack_begin.h" 1625 struct { 1626 uint32 id; /* Reserved, must be zero. */ 1627 uint32 hotspotX; 1628 uint32 hotspotY; 1629 uint32 width; 1630 uint32 height; 1631 uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1632 uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */ 1633 /* 1634 * Followed by scanline data for AND mask, then XOR mask. 1635 * Each scanline is padded to a 32-bit boundary. 1636 */ 1637 } 1638 #include "vmware_pack_end.h" 1639 SVGAFifoCmdDefineCursor; 1640 1641 1642 /* 1643 * SVGA_CMD_DEFINE_ALPHA_CURSOR -- 1644 * 1645 * Provide a new cursor image, in 32-bit BGRA format. 1646 * 1647 * The recommended way to position the cursor overlay is by using 1648 * the SVGA_FIFO_CURSOR_* registers, supported by the 1649 * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. 1650 * 1651 * Availability: 1652 * SVGA_CAP_ALPHA_CURSOR 1653 */ 1654 1655 typedef 1656 #include "vmware_pack_begin.h" 1657 struct { 1658 uint32 id; /* Reserved, must be zero. */ 1659 uint32 hotspotX; 1660 uint32 hotspotY; 1661 uint32 width; 1662 uint32 height; 1663 /* Followed by scanline data */ 1664 } 1665 #include "vmware_pack_end.h" 1666 SVGAFifoCmdDefineAlphaCursor; 1667 1668 1669 /* 1670 * SVGA_CMD_UPDATE_VERBOSE -- 1671 * 1672 * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle 1673 * 'reason' value, an opaque cookie which is used by internal 1674 * debugging tools. Third party drivers should not use this 1675 * command. 1676 * 1677 * Availability: 1678 * SVGA_CAP_EXTENDED_FIFO 1679 */ 1680 1681 typedef 1682 #include "vmware_pack_begin.h" 1683 struct { 1684 uint32 x; 1685 uint32 y; 1686 uint32 width; 1687 uint32 height; 1688 uint32 reason; 1689 } 1690 #include "vmware_pack_end.h" 1691 SVGAFifoCmdUpdateVerbose; 1692 1693 1694 /* 1695 * SVGA_CMD_FRONT_ROP_FILL -- 1696 * 1697 * This is a hint which tells the SVGA device that the driver has 1698 * just filled a rectangular region of the GFB with a solid 1699 * color. Instead of reading these pixels from the GFB, the device 1700 * can assume that they all equal 'color'. This is primarily used 1701 * for remote desktop protocols. 1702 * 1703 * Availability: 1704 * SVGA_FIFO_CAP_ACCELFRONT 1705 */ 1706 1707 #define SVGA_ROP_COPY 0x03 1708 1709 typedef 1710 #include "vmware_pack_begin.h" 1711 struct { 1712 uint32 color; /* In the same format as the GFB */ 1713 uint32 x; 1714 uint32 y; 1715 uint32 width; 1716 uint32 height; 1717 uint32 rop; /* Must be SVGA_ROP_COPY */ 1718 } 1719 #include "vmware_pack_end.h" 1720 SVGAFifoCmdFrontRopFill; 1721 1722 1723 /* 1724 * SVGA_CMD_FENCE -- 1725 * 1726 * Insert a synchronization fence. When the SVGA device reaches 1727 * this command, it will copy the 'fence' value into the 1728 * SVGA_FIFO_FENCE register. It will also compare the fence against 1729 * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the 1730 * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will 1731 * raise this interrupt. 1732 * 1733 * Availability: 1734 * SVGA_FIFO_FENCE for this command, 1735 * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. 1736 */ 1737 1738 typedef 1739 #include "vmware_pack_begin.h" 1740 struct { 1741 uint32 fence; 1742 } 1743 #include "vmware_pack_end.h" 1744 SVGAFifoCmdFence; 1745 1746 1747 /* 1748 * SVGA_CMD_ESCAPE -- 1749 * 1750 * Send an extended or vendor-specific variable length command. 1751 * This is used for video overlay, third party plugins, and 1752 * internal debugging tools. See svga_escape.h 1753 * 1754 * Availability: 1755 * SVGA_FIFO_CAP_ESCAPE 1756 */ 1757 1758 typedef 1759 #include "vmware_pack_begin.h" 1760 struct { 1761 uint32 nsid; 1762 uint32 size; 1763 /* followed by 'size' bytes of data */ 1764 } 1765 #include "vmware_pack_end.h" 1766 SVGAFifoCmdEscape; 1767 1768 1769 /* 1770 * SVGA_CMD_DEFINE_SCREEN -- 1771 * 1772 * Define or redefine an SVGAScreenObject. See the description of 1773 * SVGAScreenObject above. The video driver is responsible for 1774 * generating new screen IDs. They should be small positive 1775 * integers. The virtual device will have an implementation 1776 * specific upper limit on the number of screen IDs 1777 * supported. Drivers are responsible for recycling IDs. The first 1778 * valid ID is zero. 1779 * 1780 * - Interaction with other registers: 1781 * 1782 * For backwards compatibility, when the GFB mode registers (WIDTH, 1783 * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device 1784 * deletes all screens other than screen #0, and redefines screen 1785 * #0 according to the specified mode. Drivers that use 1786 * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. 1787 * 1788 * If you use screen objects, do not use the legacy multi-mon 1789 * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). 1790 * 1791 * Availability: 1792 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1793 */ 1794 1795 typedef 1796 #include "vmware_pack_begin.h" 1797 struct { 1798 SVGAScreenObject screen; /* Variable-length according to version */ 1799 } 1800 #include "vmware_pack_end.h" 1801 SVGAFifoCmdDefineScreen; 1802 1803 1804 /* 1805 * SVGA_CMD_DESTROY_SCREEN -- 1806 * 1807 * Destroy an SVGAScreenObject. Its ID is immediately available for 1808 * re-use. 1809 * 1810 * Availability: 1811 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1812 */ 1813 1814 typedef 1815 #include "vmware_pack_begin.h" 1816 struct { 1817 uint32 screenId; 1818 } 1819 #include "vmware_pack_end.h" 1820 SVGAFifoCmdDestroyScreen; 1821 1822 1823 /* 1824 * SVGA_CMD_DEFINE_GMRFB -- 1825 * 1826 * This command sets a piece of SVGA device state called the 1827 * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a 1828 * piece of light-weight state which identifies the location and 1829 * format of an image in guest memory or in BAR1. The GMRFB has 1830 * an arbitrary size, and it doesn't need to match the geometry 1831 * of the GFB or any screen object. 1832 * 1833 * The GMRFB can be redefined as often as you like. You could 1834 * always use the same GMRFB, you could redefine it before 1835 * rendering from a different guest screen, or you could even 1836 * redefine it before every blit. 1837 * 1838 * There are multiple ways to use this command. The simplest way is 1839 * to use it to move the framebuffer either to elsewhere in the GFB 1840 * (BAR1) memory region, or to a user-defined GMR. This lets a 1841 * driver use a framebuffer allocated entirely out of normal system 1842 * memory, which we encourage. 1843 * 1844 * Another way to use this command is to set up a ring buffer of 1845 * updates in GFB memory. If a driver wants to ensure that no 1846 * frames are skipped by the SVGA device, it is important that the 1847 * driver not modify the source data for a blit until the device is 1848 * done processing the command. One efficient way to accomplish 1849 * this is to use a ring of small DMA buffers. Each buffer is used 1850 * for one blit, then we move on to the next buffer in the 1851 * ring. The FENCE mechanism is used to protect each buffer from 1852 * re-use until the device is finished with that buffer's 1853 * corresponding blit. 1854 * 1855 * This command does not affect the meaning of SVGA_CMD_UPDATE. 1856 * UPDATEs always occur from the legacy GFB memory area. This 1857 * command has no support for pseudocolor GMRFBs. Currently only 1858 * true-color 15, 16, and 24-bit depths are supported. Future 1859 * devices may expose capabilities for additional framebuffer 1860 * formats. 1861 * 1862 * The default GMRFB value is undefined. Drivers must always send 1863 * this command at least once before performing any blit from the 1864 * GMRFB. 1865 * 1866 * Availability: 1867 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1868 */ 1869 1870 typedef 1871 #include "vmware_pack_begin.h" 1872 struct { 1873 SVGAGuestPtr ptr; 1874 uint32 bytesPerLine; 1875 SVGAGMRImageFormat format; 1876 } 1877 #include "vmware_pack_end.h" 1878 SVGAFifoCmdDefineGMRFB; 1879 1880 1881 /* 1882 * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- 1883 * 1884 * This is a guest-to-host blit. It performs a DMA operation to 1885 * copy a rectangular region of pixels from the current GMRFB to 1886 * a ScreenObject. 1887 * 1888 * The destination coordinate may be specified relative to a 1889 * screen's origin. The provided screen ID must be valid. 1890 * 1891 * The SVGA device is guaranteed to finish reading from the GMRFB 1892 * by the time any subsequent FENCE commands are reached. 1893 * 1894 * This command consumes an annotation. See the 1895 * SVGA_CMD_ANNOTATION_* commands for details. 1896 * 1897 * Availability: 1898 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1899 */ 1900 1901 typedef 1902 #include "vmware_pack_begin.h" 1903 struct { 1904 SVGASignedPoint srcOrigin; 1905 SVGASignedRect destRect; 1906 uint32 destScreenId; 1907 } 1908 #include "vmware_pack_end.h" 1909 SVGAFifoCmdBlitGMRFBToScreen; 1910 1911 1912 /* 1913 * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- 1914 * 1915 * This is a host-to-guest blit. It performs a DMA operation to 1916 * copy a rectangular region of pixels from a single ScreenObject 1917 * back to the current GMRFB. 1918 * 1919 * The source coordinate is specified relative to a screen's 1920 * origin. The provided screen ID must be valid. If any parameters 1921 * are invalid, the resulting pixel values are undefined. 1922 * 1923 * The SVGA device is guaranteed to finish writing to the GMRFB by 1924 * the time any subsequent FENCE commands are reached. 1925 * 1926 * Availability: 1927 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1928 */ 1929 1930 typedef 1931 #include "vmware_pack_begin.h" 1932 struct { 1933 SVGASignedPoint destOrigin; 1934 SVGASignedRect srcRect; 1935 uint32 srcScreenId; 1936 } 1937 #include "vmware_pack_end.h" 1938 SVGAFifoCmdBlitScreenToGMRFB; 1939 1940 1941 /* 1942 * SVGA_CMD_ANNOTATION_FILL -- 1943 * 1944 * The annotation commands have been deprecated, should not be used 1945 * by new drivers. They used to provide performance hints to the SVGA 1946 * device about the content of screen updates, but newer SVGA devices 1947 * ignore these. 1948 * 1949 * Availability: 1950 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1951 */ 1952 1953 typedef 1954 #include "vmware_pack_begin.h" 1955 struct { 1956 SVGAColorBGRX color; 1957 } 1958 #include "vmware_pack_end.h" 1959 SVGAFifoCmdAnnotationFill; 1960 1961 1962 /* 1963 * SVGA_CMD_ANNOTATION_COPY -- 1964 * 1965 * The annotation commands have been deprecated, should not be used 1966 * by new drivers. They used to provide performance hints to the SVGA 1967 * device about the content of screen updates, but newer SVGA devices 1968 * ignore these. 1969 * 1970 * Availability: 1971 * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2 1972 */ 1973 1974 typedef 1975 #include "vmware_pack_begin.h" 1976 struct { 1977 SVGASignedPoint srcOrigin; 1978 uint32 srcScreenId; 1979 } 1980 #include "vmware_pack_end.h" 1981 SVGAFifoCmdAnnotationCopy; 1982 1983 1984 /* 1985 * SVGA_CMD_DEFINE_GMR2 -- 1986 * 1987 * Define guest memory region v2. See the description of GMRs above. 1988 * 1989 * Availability: 1990 * SVGA_CAP_GMR2 1991 */ 1992 1993 typedef 1994 #include "vmware_pack_begin.h" 1995 struct { 1996 uint32 gmrId; 1997 uint32 numPages; 1998 } 1999 #include "vmware_pack_end.h" 2000 SVGAFifoCmdDefineGMR2; 2001 2002 2003 /* 2004 * SVGA_CMD_REMAP_GMR2 -- 2005 * 2006 * Remap guest memory region v2. See the description of GMRs above. 2007 * 2008 * This command allows guest to modify a portion of an existing GMR by 2009 * invalidating it or reassigning it to different guest physical pages. 2010 * The pages are identified by physical page number (PPN). The pages 2011 * are assumed to be pinned and valid for DMA operations. 2012 * 2013 * Description of command flags: 2014 * 2015 * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR. 2016 * The PPN list must not overlap with the remap region (this can be 2017 * handled trivially by referencing a separate GMR). If flag is 2018 * disabled, PPN list is appended to SVGARemapGMR command. 2019 * 2020 * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise 2021 * it is in PPN32 format. 2022 * 2023 * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry. 2024 * A single PPN can be used to invalidate a portion of a GMR or 2025 * map it to to a single guest scratch page. 2026 * 2027 * Availability: 2028 * SVGA_CAP_GMR2 2029 */ 2030 2031 typedef enum { 2032 SVGA_REMAP_GMR2_PPN32 = 0, 2033 SVGA_REMAP_GMR2_VIA_GMR = (1 << 0), 2034 SVGA_REMAP_GMR2_PPN64 = (1 << 1), 2035 SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2), 2036 } SVGARemapGMR2Flags; 2037 2038 typedef 2039 #include "vmware_pack_begin.h" 2040 struct { 2041 uint32 gmrId; 2042 SVGARemapGMR2Flags flags; 2043 uint32 offsetPages; /* offset in pages to begin remap */ 2044 uint32 numPages; /* number of pages to remap */ 2045 /* 2046 * Followed by additional data depending on SVGARemapGMR2Flags. 2047 * 2048 * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows. 2049 * Otherwise an array of page descriptors in PPN32 or PPN64 format 2050 * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag 2051 * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry. 2052 */ 2053 } 2054 #include "vmware_pack_end.h" 2055 SVGAFifoCmdRemapGMR2; 2056 2057 2058 /* 2059 * Size of SVGA device memory such as frame buffer and FIFO. 2060 */ 2061 #define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */ 2062 #define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024) 2063 #define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024) 2064 #define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024) 2065 #define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024) 2066 #define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024) 2067 #define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024) 2068 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024) 2069 2070 #define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */ 2071 2072 #if defined(VMX86_SERVER) 2073 #define SVGA_VRAM_SIZE (4 * 1024 * 1024) 2074 #define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024) 2075 #define SVGA_FIFO_SIZE (256 * 1024) 2076 #define SVGA_FIFO_SIZE_3D (516 * 1024) 2077 #define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024) 2078 #define SVGA_AUTODETECT_DEFAULT FALSE 2079 #else 2080 #define SVGA_VRAM_SIZE (16 * 1024 * 1024) 2081 #define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE 2082 #define SVGA_FIFO_SIZE (2 * 1024 * 1024) 2083 #define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE 2084 #define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024) 2085 #define SVGA_AUTODETECT_DEFAULT TRUE 2086 #endif 2087 2088 #define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024) 2089 #define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024) 2090 2091 #endif 2092