1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Microchip KSZ8795 register definitions 4 * 5 * Copyright (c) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #ifndef __KSZ8795_REG_H 10 #define __KSZ8795_REG_H 11 12 #define KS_PORT_M 0x1F 13 14 #define KS_PRIO_M 0x3 15 #define KS_PRIO_S 2 16 17 #define SW_REVISION_M 0x0E 18 #define SW_REVISION_S 1 19 20 #define KSZ8863_REG_SW_RESET 0x43 21 22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4) 23 #define KSZ8863_PCS_RESET BIT(0) 24 25 #define KSZ88X3_REG_FVID_AND_HOST_MODE 0xC6 26 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3) 27 28 #define REG_SW_CTRL_0 0x02 29 30 #define SW_NEW_BACKOFF BIT(7) 31 #define SW_GLOBAL_RESET BIT(6) 32 #define SW_FLUSH_DYN_MAC_TABLE BIT(5) 33 #define SW_FLUSH_STA_MAC_TABLE BIT(4) 34 #define SW_LINK_AUTO_AGING BIT(0) 35 36 #define REG_SW_CTRL_1 0x03 37 38 #define SW_HUGE_PACKET BIT(6) 39 #define SW_TX_FLOW_CTRL_DISABLE BIT(5) 40 #define SW_RX_FLOW_CTRL_DISABLE BIT(4) 41 #define SW_CHECK_LENGTH BIT(3) 42 #define SW_AGING_ENABLE BIT(2) 43 #define SW_FAST_AGING BIT(1) 44 #define SW_AGGR_BACKOFF BIT(0) 45 46 #define REG_SW_CTRL_2 0x04 47 48 #define UNICAST_VLAN_BOUNDARY BIT(7) 49 #define SW_BACK_PRESSURE BIT(5) 50 #define FAIR_FLOW_CTRL BIT(4) 51 #define NO_EXC_COLLISION_DROP BIT(3) 52 #define SW_LEGAL_PACKET_DISABLE BIT(1) 53 54 #define KSZ8863_HUGE_PACKET_ENABLE BIT(2) 55 #define KSZ8863_LEGAL_PACKET_ENABLE BIT(1) 56 57 #define REG_SW_CTRL_3 0x05 58 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) 59 60 #define SW_VLAN_ENABLE BIT(7) 61 #define SW_IGMP_SNOOP BIT(6) 62 #define SW_MIRROR_RX_TX BIT(0) 63 64 #define REG_SW_CTRL_4 0x06 65 66 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) 67 #define SW_HALF_DUPLEX BIT(6) 68 #define SW_FLOW_CTRL BIT(5) 69 #define SW_10_MBIT BIT(4) 70 #define SW_REPLACE_VID BIT(3) 71 72 #define REG_SW_CTRL_5 0x07 73 74 #define REG_SW_CTRL_6 0x08 75 76 #define SW_MIB_COUNTER_FLUSH BIT(7) 77 #define SW_MIB_COUNTER_FREEZE BIT(6) 78 #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M 79 80 #define REG_SW_CTRL_9 0x0B 81 82 #define SPI_CLK_125_MHZ 0x80 83 #define SPI_CLK_62_5_MHZ 0x40 84 #define SPI_CLK_31_25_MHZ 0x00 85 86 #define SW_LED_MODE_M 0x3 87 #define SW_LED_MODE_S 4 88 #define SW_LED_LINK_ACT_SPEED 0 89 #define SW_LED_LINK_ACT 1 90 #define SW_LED_LINK_ACT_DUPLEX 2 91 #define SW_LED_LINK_DUPLEX 3 92 93 #define REG_SW_CTRL_10 0x0C 94 95 #define SW_PASS_PAUSE BIT(0) 96 97 #define REG_SW_CTRL_11 0x0D 98 99 #define REG_POWER_MANAGEMENT_1 0x0E 100 101 #define SW_PLL_POWER_DOWN BIT(5) 102 #define SW_POWER_MANAGEMENT_MODE_M 0x3 103 #define SW_POWER_MANAGEMENT_MODE_S 3 104 #define SW_POWER_NORMAL 0 105 #define SW_ENERGY_DETECTION 1 106 #define SW_SOFTWARE_POWER_DOWN 2 107 108 #define REG_POWER_MANAGEMENT_2 0x0F 109 110 #define REG_PORT_1_CTRL_0 0x10 111 #define REG_PORT_2_CTRL_0 0x20 112 #define REG_PORT_3_CTRL_0 0x30 113 #define REG_PORT_4_CTRL_0 0x40 114 #define REG_PORT_5_CTRL_0 0x50 115 116 #define PORT_BROADCAST_STORM BIT(7) 117 #define PORT_DIFFSERV_ENABLE BIT(6) 118 #define PORT_802_1P_ENABLE BIT(5) 119 #define PORT_BASED_PRIO_S 3 120 #define PORT_BASED_PRIO_M KS_PRIO_M 121 #define PORT_BASED_PRIO_0 0 122 #define PORT_BASED_PRIO_1 1 123 #define PORT_BASED_PRIO_2 2 124 #define PORT_BASED_PRIO_3 3 125 #define PORT_INSERT_TAG BIT(2) 126 #define PORT_REMOVE_TAG BIT(1) 127 #define KSZ8795_PORT_2QUEUE_SPLIT_EN BIT(0) 128 #define KSZ8873_PORT_4QUEUE_SPLIT_EN BIT(0) 129 130 #define REG_PORT_1_CTRL_1 0x11 131 #define REG_PORT_2_CTRL_1 0x21 132 #define REG_PORT_3_CTRL_1 0x31 133 #define REG_PORT_4_CTRL_1 0x41 134 #define REG_PORT_5_CTRL_1 0x51 135 136 #define PORT_MIRROR_SNIFFER BIT(7) 137 #define PORT_MIRROR_RX BIT(6) 138 #define PORT_MIRROR_TX BIT(5) 139 #define PORT_VLAN_MEMBERSHIP KS_PORT_M 140 141 #define REG_PORT_1_CTRL_2 0x12 142 #define REG_PORT_2_CTRL_2 0x22 143 #define REG_PORT_3_CTRL_2 0x32 144 #define REG_PORT_4_CTRL_2 0x42 145 #define REG_PORT_5_CTRL_2 0x52 146 147 #define KSZ8873_PORT_2QUEUE_SPLIT_EN BIT(7) 148 #define PORT_INGRESS_FILTER BIT(6) 149 #define PORT_DISCARD_NON_VID BIT(5) 150 #define PORT_FORCE_FLOW_CTRL BIT(4) 151 #define PORT_BACK_PRESSURE BIT(3) 152 153 #define REG_PORT_1_CTRL_3 0x13 154 #define REG_PORT_2_CTRL_3 0x23 155 #define REG_PORT_3_CTRL_3 0x33 156 #define REG_PORT_4_CTRL_3 0x43 157 #define REG_PORT_5_CTRL_3 0x53 158 #define REG_PORT_1_CTRL_4 0x14 159 #define REG_PORT_2_CTRL_4 0x24 160 #define REG_PORT_3_CTRL_4 0x34 161 #define REG_PORT_4_CTRL_4 0x44 162 #define REG_PORT_5_CTRL_4 0x54 163 164 #define PORT_DEFAULT_VID 0x0001 165 166 #define REG_PORT_1_CTRL_5 0x15 167 #define REG_PORT_2_CTRL_5 0x25 168 #define REG_PORT_3_CTRL_5 0x35 169 #define REG_PORT_4_CTRL_5 0x45 170 #define REG_PORT_5_CTRL_5 0x55 171 172 #define PORT_ACL_ENABLE BIT(2) 173 #define PORT_AUTHEN_MODE 0x3 174 #define PORT_AUTHEN_PASS 0 175 #define PORT_AUTHEN_BLOCK 1 176 #define PORT_AUTHEN_TRAP 2 177 178 #define REG_PORT_5_CTRL_6 0x56 179 180 #define PORT_MII_INTERNAL_CLOCK BIT(7) 181 #define PORT_GMII_MAC_MODE BIT(2) 182 183 #define REG_PORT_1_CTRL_7 0x17 184 #define REG_PORT_2_CTRL_7 0x27 185 #define REG_PORT_3_CTRL_7 0x37 186 #define REG_PORT_4_CTRL_7 0x47 187 188 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) 189 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) 190 #define PORT_AUTO_NEG_100BTX_FD BIT(3) 191 #define PORT_AUTO_NEG_100BTX BIT(2) 192 #define PORT_AUTO_NEG_10BT_FD BIT(1) 193 #define PORT_AUTO_NEG_10BT BIT(0) 194 195 #define REG_PORT_1_STATUS_0 0x18 196 #define REG_PORT_2_STATUS_0 0x28 197 #define REG_PORT_3_STATUS_0 0x38 198 #define REG_PORT_4_STATUS_0 0x48 199 200 /* For KSZ8765. */ 201 #define PORT_REMOTE_ASYM_PAUSE BIT(5) 202 #define PORT_REMOTE_SYM_PAUSE BIT(4) 203 #define PORT_REMOTE_100BTX_FD BIT(3) 204 #define PORT_REMOTE_100BTX BIT(2) 205 #define PORT_REMOTE_10BT_FD BIT(1) 206 #define PORT_REMOTE_10BT BIT(0) 207 208 #define REG_PORT_1_STATUS_1 0x19 209 #define REG_PORT_2_STATUS_1 0x29 210 #define REG_PORT_3_STATUS_1 0x39 211 #define REG_PORT_4_STATUS_1 0x49 212 213 #define PORT_HP_MDIX BIT(7) 214 #define PORT_REVERSED_POLARITY BIT(5) 215 #define PORT_TX_FLOW_CTRL BIT(4) 216 #define PORT_RX_FLOW_CTRL BIT(3) 217 #define PORT_STAT_SPEED_100MBIT BIT(2) 218 #define PORT_STAT_FULL_DUPLEX BIT(1) 219 220 #define PORT_REMOTE_FAULT BIT(0) 221 222 #define REG_PORT_1_LINK_MD_CTRL 0x1A 223 #define REG_PORT_2_LINK_MD_CTRL 0x2A 224 #define REG_PORT_3_LINK_MD_CTRL 0x3A 225 #define REG_PORT_4_LINK_MD_CTRL 0x4A 226 227 #define PORT_CABLE_10M_SHORT BIT(7) 228 #define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5) 229 #define PORT_CABLE_DIAG_RESULT_S 5 230 #define PORT_CABLE_STAT_NORMAL 0 231 #define PORT_CABLE_STAT_OPEN 1 232 #define PORT_CABLE_STAT_SHORT 2 233 #define PORT_CABLE_STAT_FAILED 3 234 #define PORT_START_CABLE_DIAG BIT(4) 235 #define PORT_FORCE_LINK BIT(3) 236 #define PORT_POWER_SAVING BIT(2) 237 #define PORT_PHY_REMOTE_LOOPBACK BIT(1) 238 #define PORT_CABLE_FAULT_COUNTER_H 0x01 239 240 #define REG_PORT_1_LINK_MD_RESULT 0x1B 241 #define REG_PORT_2_LINK_MD_RESULT 0x2B 242 #define REG_PORT_3_LINK_MD_RESULT 0x3B 243 #define REG_PORT_4_LINK_MD_RESULT 0x4B 244 245 #define PORT_CABLE_FAULT_COUNTER_L 0xFF 246 #define PORT_CABLE_FAULT_COUNTER 0x1FF 247 248 #define REG_PORT_1_CTRL_9 0x1C 249 #define REG_PORT_2_CTRL_9 0x2C 250 #define REG_PORT_3_CTRL_9 0x3C 251 #define REG_PORT_4_CTRL_9 0x4C 252 253 #define PORT_AUTO_NEG_ENABLE BIT(7) 254 #define PORT_AUTO_NEG_DISABLE BIT(7) 255 #define PORT_FORCE_100_MBIT BIT(6) 256 #define PORT_FORCE_FULL_DUPLEX BIT(5) 257 258 #define REG_PORT_1_CTRL_10 0x1D 259 #define REG_PORT_2_CTRL_10 0x2D 260 #define REG_PORT_3_CTRL_10 0x3D 261 #define REG_PORT_4_CTRL_10 0x4D 262 263 #define PORT_LED_OFF BIT(7) 264 #define PORT_TX_DISABLE BIT(6) 265 #define PORT_AUTO_NEG_RESTART BIT(5) 266 #define PORT_POWER_DOWN BIT(3) 267 #define PORT_AUTO_MDIX_DISABLE BIT(2) 268 #define PORT_FORCE_MDIX BIT(1) 269 #define PORT_MAC_LOOPBACK BIT(0) 270 #define KSZ8873_PORT_PHY_LOOPBACK BIT(0) 271 272 #define REG_PORT_1_STATUS_2 0x1E 273 #define REG_PORT_2_STATUS_2 0x2E 274 #define REG_PORT_3_STATUS_2 0x3E 275 #define REG_PORT_4_STATUS_2 0x4E 276 277 #define PORT_MDIX_STATUS BIT(7) 278 #define PORT_AUTO_NEG_COMPLETE BIT(6) 279 #define PORT_STAT_LINK_GOOD BIT(5) 280 281 #define REG_PORT_1_STATUS_3 0x1F 282 #define REG_PORT_2_STATUS_3 0x2F 283 #define REG_PORT_3_STATUS_3 0x3F 284 #define REG_PORT_4_STATUS_3 0x4F 285 286 #define PORT_PHY_LOOPBACK BIT(7) 287 #define PORT_PHY_ISOLATE BIT(5) 288 #define PORT_PHY_SOFT_RESET BIT(4) 289 #define PORT_PHY_FORCE_LINK BIT(3) 290 #define PORT_PHY_MODE_M 0x7 291 #define PHY_MODE_IN_AUTO_NEG 1 292 #define PHY_MODE_10BT_HALF 2 293 #define PHY_MODE_100BT_HALF 3 294 #define PHY_MODE_10BT_FULL 5 295 #define PHY_MODE_100BT_FULL 6 296 #define PHY_MODE_ISOLDATE 7 297 298 #define REG_PORT_CTRL_0 0x00 299 #define REG_PORT_CTRL_1 0x01 300 #define REG_PORT_CTRL_2 0x02 301 #define REG_PORT_CTRL_VID 0x03 302 303 #define REG_PORT_CTRL_5 0x05 304 305 #define REG_PORT_STATUS_1 0x09 306 #define REG_PORT_LINK_MD_CTRL 0x0A 307 #define REG_PORT_LINK_MD_RESULT 0x0B 308 #define REG_PORT_CTRL_9 0x0C 309 #define REG_PORT_CTRL_10 0x0D 310 #define REG_PORT_STATUS_3 0x0F 311 312 #define REG_PORT_CTRL_12 0xA0 313 #define REG_PORT_CTRL_13 0xA1 314 #define REG_PORT_RATE_CTRL_3 0xA2 315 #define REG_PORT_RATE_CTRL_2 0xA3 316 #define REG_PORT_RATE_CTRL_1 0xA4 317 #define REG_PORT_RATE_CTRL_0 0xA5 318 #define REG_PORT_RATE_LIMIT 0xA6 319 #define REG_PORT_IN_RATE_0 0xA7 320 #define REG_PORT_IN_RATE_1 0xA8 321 #define REG_PORT_IN_RATE_2 0xA9 322 #define REG_PORT_IN_RATE_3 0xAA 323 #define REG_PORT_OUT_RATE_0 0xAB 324 #define REG_PORT_OUT_RATE_1 0xAC 325 #define REG_PORT_OUT_RATE_2 0xAD 326 #define REG_PORT_OUT_RATE_3 0xAE 327 328 #define PORT_CTRL_ADDR(port, addr) \ 329 ((addr) + REG_PORT_1_CTRL_0 + (port) * \ 330 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0)) 331 332 #define TABLE_EXT_SELECT_S 5 333 #define TABLE_EEE_V 1 334 #define TABLE_ACL_V 2 335 #define TABLE_PME_V 4 336 #define TABLE_LINK_MD_V 5 337 #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) 338 #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) 339 #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) 340 #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) 341 #define TABLE_READ BIT(4) 342 #define TABLE_SELECT_S 2 343 #define TABLE_STATIC_MAC_V 0 344 #define TABLE_VLAN_V 1 345 #define TABLE_DYNAMIC_MAC_V 2 346 #define TABLE_MIB_V 3 347 #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S) 348 #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S) 349 #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S) 350 #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S) 351 352 #define REG_IND_CTRL_1 0x6F 353 354 #define TABLE_ENTRY_MASK 0x03FF 355 #define TABLE_EXT_ENTRY_MASK 0x0FFF 356 357 #define REG_IND_DATA_5 0x73 358 #define REG_IND_DATA_2 0x76 359 #define REG_IND_DATA_1 0x77 360 #define REG_IND_DATA_0 0x78 361 362 #define REG_IND_DATA_PME_EEE_ACL 0xA0 363 364 #define REG_INT_STATUS 0x7C 365 #define REG_INT_ENABLE 0x7D 366 367 #define INT_PME BIT(4) 368 369 #define REG_ACL_INT_STATUS 0x7E 370 #define REG_ACL_INT_ENABLE 0x7F 371 372 #define INT_PORT_5 BIT(4) 373 #define INT_PORT_4 BIT(3) 374 #define INT_PORT_3 BIT(2) 375 #define INT_PORT_2 BIT(1) 376 #define INT_PORT_1 BIT(0) 377 378 #define INT_PORT_ALL \ 379 (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1) 380 381 #define REG_SW_CTRL_12 0x80 382 #define REG_SW_CTRL_13 0x81 383 384 #define SWITCH_802_1P_MASK 3 385 #define SWITCH_802_1P_BASE 3 386 #define SWITCH_802_1P_SHIFT 2 387 388 #define SW_802_1P_MAP_M KS_PRIO_M 389 #define SW_802_1P_MAP_S KS_PRIO_S 390 391 #define REG_SWITCH_CTRL_14 0x82 392 393 #define SW_PRIO_MAPPING_M KS_PRIO_M 394 #define SW_PRIO_MAPPING_S 6 395 #define SW_PRIO_MAP_3_HI 0 396 #define SW_PRIO_MAP_2_HI 2 397 #define SW_PRIO_MAP_0_LO 3 398 399 #define REG_SW_CTRL_15 0x83 400 #define REG_SW_CTRL_16 0x84 401 #define REG_SW_CTRL_17 0x85 402 #define REG_SW_CTRL_18 0x86 403 404 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) 405 406 #define REG_SW_UNK_UCAST_CTRL 0x83 407 #define REG_SW_UNK_MCAST_CTRL 0x84 408 #define REG_SW_UNK_VID_CTRL 0x85 409 #define REG_SW_UNK_IP_MCAST_CTRL 0x86 410 411 #define SW_UNK_FWD_ENABLE BIT(5) 412 #define SW_UNK_FWD_MAP KS_PORT_M 413 414 #define REG_SW_CTRL_19 0x87 415 416 #define SW_IN_RATE_LIMIT_PERIOD_M 0x3 417 #define SW_IN_RATE_LIMIT_PERIOD_S 4 418 #define SW_IN_RATE_LIMIT_16_MS 0 419 #define SW_IN_RATE_LIMIT_64_MS 1 420 #define SW_IN_RATE_LIMIT_256_MS 2 421 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 422 #define SW_INS_TAG_ENABLE BIT(2) 423 424 #define REG_TOS_PRIO_CTRL_0 0x90 425 #define REG_TOS_PRIO_CTRL_1 0x91 426 #define REG_TOS_PRIO_CTRL_2 0x92 427 #define REG_TOS_PRIO_CTRL_3 0x93 428 #define REG_TOS_PRIO_CTRL_4 0x94 429 #define REG_TOS_PRIO_CTRL_5 0x95 430 #define REG_TOS_PRIO_CTRL_6 0x96 431 #define REG_TOS_PRIO_CTRL_7 0x97 432 #define REG_TOS_PRIO_CTRL_8 0x98 433 #define REG_TOS_PRIO_CTRL_9 0x99 434 #define REG_TOS_PRIO_CTRL_10 0x9A 435 #define REG_TOS_PRIO_CTRL_11 0x9B 436 #define REG_TOS_PRIO_CTRL_12 0x9C 437 #define REG_TOS_PRIO_CTRL_13 0x9D 438 #define REG_TOS_PRIO_CTRL_14 0x9E 439 #define REG_TOS_PRIO_CTRL_15 0x9F 440 441 #define TOS_PRIO_M KS_PRIO_M 442 #define TOS_PRIO_S KS_PRIO_S 443 444 #define REG_SW_CTRL_21 0xA4 445 446 #define SW_IPV6_MLD_OPTION BIT(3) 447 #define SW_IPV6_MLD_SNOOP BIT(2) 448 449 #define REG_PORT_1_CTRL_12 0xB0 450 #define REG_PORT_2_CTRL_12 0xC0 451 #define REG_PORT_3_CTRL_12 0xD0 452 #define REG_PORT_4_CTRL_12 0xE0 453 #define REG_PORT_5_CTRL_12 0xF0 454 455 #define PORT_PASS_ALL BIT(6) 456 #define PORT_INS_TAG_FOR_PORT_5_S 3 457 #define PORT_INS_TAG_FOR_PORT_5 BIT(3) 458 #define PORT_INS_TAG_FOR_PORT_4 BIT(2) 459 #define PORT_INS_TAG_FOR_PORT_3 BIT(1) 460 #define PORT_INS_TAG_FOR_PORT_2 BIT(0) 461 462 #define REG_PORT_1_CTRL_13 0xB1 463 #define REG_PORT_2_CTRL_13 0xC1 464 #define REG_PORT_3_CTRL_13 0xD1 465 #define REG_PORT_4_CTRL_13 0xE1 466 #define REG_PORT_5_CTRL_13 0xF1 467 468 #define KSZ8795_PORT_4QUEUE_SPLIT_EN BIT(1) 469 #define PORT_DROP_TAG BIT(0) 470 471 #define REG_PORT_1_CTRL_14 0xB2 472 #define REG_PORT_2_CTRL_14 0xC2 473 #define REG_PORT_3_CTRL_14 0xD2 474 #define REG_PORT_4_CTRL_14 0xE2 475 #define REG_PORT_5_CTRL_14 0xF2 476 #define REG_PORT_1_CTRL_15 0xB3 477 #define REG_PORT_2_CTRL_15 0xC3 478 #define REG_PORT_3_CTRL_15 0xD3 479 #define REG_PORT_4_CTRL_15 0xE3 480 #define REG_PORT_5_CTRL_15 0xF3 481 #define REG_PORT_1_CTRL_16 0xB4 482 #define REG_PORT_2_CTRL_16 0xC4 483 #define REG_PORT_3_CTRL_16 0xD4 484 #define REG_PORT_4_CTRL_16 0xE4 485 #define REG_PORT_5_CTRL_16 0xF4 486 #define REG_PORT_1_CTRL_17 0xB5 487 #define REG_PORT_2_CTRL_17 0xC5 488 #define REG_PORT_3_CTRL_17 0xD5 489 #define REG_PORT_4_CTRL_17 0xE5 490 #define REG_PORT_5_CTRL_17 0xF5 491 492 #define REG_PORT_1_RATE_CTRL_3 0xB2 493 #define REG_PORT_1_RATE_CTRL_2 0xB3 494 #define REG_PORT_1_RATE_CTRL_1 0xB4 495 #define REG_PORT_1_RATE_CTRL_0 0xB5 496 #define REG_PORT_2_RATE_CTRL_3 0xC2 497 #define REG_PORT_2_RATE_CTRL_2 0xC3 498 #define REG_PORT_2_RATE_CTRL_1 0xC4 499 #define REG_PORT_2_RATE_CTRL_0 0xC5 500 #define REG_PORT_3_RATE_CTRL_3 0xD2 501 #define REG_PORT_3_RATE_CTRL_2 0xD3 502 #define REG_PORT_3_RATE_CTRL_1 0xD4 503 #define REG_PORT_3_RATE_CTRL_0 0xD5 504 #define REG_PORT_4_RATE_CTRL_3 0xE2 505 #define REG_PORT_4_RATE_CTRL_2 0xE3 506 #define REG_PORT_4_RATE_CTRL_1 0xE4 507 #define REG_PORT_4_RATE_CTRL_0 0xE5 508 #define REG_PORT_5_RATE_CTRL_3 0xF2 509 #define REG_PORT_5_RATE_CTRL_2 0xF3 510 #define REG_PORT_5_RATE_CTRL_1 0xF4 511 #define REG_PORT_5_RATE_CTRL_0 0xF5 512 513 #define RATE_CTRL_ENABLE BIT(7) 514 #define RATE_RATIO_M (BIT(7) - 1) 515 516 #define PORT_OUT_RATE_ENABLE BIT(7) 517 518 #define REG_PORT_1_RATE_LIMIT 0xB6 519 #define REG_PORT_2_RATE_LIMIT 0xC6 520 #define REG_PORT_3_RATE_LIMIT 0xD6 521 #define REG_PORT_4_RATE_LIMIT 0xE6 522 #define REG_PORT_5_RATE_LIMIT 0xF6 523 524 #define PORT_IN_PORT_BASED_S 6 525 #define PORT_RATE_PACKET_BASED_S 5 526 #define PORT_IN_FLOW_CTRL_S 4 527 #define PORT_IN_LIMIT_MODE_M 0x3 528 #define PORT_IN_LIMIT_MODE_S 2 529 #define PORT_COUNT_IFG_S 1 530 #define PORT_COUNT_PREAMBLE_S 0 531 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) 532 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) 533 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) 534 #define PORT_IN_ALL 0 535 #define PORT_IN_UNICAST 1 536 #define PORT_IN_MULTICAST 2 537 #define PORT_IN_BROADCAST 3 538 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) 539 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) 540 541 #define REG_PORT_1_IN_RATE_0 0xB7 542 #define REG_PORT_2_IN_RATE_0 0xC7 543 #define REG_PORT_3_IN_RATE_0 0xD7 544 #define REG_PORT_4_IN_RATE_0 0xE7 545 #define REG_PORT_5_IN_RATE_0 0xF7 546 #define REG_PORT_1_IN_RATE_1 0xB8 547 #define REG_PORT_2_IN_RATE_1 0xC8 548 #define REG_PORT_3_IN_RATE_1 0xD8 549 #define REG_PORT_4_IN_RATE_1 0xE8 550 #define REG_PORT_5_IN_RATE_1 0xF8 551 #define REG_PORT_1_IN_RATE_2 0xB9 552 #define REG_PORT_2_IN_RATE_2 0xC9 553 #define REG_PORT_3_IN_RATE_2 0xD9 554 #define REG_PORT_4_IN_RATE_2 0xE9 555 #define REG_PORT_5_IN_RATE_2 0xF9 556 #define REG_PORT_1_IN_RATE_3 0xBA 557 #define REG_PORT_2_IN_RATE_3 0xCA 558 #define REG_PORT_3_IN_RATE_3 0xDA 559 #define REG_PORT_4_IN_RATE_3 0xEA 560 #define REG_PORT_5_IN_RATE_3 0xFA 561 562 #define PORT_IN_RATE_ENABLE BIT(7) 563 #define PORT_RATE_LIMIT_M (BIT(7) - 1) 564 565 #define REG_PORT_1_OUT_RATE_0 0xBB 566 #define REG_PORT_2_OUT_RATE_0 0xCB 567 #define REG_PORT_3_OUT_RATE_0 0xDB 568 #define REG_PORT_4_OUT_RATE_0 0xEB 569 #define REG_PORT_5_OUT_RATE_0 0xFB 570 #define REG_PORT_1_OUT_RATE_1 0xBC 571 #define REG_PORT_2_OUT_RATE_1 0xCC 572 #define REG_PORT_3_OUT_RATE_1 0xDC 573 #define REG_PORT_4_OUT_RATE_1 0xEC 574 #define REG_PORT_5_OUT_RATE_1 0xFC 575 #define REG_PORT_1_OUT_RATE_2 0xBD 576 #define REG_PORT_2_OUT_RATE_2 0xCD 577 #define REG_PORT_3_OUT_RATE_2 0xDD 578 #define REG_PORT_4_OUT_RATE_2 0xED 579 #define REG_PORT_5_OUT_RATE_2 0xFD 580 #define REG_PORT_1_OUT_RATE_3 0xBE 581 #define REG_PORT_2_OUT_RATE_3 0xCE 582 #define REG_PORT_3_OUT_RATE_3 0xDE 583 #define REG_PORT_4_OUT_RATE_3 0xEE 584 #define REG_PORT_5_OUT_RATE_3 0xFE 585 586 /* 88x3 specific */ 587 588 #define REG_SW_INSERT_SRC_PVID 0xC2 589 590 /* PME */ 591 592 #define SW_PME_OUTPUT_ENABLE BIT(1) 593 #define SW_PME_ACTIVE_HIGH BIT(0) 594 595 #define PORT_MAGIC_PACKET_DETECT BIT(2) 596 #define PORT_LINK_UP_DETECT BIT(1) 597 #define PORT_ENERGY_DETECT BIT(0) 598 599 /* ACL */ 600 601 #define ACL_FIRST_RULE_M 0xF 602 603 #define ACL_MODE_M 0x3 604 #define ACL_MODE_S 4 605 #define ACL_MODE_DISABLE 0 606 #define ACL_MODE_LAYER_2 1 607 #define ACL_MODE_LAYER_3 2 608 #define ACL_MODE_LAYER_4 3 609 #define ACL_ENABLE_M 0x3 610 #define ACL_ENABLE_S 2 611 #define ACL_ENABLE_2_COUNT 0 612 #define ACL_ENABLE_2_TYPE 1 613 #define ACL_ENABLE_2_MAC 2 614 #define ACL_ENABLE_2_BOTH 3 615 #define ACL_ENABLE_3_IP 1 616 #define ACL_ENABLE_3_SRC_DST_COMP 2 617 #define ACL_ENABLE_4_PROTOCOL 0 618 #define ACL_ENABLE_4_TCP_PORT_COMP 1 619 #define ACL_ENABLE_4_UDP_PORT_COMP 2 620 #define ACL_ENABLE_4_TCP_SEQN_COMP 3 621 #define ACL_SRC BIT(1) 622 #define ACL_EQUAL BIT(0) 623 624 #define ACL_MAX_PORT 0xFFFF 625 626 #define ACL_MIN_PORT 0xFFFF 627 #define ACL_IP_ADDR 0xFFFFFFFF 628 #define ACL_TCP_SEQNUM 0xFFFFFFFF 629 630 #define ACL_RESERVED 0xF8 631 #define ACL_PORT_MODE_M 0x3 632 #define ACL_PORT_MODE_S 1 633 #define ACL_PORT_MODE_DISABLE 0 634 #define ACL_PORT_MODE_EITHER 1 635 #define ACL_PORT_MODE_IN_RANGE 2 636 #define ACL_PORT_MODE_OUT_OF_RANGE 3 637 638 #define ACL_TCP_FLAG_ENABLE BIT(0) 639 640 #define ACL_TCP_FLAG_M 0xFF 641 642 #define ACL_TCP_FLAG 0xFF 643 #define ACL_ETH_TYPE 0xFFFF 644 #define ACL_IP_M 0xFFFFFFFF 645 646 #define ACL_PRIO_MODE_M 0x3 647 #define ACL_PRIO_MODE_S 6 648 #define ACL_PRIO_MODE_DISABLE 0 649 #define ACL_PRIO_MODE_HIGHER 1 650 #define ACL_PRIO_MODE_LOWER 2 651 #define ACL_PRIO_MODE_REPLACE 3 652 #define ACL_PRIO_M 0x7 653 #define ACL_PRIO_S 3 654 #define ACL_VLAN_PRIO_REPLACE BIT(2) 655 #define ACL_VLAN_PRIO_M 0x7 656 #define ACL_VLAN_PRIO_HI_M 0x3 657 658 #define ACL_VLAN_PRIO_LO_M 0x8 659 #define ACL_VLAN_PRIO_S 7 660 #define ACL_MAP_MODE_M 0x3 661 #define ACL_MAP_MODE_S 5 662 #define ACL_MAP_MODE_DISABLE 0 663 #define ACL_MAP_MODE_OR 1 664 #define ACL_MAP_MODE_AND 2 665 #define ACL_MAP_MODE_REPLACE 3 666 #define ACL_MAP_PORT_M 0x1F 667 668 #define ACL_CNT_M (BIT(11) - 1) 669 #define ACL_CNT_S 5 670 #define ACL_MSEC_UNIT BIT(4) 671 #define ACL_INTR_MODE BIT(3) 672 673 #define REG_PORT_ACL_BYTE_EN_MSB 0x10 674 675 #define ACL_BYTE_EN_MSB_M 0x3F 676 677 #define REG_PORT_ACL_BYTE_EN_LSB 0x11 678 679 #define ACL_ACTION_START 0xA 680 #define ACL_ACTION_LEN 2 681 #define ACL_INTR_CNT_START 0xB 682 #define ACL_RULESET_START 0xC 683 #define ACL_RULESET_LEN 2 684 #define ACL_TABLE_LEN 14 685 686 #define ACL_ACTION_ENABLE 0x000C 687 #define ACL_MATCH_ENABLE 0x1FF0 688 #define ACL_RULESET_ENABLE 0x2003 689 #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF) 690 #define ACL_MODE_ENABLE (0x10 << 8) 691 692 #define REG_PORT_ACL_CTRL_0 0x12 693 694 #define PORT_ACL_WRITE_DONE BIT(6) 695 #define PORT_ACL_READ_DONE BIT(5) 696 #define PORT_ACL_WRITE BIT(4) 697 #define PORT_ACL_INDEX_M 0xF 698 699 #define REG_PORT_ACL_CTRL_1 0x13 700 701 #define PORT_ACL_FORCE_DLR_MISS BIT(0) 702 703 #define KSZ8795_ID_HI 0x0022 704 #define KSZ8795_ID_LO 0x1550 705 #define KSZ8863_ID_LO 0x1430 706 707 #define KSZ8795_SW_ID 0x8795 708 709 #define PHY_REG_LINK_MD 0x1D 710 711 #define PHY_START_CABLE_DIAG BIT(15) 712 #define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13) 713 #define PHY_CABLE_DIAG_RESULT 0x6000 714 #define PHY_CABLE_STAT_NORMAL 0x0000 715 #define PHY_CABLE_STAT_OPEN 0x2000 716 #define PHY_CABLE_STAT_SHORT 0x4000 717 #define PHY_CABLE_STAT_FAILED 0x6000 718 #define PHY_CABLE_10M_SHORT BIT(12) 719 #define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0) 720 721 #define PHY_REG_PHY_CTRL 0x1F 722 723 #define PHY_MODE_M 0x7 724 #define PHY_MODE_S 8 725 #define PHY_STAT_REVERSED_POLARITY BIT(5) 726 #define PHY_STAT_MDIX BIT(4) 727 #define PHY_FORCE_LINK BIT(3) 728 #define PHY_POWER_SAVING_ENABLE BIT(2) 729 #define PHY_REMOTE_LOOPBACK BIT(1) 730 731 /* Chip resource */ 732 733 #define PRIO_QUEUES 4 734 735 #define KS_PRIO_IN_REG 4 736 737 #define MIB_COUNTER_NUM 0x20 738 739 /* Common names used by other drivers */ 740 741 #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0 742 #define P_PRIO_CTRL REG_PORT_CTRL_0 743 #define P_TAG_CTRL REG_PORT_CTRL_0 744 #define P_MIRROR_CTRL REG_PORT_CTRL_1 745 #define P_802_1P_CTRL REG_PORT_CTRL_2 746 #define P_PASS_ALL_CTRL REG_PORT_CTRL_12 747 #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 748 #define P_DROP_TAG_CTRL REG_PORT_CTRL_13 749 #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT 750 751 #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12 752 #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID 753 754 #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0 755 #define S_LINK_AGING_CTRL REG_SW_CTRL_0 756 #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1 757 #define S_MIRROR_CTRL REG_SW_CTRL_3 758 #define S_REPLACE_VID_CTRL REG_SW_CTRL_4 759 #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 760 #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 761 #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 762 #define S_IPV6_MLD_CTRL REG_SW_CTRL_21 763 764 #define IND_ACC_TABLE(table) ((table) << 8) 765 766 /* */ 767 #define REG_IND_EEE_GLOB2_LO 0x34 768 #define REG_IND_EEE_GLOB2_HI 0x35 769 770 /** 771 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 772 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF 773 * MIB_PACKET_DROPPED 00-00000000-0000FFFF 774 * MIB_COUNTER_VALID 00-00000020-00000000 775 * MIB_COUNTER_OVERFLOW 00-00000040-00000000 776 */ 777 778 #define MIB_COUNTER_VALUE 0x3FFFFFFF 779 780 #define KSZ8795_MIB_TOTAL_RX_0 0x100 781 #define KSZ8795_MIB_TOTAL_TX_0 0x101 782 #define KSZ8795_MIB_TOTAL_RX_1 0x104 783 #define KSZ8795_MIB_TOTAL_TX_1 0x105 784 785 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100 786 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105 787 788 #define MIB_PACKET_DROPPED 0x0000FFFF 789 790 #define MIB_TOTAL_BYTES_H 0x0000000F 791 792 #define TAIL_TAG_OVERRIDE BIT(6) 793 #define TAIL_TAG_LOOKUP BIT(7) 794 795 #define FID_ENTRIES 128 796 #define KSZ8_DYN_MAC_ENTRIES 1024 797 798 #endif 799