1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 11 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 12 13 #include "llvm/MC/MCInstrDesc.h" 14 15 namespace llvm { 16 17 // This needs to be kept in sync with the field bits in SIRegisterClass. 18 enum SIRCFlags : uint8_t { 19 RegTupleAlignUnitsWidth = 2, 20 HasVGPRBit = RegTupleAlignUnitsWidth, 21 HasAGPRBit, 22 HasSGPRbit, 23 24 HasVGPR = 1 << HasVGPRBit, 25 HasAGPR = 1 << HasAGPRBit, 26 HasSGPR = 1 << HasSGPRbit, 27 28 RegTupleAlignUnitsMask = (1 << RegTupleAlignUnitsWidth) - 1, 29 RegKindMask = (HasVGPR | HasAGPR | HasSGPR) 30 }; // enum SIRCFlagsr 31 32 namespace SIEncodingFamily { 33 // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td 34 // and the columns of the getMCOpcodeGen table. 35 enum { 36 SI = 0, 37 VI = 1, 38 SDWA = 2, 39 SDWA9 = 3, 40 GFX80 = 4, 41 GFX9 = 5, 42 GFX10 = 6, 43 SDWA10 = 7, 44 GFX90A = 8, 45 GFX940 = 9, 46 GFX11 = 10, 47 GFX12 = 11, 48 }; 49 } 50 51 namespace SIInstrFlags { 52 // This needs to be kept in sync with the field bits in InstSI. 53 enum : uint64_t { 54 // Low bits - basic encoding information. 55 SALU = 1 << 0, 56 VALU = 1 << 1, 57 58 // SALU instruction formats. 59 SOP1 = 1 << 2, 60 SOP2 = 1 << 3, 61 SOPC = 1 << 4, 62 SOPK = 1 << 5, 63 SOPP = 1 << 6, 64 65 // VALU instruction formats. 66 VOP1 = 1 << 7, 67 VOP2 = 1 << 8, 68 VOPC = 1 << 9, 69 70 // TODO: Should this be spilt into VOP3 a and b? 71 VOP3 = 1 << 10, 72 VOP3P = 1 << 12, 73 74 VINTRP = 1 << 13, 75 SDWA = 1 << 14, 76 DPP = 1 << 15, 77 TRANS = 1 << 16, 78 79 // Memory instruction formats. 80 MUBUF = 1 << 17, 81 MTBUF = 1 << 18, 82 SMRD = 1 << 19, 83 MIMG = 1 << 20, 84 VIMAGE = 1 << 21, 85 VSAMPLE = 1 << 22, 86 EXP = 1 << 23, 87 FLAT = 1 << 24, 88 DS = 1 << 25, 89 90 // Pseudo instruction formats. 91 VGPRSpill = 1 << 26, 92 SGPRSpill = 1 << 27, 93 94 // LDSDIR instruction format. 95 LDSDIR = 1 << 28, 96 97 // VINTERP instruction format. 98 VINTERP = 1 << 29, 99 100 // High bits - other information. 101 VM_CNT = UINT64_C(1) << 32, 102 EXP_CNT = UINT64_C(1) << 33, 103 LGKM_CNT = UINT64_C(1) << 34, 104 105 WQM = UINT64_C(1) << 35, 106 DisableWQM = UINT64_C(1) << 36, 107 Gather4 = UINT64_C(1) << 37, 108 SOPK_ZEXT = UINT64_C(1) << 38, 109 SCALAR_STORE = UINT64_C(1) << 39, 110 FIXED_SIZE = UINT64_C(1) << 40, 111 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 112 VOP3_OPSEL = UINT64_C(1) << 42, 113 maybeAtomic = UINT64_C(1) << 43, 114 renamedInGFX9 = UINT64_C(1) << 44, 115 116 // Is a clamp on FP type. 117 FPClamp = UINT64_C(1) << 45, 118 119 // Is an integer clamp 120 IntClamp = UINT64_C(1) << 46, 121 122 // Clamps lo component of register. 123 ClampLo = UINT64_C(1) << 47, 124 125 // Clamps hi component of register. 126 // ClampLo and ClampHi set for packed clamp. 127 ClampHi = UINT64_C(1) << 48, 128 129 // Is a packed VOP3P instruction. 130 IsPacked = UINT64_C(1) << 49, 131 132 // Is a D16 buffer instruction. 133 D16Buf = UINT64_C(1) << 50, 134 135 // FLAT instruction accesses FLAT_GLBL segment. 136 FlatGlobal = UINT64_C(1) << 51, 137 138 // Uses floating point double precision rounding mode 139 FPDPRounding = UINT64_C(1) << 52, 140 141 // Instruction is FP atomic. 142 FPAtomic = UINT64_C(1) << 53, 143 144 // Is a MFMA instruction. 145 IsMAI = UINT64_C(1) << 54, 146 147 // Is a DOT instruction. 148 IsDOT = UINT64_C(1) << 55, 149 150 // FLAT instruction accesses FLAT_SCRATCH segment. 151 FlatScratch = UINT64_C(1) << 56, 152 153 // Atomic without return. 154 IsAtomicNoRet = UINT64_C(1) << 57, 155 156 // Atomic with return. 157 IsAtomicRet = UINT64_C(1) << 58, 158 159 // Is a WMMA instruction. 160 IsWMMA = UINT64_C(1) << 59, 161 162 // Whether tied sources will be read. 163 TiedSourceNotRead = UINT64_C(1) << 60, 164 165 // Is never uniform. 166 IsNeverUniform = UINT64_C(1) << 61, 167 168 // ds_gws_* instructions. 169 GWS = UINT64_C(1) << 62, 170 171 // Is a SWMMAC instruction. 172 IsSWMMAC = UINT64_C(1) << 63, 173 }; 174 175 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 176 // The result is true if any of these tests are true. 177 enum ClassFlags : unsigned { 178 S_NAN = 1 << 0, // Signaling NaN 179 Q_NAN = 1 << 1, // Quiet NaN 180 N_INFINITY = 1 << 2, // Negative infinity 181 N_NORMAL = 1 << 3, // Negative normal 182 N_SUBNORMAL = 1 << 4, // Negative subnormal 183 N_ZERO = 1 << 5, // Negative zero 184 P_ZERO = 1 << 6, // Positive zero 185 P_SUBNORMAL = 1 << 7, // Positive subnormal 186 P_NORMAL = 1 << 8, // Positive normal 187 P_INFINITY = 1 << 9 // Positive infinity 188 }; 189 } 190 191 namespace AMDGPU { 192 enum OperandType : unsigned { 193 /// Operands with register or 32-bit immediate 194 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 195 OPERAND_REG_IMM_INT64, 196 OPERAND_REG_IMM_INT16, 197 OPERAND_REG_IMM_FP32, 198 OPERAND_REG_IMM_FP64, 199 OPERAND_REG_IMM_FP16, 200 OPERAND_REG_IMM_FP16_DEFERRED, 201 OPERAND_REG_IMM_FP32_DEFERRED, 202 OPERAND_REG_IMM_V2FP16, 203 OPERAND_REG_IMM_V2INT16, 204 OPERAND_REG_IMM_V2INT32, 205 OPERAND_REG_IMM_V2FP32, 206 207 /// Operands with register or inline constant 208 OPERAND_REG_INLINE_C_INT16, 209 OPERAND_REG_INLINE_C_INT32, 210 OPERAND_REG_INLINE_C_INT64, 211 OPERAND_REG_INLINE_C_FP16, 212 OPERAND_REG_INLINE_C_FP32, 213 OPERAND_REG_INLINE_C_FP64, 214 OPERAND_REG_INLINE_C_V2INT16, 215 OPERAND_REG_INLINE_C_V2FP16, 216 OPERAND_REG_INLINE_C_V2INT32, 217 OPERAND_REG_INLINE_C_V2FP32, 218 219 // Operand for split barrier inline constant 220 OPERAND_INLINE_SPLIT_BARRIER_INT32, 221 222 /// Operand with 32-bit immediate that uses the constant bus. 223 OPERAND_KIMM32, 224 OPERAND_KIMM16, 225 226 /// Operands with an AccVGPR register or inline constant 227 OPERAND_REG_INLINE_AC_INT16, 228 OPERAND_REG_INLINE_AC_INT32, 229 OPERAND_REG_INLINE_AC_FP16, 230 OPERAND_REG_INLINE_AC_FP32, 231 OPERAND_REG_INLINE_AC_FP64, 232 OPERAND_REG_INLINE_AC_V2INT16, 233 OPERAND_REG_INLINE_AC_V2FP16, 234 OPERAND_REG_INLINE_AC_V2INT32, 235 OPERAND_REG_INLINE_AC_V2FP32, 236 237 // Operand for source modifiers for VOP instructions 238 OPERAND_INPUT_MODS, 239 240 // Operand for SDWA instructions 241 OPERAND_SDWA_VOPC_DST, 242 243 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 244 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, 245 246 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 247 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32, 248 249 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 250 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32, 251 252 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 253 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 254 255 OPERAND_KIMM_FIRST = OPERAND_KIMM32, 256 OPERAND_KIMM_LAST = OPERAND_KIMM16 257 258 }; 259 } 260 261 // Input operand modifiers bit-masks 262 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 263 namespace SISrcMods { 264 enum : unsigned { 265 NONE = 0, 266 NEG = 1 << 0, // Floating-point negate modifier 267 ABS = 1 << 1, // Floating-point absolute modifier 268 SEXT = 1 << 0, // Integer sign-extend modifier 269 NEG_HI = ABS, // Floating-point negate high packed component modifier. 270 OP_SEL_0 = 1 << 2, 271 OP_SEL_1 = 1 << 3, 272 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 273 }; 274 } 275 276 namespace SIOutMods { 277 enum : unsigned { 278 NONE = 0, 279 MUL2 = 1, 280 MUL4 = 2, 281 DIV2 = 3 282 }; 283 } 284 285 namespace AMDGPU { 286 namespace VGPRIndexMode { 287 288 enum Id : unsigned { // id of symbolic names 289 ID_SRC0 = 0, 290 ID_SRC1, 291 ID_SRC2, 292 ID_DST, 293 294 ID_MIN = ID_SRC0, 295 ID_MAX = ID_DST 296 }; 297 298 enum EncBits : unsigned { 299 OFF = 0, 300 SRC0_ENABLE = 1 << ID_SRC0, 301 SRC1_ENABLE = 1 << ID_SRC1, 302 SRC2_ENABLE = 1 << ID_SRC2, 303 DST_ENABLE = 1 << ID_DST, 304 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 305 UNDEF = 0xFFFF 306 }; 307 308 } // namespace VGPRIndexMode 309 } // namespace AMDGPU 310 311 namespace AMDGPUAsmVariants { 312 enum : unsigned { 313 DEFAULT = 0, 314 VOP3 = 1, 315 SDWA = 2, 316 SDWA9 = 3, 317 DPP = 4, 318 VOP3_DPP = 5 319 }; 320 } // namespace AMDGPUAsmVariants 321 322 namespace AMDGPU { 323 namespace EncValues { // Encoding values of enum9/8/7 operands 324 325 enum : unsigned { 326 SGPR_MIN = 0, 327 SGPR_MAX_SI = 101, 328 SGPR_MAX_GFX10 = 105, 329 TTMP_VI_MIN = 112, 330 TTMP_VI_MAX = 123, 331 TTMP_GFX9PLUS_MIN = 108, 332 TTMP_GFX9PLUS_MAX = 123, 333 INLINE_INTEGER_C_MIN = 128, 334 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 335 INLINE_INTEGER_C_MAX = 208, 336 INLINE_FLOATING_C_MIN = 240, 337 INLINE_FLOATING_C_MAX = 248, 338 LITERAL_CONST = 255, 339 VGPR_MIN = 256, 340 VGPR_MAX = 511, 341 IS_VGPR = 256, // Indicates VGPR or AGPR 342 }; 343 344 } // namespace EncValues 345 346 // Register codes as defined in the TableGen's HWEncoding field. 347 namespace HWEncoding { 348 enum : unsigned { 349 REG_IDX_MASK = 0xff, 350 IS_VGPR_OR_AGPR = 1 << 8, 351 IS_HI = 1 << 9, // High 16-bit register. 352 }; 353 } // namespace HWEncoding 354 355 namespace CPol { 356 357 enum CPol { 358 GLC = 1, 359 SLC = 2, 360 DLC = 4, 361 SCC = 16, 362 SC0 = GLC, 363 SC1 = SCC, 364 NT = SLC, 365 ALL_pregfx12 = GLC | SLC | DLC | SCC, 366 SWZ_pregfx12 = 8, 367 368 // Below are GFX12+ cache policy bits 369 370 // Temporal hint 371 TH = 0x7, // All TH bits 372 TH_RT = 0, // regular 373 TH_NT = 1, // non-temporal 374 TH_HT = 2, // high-temporal 375 TH_LU = 3, // last use 376 TH_RT_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL) 377 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL) 378 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL) 379 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL) 380 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL) 381 TH_BYPASS = 3, // only to be used with scope = 3 382 383 TH_RESERVED = 7, // unused value for load insts 384 385 // Bits of TH for atomics 386 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning 387 TH_ATOMIC_NT = SLC, // Non-temporal vs regular 388 TH_ATOMIC_CASCADE = 4, // Cascading vs regular 389 390 // Scope 391 SCOPE = 0x3 << 3, // All Scope bits 392 SCOPE_CU = 0 << 3, 393 SCOPE_SE = 1 << 3, 394 SCOPE_DEV = 2 << 3, 395 SCOPE_SYS = 3 << 3, 396 397 SWZ = 1 << 6, // Swizzle bit 398 399 ALL = TH | SCOPE, 400 401 // Helper bits 402 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy 403 TH_TYPE_STORE = 1 << 8, // TH_STORE policy 404 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy 405 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not 406 407 // Volatile (used to preserve/signal operation volatility for buffer 408 // operations not a real instruction bit) 409 VOLATILE = 1 << 31, 410 }; 411 412 } // namespace CPol 413 414 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 415 416 enum Id { // Message ID, width(4) [3:0]. 417 ID_INTERRUPT = 1, 418 419 ID_GS_PreGFX11 = 2, // replaced in GFX11 420 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11 421 422 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11 423 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11 424 425 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11 426 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12 427 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12 428 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11 429 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 430 ID_GS_ALLOC_REQ = 9, // added in GFX9 431 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11 432 ID_GET_DDID = 11, // added in GFX10, removed in GFX11 433 ID_SYSMSG = 15, 434 435 ID_RTN_GET_DOORBELL = 128, 436 ID_RTN_GET_DDID = 129, 437 ID_RTN_GET_TMA = 130, 438 ID_RTN_GET_REALTIME = 131, 439 ID_RTN_SAVE_WAVE = 132, 440 ID_RTN_GET_TBA = 133, 441 ID_RTN_GET_SE_AID_ID = 134, 442 443 ID_MASK_PreGFX11_ = 0xF, 444 ID_MASK_GFX11Plus_ = 0xFF 445 }; 446 447 enum Op { // Both GS and SYS operation IDs. 448 OP_UNKNOWN_ = -1, 449 OP_SHIFT_ = 4, 450 OP_NONE_ = 0, 451 // Bits used for operation encoding 452 OP_WIDTH_ = 3, 453 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 454 // GS operations are encoded in bits 5:4 455 OP_GS_NOP = 0, 456 OP_GS_CUT = 1, 457 OP_GS_EMIT = 2, 458 OP_GS_EMIT_CUT = 3, 459 OP_GS_LAST_, 460 OP_GS_FIRST_ = OP_GS_NOP, 461 // SYS operations are encoded in bits 6:4 462 OP_SYS_ECC_ERR_INTERRUPT = 1, 463 OP_SYS_REG_RD = 2, 464 OP_SYS_HOST_TRAP_ACK = 3, 465 OP_SYS_TTRACE_PC = 4, 466 OP_SYS_LAST_, 467 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 468 }; 469 470 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 471 STREAM_ID_NONE_ = 0, 472 STREAM_ID_DEFAULT_ = 0, 473 STREAM_ID_LAST_ = 4, 474 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 475 STREAM_ID_SHIFT_ = 8, 476 STREAM_ID_WIDTH_= 2, 477 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 478 }; 479 480 } // namespace SendMsg 481 482 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 483 484 enum Id { // HwRegCode, (6) [5:0] 485 ID_MODE = 1, 486 ID_STATUS = 2, 487 ID_TRAPSTS = 3, 488 ID_HW_ID = 4, 489 ID_GPR_ALLOC = 5, 490 ID_LDS_ALLOC = 6, 491 ID_IB_STS = 7, 492 ID_PERF_SNAPSHOT_DATA_gfx12 = 10, 493 ID_PERF_SNAPSHOT_PC_LO_gfx12 = 11, 494 ID_PERF_SNAPSHOT_PC_HI_gfx12 = 12, 495 ID_MEM_BASES = 15, 496 ID_TBA_LO = 16, 497 ID_TBA_HI = 17, 498 ID_TMA_LO = 18, 499 ID_TMA_HI = 19, 500 ID_FLAT_SCR_LO = 20, 501 ID_FLAT_SCR_HI = 21, 502 ID_XNACK_MASK = 22, 503 ID_HW_ID1 = 23, 504 ID_HW_ID2 = 24, 505 ID_POPS_PACKER = 25, 506 ID_PERF_SNAPSHOT_DATA_gfx11 = 27, 507 ID_SHADER_CYCLES = 29, 508 ID_SHADER_CYCLES_HI = 30, 509 ID_DVGPR_ALLOC_LO = 31, 510 ID_DVGPR_ALLOC_HI = 32, 511 512 // Register numbers reused in GFX11 513 ID_PERF_SNAPSHOT_PC_LO_gfx11 = 18, 514 ID_PERF_SNAPSHOT_PC_HI_gfx11 = 19, 515 516 // Register numbers reused in GFX12+ 517 ID_STATE_PRIV = 4, 518 ID_PERF_SNAPSHOT_DATA1 = 15, 519 ID_PERF_SNAPSHOT_DATA2 = 16, 520 ID_EXCP_FLAG_PRIV = 17, 521 ID_EXCP_FLAG_USER = 18, 522 ID_TRAP_CTRL = 19, 523 524 // GFX940 specific registers 525 ID_XCC_ID = 20, 526 ID_SQ_PERF_SNAPSHOT_DATA = 21, 527 ID_SQ_PERF_SNAPSHOT_DATA1 = 22, 528 ID_SQ_PERF_SNAPSHOT_PC_LO = 23, 529 ID_SQ_PERF_SNAPSHOT_PC_HI = 24, 530 531 ID_SHIFT_ = 0, 532 ID_WIDTH_ = 6, 533 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 534 }; 535 536 enum Offset : unsigned { // Offset, (5) [10:6] 537 OFFSET_DEFAULT_ = 0, 538 OFFSET_SHIFT_ = 6, 539 OFFSET_WIDTH_ = 5, 540 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 541 542 OFFSET_MEM_VIOL = 8, 543 }; 544 545 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 546 WIDTH_M1_DEFAULT_ = 31, 547 WIDTH_M1_SHIFT_ = 11, 548 WIDTH_M1_WIDTH_ = 5, 549 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 550 }; 551 552 // Some values from WidthMinusOne mapped into Width domain. 553 enum Width : unsigned { 554 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 555 }; 556 557 enum ModeRegisterMasks : uint32_t { 558 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 559 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 560 DX10_CLAMP_MASK = 1 << 8, 561 IEEE_MODE_MASK = 1 << 9, 562 LOD_CLAMP_MASK = 1 << 10, 563 DEBUG_MASK = 1 << 11, 564 565 // EXCP_EN fields. 566 EXCP_EN_INVALID_MASK = 1 << 12, 567 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 568 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 569 EXCP_EN_OVERFLOW_MASK = 1 << 15, 570 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 571 EXCP_EN_INEXACT_MASK = 1 << 17, 572 EXCP_EN_INT_DIV0_MASK = 1 << 18, 573 574 GPR_IDX_EN_MASK = 1 << 27, 575 VSKIP_MASK = 1 << 28, 576 CSP_MASK = 0x7u << 29 // Bits 29..31 577 }; 578 579 } // namespace Hwreg 580 581 namespace MTBUFFormat { 582 583 enum DataFormat : int64_t { 584 DFMT_INVALID = 0, 585 DFMT_8, 586 DFMT_16, 587 DFMT_8_8, 588 DFMT_32, 589 DFMT_16_16, 590 DFMT_10_11_11, 591 DFMT_11_11_10, 592 DFMT_10_10_10_2, 593 DFMT_2_10_10_10, 594 DFMT_8_8_8_8, 595 DFMT_32_32, 596 DFMT_16_16_16_16, 597 DFMT_32_32_32, 598 DFMT_32_32_32_32, 599 DFMT_RESERVED_15, 600 601 DFMT_MIN = DFMT_INVALID, 602 DFMT_MAX = DFMT_RESERVED_15, 603 604 DFMT_UNDEF = -1, 605 DFMT_DEFAULT = DFMT_8, 606 607 DFMT_SHIFT = 0, 608 DFMT_MASK = 0xF 609 }; 610 611 enum NumFormat : int64_t { 612 NFMT_UNORM = 0, 613 NFMT_SNORM, 614 NFMT_USCALED, 615 NFMT_SSCALED, 616 NFMT_UINT, 617 NFMT_SINT, 618 NFMT_RESERVED_6, // VI and GFX9 619 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 620 NFMT_FLOAT, 621 622 NFMT_MIN = NFMT_UNORM, 623 NFMT_MAX = NFMT_FLOAT, 624 625 NFMT_UNDEF = -1, 626 NFMT_DEFAULT = NFMT_UNORM, 627 628 NFMT_SHIFT = 4, 629 NFMT_MASK = 7 630 }; 631 632 enum MergedFormat : int64_t { 633 DFMT_NFMT_UNDEF = -1, 634 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 635 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 636 637 638 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 639 640 DFMT_NFMT_MAX = DFMT_NFMT_MASK 641 }; 642 643 enum UnifiedFormatCommon : int64_t { 644 UFMT_MAX = 127, 645 UFMT_UNDEF = -1, 646 UFMT_DEFAULT = 1 647 }; 648 649 } // namespace MTBUFFormat 650 651 namespace UfmtGFX10 { 652 enum UnifiedFormat : int64_t { 653 UFMT_INVALID = 0, 654 655 UFMT_8_UNORM, 656 UFMT_8_SNORM, 657 UFMT_8_USCALED, 658 UFMT_8_SSCALED, 659 UFMT_8_UINT, 660 UFMT_8_SINT, 661 662 UFMT_16_UNORM, 663 UFMT_16_SNORM, 664 UFMT_16_USCALED, 665 UFMT_16_SSCALED, 666 UFMT_16_UINT, 667 UFMT_16_SINT, 668 UFMT_16_FLOAT, 669 670 UFMT_8_8_UNORM, 671 UFMT_8_8_SNORM, 672 UFMT_8_8_USCALED, 673 UFMT_8_8_SSCALED, 674 UFMT_8_8_UINT, 675 UFMT_8_8_SINT, 676 677 UFMT_32_UINT, 678 UFMT_32_SINT, 679 UFMT_32_FLOAT, 680 681 UFMT_16_16_UNORM, 682 UFMT_16_16_SNORM, 683 UFMT_16_16_USCALED, 684 UFMT_16_16_SSCALED, 685 UFMT_16_16_UINT, 686 UFMT_16_16_SINT, 687 UFMT_16_16_FLOAT, 688 689 UFMT_10_11_11_UNORM, 690 UFMT_10_11_11_SNORM, 691 UFMT_10_11_11_USCALED, 692 UFMT_10_11_11_SSCALED, 693 UFMT_10_11_11_UINT, 694 UFMT_10_11_11_SINT, 695 UFMT_10_11_11_FLOAT, 696 697 UFMT_11_11_10_UNORM, 698 UFMT_11_11_10_SNORM, 699 UFMT_11_11_10_USCALED, 700 UFMT_11_11_10_SSCALED, 701 UFMT_11_11_10_UINT, 702 UFMT_11_11_10_SINT, 703 UFMT_11_11_10_FLOAT, 704 705 UFMT_10_10_10_2_UNORM, 706 UFMT_10_10_10_2_SNORM, 707 UFMT_10_10_10_2_USCALED, 708 UFMT_10_10_10_2_SSCALED, 709 UFMT_10_10_10_2_UINT, 710 UFMT_10_10_10_2_SINT, 711 712 UFMT_2_10_10_10_UNORM, 713 UFMT_2_10_10_10_SNORM, 714 UFMT_2_10_10_10_USCALED, 715 UFMT_2_10_10_10_SSCALED, 716 UFMT_2_10_10_10_UINT, 717 UFMT_2_10_10_10_SINT, 718 719 UFMT_8_8_8_8_UNORM, 720 UFMT_8_8_8_8_SNORM, 721 UFMT_8_8_8_8_USCALED, 722 UFMT_8_8_8_8_SSCALED, 723 UFMT_8_8_8_8_UINT, 724 UFMT_8_8_8_8_SINT, 725 726 UFMT_32_32_UINT, 727 UFMT_32_32_SINT, 728 UFMT_32_32_FLOAT, 729 730 UFMT_16_16_16_16_UNORM, 731 UFMT_16_16_16_16_SNORM, 732 UFMT_16_16_16_16_USCALED, 733 UFMT_16_16_16_16_SSCALED, 734 UFMT_16_16_16_16_UINT, 735 UFMT_16_16_16_16_SINT, 736 UFMT_16_16_16_16_FLOAT, 737 738 UFMT_32_32_32_UINT, 739 UFMT_32_32_32_SINT, 740 UFMT_32_32_32_FLOAT, 741 UFMT_32_32_32_32_UINT, 742 UFMT_32_32_32_32_SINT, 743 UFMT_32_32_32_32_FLOAT, 744 745 UFMT_FIRST = UFMT_INVALID, 746 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 747 }; 748 749 } // namespace UfmtGFX10 750 751 namespace UfmtGFX11 { 752 enum UnifiedFormat : int64_t { 753 UFMT_INVALID = 0, 754 755 UFMT_8_UNORM, 756 UFMT_8_SNORM, 757 UFMT_8_USCALED, 758 UFMT_8_SSCALED, 759 UFMT_8_UINT, 760 UFMT_8_SINT, 761 762 UFMT_16_UNORM, 763 UFMT_16_SNORM, 764 UFMT_16_USCALED, 765 UFMT_16_SSCALED, 766 UFMT_16_UINT, 767 UFMT_16_SINT, 768 UFMT_16_FLOAT, 769 770 UFMT_8_8_UNORM, 771 UFMT_8_8_SNORM, 772 UFMT_8_8_USCALED, 773 UFMT_8_8_SSCALED, 774 UFMT_8_8_UINT, 775 UFMT_8_8_SINT, 776 777 UFMT_32_UINT, 778 UFMT_32_SINT, 779 UFMT_32_FLOAT, 780 781 UFMT_16_16_UNORM, 782 UFMT_16_16_SNORM, 783 UFMT_16_16_USCALED, 784 UFMT_16_16_SSCALED, 785 UFMT_16_16_UINT, 786 UFMT_16_16_SINT, 787 UFMT_16_16_FLOAT, 788 789 UFMT_10_11_11_FLOAT, 790 791 UFMT_11_11_10_FLOAT, 792 793 UFMT_10_10_10_2_UNORM, 794 UFMT_10_10_10_2_SNORM, 795 UFMT_10_10_10_2_UINT, 796 UFMT_10_10_10_2_SINT, 797 798 UFMT_2_10_10_10_UNORM, 799 UFMT_2_10_10_10_SNORM, 800 UFMT_2_10_10_10_USCALED, 801 UFMT_2_10_10_10_SSCALED, 802 UFMT_2_10_10_10_UINT, 803 UFMT_2_10_10_10_SINT, 804 805 UFMT_8_8_8_8_UNORM, 806 UFMT_8_8_8_8_SNORM, 807 UFMT_8_8_8_8_USCALED, 808 UFMT_8_8_8_8_SSCALED, 809 UFMT_8_8_8_8_UINT, 810 UFMT_8_8_8_8_SINT, 811 812 UFMT_32_32_UINT, 813 UFMT_32_32_SINT, 814 UFMT_32_32_FLOAT, 815 816 UFMT_16_16_16_16_UNORM, 817 UFMT_16_16_16_16_SNORM, 818 UFMT_16_16_16_16_USCALED, 819 UFMT_16_16_16_16_SSCALED, 820 UFMT_16_16_16_16_UINT, 821 UFMT_16_16_16_16_SINT, 822 UFMT_16_16_16_16_FLOAT, 823 824 UFMT_32_32_32_UINT, 825 UFMT_32_32_32_SINT, 826 UFMT_32_32_32_FLOAT, 827 UFMT_32_32_32_32_UINT, 828 UFMT_32_32_32_32_SINT, 829 UFMT_32_32_32_32_FLOAT, 830 831 UFMT_FIRST = UFMT_INVALID, 832 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 833 }; 834 835 } // namespace UfmtGFX11 836 837 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 838 839 enum Id : unsigned { // id of symbolic names 840 ID_QUAD_PERM = 0, 841 ID_BITMASK_PERM, 842 ID_SWAP, 843 ID_REVERSE, 844 ID_BROADCAST 845 }; 846 847 enum EncBits : unsigned { 848 849 // swizzle mode encodings 850 851 QUAD_PERM_ENC = 0x8000, 852 QUAD_PERM_ENC_MASK = 0xFF00, 853 854 BITMASK_PERM_ENC = 0x0000, 855 BITMASK_PERM_ENC_MASK = 0x8000, 856 857 // QUAD_PERM encodings 858 859 LANE_MASK = 0x3, 860 LANE_MAX = LANE_MASK, 861 LANE_SHIFT = 2, 862 LANE_NUM = 4, 863 864 // BITMASK_PERM encodings 865 866 BITMASK_MASK = 0x1F, 867 BITMASK_MAX = BITMASK_MASK, 868 BITMASK_WIDTH = 5, 869 870 BITMASK_AND_SHIFT = 0, 871 BITMASK_OR_SHIFT = 5, 872 BITMASK_XOR_SHIFT = 10 873 }; 874 875 } // namespace Swizzle 876 877 namespace SDWA { 878 879 enum SdwaSel : unsigned { 880 BYTE_0 = 0, 881 BYTE_1 = 1, 882 BYTE_2 = 2, 883 BYTE_3 = 3, 884 WORD_0 = 4, 885 WORD_1 = 5, 886 DWORD = 6, 887 }; 888 889 enum DstUnused : unsigned { 890 UNUSED_PAD = 0, 891 UNUSED_SEXT = 1, 892 UNUSED_PRESERVE = 2, 893 }; 894 895 enum SDWA9EncValues : unsigned { 896 SRC_SGPR_MASK = 0x100, 897 SRC_VGPR_MASK = 0xFF, 898 VOPC_DST_VCC_MASK = 0x80, 899 VOPC_DST_SGPR_MASK = 0x7F, 900 901 SRC_VGPR_MIN = 0, 902 SRC_VGPR_MAX = 255, 903 SRC_SGPR_MIN = 256, 904 SRC_SGPR_MAX_SI = 357, 905 SRC_SGPR_MAX_GFX10 = 361, 906 SRC_TTMP_MIN = 364, 907 SRC_TTMP_MAX = 379, 908 }; 909 910 } // namespace SDWA 911 912 namespace DPP { 913 914 // clang-format off 915 enum DppCtrl : unsigned { 916 QUAD_PERM_FIRST = 0, 917 QUAD_PERM_ID = 0xE4, // identity permutation 918 QUAD_PERM_LAST = 0xFF, 919 DPP_UNUSED1 = 0x100, 920 ROW_SHL0 = 0x100, 921 ROW_SHL_FIRST = 0x101, 922 ROW_SHL_LAST = 0x10F, 923 DPP_UNUSED2 = 0x110, 924 ROW_SHR0 = 0x110, 925 ROW_SHR_FIRST = 0x111, 926 ROW_SHR_LAST = 0x11F, 927 DPP_UNUSED3 = 0x120, 928 ROW_ROR0 = 0x120, 929 ROW_ROR_FIRST = 0x121, 930 ROW_ROR_LAST = 0x12F, 931 WAVE_SHL1 = 0x130, 932 DPP_UNUSED4_FIRST = 0x131, 933 DPP_UNUSED4_LAST = 0x133, 934 WAVE_ROL1 = 0x134, 935 DPP_UNUSED5_FIRST = 0x135, 936 DPP_UNUSED5_LAST = 0x137, 937 WAVE_SHR1 = 0x138, 938 DPP_UNUSED6_FIRST = 0x139, 939 DPP_UNUSED6_LAST = 0x13B, 940 WAVE_ROR1 = 0x13C, 941 DPP_UNUSED7_FIRST = 0x13D, 942 DPP_UNUSED7_LAST = 0x13F, 943 ROW_MIRROR = 0x140, 944 ROW_HALF_MIRROR = 0x141, 945 BCAST15 = 0x142, 946 BCAST31 = 0x143, 947 DPP_UNUSED8_FIRST = 0x144, 948 DPP_UNUSED8_LAST = 0x14F, 949 ROW_NEWBCAST_FIRST= 0x150, 950 ROW_NEWBCAST_LAST = 0x15F, 951 ROW_SHARE0 = 0x150, 952 ROW_SHARE_FIRST = 0x150, 953 ROW_SHARE_LAST = 0x15F, 954 ROW_XMASK0 = 0x160, 955 ROW_XMASK_FIRST = 0x160, 956 ROW_XMASK_LAST = 0x16F, 957 DPP_LAST = ROW_XMASK_LAST 958 }; 959 // clang-format on 960 961 enum DppFiMode { 962 DPP_FI_0 = 0, 963 DPP_FI_1 = 1, 964 DPP8_FI_0 = 0xE9, 965 DPP8_FI_1 = 0xEA, 966 }; 967 968 } // namespace DPP 969 970 namespace Exp { 971 972 enum Target : unsigned { 973 ET_MRT0 = 0, 974 ET_MRT7 = 7, 975 ET_MRTZ = 8, 976 ET_NULL = 9, // Pre-GFX11 977 ET_POS0 = 12, 978 ET_POS3 = 15, 979 ET_POS4 = 16, // GFX10+ 980 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 981 ET_PRIM = 20, // GFX10+ 982 ET_DUAL_SRC_BLEND0 = 21, // GFX11+ 983 ET_DUAL_SRC_BLEND1 = 22, // GFX11+ 984 ET_PARAM0 = 32, // Pre-GFX11 985 ET_PARAM31 = 63, // Pre-GFX11 986 987 ET_NULL_MAX_IDX = 0, 988 ET_MRTZ_MAX_IDX = 0, 989 ET_PRIM_MAX_IDX = 0, 990 ET_MRT_MAX_IDX = 7, 991 ET_POS_MAX_IDX = 4, 992 ET_DUAL_SRC_BLEND_MAX_IDX = 1, 993 ET_PARAM_MAX_IDX = 31, 994 995 ET_INVALID = 255, 996 }; 997 998 } // namespace Exp 999 1000 namespace VOP3PEncoding { 1001 1002 enum OpSel : uint64_t { 1003 OP_SEL_HI_0 = UINT64_C(1) << 59, 1004 OP_SEL_HI_1 = UINT64_C(1) << 60, 1005 OP_SEL_HI_2 = UINT64_C(1) << 14, 1006 }; 1007 1008 } // namespace VOP3PEncoding 1009 1010 namespace ImplicitArg { 1011 // Implicit kernel argument offset for code object version 5. 1012 enum Offset_COV5 : unsigned { 1013 HOSTCALL_PTR_OFFSET = 80, 1014 MULTIGRID_SYNC_ARG_OFFSET = 88, 1015 HEAP_PTR_OFFSET = 96, 1016 1017 DEFAULT_QUEUE_OFFSET = 104, 1018 COMPLETION_ACTION_OFFSET = 112, 1019 1020 PRIVATE_BASE_OFFSET = 192, 1021 SHARED_BASE_OFFSET = 196, 1022 QUEUE_PTR_OFFSET = 200, 1023 }; 1024 1025 } // namespace ImplicitArg 1026 1027 namespace VirtRegFlag { 1028 // Virtual register flags used for various target specific handlings during 1029 // codegen. 1030 enum Register_Flag : uint8_t { 1031 // Register operand in a whole-wave mode operation. 1032 WWM_REG = 1 << 0, 1033 }; 1034 1035 } // namespace VirtRegFlag 1036 1037 } // namespace AMDGPU 1038 1039 namespace AMDGPU { 1040 namespace Barrier { 1041 enum Type { TRAP = -2, WORKGROUP = -1 }; 1042 } // namespace Barrier 1043 } // namespace AMDGPU 1044 1045 // clang-format off 1046 1047 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 1048 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 1049 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 1050 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 1051 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 1052 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 1053 1054 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 1055 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 1056 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 1057 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 1058 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 1059 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 1060 1061 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 1062 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 1063 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 1064 #define C_00B228_WGP_MODE 0xF7FFFFFF 1065 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 1066 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 1067 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 1068 1069 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 1070 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 1071 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 1072 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 1073 #define C_00B428_WGP_MODE 0xFBFFFFFF 1074 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 1075 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 1076 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 1077 1078 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 1079 1080 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 1081 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 1082 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 1083 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 1084 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 1085 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 1086 #define C_00B84C_USER_SGPR 0xFFFFFFC1 1087 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 1088 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 1089 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 1090 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 1091 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 1092 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 1093 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 1094 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 1095 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 1096 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 1097 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 1098 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 1099 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 1100 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 1101 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 1102 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 1103 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 1104 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 1105 /* CIK */ 1106 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 1107 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 1108 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 1109 /* */ 1110 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 1111 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 1112 #define C_00B84C_LDS_SIZE 0xFF007FFF 1113 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 1114 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 1115 #define C_00B84C_EXCP_EN 1116 1117 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 1118 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 1119 1120 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 1121 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 1122 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 1123 #define C_00B848_VGPRS 0xFFFFFFC0 1124 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 1125 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 1126 #define C_00B848_SGPRS 0xFFFFFC3F 1127 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 1128 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 1129 #define C_00B848_PRIORITY 0xFFFFF3FF 1130 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 1131 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 1132 #define C_00B848_FLOAT_MODE 0xFFF00FFF 1133 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 1134 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 1135 #define C_00B848_PRIV 0xFFEFFFFF 1136 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 1137 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 1138 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 1139 #define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21) 1140 #define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1) 1141 #define C_00B848_RR_WG_MODE 0xFFDFFFFF 1142 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 1143 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 1144 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 1145 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 1146 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 1147 #define C_00B848_IEEE_MODE 0xFF7FFFFF 1148 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 1149 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 1150 #define C_00B848_WGP_MODE 0xDFFFFFFF 1151 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 1152 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 1153 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 1154 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 1155 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 1156 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 1157 1158 // Helpers for setting FLOAT_MODE 1159 #define FP_ROUND_ROUND_TO_NEAREST 0 1160 #define FP_ROUND_ROUND_TO_INF 1 1161 #define FP_ROUND_ROUND_TO_NEGINF 2 1162 #define FP_ROUND_ROUND_TO_ZERO 3 1163 1164 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 1165 // precision. 1166 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 1167 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 1168 1169 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 1170 #define FP_DENORM_FLUSH_OUT 1 1171 #define FP_DENORM_FLUSH_IN 2 1172 #define FP_DENORM_FLUSH_NONE 3 1173 1174 1175 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 1176 // precision. 1177 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 1178 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 1179 1180 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 1181 #define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1182 #define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) 1183 #define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) 1184 1185 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 1186 #define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12) 1187 #define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12) 1188 #define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12) 1189 1190 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 1191 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 1192 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 1193 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 1194 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 1195 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 1196 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 1197 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 1198 1199 #define R_SPILLED_SGPRS 0x4 1200 #define R_SPILLED_VGPRS 0x8 1201 1202 // clang-format on 1203 1204 } // End namespace llvm 1205 1206 #endif 1207