1# -*- coding: utf-8 -*- 2"""VISA VPP-4.3 constants (VPP-4.3.2 spec, section 3). 3 4Makes all "completion and error codes", "attribute values", "event type 5values", and "values and ranges" defined in the VISA specification VPP-4.3.2, 6section 3, available as variable values. 7 8The module exports the values under the original, all-uppercase names. 9 10This file is part of PyVISA. 11 12:copyright: 2014-2020 by PyVISA Authors, see AUTHORS for more details. 13:license: MIT, see LICENSE for more details. 14 15""" 16import enum 17import sys 18 19from typing_extensions import Literal 20 21is_64bits = sys.maxsize > 2 ** 32 22 23 24def _to_int(x: int) -> int: 25 """Convert a signed completion and error code to the proper value. 26 27 This function is necessary because the VISA specification is flawed: It defines 28 the VISA codes, which have a value less than zero, in their internal 32-bit 29 signed integer representation. However, this is positive. ctypes doesn't 30 care about that and (correctly) returns the negative value, which is left as 31 such by Python. 32 33 Parameters 34 ---------- 35 x : int 36 Value in 32-bit notation as listed in the VPP-4.3.2 specification 37 38 Returns 39 ------- 40 int 41 Properly signed value 42 43 """ 44 if x > 0x7FFFFFFF: 45 return int(x - 0x100000000) 46 else: 47 return int(x) 48 49 50# fmt: off 51 52# ====================================================================================== 53# --- VISA constants ------------------------------------------------------------------ 54# ====================================================================================== 55 56# Status codes : success 57VI_SUCCESS = _to_int(0x00000000) 58VI_SUCCESS_EVENT_EN = _to_int(0x3FFF0002) 59VI_SUCCESS_EVENT_DIS = _to_int(0x3FFF0003) 60VI_SUCCESS_QUEUE_EMPTY = _to_int(0x3FFF0004) 61VI_SUCCESS_TERM_CHAR = _to_int(0x3FFF0005) 62VI_SUCCESS_MAX_CNT = _to_int(0x3FFF0006) 63VI_SUCCESS_DEV_NPRESENT = _to_int(0x3FFF007D) 64VI_SUCCESS_TRIG_MAPPED = _to_int(0x3FFF007E) 65VI_SUCCESS_QUEUE_NEMPTY = _to_int(0x3FFF0080) 66VI_SUCCESS_NCHAIN = _to_int(0x3FFF0098) 67VI_SUCCESS_NESTED_SHARED = _to_int(0x3FFF0099) 68VI_SUCCESS_NESTED_EXCLUSIVE = _to_int(0x3FFF009A) 69VI_SUCCESS_SYNC = _to_int(0x3FFF009B) 70 71# Status codes : warning 72VI_WARN_QUEUE_OVERFLOW = _to_int(0x3FFF000C) 73VI_WARN_CONFIG_NLOADED = _to_int(0x3FFF0077) 74VI_WARN_NULL_OBJECT = _to_int(0x3FFF0082) 75VI_WARN_NSUP_ATTR_STATE = _to_int(0x3FFF0084) 76VI_WARN_UNKNOWN_STATUS = _to_int(0x3FFF0085) 77VI_WARN_NSUP_BUF = _to_int(0x3FFF0088) 78 79# The following one is a non-standard NI extension 80VI_WARN_EXT_FUNC_NIMPL = _to_int(0x3FFF00A9) 81 82# Status codes : errors 83VI_ERROR_SYSTEM_ERROR = _to_int(0xBFFF0000) 84VI_ERROR_INV_OBJECT = _to_int(0xBFFF000E) 85VI_ERROR_RSRC_LOCKED = _to_int(0xBFFF000F) 86VI_ERROR_INV_EXPR = _to_int(0xBFFF0010) 87VI_ERROR_RSRC_NFOUND = _to_int(0xBFFF0011) 88VI_ERROR_INV_RSRC_NAME = _to_int(0xBFFF0012) 89VI_ERROR_INV_ACC_MODE = _to_int(0xBFFF0013) 90VI_ERROR_TMO = _to_int(0xBFFF0015) 91VI_ERROR_CLOSING_FAILED = _to_int(0xBFFF0016) 92VI_ERROR_INV_DEGREE = _to_int(0xBFFF001B) 93VI_ERROR_INV_JOB_ID = _to_int(0xBFFF001C) 94VI_ERROR_NSUP_ATTR = _to_int(0xBFFF001D) 95VI_ERROR_NSUP_ATTR_STATE = _to_int(0xBFFF001E) 96VI_ERROR_ATTR_READONLY = _to_int(0xBFFF001F) 97VI_ERROR_INV_LOCK_TYPE = _to_int(0xBFFF0020) 98VI_ERROR_INV_ACCESS_KEY = _to_int(0xBFFF0021) 99VI_ERROR_INV_EVENT = _to_int(0xBFFF0026) 100VI_ERROR_INV_MECH = _to_int(0xBFFF0027) 101VI_ERROR_HNDLR_NINSTALLED = _to_int(0xBFFF0028) 102VI_ERROR_INV_HNDLR_REF = _to_int(0xBFFF0029) 103VI_ERROR_INV_CONTEXT = _to_int(0xBFFF002A) 104VI_ERROR_QUEUE_OVERFLOW = _to_int(0xBFFF002D) 105VI_ERROR_NENABLED = _to_int(0xBFFF002F) 106VI_ERROR_ABORT = _to_int(0xBFFF0030) 107VI_ERROR_RAW_WR_PROT_VIOL = _to_int(0xBFFF0034) 108VI_ERROR_RAW_RD_PROT_VIOL = _to_int(0xBFFF0035) 109VI_ERROR_OUTP_PROT_VIOL = _to_int(0xBFFF0036) 110VI_ERROR_INP_PROT_VIOL = _to_int(0xBFFF0037) 111VI_ERROR_BERR = _to_int(0xBFFF0038) 112VI_ERROR_IN_PROGRESS = _to_int(0xBFFF0039) 113VI_ERROR_INV_SETUP = _to_int(0xBFFF003A) 114VI_ERROR_QUEUE_ERROR = _to_int(0xBFFF003B) 115VI_ERROR_ALLOC = _to_int(0xBFFF003C) 116VI_ERROR_INV_MASK = _to_int(0xBFFF003D) 117VI_ERROR_IO = _to_int(0xBFFF003E) 118VI_ERROR_INV_FMT = _to_int(0xBFFF003F) 119VI_ERROR_NSUP_FMT = _to_int(0xBFFF0041) 120VI_ERROR_LINE_IN_USE = _to_int(0xBFFF0042) 121VI_ERROR_NSUP_MODE = _to_int(0xBFFF0046) 122VI_ERROR_SRQ_NOCCURRED = _to_int(0xBFFF004A) 123VI_ERROR_INV_SPACE = _to_int(0xBFFF004E) 124VI_ERROR_INV_OFFSET = _to_int(0xBFFF0051) 125VI_ERROR_INV_WIDTH = _to_int(0xBFFF0052) 126VI_ERROR_NSUP_OFFSET = _to_int(0xBFFF0054) 127VI_ERROR_NSUP_VAR_WIDTH = _to_int(0xBFFF0055) 128VI_ERROR_WINDOW_NMAPPED = _to_int(0xBFFF0057) 129VI_ERROR_RESP_PENDING = _to_int(0xBFFF0059) 130VI_ERROR_NLISTENERS = _to_int(0xBFFF005F) 131VI_ERROR_NCIC = _to_int(0xBFFF0060) 132VI_ERROR_NSYS_CNTLR = _to_int(0xBFFF0061) 133VI_ERROR_NSUP_OPER = _to_int(0xBFFF0067) 134VI_ERROR_INTR_PENDING = _to_int(0xBFFF0068) 135VI_ERROR_ASRL_PARITY = _to_int(0xBFFF006A) 136VI_ERROR_ASRL_FRAMING = _to_int(0xBFFF006B) 137VI_ERROR_ASRL_OVERRUN = _to_int(0xBFFF006C) 138VI_ERROR_TRIG_NMAPPED = _to_int(0xBFFF006E) 139VI_ERROR_NSUP_ALIGN_OFFSET = _to_int(0xBFFF0070) 140VI_ERROR_USER_BUF = _to_int(0xBFFF0071) 141VI_ERROR_RSRC_BUSY = _to_int(0xBFFF0072) 142VI_ERROR_NSUP_WIDTH = _to_int(0xBFFF0076) 143VI_ERROR_INV_PARAMETER = _to_int(0xBFFF0078) 144VI_ERROR_INV_PROT = _to_int(0xBFFF0079) 145VI_ERROR_INV_SIZE = _to_int(0xBFFF007B) 146VI_ERROR_WINDOW_MAPPED = _to_int(0xBFFF0080) 147VI_ERROR_NIMPL_OPER = _to_int(0xBFFF0081) 148VI_ERROR_INV_LENGTH = _to_int(0xBFFF0083) 149VI_ERROR_INV_MODE = _to_int(0xBFFF0091) 150VI_ERROR_SESN_NLOCKED = _to_int(0xBFFF009C) 151VI_ERROR_MEM_NSHARED = _to_int(0xBFFF009D) 152VI_ERROR_LIBRARY_NFOUND = _to_int(0xBFFF009E) 153VI_ERROR_NSUP_INTR = _to_int(0xBFFF009F) 154VI_ERROR_INV_LINE = _to_int(0xBFFF00A0) 155VI_ERROR_FILE_ACCESS = _to_int(0xBFFF00A1) 156VI_ERROR_FILE_IO = _to_int(0xBFFF00A2) 157VI_ERROR_NSUP_LINE = _to_int(0xBFFF00A3) 158VI_ERROR_NSUP_MECH = _to_int(0xBFFF00A4) 159VI_ERROR_INTF_NUM_NCONFIG = _to_int(0xBFFF00A5) 160VI_ERROR_CONN_LOST = _to_int(0xBFFF00A6) 161 162# The following two are a non-standard NI extensions 163VI_ERROR_MACHINE_NAVAIL = _to_int(0xBFFF00A7) 164VI_ERROR_NPERMISSION = _to_int(0xBFFF00A8) 165 166 167# 168# Attribute constants 169# 170# All attribute codes are unsigned long, so no _to_int() is necessary. 171# 172 173VI_ATTR_RSRC_CLASS = 0xBFFF0001 174VI_ATTR_RSRC_NAME = 0xBFFF0002 175VI_ATTR_RSRC_IMPL_VERSION = 0x3FFF0003 176VI_ATTR_RSRC_LOCK_STATE = 0x3FFF0004 177VI_ATTR_MAX_QUEUE_LENGTH = 0x3FFF0005 178VI_ATTR_USER_DATA_32 = 0x3FFF0007 179VI_ATTR_USER_DATA_64 = 0x3FFF000A 180VI_ATTR_USER_DATA = ( 181 VI_ATTR_USER_DATA_64 if is_64bits else VI_ATTR_USER_DATA_64 182) 183VI_ATTR_FDC_CHNL = 0x3FFF000D 184VI_ATTR_FDC_MODE = 0x3FFF000F 185VI_ATTR_FDC_GEN_SIGNAL_EN = 0x3FFF0011 186VI_ATTR_FDC_USE_PAIR = 0x3FFF0013 187VI_ATTR_SEND_END_EN = 0x3FFF0016 188VI_ATTR_TERMCHAR = 0x3FFF0018 189VI_ATTR_TMO_VALUE = 0x3FFF001A 190VI_ATTR_GPIB_READDR_EN = 0x3FFF001B 191VI_ATTR_IO_PROT = 0x3FFF001C 192VI_ATTR_DMA_ALLOW_EN = 0x3FFF001E 193 194VI_ATTR_ASRL_BAUD = 0x3FFF0021 195VI_ATTR_ASRL_DATA_BITS = 0x3FFF0022 196VI_ATTR_ASRL_PARITY = 0x3FFF0023 197VI_ATTR_ASRL_STOP_BITS = 0x3FFF0024 198VI_ATTR_ASRL_FLOW_CNTRL = 0x3FFF0025 199VI_ATTR_ASRL_DISCARD_NULL = 0x3FFF00B0 200VI_ATTR_ASRL_CONNECTED = 0x3FFF01BB 201VI_ATTR_ASRL_BREAK_STATE = 0x3FFF01BC 202VI_ATTR_ASRL_BREAK_LEN = 0x3FFF01BD 203VI_ATTR_ASRL_ALLOW_TRANSMIT = 0x3FFF01BE 204VI_ATTR_ASRL_WIRE_MODE = 0x3FFF01BF # National instrument only 205 206VI_ATTR_RD_BUF_OPER_MODE = 0x3FFF002A 207VI_ATTR_RD_BUF_SIZE = 0x3FFF002B 208VI_ATTR_WR_BUF_OPER_MODE = 0x3FFF002D 209VI_ATTR_WR_BUF_SIZE = 0x3FFF002E 210VI_ATTR_SUPPRESS_END_EN = 0x3FFF0036 211VI_ATTR_TERMCHAR_EN = 0x3FFF0038 212VI_ATTR_DEST_ACCESS_PRIV = 0x3FFF0039 213VI_ATTR_DEST_BYTE_ORDER = 0x3FFF003A 214VI_ATTR_SRC_ACCESS_PRIV = 0x3FFF003C 215VI_ATTR_SRC_BYTE_ORDER = 0x3FFF003D 216VI_ATTR_SRC_INCREMENT = 0x3FFF0040 217VI_ATTR_DEST_INCREMENT = 0x3FFF0041 218VI_ATTR_WIN_ACCESS_PRIV = 0x3FFF0045 219VI_ATTR_WIN_BYTE_ORDER = 0x3FFF0047 220 221VI_ATTR_GPIB_ATN_STATE = 0x3FFF0057 222VI_ATTR_GPIB_ADDR_STATE = 0x3FFF005C 223VI_ATTR_GPIB_CIC_STATE = 0x3FFF005E 224VI_ATTR_GPIB_NDAC_STATE = 0x3FFF0062 225VI_ATTR_GPIB_SRQ_STATE = 0x3FFF0067 226VI_ATTR_GPIB_SYS_CNTRL_STATE = 0x3FFF0068 227VI_ATTR_GPIB_HS488_CBL_LEN = 0x3FFF0069 228VI_ATTR_CMDR_LA = 0x3FFF006B 229VI_ATTR_VXI_DEV_CLASS = 0x3FFF006C 230VI_ATTR_MAINFRAME_LA = 0x3FFF0070 231VI_ATTR_MANF_NAME = 0xBFFF0072 232VI_ATTR_MODEL_NAME = 0xBFFF0077 233VI_ATTR_VXI_VME_INTR_STATUS = 0x3FFF008B 234VI_ATTR_VXI_TRIG_STATUS = 0x3FFF008D 235VI_ATTR_VXI_VME_SYSFAIL_STATE = 0x3FFF0094 236 237VI_ATTR_WIN_BASE_ADDR_32 = 0x3FFF0098 238VI_ATTR_WIN_BASE_ADDR_64 = 0x3FFF009B 239VI_ATTR_WIN_BASE_ADDR = ( 240 VI_ATTR_WIN_BASE_ADDR_64 if is_64bits else VI_ATTR_WIN_BASE_ADDR_32 241) 242VI_ATTR_WIN_SIZE = 0x3FFF009A 243VI_ATTR_ASRL_AVAIL_NUM = 0x3FFF00AC 244VI_ATTR_MEM_BASE_32 = 0x3FFF00AD 245VI_ATTR_MEM_BASE_64 = 0x3FFF00D0 246VI_ATTR_MEM_BASE = ( 247 VI_ATTR_MEM_BASE_64 if is_64bits else VI_ATTR_MEM_BASE_32 248) 249VI_ATTR_ASRL_CTS_STATE = 0x3FFF00AE 250VI_ATTR_ASRL_DCD_STATE = 0x3FFF00AF 251VI_ATTR_ASRL_DSR_STATE = 0x3FFF00B1 252VI_ATTR_ASRL_DTR_STATE = 0x3FFF00B2 253VI_ATTR_ASRL_END_IN = 0x3FFF00B3 254VI_ATTR_ASRL_END_OUT = 0x3FFF00B4 255VI_ATTR_ASRL_REPLACE_CHAR = 0x3FFF00BE 256VI_ATTR_ASRL_RI_STATE = 0x3FFF00BF 257VI_ATTR_ASRL_RTS_STATE = 0x3FFF00C0 258VI_ATTR_ASRL_XON_CHAR = 0x3FFF00C1 259VI_ATTR_ASRL_XOFF_CHAR = 0x3FFF00C2 260VI_ATTR_WIN_ACCESS = 0x3FFF00C3 261VI_ATTR_RM_SESSION = 0x3FFF00C4 262VI_ATTR_VXI_LA = 0x3FFF00D5 263VI_ATTR_MANF_ID = 0x3FFF00D9 264VI_ATTR_MEM_SIZE_32 = 0x3FFF00DD 265VI_ATTR_MEM_SIZE_64 = 0x3FFF00D1 266VI_ATTR_MEM_SIZE = ( 267 VI_ATTR_MEM_SIZE_64 if is_64bits else VI_ATTR_MEM_SIZE_32 268) 269VI_ATTR_MEM_SPACE = 0x3FFF00DE 270VI_ATTR_MODEL_CODE = 0x3FFF00DF 271VI_ATTR_SLOT = 0x3FFF00E8 272VI_ATTR_INTF_INST_NAME = 0xBFFF00E9 273VI_ATTR_IMMEDIATE_SERV = 0x3FFF0100 274VI_ATTR_INTF_PARENT_NUM = 0x3FFF0101 275VI_ATTR_RSRC_SPEC_VERSION = 0x3FFF0170 276VI_ATTR_INTF_TYPE = 0x3FFF0171 277VI_ATTR_GPIB_PRIMARY_ADDR = 0x3FFF0172 278VI_ATTR_GPIB_SECONDARY_ADDR = 0x3FFF0173 279VI_ATTR_RSRC_MANF_NAME = 0xBFFF0174 280VI_ATTR_RSRC_MANF_ID = 0x3FFF0175 281VI_ATTR_INTF_NUM = 0x3FFF0176 282VI_ATTR_TRIG_ID = 0x3FFF0177 283VI_ATTR_GPIB_REN_STATE = 0x3FFF0181 284VI_ATTR_GPIB_UNADDR_EN = 0x3FFF0184 285VI_ATTR_DEV_STATUS_BYTE = 0x3FFF0189 286VI_ATTR_FILE_APPEND_EN = 0x3FFF0192 287VI_ATTR_VXI_TRIG_SUPPORT = 0x3FFF0194 288VI_ATTR_TCPIP_ADDR = 0xBFFF0195 289VI_ATTR_TCPIP_HOSTNAME = 0xBFFF0196 290VI_ATTR_TCPIP_PORT = 0x3FFF0197 291VI_ATTR_TCPIP_DEVICE_NAME = 0xBFFF0199 292VI_ATTR_TCPIP_NODELAY = 0x3FFF019A 293VI_ATTR_TCPIP_KEEPALIVE = 0x3FFF019B 294VI_ATTR_TCPIP_HISLIP_OVERLAP_EN = 0x3FFF0300 295VI_ATTR_TCPIP_HISLIP_VERSION = 0x3FFF0301 296VI_ATTR_TCPIP_HISLIP_MAX_MESSAGE_KB = 0x3FFF0302 297VI_ATTR_TCPIP_IS_HISLIP = 0x3FFF0303 298VI_ATTR_4882_COMPLIANT = 0x3FFF019F 299VI_ATTR_USB_SERIAL_NUM = 0xBFFF01A0 300VI_ATTR_USB_INTFC_NUM = 0x3FFF01A1 301VI_ATTR_USB_PROTOCOL = 0x3FFF01A7 302VI_ATTR_USB_MAX_INTR_SIZE = 0x3FFF01AF 303VI_ATTR_USB_BULK_OUT_PIPE = _to_int(0x3FFF01A2) 304VI_ATTR_USB_BULK_IN_PIPE = _to_int(0x3FFF01A3) 305VI_ATTR_USB_INTR_IN_PIPE = _to_int(0x3FFF01A4) 306VI_ATTR_USB_CLASS = _to_int(0x3FFF01A5) 307VI_ATTR_USB_SUBCLASS = _to_int(0x3FFF01A6) 308VI_ATTR_USB_ALT_SETTING = _to_int(0x3FFF01A8) 309VI_ATTR_USB_END_IN = _to_int(0x3FFF01A9) 310VI_ATTR_USB_NUM_INTFCS = _to_int(0x3FFF01AA) 311VI_ATTR_USB_NUM_PIPES = _to_int(0x3FFF01AB) 312VI_ATTR_USB_BULK_OUT_STATUS = _to_int(0x3FFF01AC) 313VI_ATTR_USB_BULK_IN_STATUS = _to_int(0x3FFF01AD) 314VI_ATTR_USB_INTR_IN_STATUS = _to_int(0x3FFF01AE) 315VI_ATTR_USB_CTRL_PIPE = _to_int(0x3FFF01B0) 316VI_ATTR_USB_RECV_INTR_SIZE = 0x3FFF41B0 317VI_ATTR_USB_RECV_INTR_DATA = 0xBFFF41B1 318 319VI_ATTR_JOB_ID = 0x3FFF4006 320VI_ATTR_EVENT_TYPE = 0x3FFF4010 321VI_ATTR_SIGP_STATUS_ID = 0x3FFF4011 322VI_ATTR_RECV_TRIG_ID = 0x3FFF4012 323VI_ATTR_INTR_STATUS_ID = 0x3FFF4023 324VI_ATTR_STATUS = 0x3FFF4025 325VI_ATTR_RET_COUNT_32 = 0x3FFF4026 326VI_ATTR_RET_COUNT_64 = 0x3FFF4028 327VI_ATTR_RET_COUNT = VI_ATTR_RET_COUNT_64 if is_64bits else VI_ATTR_RET_COUNT_64 328VI_ATTR_BUFFER = 0x3FFF4027 329VI_ATTR_RECV_INTR_LEVEL = 0x3FFF4041 330VI_ATTR_OPER_NAME = 0xBFFF4042 331VI_ATTR_GPIB_RECV_CIC_STATE = 0x3FFF4193 332VI_ATTR_RECV_TCPIP_ADDR = 0xBFFF4198 333 334VI_ATTR_PXI_DEV_NUM = _to_int(0x3FFF0201) 335VI_ATTR_PXI_FUNC_NUM = _to_int(0x3FFF0202) 336VI_ATTR_PXI_BUS_NUM = _to_int(0x3FFF0205) 337VI_ATTR_PXI_CHASSIS = _to_int(0x3FFF0206) 338VI_ATTR_PXI_SLOTPATH = _to_int(0xBFFF0207) 339VI_ATTR_PXI_SLOT_LBUS_LEFT = _to_int(0x3FFF0208) 340VI_ATTR_PXI_SLOT_LBUS_RIGHT = _to_int(0x3FFF0209) 341VI_ATTR_PXI_TRIG_BUS = _to_int(0x3FFF020A) 342VI_ATTR_PXI_STAR_TRIG_BUS = _to_int(0x3FFF020B) 343VI_ATTR_PXI_STAR_TRIG_LINE = _to_int(0x3FFF020C) 344 345VI_ATTR_PXI_IS_EXPRESS = _to_int(0x3FFF0240) 346VI_ATTR_PXI_SLOT_LWIDTH = _to_int(0x3FFF0241) 347VI_ATTR_PXI_MAX_LWIDTH = _to_int(0x3FFF0242) 348VI_ATTR_PXI_ACTUAL_LWIDTH = _to_int(0x3FFF0243) 349VI_ATTR_PXI_DSTAR_BUS = _to_int(0x3FFF0244) 350VI_ATTR_PXI_DSTAR_SET = _to_int(0x3FFF0245) 351 352VI_ATTR_PXI_SRC_TRIG_BUS = _to_int(0x3FFF020D) 353VI_ATTR_PXI_DEST_TRIG_BUS = _to_int(0x3FFF020E) 354 355VI_ATTR_PXI_RECV_INTR_SEQ = _to_int(0x3FFF4240) 356VI_ATTR_PXI_RECV_INTR_DATA = _to_int(0x3FFF4241) 357 358VI_ATTR_PXI_MEM_TYPE_BAR0 = _to_int(0x3FFF0211) 359VI_ATTR_PXI_MEM_TYPE_BAR1 = _to_int(0x3FFF0212) 360VI_ATTR_PXI_MEM_TYPE_BAR2 = _to_int(0x3FFF0213) 361VI_ATTR_PXI_MEM_TYPE_BAR3 = _to_int(0x3FFF0214) 362VI_ATTR_PXI_MEM_TYPE_BAR4 = _to_int(0x3FFF0215) 363VI_ATTR_PXI_MEM_TYPE_BAR5 = _to_int(0x3FFF0216) 364 365VI_ATTR_PXI_MEM_BASE_BAR0_32 = _to_int(0x3FFF0221) 366VI_ATTR_PXI_MEM_BASE_BAR1_32 = _to_int(0x3FFF0222) 367VI_ATTR_PXI_MEM_BASE_BAR2_32 = _to_int(0x3FFF0223) 368VI_ATTR_PXI_MEM_BASE_BAR3_32 = _to_int(0x3FFF0224) 369VI_ATTR_PXI_MEM_BASE_BAR4_32 = _to_int(0x3FFF0225) 370VI_ATTR_PXI_MEM_BASE_BAR5_32 = _to_int(0x3FFF0226) 371VI_ATTR_PXI_MEM_SIZE_BAR0_32 = _to_int(0x3FFF0231) 372VI_ATTR_PXI_MEM_SIZE_BAR1_32 = _to_int(0x3FFF0232) 373VI_ATTR_PXI_MEM_SIZE_BAR2_32 = _to_int(0x3FFF0233) 374VI_ATTR_PXI_MEM_SIZE_BAR3_32 = _to_int(0x3FFF0234) 375VI_ATTR_PXI_MEM_SIZE_BAR4_32 = _to_int(0x3FFF0235) 376VI_ATTR_PXI_MEM_SIZE_BAR5_32 = _to_int(0x3FFF0236) 377 378VI_ATTR_PXI_MEM_BASE_BAR0_64 = _to_int(0x3FFF0228) 379VI_ATTR_PXI_MEM_BASE_BAR1_64 = _to_int(0x3FFF0229) 380VI_ATTR_PXI_MEM_BASE_BAR2_64 = _to_int(0x3FFF022A) 381VI_ATTR_PXI_MEM_BASE_BAR3_64 = _to_int(0x3FFF022B) 382VI_ATTR_PXI_MEM_BASE_BAR4_64 = _to_int(0x3FFF022C) 383VI_ATTR_PXI_MEM_BASE_BAR5_64 = _to_int(0x3FFF022D) 384VI_ATTR_PXI_MEM_SIZE_BAR0_64 = _to_int(0x3FFF0238) 385VI_ATTR_PXI_MEM_SIZE_BAR1_64 = _to_int(0x3FFF0239) 386VI_ATTR_PXI_MEM_SIZE_BAR2_64 = _to_int(0x3FFF023A) 387VI_ATTR_PXI_MEM_SIZE_BAR3_64 = _to_int(0x3FFF023B) 388VI_ATTR_PXI_MEM_SIZE_BAR4_64 = _to_int(0x3FFF023C) 389VI_ATTR_PXI_MEM_SIZE_BAR5_64 = _to_int(0x3FFF023D) 390 391VI_ATTR_PXI_MEM_BASE_BAR0 = ( 392 VI_ATTR_PXI_MEM_BASE_BAR0_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR0_32 393) 394VI_ATTR_PXI_MEM_BASE_BAR1 = ( 395 VI_ATTR_PXI_MEM_BASE_BAR1_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR1_32 396) 397VI_ATTR_PXI_MEM_BASE_BAR2 = ( 398 VI_ATTR_PXI_MEM_BASE_BAR2_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR2_32 399) 400VI_ATTR_PXI_MEM_BASE_BAR3 = ( 401 VI_ATTR_PXI_MEM_BASE_BAR3_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR3_32 402) 403VI_ATTR_PXI_MEM_BASE_BAR4 = ( 404 VI_ATTR_PXI_MEM_BASE_BAR4_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR4_32 405) 406VI_ATTR_PXI_MEM_BASE_BAR5 = ( 407 VI_ATTR_PXI_MEM_BASE_BAR5_64 if is_64bits else VI_ATTR_PXI_MEM_BASE_BAR5_32 408) 409VI_ATTR_PXI_MEM_SIZE_BAR0 = ( 410 VI_ATTR_PXI_MEM_SIZE_BAR0_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR0_32 411) 412VI_ATTR_PXI_MEM_SIZE_BAR1 = ( 413 VI_ATTR_PXI_MEM_SIZE_BAR1_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR1_32 414) 415VI_ATTR_PXI_MEM_SIZE_BAR2 = ( 416 VI_ATTR_PXI_MEM_SIZE_BAR2_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR2_32 417) 418VI_ATTR_PXI_MEM_SIZE_BAR3 = ( 419 VI_ATTR_PXI_MEM_SIZE_BAR3_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR3_32 420) 421VI_ATTR_PXI_MEM_SIZE_BAR4 = ( 422 VI_ATTR_PXI_MEM_SIZE_BAR4_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR4_32 423) 424VI_ATTR_PXI_MEM_SIZE_BAR5 = ( 425 VI_ATTR_PXI_MEM_SIZE_BAR5_64 if is_64bits else VI_ATTR_PXI_MEM_SIZE_BAR5_32 426) 427 428# 429# Event Types 430# 431# All event codes are unsigned long, so no _to_int() is necessary. 432# 433 434VI_EVENT_IO_COMPLETION = 0x3FFF2009 435VI_EVENT_TRIG = 0xBFFF200A 436VI_EVENT_SERVICE_REQ = 0x3FFF200B 437VI_EVENT_CLEAR = 0x3FFF200D 438VI_EVENT_EXCEPTION = 0xBFFF200E 439VI_EVENT_GPIB_CIC = 0x3FFF2012 440VI_EVENT_GPIB_TALK = 0x3FFF2013 441VI_EVENT_GPIB_LISTEN = 0x3FFF2014 442VI_EVENT_VXI_VME_SYSFAIL = 0x3FFF201D 443VI_EVENT_VXI_VME_SYSRESET = 0x3FFF201E 444VI_EVENT_VXI_SIGP = 0x3FFF2020 445VI_EVENT_VXI_VME_INTR = 0xBFFF2021 446VI_EVENT_PXI_INTR = 0x3FFF2022 447VI_EVENT_TCPIP_CONNECT = 0x3FFF2036 448VI_EVENT_USB_INTR = 0x3FFF2037 449VI_ALL_ENABLED_EVENTS = 0x3FFF7FFF 450 451VI_ATTR_VXI_TRIG_DIR = _to_int(0x3FFF4044) 452VI_ATTR_VXI_TRIG_LINES_EN = _to_int(0x3FFF4043) 453 454# 455# Values and Ranges 456# 457 458VI_FIND_BUFLEN = 256 459VI_NULL = 0 460 461VI_TRUE = 1 462VI_FALSE = 0 463 464VI_INTF_GPIB = 1 465VI_INTF_VXI = 2 466VI_INTF_GPIB_VXI = 3 467VI_INTF_ASRL = 4 468VI_INTF_PXI = 5 469VI_INTF_TCPIP = 6 470VI_INTF_USB = 7 471VI_INTF_RIO = 8 472VI_INTF_FIREWIRE = 9 473 474VI_PROT_NORMAL = 1 475VI_PROT_FDC = 2 476VI_PROT_HS488 = 3 477VI_PROT_4882_STRS = 4 478VI_PROT_USBTMC_VENDOR = 5 479 480VI_FDC_NORMAL = 1 481VI_FDC_STREAM = 2 482 483VI_LOCAL_SPACE = 0 484VI_A16_SPACE = 1 485VI_A24_SPACE = 2 486VI_A32_SPACE = 3 487VI_A64_SPACE = 4 488VI_OPAQUE_SPACE = 0xFFFF 489 490VI_UNKNOWN_LA = -1 491VI_UNKNOWN_SLOT = -1 492VI_UNKNOWN_LEVEL = -1 493 494VI_QUEUE = 1 495VI_HNDLR = 2 496VI_SUSPEND_HNDLR = 4 497VI_ALL_MECH = 0xFFFF 498 499VI_ANY_HNDLR = 0 500 501VI_TRIG_ALL = -2 502VI_TRIG_SW = -1 503VI_TRIG_TTL0 = 0 504VI_TRIG_TTL1 = 1 505VI_TRIG_TTL2 = 2 506VI_TRIG_TTL3 = 3 507VI_TRIG_TTL4 = 4 508VI_TRIG_TTL5 = 5 509VI_TRIG_TTL6 = 6 510VI_TRIG_TTL7 = 7 511VI_TRIG_TTL8 = 32 512VI_TRIG_TTL9 = 33 513VI_TRIG_TTL10 = 34 514VI_TRIG_TTL11 = 35 515VI_TRIG_ECL0 = 8 516VI_TRIG_ECL1 = 9 517VI_TRIG_ECL2 = 10 518VI_TRIG_ECL3 = 11 519VI_TRIG_ECL4 = 12 520VI_TRIG_ECL5 = 13 521VI_TRIG_STAR_SLOT1 = 14 522VI_TRIG_STAR_SLOT2 = 15 523VI_TRIG_STAR_SLOT3 = 16 524VI_TRIG_STAR_SLOT4 = 17 525VI_TRIG_STAR_SLOT5 = 18 526VI_TRIG_STAR_SLOT6 = 19 527VI_TRIG_STAR_SLOT7 = 20 528VI_TRIG_STAR_SLOT8 = 21 529VI_TRIG_STAR_SLOT9 = 22 530VI_TRIG_STAR_SLOT10 = 23 531VI_TRIG_STAR_SLOT11 = 24 532VI_TRIG_STAR_SLOT12 = 25 533VI_TRIG_STAR_INSTR = 26 534VI_TRIG_PANEL_IN = 27 535VI_TRIG_PANEL_OUT = 28 536VI_TRIG_STAR_VXI0 = 29 537VI_TRIG_STAR_VXI1 = 30 538VI_TRIG_STAR_VXI2 = 31 539 540VI_TRIG_PROT_DEFAULT = 0 541VI_TRIG_PROT_ON = 1 542VI_TRIG_PROT_OFF = 2 543VI_TRIG_PROT_SYNC = 5 544VI_TRIG_PROT_RESERVE = 6 545VI_TRIG_PROT_UNRESERVE = 7 546 547VI_READ_BUF = 1 548VI_WRITE_BUF = 2 549VI_READ_BUF_DISCARD = 4 550VI_WRITE_BUF_DISCARD = 8 551VI_IO_IN_BUF = 16 552VI_IO_OUT_BUF = 32 553VI_IO_IN_BUF_DISCARD = 64 554VI_IO_OUT_BUF_DISCARD = 128 555 556VI_FLUSH_ON_ACCESS = 1 557VI_FLUSH_WHEN_FULL = 2 558VI_FLUSH_DISABLE = 3 559 560VI_NMAPPED = 1 561VI_USE_OPERS = 2 562VI_DEREF_ADDR = 3 563 564VI_TMO_IMMEDIATE = 0 565# Attention! The following is *really* positive! (unsigned long) 566VI_TMO_INFINITE = 0xFFFFFFFF 567 568VI_NO_LOCK = 0 569VI_EXCLUSIVE_LOCK = 1 570VI_SHARED_LOCK = 2 571VI_LOAD_CONFIG = 4 572 573VI_NO_SEC_ADDR = 0xFFFF 574 575VI_ASRL_PAR_NONE = 0 576VI_ASRL_PAR_ODD = 1 577VI_ASRL_PAR_EVEN = 2 578VI_ASRL_PAR_MARK = 3 579VI_ASRL_PAR_SPACE = 4 580 581VI_ASRL_STOP_ONE = 10 582VI_ASRL_STOP_ONE5 = 15 583VI_ASRL_STOP_TWO = 20 584 585VI_ASRL_FLOW_NONE = 0 586VI_ASRL_FLOW_XON_XOFF = 1 587VI_ASRL_FLOW_RTS_CTS = 2 588VI_ASRL_FLOW_DTR_DSR = 4 589 590VI_ASRL_END_NONE = 0 591VI_ASRL_END_LAST_BIT = 1 592VI_ASRL_END_TERMCHAR = 2 593VI_ASRL_END_BREAK = 3 594 595# The following are National Instrument only 596VI_ASRL_WIRE_485_4 = 0 597VI_ASRL_WIRE_485_2_DTR_ECHO = 1 598VI_ASRL_WIRE_485_2_DTR_CTRL = 2 599VI_ASRL_WIRE_485_2_AUTO = 3 600VI_ASRL_WIRE_232_DTE = 128 601VI_ASRL_WIRE_232_DCE = 129 602VI_ASRL_WIRE_232_AUTO = 130 603 604VI_STATE_ASSERTED = 1 605VI_STATE_UNASSERTED = 0 606VI_STATE_UNKNOWN = -1 607 608VI_BIG_ENDIAN = 0 609VI_LITTLE_ENDIAN = 1 610 611VI_DATA_PRIV = 0 612VI_DATA_NPRIV = 1 613VI_PROG_PRIV = 2 614VI_PROG_NPRIV = 3 615VI_BLCK_PRIV = 4 616VI_BLCK_NPRIV = 5 617VI_D64_PRIV = 6 618VI_D64_NPRIV = 7 619VI_D64_2EVME = 8 620VI_D64_SST160 = 9 621VI_D64_SST267 = 10 622VI_D64_SST320 = 11 623 624 625VI_WIDTH_8 = 1 626VI_WIDTH_16 = 2 627VI_WIDTH_32 = 4 628VI_WIDTH_64 = 8 629 630VI_GPIB_REN_DEASSERT = 0 631VI_GPIB_REN_ASSERT = 1 632VI_GPIB_REN_DEASSERT_GTL = 2 633VI_GPIB_REN_ASSERT_ADDRESS = 3 634VI_GPIB_REN_ASSERT_LLO = 4 635VI_GPIB_REN_ASSERT_ADDRESS_LLO = 5 636VI_GPIB_REN_ADDRESS_GTL = 6 637 638VI_GPIB_ATN_DEASSERT = 0 639VI_GPIB_ATN_ASSERT = 1 640VI_GPIB_ATN_DEASSERT_HANDSHAKE = 2 641VI_GPIB_ATN_ASSERT_IMMEDIATE = 3 642 643VI_GPIB_HS488_DISABLED = 0 644VI_GPIB_HS488_NIMPL = -1 645 646VI_GPIB_UNADDRESSED = 0 647VI_GPIB_TALKER = 1 648VI_GPIB_LISTENER = 2 649 650VI_VXI_CMD16 = 0x0200 651VI_VXI_CMD16_RESP16 = 0x0202 652VI_VXI_RESP16 = 0x0002 653VI_VXI_CMD32 = 0x0400 654VI_VXI_CMD32_RESP16 = 0x0402 655VI_VXI_CMD32_RESP32 = 0x0404 656VI_VXI_RESP32 = 0x0004 657 658VI_ASSERT_SIGNAL = -1 659VI_ASSERT_USE_ASSIGNED = 0 660VI_ASSERT_IRQ1 = 1 661VI_ASSERT_IRQ2 = 2 662VI_ASSERT_IRQ3 = 3 663VI_ASSERT_IRQ4 = 4 664VI_ASSERT_IRQ5 = 5 665VI_ASSERT_IRQ6 = 6 666VI_ASSERT_IRQ7 = 7 667 668VI_UTIL_ASSERT_SYSRESET = 1 669VI_UTIL_ASSERT_SYSFAIL = 2 670VI_UTIL_DEASSERT_SYSFAIL = 3 671 672VI_VXI_CLASS_MEMORY = 0 673VI_VXI_CLASS_EXTENDED = 1 674VI_VXI_CLASS_MESSAGE = 2 675VI_VXI_CLASS_REGISTER = 3 676VI_VXI_CLASS_OTHER = 4 677 678VI_PXI_LBUS_UNKNOWN = -1 679VI_PXI_LBUS_NONE = 0 680VI_PXI_LBUS_STAR_TRIG_BUS_0 = 1000 681VI_PXI_LBUS_STAR_TRIG_BUS_1 = 1001 682VI_PXI_LBUS_STAR_TRIG_BUS_2 = 1002 683VI_PXI_LBUS_STAR_TRIG_BUS_3 = 1003 684VI_PXI_LBUS_STAR_TRIG_BUS_4 = 1004 685VI_PXI_LBUS_STAR_TRIG_BUS_5 = 1005 686VI_PXI_LBUS_STAR_TRIG_BUS_6 = 1006 687VI_PXI_LBUS_STAR_TRIG_BUS_7 = 1007 688VI_PXI_LBUS_STAR_TRIG_BUS_8 = 1008 689VI_PXI_LBUS_STAR_TRIG_BUS_9 = 1009 690VI_PXI_STAR_TRIG_CONTROLLER = 1413 691VI_PXI_LBUS_SCXI = 2000 692VI_PXI_ALLOC_SPACE = 9 693VI_PXI_CFG_SPACE = 10 694VI_PXI_BAR0_SPACE = 11 695VI_PXI_BAR1_SPACE = 12 696VI_PXI_BAR2_SPACE = 13 697VI_PXI_BAR3_SPACE = 14 698VI_PXI_BAR4_SPACE = 15 699VI_PXI_BAR5_SPACE = 16 700 701VI_PXI_ADDR_NONE = 0 702VI_PXI_ADDR_MEM = 1 703VI_PXI_ADDR_IO = 2 704VI_PXI_ADDR_CFG = 3 705 706VI_USB_PIPE_STATE_UNKNOWN = -1 707VI_USB_PIPE_READY = 0 708VI_USB_PIPE_STALLED = 1 709 710# From VI_ATTR_USB_END_IN 711VI_USB_END_NONE = 0 712VI_USB_END_SHORT = 4 713VI_USB_END_SHORT_OR_COUNT = 5 714 715# "Backwards compatibility" according to NI 716 717VI_NORMAL = VI_PROT_NORMAL 718VI_FDC = VI_PROT_FDC 719VI_HS488 = VI_PROT_HS488 720VI_ASRL488 = VI_PROT_4882_STRS 721VI_ASRL_IN_BUF = VI_IO_IN_BUF 722VI_ASRL_OUT_BUF = VI_IO_OUT_BUF 723VI_ASRL_IN_BUF_DISCARD = VI_IO_IN_BUF_DISCARD 724VI_ASRL_OUT_BUF_DISCARD = VI_IO_OUT_BUF_DISCARD 725 726# fmt: on 727 728# ====================================================================================== 729# --- Enumeration for easier handling of the constants --------------------------------- 730# ====================================================================================== 731 732 733@enum.unique 734class VisaBoolean(enum.IntEnum): 735 """Visa boolean values.""" 736 737 true = VI_TRUE 738 false = VI_FALSE 739 740 741# Constants useful for all kind of resources. 742 743 744@enum.unique 745class Timeouts(enum.IntEnum): 746 """Special timeout values.""" 747 748 #: Minimal timeout value 749 immediate = VI_TMO_IMMEDIATE 750 751 #: Infinite timeout 752 infinite = VI_TMO_INFINITE 753 754 755@enum.unique 756class Lock(enum.IntEnum): 757 """Kind of lock to use when locking a resource.""" 758 759 #: Obtains a exclusive lock on the VISA resource. 760 exclusive = VI_EXCLUSIVE_LOCK 761 762 #: Obtains a lock on the VISA resouce which may be shared 763 #: between multiple VISA sessions. 764 shared = VI_SHARED_LOCK 765 766 767@enum.unique 768class AccessModes(enum.IntEnum): 769 """Whether and how to lock a resource when opening a connection.""" 770 771 #: Does not obtain any lock on the VISA resource. 772 no_lock = VI_NO_LOCK 773 774 #: Obtains a exclusive lock on the VISA resource. 775 exclusive_lock = VI_EXCLUSIVE_LOCK 776 777 #: Obtains a lock on the VISA resouce which may be shared 778 #: between multiple VISA sessions. 779 shared_lock = VI_SHARED_LOCK 780 781 782@enum.unique 783class InterfaceType(enum.IntEnum): 784 """The hardware interface.""" 785 786 # Used for unknown interface type strings. 787 unknown = -1 788 789 #: GPIB Interface. 790 gpib = VI_INTF_GPIB 791 792 #: VXI (VME eXtensions for Instrumentation), VME, MXI (Multisystem eXtension Interface). 793 vxi = VI_INTF_VXI 794 795 #: GPIB VXI (VME eXtensions for Instrumentation). 796 gpib_vxi = VI_INTF_GPIB_VXI 797 798 #: Serial devices connected to either an RS-232 or RS-485 controller. 799 asrl = VI_INTF_ASRL 800 801 #: PXI device. 802 pxi = VI_INTF_PXI 803 804 #: TCPIP device. 805 tcpip = VI_INTF_TCPIP 806 807 #: Universal Serial Bus (USB) hardware bus. 808 usb = VI_INTF_USB 809 810 #: Rio device. 811 rio = VI_INTF_RIO 812 813 #: Firewire device. 814 firewire = VI_INTF_FIREWIRE 815 816 #: Rohde and Schwarz Device via Passport 817 rsnrp = 33024 818 819 820@enum.unique 821class LineState(enum.IntEnum): 822 """State of a hardware line or signal. 823 824 The line for which the state can be queried are: 825 - ASRC resource: BREAK, CTS, DCD, DSR, DTR, RI, RTS signals 826 - GPIB resources: ATN, NDAC, REN, SRQ lines 827 - VXI BACKPLANE: VXI/VME SYSFAIL backplane line 828 829 Search for LineState in attributes.py for more details. 830 831 """ 832 833 #: The line/signal is currently asserted 834 asserted = VI_STATE_ASSERTED 835 836 #: The line/signal is currently deasserted 837 unasserted = VI_STATE_UNASSERTED 838 839 #: The state of the line/signal is unknown 840 unknown = VI_STATE_UNKNOWN 841 842 843@enum.unique 844class IOProtocol(enum.IntEnum): 845 """IO protocol used for communication. 846 847 See attributes.AttrVI_ATTR_IO_PROT for more details. 848 849 """ 850 851 normal = VI_PROT_NORMAL 852 853 #: Fast data channel (FDC) protocol for VXI 854 fdc = VI_PROT_FDC 855 856 #: High speed 488 transfer for GPIB 857 hs488 = VI_PROT_HS488 858 859 #: 488 style transfer for serial 860 protocol4882_strs = VI_PROT_4882_STRS 861 862 #: Test measurement class vendor specific for USB 863 usbtmc_vendor = VI_PROT_USBTMC_VENDOR 864 865 866@enum.unique 867class EventMechanism(enum.IntEnum): 868 """The available event mechanisms for event handling.""" 869 870 #: Queue events that can then be queried using wait_on_event 871 queue = VI_QUEUE 872 873 #: Use a specified callback handler to deal with events 874 handler = VI_HNDLR 875 876 #: Queue events to be passed to the handler when the system is switch to the 877 #: handler mechanism. 878 suspend_handler = VI_SUSPEND_HNDLR 879 880 #: Use to disable or discard events no matter the handling mechanism 881 all = VI_ALL_MECH 882 883 884# Message based resources relevant constants 885 886 887@enum.unique 888class EventType(enum.IntEnum): 889 """The available event types for event handling.""" 890 891 #: Notification that an asynchronous operation has completed. 892 io_completion = VI_EVENT_IO_COMPLETION 893 894 #: Notification that a trigger interrupt was received from the device. 895 #: For VISA, the only triggers that can be sensed are VXI hardware triggers 896 #: on the assertion edge (SYNC and ON trigger protocols only). 897 trig = VI_EVENT_TRIG 898 899 #: Notification that a service request was received from the device. 900 service_request = VI_EVENT_SERVICE_REQ 901 902 #: Notification that the local controller has been sent a device clear message. 903 clear = VI_EVENT_CLEAR 904 905 #: Notification that an error condition has occurred during an operation 906 #: invocation. 907 exception = VI_EVENT_EXCEPTION 908 909 #: Notification that the GPIB controller has gained or lost CIC (controller 910 #: in charge) status. 911 gpib_controller_in_charge = VI_EVENT_GPIB_CIC 912 913 #: Notification that the GPIB controller has been addressed to talk. 914 gpib_talk = VI_EVENT_GPIB_TALK 915 916 #: Notification that the GPIB controller has been addressed to listen. 917 gpib_listen = VI_EVENT_GPIB_LISTEN 918 919 #: Notification that the VXI/VME SYSFAIL* line has been asserted. 920 vxi_vme_sysfail = VI_EVENT_VXI_VME_SYSFAIL 921 922 #: Notification that the VXI/VME SYSRESET* line has been asserted. 923 vxi_vme_sysreset = VI_EVENT_VXI_VME_SYSRESET 924 925 #: Notification that a VXIbus signal or VXIbus interrupt was received from 926 #: the device. 927 vxi_signal_interrupt = VI_EVENT_VXI_SIGP 928 929 #: Notification that a VXIbus interrupt was received from the device. 930 vxi_vme_interrupt = VI_EVENT_VXI_VME_INTR 931 932 #: Notification that a PCI Interrupt was received from the device. 933 pxi_interrupt = VI_EVENT_PXI_INTR 934 935 #: Notification that a TCP/IP connection has been made. 936 tcpip_connect = VI_EVENT_TCPIP_CONNECT 937 938 #: Notification that a vendor-specific USB interrupt was received from the device. 939 usb_interrupt = VI_EVENT_USB_INTR 940 941 #: Value equivalent to all events. Use to switch handling mechanism for all 942 #: events in one call or disabling all events. 943 all_enabled = VI_ALL_ENABLED_EVENTS 944 945 946@enum.unique 947class BufferType(enum.IntFlag): 948 """Buffer potentially available on a message based resource. 949 950 Used with the set_buffer function to alter the size of a buffer. 951 952 """ 953 954 #: Formatted read buffer 955 read = VI_READ_BUF 956 957 #: Formatted write buffer 958 write = VI_WRITE_BUF 959 960 #: I/O communication receive buffer. 961 io_in = VI_IO_IN_BUF 962 963 #: I/O communication transmit buffer. 964 io_out = VI_IO_OUT_BUF 965 966 967@enum.unique 968class BufferOperation(enum.IntFlag): 969 """Possible action of the buffer when performing a flush.""" 970 971 #: Discard the read buffer contents and if data was present in the read buffer 972 #: and no END-indicator was present, read from the device until encountering 973 #: an END indicator (which causes the loss of data). 974 discard_read_buffer = VI_READ_BUF 975 976 #: Discard the read buffer contents (does not perform any I/O to the device). 977 discard_read_buffer_no_io = VI_READ_BUF_DISCARD 978 979 #: Flush the write buffer by writing all buffered data to the device. 980 flush_write_buffer = VI_WRITE_BUF 981 982 #: Discard the write buffer contents (does not perform any I/O to the device). 983 discard_write_buffer = VI_WRITE_BUF_DISCARD 984 985 #: Discard the receive buffer contents (does not perform any I/O to the device). 986 discard_receive_buffer = VI_IO_IN_BUF_DISCARD 987 988 #: Discards the receive buffer contents (same as VI_IO_IN_BUF_DISCARD) 989 discard_receive_buffer2 = VI_IO_IN_BUF 990 991 #: Flush the transmit buffer by writing all buffered data to the device. 992 flush_transmit_buffer = VI_IO_OUT_BUF 993 994 #: Discard the transmit buffer contents (does not perform any I/O to the device). 995 discard_transmit_buffer = VI_IO_OUT_BUF_DISCARD 996 997 998# Constants related to serial resources 999 1000 1001@enum.unique 1002class StopBits(enum.IntEnum): 1003 """The number of stop bits that indicate the end of a frame on a serial resource. 1004 1005 Used only for ASRL resources. 1006 1007 """ 1008 1009 one = VI_ASRL_STOP_ONE 1010 one_and_a_half = VI_ASRL_STOP_ONE5 1011 two = VI_ASRL_STOP_TWO 1012 1013 1014@enum.unique 1015class Parity(enum.IntEnum): 1016 """Parity type to use with every frame transmitted and received on a serial session. 1017 1018 Used only for ASRL resources. 1019 1020 """ 1021 1022 none = VI_ASRL_PAR_NONE 1023 odd = VI_ASRL_PAR_ODD 1024 even = VI_ASRL_PAR_EVEN 1025 mark = VI_ASRL_PAR_MARK 1026 space = VI_ASRL_PAR_SPACE 1027 1028 1029@enum.unique 1030class SerialTermination(enum.IntEnum): 1031 """The available methods for terminating a serial transfer.""" 1032 1033 #: The transfer terminates when all requested data is transferred 1034 #: or when an error occurs. 1035 none = VI_ASRL_END_NONE 1036 1037 #: The transfer occurs with the last bit not set until the last 1038 #: character is sent. 1039 last_bit = VI_ASRL_END_LAST_BIT 1040 1041 #: The transfer terminate by searching for "/" 1042 #: appending the termination character. 1043 termination_char = VI_ASRL_END_TERMCHAR 1044 1045 #: The write transmits a break after all the characters for the 1046 #: write are sent. 1047 termination_break = VI_ASRL_END_BREAK 1048 1049 1050@enum.unique 1051class WireMode(enum.IntEnum): 1052 """Valid modes for National Instruments hardware supporting it.""" 1053 1054 #: 4-wire mode. 1055 rs485_4 = VI_ASRL_WIRE_485_4 1056 1057 #: 2-wire DTR mode controlled with echo. 1058 rs485_2_dtr_echo = VI_ASRL_WIRE_485_2_DTR_ECHO 1059 1060 #: 2-wire DTR mode controlled without echo 1061 rs485_2_dtr_ctrl = VI_ASRL_WIRE_485_2_DTR_CTRL 1062 1063 #: 2-wire auto mode controlled with TXRDY 1064 rs485_2_auto = VI_ASRL_WIRE_485_2_AUTO 1065 1066 #: Use DTE mode 1067 rs232_dte = VI_ASRL_WIRE_232_DTE 1068 1069 #: Use DCE mode 1070 rs232_dce = VI_ASRL_WIRE_232_DCE 1071 1072 #: Auto detect the mode to use 1073 rs232_auto = VI_ASRL_WIRE_232_AUTO 1074 1075 #: Unknown mode 1076 unknown = VI_STATE_UNKNOWN 1077 1078 1079@enum.unique 1080class ControlFlow(enum.IntEnum): 1081 """Control flow for a serial resource.""" 1082 1083 none = VI_ASRL_FLOW_NONE 1084 xon_xoff = VI_ASRL_FLOW_XON_XOFF 1085 rts_cts = VI_ASRL_FLOW_RTS_CTS 1086 dtr_dsr = VI_ASRL_FLOW_DTR_DSR 1087 1088 1089# USB specific constants 1090 1091 1092@enum.unique 1093class USBEndInput(enum.IntEnum): 1094 """Method used to terminate input on USB RAW.""" 1095 1096 none = VI_USB_END_NONE 1097 short = VI_USB_END_SHORT 1098 short_or_count = VI_USB_END_SHORT_OR_COUNT 1099 1100 1101# GPIB specific value 1102 1103 1104@enum.unique 1105class AddressState(enum.IntEnum): 1106 """State of a GPIB resource. 1107 1108 Corresponds to the Attribute.GPIB_address_state attribute 1109 1110 """ 1111 1112 #: The resource is unadressed 1113 unaddressed = VI_GPIB_UNADDRESSED 1114 1115 #: The resource is addressed to talk 1116 talker = VI_GPIB_TALKER 1117 1118 #: The resource is addressed to listen 1119 listenr = VI_GPIB_LISTENER 1120 1121 1122@enum.unique 1123class ATNLineOperation(enum.IntEnum): 1124 """Operation that can be performed on the GPIB ATN line. 1125 1126 These operations are available only to GPIB INTFC resources 1127 1128 """ 1129 1130 #: Assert ATN line synchronously (in 488 terminology). If a data handshake 1131 #: is in progress, ATN will not be asserted until the handshake is complete. 1132 asrt = VI_GPIB_ATN_ASSERT 1133 1134 #: Assert ATN line asynchronously (in 488 terminology). This should generally 1135 #: be used only under error conditions. 1136 asrt_immediate = VI_GPIB_ATN_ASSERT_IMMEDIATE 1137 1138 #: Deassert the ATN line 1139 deassert = VI_GPIB_ATN_DEASSERT 1140 1141 #: Deassert ATN line, and enter shadow handshake mode. The local board will 1142 #: participate in data handshakes as an Acceptor without actually reading the data. 1143 deassert_handshake = VI_GPIB_ATN_DEASSERT_HANDSHAKE 1144 1145 1146@enum.unique 1147class RENLineOperation(enum.IntEnum): 1148 """Operation that can be performed on the REN line. 1149 1150 Some of these operation are available to GPIB INSTR, GPIB INTFC, USB INSTR, 1151 TCPIP INSTR, please see the VISA reference for more details. 1152 1153 """ 1154 1155 #: Send the Go To Local command (GTL) to this device. 1156 address_gtl = VI_GPIB_REN_ADDRESS_GTL 1157 1158 #: Assert REN line. 1159 asrt = VI_GPIB_REN_ASSERT 1160 1161 #: Assert REN line and address this device. 1162 asrt_address = VI_GPIB_REN_ASSERT_ADDRESS 1163 1164 #: Address this device and send it LLO, putting it in RWLS 1165 asrt_address_llo = VI_GPIB_REN_ASSERT_ADDRESS_LLO 1166 1167 #: Send LLO to any devices that are addressed to listen. 1168 asrt_llo = VI_GPIB_REN_ASSERT_LLO 1169 1170 #: Deassert REN line. 1171 deassert = VI_GPIB_REN_DEASSERT 1172 1173 #: Send the Go To Local command (GTL) to this device and deassert REN line. 1174 deassert_gtl = VI_GPIB_REN_DEASSERT_GTL 1175 1176 1177@enum.unique 1178class AddressSpace(enum.IntEnum): 1179 """Address space for register based resources.""" 1180 1181 #: A16 address space of VXI/MXI bus. 1182 a16 = VI_A16_SPACE 1183 1184 #: A24 address space of VXI/MXI bus. 1185 a24 = VI_A24_SPACE 1186 1187 #: A32 address space of VXI/MXI bus. 1188 a32 = VI_A32_SPACE 1189 1190 #: A64 address space of VXI/MXI bus. 1191 a64 = VI_A64_SPACE 1192 1193 #: PCI configuration space. 1194 pxi_config = VI_PXI_CFG_SPACE 1195 1196 #: Specified PCI memory or I/O space 1197 pxi_bar0 = VI_PXI_BAR0_SPACE 1198 pxi_bar1 = VI_PXI_BAR1_SPACE 1199 pxi_bar2 = VI_PXI_BAR2_SPACE 1200 pxi_bar3 = VI_PXI_BAR3_SPACE 1201 pxi_bar4 = VI_PXI_BAR4_SPACE 1202 pxi_bar5 = VI_PXI_BAR5_SPACE 1203 1204 #: Physical locally allocated memory. 1205 pxi_allocated = VI_PXI_ALLOC_SPACE 1206 1207 1208@enum.unique 1209class AddressModifiers(enum.IntEnum): 1210 """Address modifier to be used in high-level register operations.""" 1211 1212 data_private = VI_DATA_PRIV 1213 data_non_private = VI_DATA_NPRIV 1214 program_private = VI_PROG_PRIV 1215 program_non_private = VI_PROG_NPRIV 1216 block_private = VI_BLCK_PRIV 1217 block_non_private = VI_BLCK_NPRIV 1218 d64_private = VI_D64_PRIV 1219 d64_non_private = VI_D64_NPRIV 1220 d64_2vme = VI_D64_2EVME 1221 d64_sst160 = VI_D64_SST160 1222 d64_sst267 = VI_D64_SST267 1223 d64_sst320 = VI_D64_SST320 1224 1225 1226@enum.unique 1227class AssertSignalInterrupt(enum.IntEnum): 1228 """Line on which to perform an assertion or interrupt. 1229 1230 Used only for VXI backplane and servant resources. 1231 1232 """ 1233 1234 #: Use a VXI signal 1235 signal = VI_ASSERT_SIGNAL 1236 1237 #: Use the mechanism specified in the response of Asynchronous Mode Control 1238 #: command. (VXI SERVANT only) 1239 use_assigned = VI_ASSERT_USE_ASSIGNED 1240 1241 #: Send the interrupt via the specified VXI/VME IRQ line 1242 irq1 = VI_ASSERT_IRQ1 1243 irq2 = VI_ASSERT_IRQ2 1244 irq3 = VI_ASSERT_IRQ3 1245 irq4 = VI_ASSERT_IRQ4 1246 irq5 = VI_ASSERT_IRQ5 1247 irq6 = VI_ASSERT_IRQ6 1248 irq7 = VI_ASSERT_IRQ7 1249 1250 1251@enum.unique 1252class UtilityBusSignal(enum.IntEnum): 1253 """Operation on the utility line of a VXI backplane or servant.""" 1254 1255 #: Assert the SYSRESET ie perform a HARD RESET on the whole VXI bus. 1256 sysrest = VI_UTIL_ASSERT_SYSRESET 1257 1258 #: Assert the SYSFAIL line. 1259 sysfail_assert = VI_UTIL_ASSERT_SYSFAIL 1260 1261 #: Deassert the SYSFAIL line. 1262 sysfail_deassert = VI_UTIL_DEASSERT_SYSFAIL 1263 1264 1265@enum.unique 1266class VXICommands(enum.IntEnum): 1267 """VXI commands that can be sent using the vxi_command_query.""" 1268 1269 #: Send a command fitting in a 16-bit integer 1270 command_16 = VI_VXI_CMD16 1271 1272 #: Read a response fitting in a 16-bit integer 1273 response16 = VI_VXI_RESP16 1274 1275 #: Send a command and read a response both fitting in a 16-bit integer 1276 command_response_16 = VI_VXI_CMD16_RESP16 1277 1278 #: Send a command fitting in a 32-bit integer 1279 command_32 = VI_VXI_CMD32 1280 1281 #: Read a response fitting in a 32-bit integer 1282 response32 = VI_VXI_RESP32 1283 1284 #: Send a command and read a response both fitting in a 32-bit integer 1285 command_response_32 = VI_VXI_CMD32_RESP32 1286 1287 #: Send a command (32-bit integer) and read a response (16-bit integer) 1288 command_32_response_16 = VI_VXI_CMD32_RESP16 1289 1290 1291@enum.unique 1292class PXIMemory(enum.IntEnum): 1293 """Memory type used in a PXI BAR.""" 1294 1295 none = VI_PXI_ADDR_NONE 1296 memory = VI_PXI_ADDR_MEM 1297 io = VI_PXI_ADDR_IO 1298 cfg = VI_PXI_ADDR_CFG 1299 1300 1301@enum.unique 1302class VXIClass(enum.IntEnum): 1303 """VXI-defined device class.""" 1304 1305 memory = VI_VXI_CLASS_MEMORY 1306 extended = VI_VXI_CLASS_EXTENDED 1307 message = VI_VXI_CLASS_MESSAGE 1308 register = VI_VXI_CLASS_REGISTER 1309 other = VI_VXI_CLASS_OTHER 1310 1311 1312@enum.unique 1313class TriggerProtocol(enum.IntEnum): 1314 """Trigger protocol used when assering a resource trigger.""" 1315 1316 # FIXME The VISA standard is not very detailed on those 1317 #: Default protocol. 1318 #: This is the only valid protocol for software trigger on ASRL, GPIB, USB 1319 #: and VXI resources 1320 default = VI_TRIG_PROT_DEFAULT 1321 1322 #: 1323 on = VI_TRIG_PROT_ON 1324 1325 #: 1326 off = VI_TRIG_PROT_OFF 1327 1328 #: For VXI devices equivalent to default 1329 sync = VI_TRIG_PROT_SYNC 1330 1331 #: On PXI resources used to reserve a line for triggering 1332 reserve = VI_TRIG_PROT_RESERVE 1333 1334 #: On PXI resources used to unreserve a line for triggering 1335 unreserve = VI_TRIG_PROT_UNRESERVE 1336 1337 1338@enum.unique 1339class InputTriggerLine(enum.IntEnum): 1340 """Trigger lines which can be mapped to another line. 1341 1342 VXI, PXI devices. 1343 1344 """ 1345 1346 #: TTL trigger lines 1347 ttl0 = VI_TRIG_TTL0 1348 ttl1 = VI_TRIG_TTL1 1349 ttl2 = VI_TRIG_TTL2 1350 ttl3 = VI_TRIG_TTL3 1351 ttl4 = VI_TRIG_TTL4 1352 ttl5 = VI_TRIG_TTL5 1353 ttl6 = VI_TRIG_TTL6 1354 ttl7 = VI_TRIG_TTL7 1355 1356 # PXI specific TTL trigger lines 1357 ttl8 = VI_TRIG_TTL8 1358 ttl9 = VI_TRIG_TTL9 1359 ttl10 = VI_TRIG_TTL10 1360 ttl11 = VI_TRIG_TTL11 1361 1362 #: ECL trigger lines 1363 ecl0 = VI_TRIG_ECL0 1364 ecl1 = VI_TRIG_ECL1 1365 ecl2 = VI_TRIG_ECL2 1366 ecl3 = VI_TRIG_ECL3 1367 ecl4 = VI_TRIG_ECL4 1368 ecl5 = VI_TRIG_ECL5 1369 1370 #: Panel IN trigger line 1371 panel = VI_TRIG_PANEL_IN 1372 1373 #: VXI STAR trigger input lines 1374 slot1 = VI_TRIG_STAR_SLOT1 1375 slot2 = VI_TRIG_STAR_SLOT2 1376 slot3 = VI_TRIG_STAR_SLOT3 1377 slot4 = VI_TRIG_STAR_SLOT4 1378 slot5 = VI_TRIG_STAR_SLOT5 1379 slot6 = VI_TRIG_STAR_SLOT6 1380 slot7 = VI_TRIG_STAR_SLOT7 1381 slot8 = VI_TRIG_STAR_SLOT8 1382 slot9 = VI_TRIG_STAR_SLOT9 1383 slot10 = VI_TRIG_STAR_SLOT10 1384 slot11 = VI_TRIG_STAR_SLOT11 1385 slot12 = VI_TRIG_STAR_SLOT12 1386 1387 1388@enum.unique 1389class OutputTriggerLine(enum.IntEnum): 1390 """Trigger lines to which another line can be mapped to. 1391 1392 VXI, PXI devices. 1393 1394 """ 1395 1396 #: TTL trigger lines 1397 ttl0 = VI_TRIG_TTL0 1398 ttl1 = VI_TRIG_TTL1 1399 ttl2 = VI_TRIG_TTL2 1400 ttl3 = VI_TRIG_TTL3 1401 ttl4 = VI_TRIG_TTL4 1402 ttl5 = VI_TRIG_TTL5 1403 ttl6 = VI_TRIG_TTL6 1404 ttl7 = VI_TRIG_TTL7 1405 1406 # PXI specific TTL trigger lines 1407 ttl8 = VI_TRIG_TTL8 1408 ttl9 = VI_TRIG_TTL9 1409 ttl10 = VI_TRIG_TTL10 1410 ttl11 = VI_TRIG_TTL11 1411 1412 #: VXI ECL trigger lines 1413 ecl0 = VI_TRIG_ECL0 1414 ecl1 = VI_TRIG_ECL1 1415 ecl2 = VI_TRIG_ECL2 1416 ecl3 = VI_TRIG_ECL3 1417 ecl4 = VI_TRIG_ECL4 1418 ecl5 = VI_TRIG_ECL5 1419 1420 #: VXI STAR trigger out lines 1421 vxi0 = VI_TRIG_STAR_VXI0 1422 vxi1 = VI_TRIG_STAR_VXI1 1423 vxi2 = VI_TRIG_STAR_VXI2 1424 1425 #: Panel OUT trigger line 1426 panel = VI_TRIG_PANEL_OUT 1427 1428 #: All trigger lines (used only when unmapping lines) 1429 all = VI_TRIG_ALL 1430 1431 1432@enum.unique 1433class TriggerID(enum.IntEnum): 1434 """Identifier of the currently active trigerring mechanism on a resource.""" 1435 1436 #: Trigger using a serial word 1437 serial_word = VI_TRIG_SW 1438 1439 #: TTL trigger lines 1440 ttl0 = VI_TRIG_TTL0 1441 ttl1 = VI_TRIG_TTL1 1442 ttl2 = VI_TRIG_TTL2 1443 ttl3 = VI_TRIG_TTL3 1444 ttl4 = VI_TRIG_TTL4 1445 ttl5 = VI_TRIG_TTL5 1446 ttl6 = VI_TRIG_TTL6 1447 ttl7 = VI_TRIG_TTL7 1448 1449 # PXI specific TTL trigger lines 1450 ttl8 = VI_TRIG_TTL8 1451 ttl9 = VI_TRIG_TTL9 1452 ttl10 = VI_TRIG_TTL10 1453 ttl11 = VI_TRIG_TTL11 1454 1455 #: VXI ECL trigger lines 1456 ecl0 = VI_TRIG_ECL0 1457 ecl1 = VI_TRIG_ECL1 1458 ecl2 = VI_TRIG_ECL2 1459 ecl3 = VI_TRIG_ECL3 1460 ecl4 = VI_TRIG_ECL4 1461 ecl5 = VI_TRIG_ECL5 1462 1463 #: VXI STAR trigger out lines 1464 vxi0 = VI_TRIG_STAR_VXI0 1465 vxi1 = VI_TRIG_STAR_VXI1 1466 vxi2 = VI_TRIG_STAR_VXI2 1467 1468 #: FIXME No definition in the VISA standards 1469 instr = VI_TRIG_STAR_INSTR 1470 1471 1472@enum.unique 1473class TriggerEventID(enum.IntEnum): 1474 """Identifier of the triggering mechanism on which a trigger event was received.""" 1475 1476 #: TTL trigger lines 1477 ttl0 = VI_TRIG_TTL0 1478 ttl1 = VI_TRIG_TTL1 1479 ttl2 = VI_TRIG_TTL2 1480 ttl3 = VI_TRIG_TTL3 1481 ttl4 = VI_TRIG_TTL4 1482 ttl5 = VI_TRIG_TTL5 1483 ttl6 = VI_TRIG_TTL6 1484 ttl7 = VI_TRIG_TTL7 1485 1486 # PXI specific TTL trigger lines 1487 ttl8 = VI_TRIG_TTL8 1488 ttl9 = VI_TRIG_TTL9 1489 ttl10 = VI_TRIG_TTL10 1490 ttl11 = VI_TRIG_TTL11 1491 1492 #: VXI ECL trigger lines 1493 ecl0 = VI_TRIG_ECL0 1494 ecl1 = VI_TRIG_ECL1 1495 ecl2 = VI_TRIG_ECL2 1496 ecl3 = VI_TRIG_ECL3 1497 ecl4 = VI_TRIG_ECL4 1498 ecl5 = VI_TRIG_ECL5 1499 1500 #: FIXME No definition in the VISA standards 1501 instr = VI_TRIG_STAR_INSTR 1502 1503 1504@enum.unique 1505class ByteOrder(enum.IntEnum): 1506 """Byte order in register data transfer.""" 1507 1508 big_endian = VI_BIG_ENDIAN 1509 little_endian = VI_LITTLE_ENDIAN 1510 1511 1512@enum.unique 1513class DataWidth(enum.IntEnum): 1514 """Word width used when transferring data to/from register based resources.""" 1515 1516 #: Transfer data using 1 byte word 1517 bit_8 = VI_WIDTH_8 1518 1519 #: Transfer data using 2 byte word 1520 bit_16 = VI_WIDTH_16 1521 1522 #: Transfer data using 4 byte word 1523 bit_32 = VI_WIDTH_32 1524 1525 #: Transfer data using 8 byte word 1526 bit_64 = VI_WIDTH_64 1527 1528 @classmethod 1529 def from_literal(cls, value: Literal[8, 16, 32, 64]) -> "DataWidth": 1530 """Convert a literal width in the proper enum value.""" 1531 if value not in (8, 16, 32, 64): 1532 raise ValueError( 1533 f"Invalid datawidth {value} specified. Valid values are (8, 16, 32, 64" 1534 ) 1535 return cls(value // 8) 1536 1537 1538# Status code 1539 1540 1541@enum.unique 1542class StatusCode(enum.IntEnum): 1543 """Status codes that VISA driver-level operations can return.""" 1544 1545 #: The operation was aborted. 1546 error_abort = VI_ERROR_ABORT 1547 1548 #: Insufficient system resources to perform necessary memory allocation. 1549 error_allocation = VI_ERROR_ALLOC 1550 1551 #: The specified attribute is read-only. 1552 error_attribute_read_only = VI_ERROR_ATTR_READONLY 1553 1554 #: Bus error occurred during transfer. 1555 error_bus_error = VI_ERROR_BERR 1556 1557 #: Unable to deallocate the previously allocated data structures corresponding 1558 #: to this session or object reference. 1559 error_closing_failed = VI_ERROR_CLOSING_FAILED 1560 1561 #: The connection for the specified session has been lost. 1562 error_connection_lost = VI_ERROR_CONN_LOST 1563 1564 #: An error occurred while trying to open the specified file. 1565 #: Possible causes include an invalid path or lack of access rights. 1566 error_file_access = VI_ERROR_FILE_ACCESS 1567 1568 #: An error occurred while performing I/O on the specified file. 1569 error_file_i_o = VI_ERROR_FILE_IO 1570 1571 #: A handler is not currently installed for the specified event. 1572 error_handler_not_installed = VI_ERROR_HNDLR_NINSTALLED 1573 1574 #: Unable to queue the asynchronous operation because there is already 1575 #: an operation in progress. 1576 error_in_progress = VI_ERROR_IN_PROGRESS 1577 1578 #: Device reported an input protocol error during transfer. 1579 error_input_protocol_violation = VI_ERROR_INP_PROT_VIOL 1580 1581 #: The interface type is valid but the specified interface number is not configured. 1582 error_interface_number_not_configured = VI_ERROR_INTF_NUM_NCONFIG 1583 1584 #: An interrupt is still pending from a previous call. 1585 error_interrupt_pending = VI_ERROR_INTR_PENDING 1586 1587 #: The access key to the resource associated with this session is invalid. 1588 error_invalid_access_key = VI_ERROR_INV_ACCESS_KEY 1589 1590 #: Invalid access mode. 1591 error_invalid_access_mode = VI_ERROR_INV_ACC_MODE 1592 1593 #: Invalid address space specified. 1594 error_invalid_address_space = VI_ERROR_INV_SPACE 1595 1596 #: Specified event context is invalid. 1597 error_invalid_context = VI_ERROR_INV_CONTEXT 1598 1599 #: Specified degree is invalid. 1600 error_invalid_degree = VI_ERROR_INV_DEGREE 1601 1602 #: Specified event type is not supported by the resource. 1603 error_invalid_event = VI_ERROR_INV_EVENT 1604 1605 #: Invalid expression specified for search. 1606 error_invalid_expression = VI_ERROR_INV_EXPR 1607 1608 #: A format specifier in the format string is invalid. 1609 error_invalid_format = VI_ERROR_INV_FMT 1610 1611 #: The specified handler reference is invalid. 1612 error_invalid_handler_reference = VI_ERROR_INV_HNDLR_REF 1613 1614 #: Specified job identifier is invalid. 1615 error_invalid_job_i_d = VI_ERROR_INV_JOB_ID 1616 1617 #: Invalid length specified. 1618 error_invalid_length = VI_ERROR_INV_LENGTH 1619 1620 #: The value specified by the line parameter is invalid. 1621 error_invalid_line = VI_ERROR_INV_LINE 1622 1623 #: The specified type of lock is not supported by this resource. 1624 error_invalid_lock_type = VI_ERROR_INV_LOCK_TYPE 1625 1626 #: Invalid buffer mask specified. 1627 error_invalid_mask = VI_ERROR_INV_MASK 1628 1629 #: Invalid mechanism specified. 1630 error_invalid_mechanism = VI_ERROR_INV_MECH 1631 1632 #: The specified mode is invalid. 1633 error_invalid_mode = VI_ERROR_INV_MODE 1634 1635 #: The specified session or object reference is invalid. 1636 error_invalid_object = VI_ERROR_INV_OBJECT 1637 1638 #: Invalid offset specified. 1639 error_invalid_offset = VI_ERROR_INV_OFFSET 1640 1641 #: The value of an unknown parameter is invalid. 1642 error_invalid_parameter = VI_ERROR_INV_PARAMETER 1643 1644 #: The protocol specified is invalid. 1645 error_invalid_protocol = VI_ERROR_INV_PROT 1646 1647 #: Invalid resource reference specified. Parsing error. 1648 error_invalid_resource_name = VI_ERROR_INV_RSRC_NAME 1649 1650 #: Unable to start operation because setup is invalid due to inconsistent 1651 #: state of properties. 1652 error_invalid_setup = VI_ERROR_INV_SETUP 1653 1654 #: Invalid size of window specified. 1655 error_invalid_size = VI_ERROR_INV_SIZE 1656 1657 #: Invalid source or destination width specified. 1658 error_invalid_width = VI_ERROR_INV_WIDTH 1659 1660 #: Could not perform operation because of I/O error. 1661 error_io = VI_ERROR_IO 1662 1663 #: A code library required by VISA could not be located or loaded. 1664 error_library_not_found = VI_ERROR_LIBRARY_NFOUND 1665 1666 #: The specified trigger line is currently in use. 1667 error_line_in_use = VI_ERROR_LINE_IN_USE 1668 1669 #: The remote machine does not exist or is not accepting any connections. 1670 error_machine_not_available = VI_ERROR_MACHINE_NAVAIL 1671 1672 #: The device does not export any memory. 1673 error_memory_not_shared = VI_ERROR_MEM_NSHARED 1674 1675 #: No listeners condition is detected (both NRFD and NDAC are deasserted). 1676 error_no_listeners = VI_ERROR_NLISTENERS 1677 1678 #: The specified operation is unimplemented. 1679 error_nonimplemented_operation = VI_ERROR_NIMPL_OPER 1680 1681 #: The specified attribute is not defined or supported by the referenced 1682 #: session, event, or find list. 1683 error_nonsupported_attribute = VI_ERROR_NSUP_ATTR 1684 1685 #: The specified state of the attribute is not valid or is not supported as 1686 #: defined by the session, event, or find list. 1687 error_nonsupported_attribute_state = VI_ERROR_NSUP_ATTR_STATE 1688 1689 #: A format specifier in the format string is not supported. 1690 error_nonsupported_format = VI_ERROR_NSUP_FMT 1691 1692 #: The interface cannot generate an interrupt on the requested level or with 1693 #: the requested statusID value. 1694 error_nonsupported_interrupt = VI_ERROR_NSUP_INTR 1695 1696 #: The specified trigger source line (trigSrc) or destination line (trigDest) 1697 #: is not supported by this VISA implementation, or the combination of lines 1698 #: is not a valid mapping. 1699 error_nonsupported_line = VI_ERROR_NSUP_LINE 1700 1701 #: The specified mechanism is not supported for the specified event type. 1702 error_nonsupported_mechanism = VI_ERROR_NSUP_MECH 1703 1704 #: The specified mode is not supported by this VISA implementation. 1705 error_nonsupported_mode = VI_ERROR_NSUP_MODE 1706 1707 #: Specified offset is not accessible from this hardware. 1708 error_nonsupported_offset = VI_ERROR_NSUP_OFFSET 1709 1710 #: The specified offset is not properly aligned for the access width of 1711 #: the operation. 1712 error_nonsupported_offset_alignment = VI_ERROR_NSUP_ALIGN_OFFSET 1713 1714 #: The session or object reference does not support this operation. 1715 error_nonsupported_operation = VI_ERROR_NSUP_OPER 1716 1717 #: Cannot support source and destination widths that are different. 1718 error_nonsupported_varying_widths = VI_ERROR_NSUP_VAR_WIDTH 1719 1720 #: Specified width is not supported by this hardware. 1721 error_nonsupported_width = VI_ERROR_NSUP_WIDTH 1722 1723 #: Access to the remote machine is denied. 1724 error_no_permission = VI_ERROR_NPERMISSION 1725 1726 #: The interface associated with this session is not currently the 1727 #: Controller-in-Charge. 1728 error_not_cic = VI_ERROR_NCIC 1729 1730 #: The session must be enabled for events of the specified type in order to 1731 #: receive them. 1732 error_not_enabled = VI_ERROR_NENABLED 1733 1734 #: The interface associated with this session is not the system controller. 1735 error_not_system_controller = VI_ERROR_NSYS_CNTLR 1736 1737 #: Device reported an output protocol error during transfer. 1738 error_output_protocol_violation = VI_ERROR_OUTP_PROT_VIOL 1739 1740 #: Unable to queue asynchronous operation. 1741 error_queue_error = VI_ERROR_QUEUE_ERROR 1742 1743 #: The event queue for the specified type has overflowed, usually due to 1744 #: not closing previous events. 1745 error_queue_overflow = VI_ERROR_QUEUE_OVERFLOW 1746 1747 #: Violation of raw read protocol occurred during transfer. 1748 error_raw_read_protocol_violation = VI_ERROR_RAW_RD_PROT_VIOL 1749 1750 #: Violation of raw write protocol occurred during transfer. 1751 error_raw_write_protocol_violation = VI_ERROR_RAW_WR_PROT_VIOL 1752 1753 #: The resource is valid, but VISA cannot currently access it. 1754 error_resource_busy = VI_ERROR_RSRC_BUSY 1755 1756 #: Specified type of lock cannot be obtained or specified operation cannot 1757 #: be performed because the resource is locked. 1758 error_resource_locked = VI_ERROR_RSRC_LOCKED 1759 1760 #: Insufficient location information, or the device or resource is not 1761 #: present in the system. 1762 error_resource_not_found = VI_ERROR_RSRC_NFOUND 1763 1764 #: A previous response is still pending, causing a multiple query error. 1765 error_response_pending = VI_ERROR_RESP_PENDING 1766 1767 #: A framing error occurred during transfer. 1768 error_serial_framing = VI_ERROR_ASRL_FRAMING 1769 1770 #: An overrun error occurred during transfer. A character was not read from 1771 #: the hardware before the next character arrived. 1772 error_serial_overrun = VI_ERROR_ASRL_OVERRUN 1773 1774 #: A parity error occurred during transfer. 1775 error_serial_parity = VI_ERROR_ASRL_PARITY 1776 1777 #: The current session did not have any lock on the resource. 1778 error_session_not_locked = VI_ERROR_SESN_NLOCKED 1779 1780 #: Service request has not been received for the session. 1781 error_srq_not_occurred = VI_ERROR_SRQ_NOCCURRED 1782 1783 #: Unknown system error. 1784 error_system_error = VI_ERROR_SYSTEM_ERROR 1785 1786 #: Timeout expired before operation completed. 1787 error_timeout = VI_ERROR_TMO 1788 1789 #: The path from the trigger source line (trigSrc) to the destination line 1790 #: (trigDest) is not currently mapped. 1791 error_trigger_not_mapped = VI_ERROR_TRIG_NMAPPED 1792 1793 #: A specified user buffer is not valid or cannot be accessed for the 1794 #: required size. 1795 error_user_buffer = VI_ERROR_USER_BUF 1796 1797 #: The specified session currently contains a mapped window. 1798 error_window_already_mapped = VI_ERROR_WINDOW_MAPPED 1799 1800 #: The specified session is currently unmapped. 1801 error_window_not_mapped = VI_ERROR_WINDOW_NMAPPED 1802 1803 #: Operation completed successfully. 1804 success = VI_SUCCESS 1805 1806 #: Session opened successfully, but the device at the specified address is 1807 #: not responding. 1808 success_device_not_present = VI_SUCCESS_DEV_NPRESENT 1809 1810 #: Specified event is already disabled for at least one of the specified mechanisms. 1811 success_event_already_disabled = VI_SUCCESS_EVENT_DIS 1812 1813 #: Specified event is already enabled for at least one of the specified mechanisms. 1814 success_event_already_enabled = VI_SUCCESS_EVENT_EN 1815 1816 #: The number of bytes read is equal to the input count. 1817 success_max_count_read = VI_SUCCESS_MAX_CNT 1818 1819 #: Operation completed successfully, and this session has nested exclusive locks. 1820 success_nested_exclusive = VI_SUCCESS_NESTED_EXCLUSIVE 1821 1822 #: Operation completed successfully, and this session has nested shared locks. 1823 success_nested_shared = VI_SUCCESS_NESTED_SHARED 1824 1825 #: Event handled successfully. Do not invoke any other handlers on this session 1826 #: for this event. 1827 success_no_more_handler_calls_in_chain = VI_SUCCESS_NCHAIN 1828 1829 #: Operation completed successfully, but the queue was already empty. 1830 success_queue_already_empty = VI_SUCCESS_QUEUE_EMPTY 1831 1832 #: Wait terminated successfully on receipt of an event notification. There 1833 #: is still at least one more event occurrence of the requested type(s) 1834 #: available for this session. 1835 success_queue_not_empty = VI_SUCCESS_QUEUE_NEMPTY 1836 1837 #: Asynchronous operation request was performed synchronously. 1838 success_synchronous = VI_SUCCESS_SYNC 1839 1840 #: The specified termination character was read. 1841 success_termination_character_read = VI_SUCCESS_TERM_CHAR 1842 1843 #: The path from the trigger source line (trigSrc) to the destination line 1844 #: (trigDest) is already mapped. 1845 success_trigger_already_mapped = VI_SUCCESS_TRIG_MAPPED 1846 1847 #: The specified configuration either does not exist or could not be loaded. 1848 #: The VISA-specified defaults are used. 1849 warning_configuration_not_loaded = VI_WARN_CONFIG_NLOADED 1850 1851 #: The operation succeeded, but a lower level driver did not implement the 1852 #: extended functionality. 1853 warning_ext_function_not_implemented = VI_WARN_EXT_FUNC_NIMPL 1854 1855 #: Although the specified state of the attribute is valid, it is not supported 1856 #: by this resource implementation. 1857 warning_nonsupported_attribute_state = VI_WARN_NSUP_ATTR_STATE 1858 1859 #: The specified buffer is not supported. 1860 warning_nonsupported_buffer = VI_WARN_NSUP_BUF 1861 1862 #: The specified object reference is uninitialized. 1863 warning_null_object = VI_WARN_NULL_OBJECT 1864 1865 #: VISA received more event information of the specified type than the 1866 #: configured queue size could hold. 1867 warning_queue_overflow = VI_WARN_QUEUE_OVERFLOW 1868 1869 #: The status code passed to the operation could not be interpreted. 1870 warning_unknown_status = VI_WARN_UNKNOWN_STATUS 1871 1872 1873# --- Attributes ----------------------------------------------------------------------- 1874 1875 1876@enum.unique 1877class EventAttribute(enum.IntEnum): 1878 """The possible attributes of VISA events.""" 1879 1880 event_type = VI_ATTR_EVENT_TYPE 1881 status = VI_ATTR_STATUS 1882 operation_name = VI_ATTR_OPER_NAME 1883 job_id = VI_ATTR_JOB_ID 1884 return_count = VI_ATTR_RET_COUNT 1885 buffer = VI_ATTR_BUFFER 1886 received_trigger_id = VI_ATTR_RECV_TRIG_ID 1887 gpib_received_cic_state = VI_ATTR_GPIB_RECV_CIC_STATE 1888 received_tcpip_connect = VI_ATTR_RECV_TCPIP_ADDR 1889 usb_received_interrupt_size = VI_ATTR_USB_RECV_INTR_SIZE 1890 usb_received_interrupt_data = VI_ATTR_USB_RECV_INTR_DATA 1891 signal_register_status_id = VI_ATTR_SIGP_STATUS_ID 1892 interrupt_status_id = VI_ATTR_INTR_STATUS_ID 1893 received_interrupt_level = VI_ATTR_RECV_INTR_LEVEL 1894 pxi_received_interrupt_sequence = VI_ATTR_PXI_RECV_INTR_SEQ 1895 pxi_received_interrupt_data = VI_ATTR_PXI_RECV_INTR_DATA 1896 1897 1898@enum.unique 1899class ResourceAttribute(enum.IntEnum): 1900 """The possible attributes of VISA resources.""" 1901 1902 # All sessions 1903 resource_manager_session = VI_ATTR_RM_SESSION 1904 interface_type = VI_ATTR_INTF_TYPE 1905 interface_number = VI_ATTR_INTF_NUM 1906 interface_instrument_name = VI_ATTR_INTF_INST_NAME 1907 resource_class = VI_ATTR_RSRC_CLASS 1908 resource_name = VI_ATTR_RSRC_NAME 1909 resource_impl_version = VI_ATTR_RSRC_IMPL_VERSION 1910 resource_lock_state = VI_ATTR_RSRC_LOCK_STATE 1911 resource_spec_version = VI_ATTR_RSRC_SPEC_VERSION 1912 resource_manufacturer_name = VI_ATTR_RSRC_MANF_NAME 1913 resource_manufacturer_id = VI_ATTR_RSRC_MANF_ID 1914 timeout_value = VI_ATTR_TMO_VALUE 1915 max_queue_length = VI_ATTR_MAX_QUEUE_LENGTH 1916 user_data = VI_ATTR_USER_DATA 1917 trigger_id = VI_ATTR_TRIG_ID # most resources no USB, nor TCPIP::SOCKET 1918 1919 # Message based resource attributes 1920 send_end_enabled = VI_ATTR_SEND_END_EN 1921 suppress_end_enabled = VI_ATTR_SUPPRESS_END_EN 1922 termchar_enabled = VI_ATTR_TERMCHAR_EN 1923 termchar = VI_ATTR_TERMCHAR 1924 io_prot = VI_ATTR_IO_PROT 1925 file_append_enabled = VI_ATTR_FILE_APPEND_EN 1926 read_buffer_operation_mode = VI_ATTR_RD_BUF_OPER_MODE 1927 read_buffer_size = VI_ATTR_RD_BUF_SIZE 1928 write_buffer_operation_mode = VI_ATTR_WR_BUF_OPER_MODE 1929 write_buffer_size = VI_ATTR_WR_BUF_SIZE 1930 1931 dma_allow_enabled = VI_ATTR_DMA_ALLOW_EN 1932 1933 # TCPIP specific attributes 1934 tcpip_address = VI_ATTR_TCPIP_ADDR 1935 tcpip_hostname = VI_ATTR_TCPIP_HOSTNAME 1936 tcpip_port = VI_ATTR_TCPIP_PORT 1937 tcpip_device_name = VI_ATTR_TCPIP_DEVICE_NAME 1938 tcpip_nodelay = VI_ATTR_TCPIP_NODELAY 1939 tcpip_keepalive = VI_ATTR_TCPIP_KEEPALIVE 1940 tcpip_is_hislip = VI_ATTR_TCPIP_IS_HISLIP 1941 tcpip_hislip_version = VI_ATTR_TCPIP_HISLIP_VERSION 1942 tcpip_hislip_overlap_enable = VI_ATTR_TCPIP_HISLIP_OVERLAP_EN 1943 tcpip_hislip_max_message_kb = VI_ATTR_TCPIP_HISLIP_MAX_MESSAGE_KB 1944 1945 # GPIB specific attributes 1946 gpib_primary_address = VI_ATTR_GPIB_PRIMARY_ADDR 1947 gpib_secondary_address = VI_ATTR_GPIB_SECONDARY_ADDR 1948 gpib_system_controller = VI_ATTR_GPIB_SYS_CNTRL_STATE 1949 gpib_cic_state = VI_ATTR_GPIB_CIC_STATE 1950 gpib_ren_state = VI_ATTR_GPIB_REN_STATE 1951 gpib_atn_state = VI_ATTR_GPIB_ATN_STATE 1952 gpib_ndac_state = VI_ATTR_GPIB_NDAC_STATE 1953 gpib_srq_state = VI_ATTR_GPIB_SRQ_STATE 1954 gpib_address_state = VI_ATTR_GPIB_ADDR_STATE 1955 gpib_unadress_enable = VI_ATTR_GPIB_UNADDR_EN 1956 gpib_readdress_enabled = VI_ATTR_GPIB_READDR_EN 1957 gpib_hs488_cable_length = VI_ATTR_GPIB_HS488_CBL_LEN 1958 1959 # Serial specific attributes 1960 asrl_avalaible_number = VI_ATTR_ASRL_AVAIL_NUM 1961 asrl_baud_rate = VI_ATTR_ASRL_BAUD 1962 asrl_data_bits = VI_ATTR_ASRL_DATA_BITS 1963 asrl_parity = VI_ATTR_ASRL_PARITY 1964 asrl_stop_bits = VI_ATTR_ASRL_STOP_BITS 1965 asrl_flow_control = VI_ATTR_ASRL_FLOW_CNTRL 1966 asrl_discard_null = VI_ATTR_ASRL_DISCARD_NULL 1967 asrl_connected = VI_ATTR_ASRL_CONNECTED 1968 asrl_allow_transmit = VI_ATTR_ASRL_ALLOW_TRANSMIT 1969 asrl_end_in = VI_ATTR_ASRL_END_IN 1970 asrl_end_out = VI_ATTR_ASRL_END_OUT 1971 asrl_break_length = VI_ATTR_ASRL_BREAK_LEN 1972 asrl_break_state = VI_ATTR_ASRL_BREAK_STATE 1973 asrl_replace_char = VI_ATTR_ASRL_REPLACE_CHAR 1974 asrl_xon_char = VI_ATTR_ASRL_XON_CHAR 1975 asrl_xoff_char = VI_ATTR_ASRL_XOFF_CHAR 1976 asrl_cts_state = VI_ATTR_ASRL_CTS_STATE 1977 asrl_dsr_state = VI_ATTR_ASRL_DSR_STATE 1978 asrl_dtr_state = VI_ATTR_ASRL_DTR_STATE 1979 asrl_rts_state = VI_ATTR_ASRL_RTS_STATE 1980 asrl_wire_mode = VI_ATTR_ASRL_WIRE_MODE 1981 asrl_dcd_state = VI_ATTR_ASRL_DCD_STATE 1982 asrl_ri_state = VI_ATTR_ASRL_RI_STATE 1983 1984 # USB specific attributes 1985 usb_interface_number = VI_ATTR_USB_INTFC_NUM 1986 usb_serial_number = VI_ATTR_USB_SERIAL_NUM 1987 usb_protocol = VI_ATTR_USB_PROTOCOL 1988 usb_max_interrupt_size = VI_ATTR_USB_MAX_INTR_SIZE 1989 usb_class = VI_ATTR_USB_CLASS 1990 usb_subclass = VI_ATTR_USB_SUBCLASS 1991 usb_bulk_in_status = VI_ATTR_USB_BULK_IN_STATUS 1992 usb_bulk_in_pipe = VI_ATTR_USB_BULK_IN_PIPE 1993 usb_bulk_out_status = VI_ATTR_USB_BULK_OUT_STATUS 1994 usb_bulk_out_pipe = VI_ATTR_USB_BULK_OUT_PIPE 1995 usb_interrupt_in_pipe = VI_ATTR_USB_INTR_IN_PIPE 1996 usb_alt_setting = VI_ATTR_USB_ALT_SETTING 1997 usb_end_in = VI_ATTR_USB_END_IN 1998 usb_number_interfaces = VI_ATTR_USB_NUM_INTFCS 1999 usb_number_pipes = VI_ATTR_USB_NUM_PIPES 2000 usb_interrupt_in_status = VI_ATTR_USB_INTR_IN_STATUS 2001 usb_control_pipe = VI_ATTR_USB_CTRL_PIPE 2002 2003 # USB, VXI, GPIB-VXI, PXI specific attributes 2004 manufacturer_name = VI_ATTR_MANF_NAME 2005 manufacturer_id = VI_ATTR_MANF_ID 2006 model_name = VI_ATTR_MODEL_NAME 2007 model_code = VI_ATTR_MODEL_CODE 2008 2009 # GPIB INTFC, VXI SERVANT 2010 device_status_byte = VI_ATTR_DEV_STATUS_BYTE 2011 2012 # (USB, VXI, GPIB-VXI)::INSTR specific attributes 2013 is_4882_compliant = VI_ATTR_4882_COMPLIANT 2014 2015 # (VXI, GPIB-VXI and PXI)::INSTR specific attributes 2016 slot = VI_ATTR_SLOT 2017 window_access = VI_ATTR_WIN_ACCESS 2018 window_base_address = VI_ATTR_WIN_BASE_ADDR 2019 window_size = VI_ATTR_WIN_SIZE 2020 source_increment = VI_ATTR_SRC_INCREMENT 2021 destination_increment = VI_ATTR_DEST_INCREMENT 2022 2023 # VXI and GPIB-VXI specific attributes 2024 fdc_channel = VI_ATTR_FDC_CHNL 2025 fdc_mode = VI_ATTR_FDC_MODE 2026 fdc_generate_signal_enabled = VI_ATTR_FDC_GEN_SIGNAL_EN 2027 fdc_use_pair = VI_ATTR_FDC_USE_PAIR 2028 mainframe_logical_address = VI_ATTR_MAINFRAME_LA 2029 vxi_logical_address = VI_ATTR_VXI_LA 2030 commander_logical_address = VI_ATTR_CMDR_LA 2031 memory_space = VI_ATTR_MEM_SPACE 2032 memory_size = VI_ATTR_MEM_SIZE 2033 memory_base = VI_ATTR_MEM_BASE 2034 immediate_servant = VI_ATTR_IMMEDIATE_SERV 2035 destination_access_private = VI_ATTR_DEST_ACCESS_PRIV 2036 destination_byte_order = VI_ATTR_DEST_BYTE_ORDER 2037 source_access_private = VI_ATTR_SRC_ACCESS_PRIV 2038 source_byte_order = VI_ATTR_SRC_BYTE_ORDER 2039 window_access_private = VI_ATTR_WIN_ACCESS_PRIV 2040 window_byte_order = VI_ATTR_WIN_BYTE_ORDER 2041 vxi_trigger_support = VI_ATTR_VXI_TRIG_SUPPORT 2042 2043 # GPIB-VXI specific attributes 2044 interface_parent_number = VI_ATTR_INTF_PARENT_NUM 2045 2046 # VXI specific attributes 2047 vxi_device_class = VI_ATTR_VXI_DEV_CLASS # INSTR 2048 vxi_trig_dir = VI_ATTR_VXI_TRIG_DIR # INSTR 2049 vxi_trig_lines_enabled = VI_ATTR_VXI_TRIG_LINES_EN # INSTR 2050 vxi_vme_interrupt_status = VI_ATTR_VXI_VME_INTR_STATUS # BACKPLANE 2051 vxi_trigger_status = VI_ATTR_VXI_TRIG_STATUS # BACKPLANE 2052 vxi_vme_sysfail_state = VI_ATTR_VXI_VME_SYSFAIL_STATE # BACKPLANE 2053 2054 # PXI specific attributes 2055 pxi_device_number = VI_ATTR_PXI_DEV_NUM 2056 pxi_function_num = VI_ATTR_PXI_FUNC_NUM 2057 pxi_bus_number = VI_ATTR_PXI_BUS_NUM 2058 pxi_chassis = VI_ATTR_PXI_CHASSIS 2059 pxi_slotpath = VI_ATTR_PXI_SLOTPATH 2060 pxi_slot_lbus_left = VI_ATTR_PXI_SLOT_LBUS_LEFT 2061 pxi_slot_lbus_right = VI_ATTR_PXI_SLOT_LBUS_RIGHT 2062 pxi_is_express = VI_ATTR_PXI_IS_EXPRESS 2063 pxi_slot_lwidth = VI_ATTR_PXI_SLOT_LWIDTH 2064 pxi_max_ldwidth = VI_ATTR_PXI_MAX_LWIDTH 2065 pxi_actual_ldwidth = VI_ATTR_PXI_ACTUAL_LWIDTH 2066 pxi_dstar_bus = VI_ATTR_PXI_DSTAR_BUS 2067 pxi_dstar_set = VI_ATTR_PXI_DSTAR_SET 2068 pxi_trig_bus = VI_ATTR_PXI_TRIG_BUS 2069 pxi_star_trig_bus = VI_ATTR_PXI_STAR_TRIG_BUS 2070 pxi_star_trig_line = VI_ATTR_PXI_STAR_TRIG_LINE 2071 pxi_source_trigger_bus = VI_ATTR_PXI_SRC_TRIG_BUS 2072 pxi_destination_trigger_bus = VI_ATTR_PXI_DEST_TRIG_BUS 2073 2074 # PXI BAR memory scpecific attributes 2075 pxi_memory_type_bar0 = VI_ATTR_PXI_MEM_TYPE_BAR0 2076 pxi_memory_type_bar1 = VI_ATTR_PXI_MEM_TYPE_BAR1 2077 pxi_memory_type_bar2 = VI_ATTR_PXI_MEM_TYPE_BAR2 2078 pxi_memory_type_bar3 = VI_ATTR_PXI_MEM_TYPE_BAR3 2079 pxi_memory_type_bar4 = VI_ATTR_PXI_MEM_TYPE_BAR4 2080 pxi_memory_type_bar5 = VI_ATTR_PXI_MEM_TYPE_BAR5 2081 2082 pxi_memory_base_bar0 = VI_ATTR_PXI_MEM_BASE_BAR0 2083 pxi_memory_base_bar1 = VI_ATTR_PXI_MEM_BASE_BAR1 2084 pxi_memory_base_bar2 = VI_ATTR_PXI_MEM_BASE_BAR2 2085 pxi_memory_base_bar3 = VI_ATTR_PXI_MEM_BASE_BAR3 2086 pxi_memory_base_bar4 = VI_ATTR_PXI_MEM_BASE_BAR4 2087 pxi_memory_base_bar5 = VI_ATTR_PXI_MEM_BASE_BAR5 2088 pxi_memory_size_bar0 = VI_ATTR_PXI_MEM_SIZE_BAR0 2089 pxi_memory_size_bar1 = VI_ATTR_PXI_MEM_SIZE_BAR1 2090 pxi_memory_size_bar2 = VI_ATTR_PXI_MEM_SIZE_BAR2 2091 pxi_memory_size_bar3 = VI_ATTR_PXI_MEM_SIZE_BAR3 2092 pxi_memory_size_bar4 = VI_ATTR_PXI_MEM_SIZE_BAR4 2093 pxi_memory_size_bar5 = VI_ATTR_PXI_MEM_SIZE_BAR5 2094