1 // Copyright 2008 Dolphin Emulator Project
2 // Licensed under GPLv2+
3 // Refer to the license.txt file included.
4 
5 #include <atomic>
6 #include <cstring>
7 
8 #include "Common/Assert.h"
9 #include "Common/Atomic.h"
10 #include "Common/ChunkFile.h"
11 #include "Common/CommonTypes.h"
12 #include "Common/Flag.h"
13 #include "Common/Logging/Log.h"
14 #include "Core/ConfigManager.h"
15 #include "Core/CoreTiming.h"
16 #include "Core/HW/GPFifo.h"
17 #include "Core/HW/MMIO.h"
18 #include "Core/HW/ProcessorInterface.h"
19 #include "VideoCommon/CommandProcessor.h"
20 #include "VideoCommon/Fifo.h"
21 
22 namespace CommandProcessor
23 {
24 static CoreTiming::EventType* et_UpdateInterrupts;
25 
26 // TODO(ector): Warn on bbox read/write
27 
28 // STATE_TO_SAVE
29 SCPFifoStruct fifo;
30 static UCPStatusReg m_CPStatusReg;
31 static UCPCtrlReg m_CPCtrlReg;
32 static UCPClearReg m_CPClearReg;
33 
34 static u16 m_bboxleft;
35 static u16 m_bboxtop;
36 static u16 m_bboxright;
37 static u16 m_bboxbottom;
38 static u16 m_tokenReg;
39 
40 static Common::Flag s_interrupt_set;
41 static Common::Flag s_interrupt_waiting;
42 
IsOnThread()43 static bool IsOnThread()
44 {
45   return SConfig::GetInstance().bCPUThread;
46 }
47 
UpdateInterrupts_Wrapper(u64 userdata,s64 cyclesLate)48 static void UpdateInterrupts_Wrapper(u64 userdata, s64 cyclesLate)
49 {
50   UpdateInterrupts(userdata);
51 }
52 
DoState(PointerWrap & p)53 void SCPFifoStruct::DoState(PointerWrap& p)
54 {
55   p.Do(CPBase);
56   p.Do(CPEnd);
57   p.Do(CPHiWatermark);
58   p.Do(CPLoWatermark);
59   p.Do(CPReadWriteDistance);
60   p.Do(CPWritePointer);
61   p.Do(CPReadPointer);
62   p.Do(CPBreakpoint);
63   p.Do(SafeCPReadPointer);
64 
65   p.Do(bFF_GPLinkEnable);
66   p.Do(bFF_GPReadEnable);
67   p.Do(bFF_BPEnable);
68   p.Do(bFF_BPInt);
69   p.Do(bFF_Breakpoint);
70 
71   p.Do(bFF_LoWatermarkInt);
72   p.Do(bFF_HiWatermarkInt);
73 
74   p.Do(bFF_LoWatermark);
75   p.Do(bFF_HiWatermark);
76 }
77 
DoState(PointerWrap & p)78 void DoState(PointerWrap& p)
79 {
80   p.DoPOD(m_CPStatusReg);
81   p.DoPOD(m_CPCtrlReg);
82   p.DoPOD(m_CPClearReg);
83   p.Do(m_bboxleft);
84   p.Do(m_bboxtop);
85   p.Do(m_bboxright);
86   p.Do(m_bboxbottom);
87   p.Do(m_tokenReg);
88   fifo.DoState(p);
89 
90   p.Do(s_interrupt_set);
91   p.Do(s_interrupt_waiting);
92 }
93 
WriteLow(volatile u32 & _reg,u16 lowbits)94 static inline void WriteLow(volatile u32& _reg, u16 lowbits)
95 {
96   Common::AtomicStore(_reg, (_reg & 0xFFFF0000) | lowbits);
97 }
WriteHigh(volatile u32 & _reg,u16 highbits)98 static inline void WriteHigh(volatile u32& _reg, u16 highbits)
99 {
100   Common::AtomicStore(_reg, (_reg & 0x0000FFFF) | ((u32)highbits << 16));
101 }
ReadLow(u32 _reg)102 static inline u16 ReadLow(u32 _reg)
103 {
104   return (u16)(_reg & 0xFFFF);
105 }
ReadHigh(u32 _reg)106 static inline u16 ReadHigh(u32 _reg)
107 {
108   return (u16)(_reg >> 16);
109 }
110 
Init()111 void Init()
112 {
113   m_CPStatusReg.Hex = 0;
114   m_CPStatusReg.CommandIdle = 1;
115   m_CPStatusReg.ReadIdle = 1;
116 
117   m_CPCtrlReg.Hex = 0;
118 
119   m_CPClearReg.Hex = 0;
120 
121   m_bboxleft = 0;
122   m_bboxtop = 0;
123   m_bboxright = 640;
124   m_bboxbottom = 480;
125 
126   m_tokenReg = 0;
127 
128   memset(&fifo, 0, sizeof(fifo));
129   fifo.bFF_Breakpoint = 0;
130   fifo.bFF_HiWatermark = 0;
131   fifo.bFF_HiWatermarkInt = 0;
132   fifo.bFF_LoWatermark = 0;
133   fifo.bFF_LoWatermarkInt = 0;
134 
135   s_interrupt_set.Clear();
136   s_interrupt_waiting.Clear();
137 
138   et_UpdateInterrupts = CoreTiming::RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
139 }
140 
GetPhysicalAddressMask()141 u32 GetPhysicalAddressMask()
142 {
143   // Physical addresses in CP seem to ignore some of the upper bits (depending on platform)
144   // This can be observed in CP MMIO registers by setting to 0xffffffff and then reading back.
145   return SConfig::GetInstance().bWii ? 0x1fffffff : 0x03ffffff;
146 }
147 
RegisterMMIO(MMIO::Mapping * mmio,u32 base)148 void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
149 {
150   constexpr u16 WMASK_NONE = 0x0000;
151   constexpr u16 WMASK_ALL = 0xffff;
152   constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
153   const u16 WMASK_HI_RESTRICT = GetPhysicalAddressMask() >> 16;
154 
155   struct
156   {
157     u32 addr;
158     u16* ptr;
159     bool readonly;
160     // FIFO mmio regs in the range [cc000020-cc00003e] have certain bits that always read as 0
161     // For _LO registers in this range, only bits 0xffe0 can be set
162     // For _HI registers in this range, only bits 0x03ff can be set on GCN and 0x1fff on Wii
163     u16 wmask;
164   } directly_mapped_vars[] = {
165       {FIFO_TOKEN_REGISTER, &m_tokenReg, false, WMASK_ALL},
166 
167       // Bounding box registers are read only.
168       {FIFO_BOUNDING_BOX_LEFT, &m_bboxleft, true, WMASK_NONE},
169       {FIFO_BOUNDING_BOX_RIGHT, &m_bboxright, true, WMASK_NONE},
170       {FIFO_BOUNDING_BOX_TOP, &m_bboxtop, true, WMASK_NONE},
171       {FIFO_BOUNDING_BOX_BOTTOM, &m_bboxbottom, true, WMASK_NONE},
172       {FIFO_BASE_LO, MMIO::Utils::LowPart(&fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
173       {FIFO_BASE_HI, MMIO::Utils::HighPart(&fifo.CPBase), false, WMASK_HI_RESTRICT},
174       {FIFO_END_LO, MMIO::Utils::LowPart(&fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
175       {FIFO_END_HI, MMIO::Utils::HighPart(&fifo.CPEnd), false, WMASK_HI_RESTRICT},
176       {FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPHiWatermark), false,
177        WMASK_LO_ALIGN_32BIT},
178       {FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPHiWatermark), false, WMASK_HI_RESTRICT},
179       {FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPLoWatermark), false,
180        WMASK_LO_ALIGN_32BIT},
181       {FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPLoWatermark), false, WMASK_HI_RESTRICT},
182       // FIFO_RW_DISTANCE has some complex read code different for
183       // single/dual core.
184       {FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&fifo.CPWritePointer), false,
185        WMASK_LO_ALIGN_32BIT},
186       {FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&fifo.CPWritePointer), false,
187        WMASK_HI_RESTRICT},
188       // FIFO_READ_POINTER has different code for single/dual core.
189   };
190 
191   for (auto& mapped_var : directly_mapped_vars)
192   {
193     mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
194                    mapped_var.readonly ? MMIO::InvalidWrite<u16>() :
195                                          MMIO::DirectWrite<u16>(mapped_var.ptr, mapped_var.wmask));
196   }
197 
198   mmio->Register(base | FIFO_BP_LO, MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPBreakpoint)),
199                  MMIO::ComplexWrite<u16>([](u32, u16 val) {
200                    WriteLow(fifo.CPBreakpoint, val & WMASK_LO_ALIGN_32BIT);
201                  }));
202   mmio->Register(base | FIFO_BP_HI,
203                  MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPBreakpoint)),
204                  MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
205                    WriteHigh(fifo.CPBreakpoint, val & WMASK_HI_RESTRICT);
206                  }));
207 
208   // Timing and metrics MMIOs are stubbed with fixed values.
209   struct
210   {
211     u32 addr;
212     u16 value;
213   } metrics_mmios[] = {
214       {XF_RASBUSY_L, 0},
215       {XF_RASBUSY_H, 0},
216       {XF_CLKS_L, 0},
217       {XF_CLKS_H, 0},
218       {XF_WAIT_IN_L, 0},
219       {XF_WAIT_IN_H, 0},
220       {XF_WAIT_OUT_L, 0},
221       {XF_WAIT_OUT_H, 0},
222       {VCACHE_METRIC_CHECK_L, 0},
223       {VCACHE_METRIC_CHECK_H, 0},
224       {VCACHE_METRIC_MISS_L, 0},
225       {VCACHE_METRIC_MISS_H, 0},
226       {VCACHE_METRIC_STALL_L, 0},
227       {VCACHE_METRIC_STALL_H, 0},
228       {CLKS_PER_VTX_OUT, 4},
229   };
230   for (auto& metrics_mmio : metrics_mmios)
231   {
232     mmio->Register(base | metrics_mmio.addr, MMIO::Constant<u16>(metrics_mmio.value),
233                    MMIO::InvalidWrite<u16>());
234   }
235 
236   mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
237                    SetCpStatusRegister();
238                    return m_CPStatusReg.Hex;
239                  }),
240                  MMIO::InvalidWrite<u16>());
241 
242   mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex),
243                  MMIO::ComplexWrite<u16>([](u32, u16 val) {
244                    UCPCtrlReg tmp(val);
245                    m_CPCtrlReg.Hex = tmp.Hex;
246                    SetCpControlRegister();
247                    Fifo::RunGpu();
248                  }));
249 
250   mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex),
251                  MMIO::ComplexWrite<u16>([](u32, u16 val) {
252                    UCPClearReg tmp(val);
253                    m_CPClearReg.Hex = tmp.Hex;
254                    SetCpClearRegister();
255                    Fifo::RunGpu();
256                  }));
257 
258   mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
259 
260   // Some MMIOs have different handlers for single core vs. dual core mode.
261   mmio->Register(base | FIFO_RW_DISTANCE_LO,
262                  IsOnThread() ?
263                      MMIO::ComplexRead<u16>([](u32) {
264                        if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
265                          return ReadLow(fifo.CPWritePointer - fifo.SafeCPReadPointer);
266                        else
267                          return ReadLow(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
268                                         fifo.CPBase + 32);
269                      }) :
270                      MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
271                  MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
272                                         WMASK_LO_ALIGN_32BIT));
273   mmio->Register(base | FIFO_RW_DISTANCE_HI,
274                  IsOnThread() ?
275                      MMIO::ComplexRead<u16>([](u32) {
276                        if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
277                          return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer);
278                        else
279                          return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
280                                          fifo.CPBase + 32);
281                      }) :
282                      MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadWriteDistance)),
283                  MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
284                    WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
285                    Fifo::SyncGPU(Fifo::SyncGPUReason::Other);
286                    Fifo::RunGpu();
287                  }));
288   mmio->Register(
289       base | FIFO_READ_POINTER_LO,
290       IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
291                      MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
292       MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
293   mmio->Register(
294       base | FIFO_READ_POINTER_HI,
295       IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.SafeCPReadPointer)) :
296                      MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)),
297       IsOnThread() ?
298           MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
299             WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
300             fifo.SafeCPReadPointer = fifo.CPReadPointer;
301           }) :
302           MMIO::DirectWrite<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer), WMASK_HI_RESTRICT));
303 }
304 
GatherPipeBursted()305 void GatherPipeBursted()
306 {
307   SetCPStatusFromCPU();
308 
309   // if we aren't linked, we don't care about gather pipe data
310   if (!m_CPCtrlReg.GPLinkEnable)
311   {
312     if (IsOnThread() && !Fifo::UseDeterministicGPUThread())
313     {
314       // In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
315       // Fix Pokemon XD in DC mode.
316       if ((ProcessorInterface::Fifo_CPUEnd == fifo.CPEnd) &&
317           (ProcessorInterface::Fifo_CPUBase == fifo.CPBase) && fifo.CPReadWriteDistance > 0)
318       {
319         Fifo::FlushGpu();
320       }
321     }
322     Fifo::RunGpu();
323     return;
324   }
325 
326   // update the fifo pointer
327   if (fifo.CPWritePointer == fifo.CPEnd)
328     fifo.CPWritePointer = fifo.CPBase;
329   else
330     fifo.CPWritePointer += GATHER_PIPE_SIZE;
331 
332   if (m_CPCtrlReg.GPReadEnable && m_CPCtrlReg.GPLinkEnable)
333   {
334     ProcessorInterface::Fifo_CPUWritePointer = fifo.CPWritePointer;
335     ProcessorInterface::Fifo_CPUBase = fifo.CPBase;
336     ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
337   }
338 
339   // If the game is running close to overflowing, make the exception checking more frequent.
340   if (fifo.bFF_HiWatermark)
341     CoreTiming::ForceExceptionCheck(0);
342 
343   Common::AtomicAdd(fifo.CPReadWriteDistance, GATHER_PIPE_SIZE);
344 
345   Fifo::RunGpu();
346 
347   ASSERT_MSG(COMMANDPROCESSOR, fifo.CPReadWriteDistance <= fifo.CPEnd - fifo.CPBase,
348              "FIFO is overflowed by GatherPipe !\nCPU thread is too fast!");
349 
350   // check if we are in sync
351   ASSERT_MSG(COMMANDPROCESSOR, fifo.CPWritePointer == ProcessorInterface::Fifo_CPUWritePointer,
352              "FIFOs linked but out of sync");
353   ASSERT_MSG(COMMANDPROCESSOR, fifo.CPBase == ProcessorInterface::Fifo_CPUBase,
354              "FIFOs linked but out of sync");
355   ASSERT_MSG(COMMANDPROCESSOR, fifo.CPEnd == ProcessorInterface::Fifo_CPUEnd,
356              "FIFOs linked but out of sync");
357 }
358 
UpdateInterrupts(u64 userdata)359 void UpdateInterrupts(u64 userdata)
360 {
361   if (userdata)
362   {
363     s_interrupt_set.Set();
364     DEBUG_LOG(COMMANDPROCESSOR, "Interrupt set");
365     ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
366   }
367   else
368   {
369     s_interrupt_set.Clear();
370     DEBUG_LOG(COMMANDPROCESSOR, "Interrupt cleared");
371     ProcessorInterface::SetInterrupt(INT_CAUSE_CP, false);
372   }
373   CoreTiming::ForceExceptionCheck(0);
374   s_interrupt_waiting.Clear();
375   Fifo::RunGpu();
376 }
377 
UpdateInterruptsFromVideoBackend(u64 userdata)378 void UpdateInterruptsFromVideoBackend(u64 userdata)
379 {
380   if (!Fifo::UseDeterministicGPUThread())
381     CoreTiming::ScheduleEvent(0, et_UpdateInterrupts, userdata, CoreTiming::FromThread::NON_CPU);
382 }
383 
IsInterruptWaiting()384 bool IsInterruptWaiting()
385 {
386   return s_interrupt_waiting.IsSet();
387 }
388 
SetCPStatusFromGPU()389 void SetCPStatusFromGPU()
390 {
391   // breakpoint
392   if (fifo.bFF_BPEnable)
393   {
394     if (fifo.CPBreakpoint == fifo.CPReadPointer)
395     {
396       if (!fifo.bFF_Breakpoint)
397       {
398         DEBUG_LOG(COMMANDPROCESSOR, "Hit breakpoint at %i", fifo.CPReadPointer);
399         fifo.bFF_Breakpoint = true;
400       }
401     }
402     else
403     {
404       if (fifo.bFF_Breakpoint)
405         DEBUG_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
406       fifo.bFF_Breakpoint = false;
407     }
408   }
409   else
410   {
411     if (fifo.bFF_Breakpoint)
412       DEBUG_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
413     fifo.bFF_Breakpoint = false;
414   }
415 
416   // overflow & underflow check
417   fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
418   fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
419 
420   bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
421   bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
422   bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
423 
424   bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
425 
426   if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
427   {
428     u64 userdata = interrupt ? 1 : 0;
429     if (IsOnThread())
430     {
431       if (!interrupt || bpInt || undfInt || ovfInt)
432       {
433         // Schedule the interrupt asynchronously
434         s_interrupt_waiting.Set();
435         CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
436       }
437     }
438     else
439     {
440       CommandProcessor::UpdateInterrupts(userdata);
441     }
442   }
443 }
444 
SetCPStatusFromCPU()445 void SetCPStatusFromCPU()
446 {
447   // overflow & underflow check
448   fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
449   fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
450 
451   bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
452   bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
453   bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
454 
455   bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
456 
457   if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
458   {
459     u64 userdata = interrupt ? 1 : 0;
460     if (IsOnThread())
461     {
462       if (!interrupt || bpInt || undfInt || ovfInt)
463       {
464         s_interrupt_set.Set(interrupt);
465         DEBUG_LOG(COMMANDPROCESSOR, "Interrupt set");
466         ProcessorInterface::SetInterrupt(INT_CAUSE_CP, interrupt);
467       }
468     }
469     else
470     {
471       CommandProcessor::UpdateInterrupts(userdata);
472     }
473   }
474 }
475 
SetCpStatusRegister()476 void SetCpStatusRegister()
477 {
478   // Here always there is one fifo attached to the GPU
479   m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
480   m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || (fifo.CPReadPointer == fifo.CPWritePointer);
481   m_CPStatusReg.CommandIdle =
482       !fifo.CPReadWriteDistance || Fifo::AtBreakpoint() || !fifo.bFF_GPReadEnable;
483   m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark;
484   m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark;
485 
486   DEBUG_LOG(COMMANDPROCESSOR, "\t Read from STATUS_REGISTER : %04x", m_CPStatusReg.Hex);
487   DEBUG_LOG(
488       COMMANDPROCESSOR, "(r) status: iBP %s | fReadIdle %s | fCmdIdle %s | iOvF %s | iUndF %s",
489       m_CPStatusReg.Breakpoint ? "ON" : "OFF", m_CPStatusReg.ReadIdle ? "ON" : "OFF",
490       m_CPStatusReg.CommandIdle ? "ON" : "OFF", m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF",
491       m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF");
492 }
493 
SetCpControlRegister()494 void SetCpControlRegister()
495 {
496   fifo.bFF_BPInt = m_CPCtrlReg.BPInt;
497   fifo.bFF_BPEnable = m_CPCtrlReg.BPEnable;
498   fifo.bFF_HiWatermarkInt = m_CPCtrlReg.FifoOverflowIntEnable;
499   fifo.bFF_LoWatermarkInt = m_CPCtrlReg.FifoUnderflowIntEnable;
500   fifo.bFF_GPLinkEnable = m_CPCtrlReg.GPLinkEnable;
501 
502   if (fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
503   {
504     fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
505     Fifo::FlushGpu();
506   }
507   else
508   {
509     fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
510   }
511 
512   DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | BP %s | Int %s | OvF %s | UndF %s | LINK %s",
513             fifo.bFF_GPReadEnable ? "ON" : "OFF", fifo.bFF_BPEnable ? "ON" : "OFF",
514             fifo.bFF_BPInt ? "ON" : "OFF", m_CPCtrlReg.FifoOverflowIntEnable ? "ON" : "OFF",
515             m_CPCtrlReg.FifoUnderflowIntEnable ? "ON" : "OFF",
516             m_CPCtrlReg.GPLinkEnable ? "ON" : "OFF");
517 }
518 
519 // NOTE: We intentionally don't emulate this function at the moment.
520 // We don't emulate proper GP timing anyway at the moment, so it would just slow down emulation.
SetCpClearRegister()521 void SetCpClearRegister()
522 {
523 }
524 
HandleUnknownOpcode(u8 cmd_byte,void * buffer,bool preprocess)525 void HandleUnknownOpcode(u8 cmd_byte, void* buffer, bool preprocess)
526 {
527   // TODO(Omega): Maybe dump FIFO to file on this error
528   PanicAlertT("GFX FIFO: Unknown Opcode (0x%02x @ %p, %s).\n"
529               "This means one of the following:\n"
530               "* The emulated GPU got desynced, disabling dual core can help\n"
531               "* Command stream corrupted by some spurious memory bug\n"
532               "* This really is an unknown opcode (unlikely)\n"
533               "* Some other sort of bug\n\n"
534               "Further errors will be sent to the Video Backend log and\n"
535               "Dolphin will now likely crash or hang. Enjoy.",
536               cmd_byte, buffer, preprocess ? "preprocess=true" : "preprocess=false");
537 
538   {
539     PanicAlert("Illegal command %02x\n"
540                "CPBase: 0x%08x\n"
541                "CPEnd: 0x%08x\n"
542                "CPHiWatermark: 0x%08x\n"
543                "CPLoWatermark: 0x%08x\n"
544                "CPReadWriteDistance: 0x%08x\n"
545                "CPWritePointer: 0x%08x\n"
546                "CPReadPointer: 0x%08x\n"
547                "CPBreakpoint: 0x%08x\n"
548                "bFF_GPReadEnable: %s\n"
549                "bFF_BPEnable: %s\n"
550                "bFF_BPInt: %s\n"
551                "bFF_Breakpoint: %s\n"
552                "bFF_GPLinkEnable: %s\n"
553                "bFF_HiWatermarkInt: %s\n"
554                "bFF_LoWatermarkInt: %s\n",
555                cmd_byte, fifo.CPBase, fifo.CPEnd, fifo.CPHiWatermark, fifo.CPLoWatermark,
556                fifo.CPReadWriteDistance, fifo.CPWritePointer, fifo.CPReadPointer, fifo.CPBreakpoint,
557                fifo.bFF_GPReadEnable ? "true" : "false", fifo.bFF_BPEnable ? "true" : "false",
558                fifo.bFF_BPInt ? "true" : "false", fifo.bFF_Breakpoint ? "true" : "false",
559                fifo.bFF_GPLinkEnable ? "true" : "false", fifo.bFF_HiWatermarkInt ? "true" : "false",
560                fifo.bFF_LoWatermarkInt ? "true" : "false");
561   }
562 }
563 
564 }  // end of namespace CommandProcessor
565