1 /* 2 * This program source code file is part of KiCad, a free EDA CAD application. 3 * 4 * Copyright (C) 2009-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr 5 * Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, you may find one here: 19 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.html 20 * or you may search the http://www.gnu.org website for the version 2 license, 21 * or you may write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA 23 */ 24 25 #ifndef BOARD_DESIGN_SETTINGS_H_ 26 #define BOARD_DESIGN_SETTINGS_H_ 27 28 #include <memory> 29 30 #include <netclass.h> 31 #include <config_params.h> 32 #include <board_stackup_manager/board_stackup.h> 33 #include <drc/drc_engine.h> 34 #include <settings/nested_settings.h> 35 #include <widgets/ui_common.h> 36 #include <zone_settings.h> 37 38 39 #define DEFAULT_SILK_LINE_WIDTH 0.12 40 #define DEFAULT_COPPER_LINE_WIDTH 0.20 41 #define DEFAULT_EDGE_WIDTH 0.05 42 #define DEFAULT_COURTYARD_WIDTH 0.05 43 #define DEFAULT_LINE_WIDTH 0.10 44 45 #define DEFAULT_SILK_TEXT_SIZE 1.0 46 #define DEFAULT_COPPER_TEXT_SIZE 1.5 47 #define DEFAULT_TEXT_SIZE 1.0 48 49 #define DEFAULT_SILK_TEXT_WIDTH 0.15 50 #define DEFAULT_COPPER_TEXT_WIDTH 0.30 51 #define DEFAULT_TEXT_WIDTH 0.15 52 53 #define DEFAULT_DIMENSION_ARROW_LENGTH 50 // mils, for legacy purposes 54 #define DEFAULT_DIMENSION_EXTENSION_OFFSET 0.5 55 56 // Board thickness, mainly for 3D view: 57 #define DEFAULT_BOARD_THICKNESS_MM 1.6 58 59 #define DEFAULT_PCB_EDGE_THICKNESS 0.15 60 61 // soldermask to pad clearance. The default is 0 because usually board houses 62 // create a clearance depending on their fab process: 63 // mask material, color, price ... 64 #define DEFAULT_SOLDERMASK_CLEARANCE 0.0 65 66 // DEFAULT_SOLDERMASK_MIN_WIDTH is only used in Gerber files: soldermask minimum size. 67 // Set to 0, because using non 0 value creates an annoying issue in Gerber files: 68 // pads are no longer identified as pads (Flashed items or regions) 69 // Therefore solder mask min width must be used only in specific cases 70 // for instance for home made boards 71 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0 72 73 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0 74 #define DEFAULT_SOLDERPASTE_RATIO 0.0 75 76 #define DEFAULT_CUSTOMTRACKWIDTH 0.2 77 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125 78 #define DEFAULT_CUSTOMDPAIRGAP 0.18 79 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18 80 81 #define DEFAULT_MINCLEARANCE 0.0 // overall min clearance 82 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value 83 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter 84 #define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter 85 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter 86 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter 87 #define DEFAULT_HOLETOHOLEMIN 0.25 // minimum web thickness between two drilled holes 88 #define DEFAULT_HOLECLEARANCE 0.25 // copper-to-hole clearance (from IPC level A) 89 90 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts 91 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based 92 // on edge cut line thicknesses) should be used. 93 #define DEFAULT_SILKCLEARANCE 0.0 94 95 #define MINIMUM_ERROR_SIZE_MM 0.001 96 #define MAXIMUM_ERROR_SIZE_MM 0.1 97 98 99 /** 100 * Container to handle a stock of specific vias each with unique diameter and drill sizes 101 * in the #BOARD class. 102 */ 103 struct VIA_DIMENSION 104 { 105 int m_Diameter; // <= 0 means use Netclass via diameter 106 int m_Drill; // <= 0 means use Netclass via drill 107 VIA_DIMENSIONVIA_DIMENSION108 VIA_DIMENSION() 109 { 110 m_Diameter = 0; 111 m_Drill = 0; 112 } 113 VIA_DIMENSIONVIA_DIMENSION114 VIA_DIMENSION( int aDiameter, int aDrill ) 115 { 116 m_Diameter = aDiameter; 117 m_Drill = aDrill; 118 } 119 120 bool operator==( const VIA_DIMENSION& aOther ) const 121 { 122 return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill ); 123 } 124 125 bool operator<( const VIA_DIMENSION& aOther ) const 126 { 127 if( m_Diameter != aOther.m_Diameter ) 128 return m_Diameter < aOther.m_Diameter; 129 130 return m_Drill < aOther.m_Drill; 131 } 132 }; 133 134 135 /** 136 * Container to handle a stock of specific differential pairs each with unique track width, 137 * gap and via gap. 138 */ 139 struct DIFF_PAIR_DIMENSION 140 { 141 int m_Width; // <= 0 means use Netclass differential pair width 142 int m_Gap; // <= 0 means use Netclass differential pair gap 143 int m_ViaGap; // <= 0 means use Netclass differential pair via gap 144 DIFF_PAIR_DIMENSIONDIFF_PAIR_DIMENSION145 DIFF_PAIR_DIMENSION() 146 { 147 m_Width = 0; 148 m_Gap = 0; 149 m_ViaGap = 0; 150 } 151 DIFF_PAIR_DIMENSIONDIFF_PAIR_DIMENSION152 DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap ) 153 { 154 m_Width = aWidth; 155 m_Gap = aGap; 156 m_ViaGap = aViaGap; 157 } 158 159 bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const 160 { 161 return ( m_Width == aOther.m_Width ) 162 && ( m_Gap == aOther.m_Gap ) 163 && ( m_ViaGap == aOther.m_ViaGap ); 164 } 165 166 bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const 167 { 168 if( m_Width != aOther.m_Width ) 169 return m_Width < aOther.m_Width; 170 171 if( m_Gap != aOther.m_Gap ) 172 return m_Gap < aOther.m_Gap; 173 174 return m_ViaGap < aOther.m_ViaGap; 175 } 176 }; 177 178 179 enum 180 { 181 LAYER_CLASS_SILK = 0, 182 LAYER_CLASS_COPPER, 183 LAYER_CLASS_EDGES, 184 LAYER_CLASS_COURTYARD, 185 LAYER_CLASS_FAB, 186 LAYER_CLASS_OTHERS, 187 188 LAYER_CLASS_COUNT 189 }; 190 191 192 struct TEXT_ITEM_INFO 193 { 194 wxString m_Text; 195 bool m_Visible; 196 int m_Layer; 197 TEXT_ITEM_INFOTEXT_ITEM_INFO198 TEXT_ITEM_INFO( const wxString& aText, bool aVisible, int aLayer ) 199 { 200 m_Text = aText; 201 m_Visible = aVisible; 202 m_Layer = aLayer; 203 } 204 }; 205 206 207 // forward declaration from class_track.h 208 enum class VIATYPE : int; 209 210 // forward declarations from dimension.h 211 enum class DIM_UNITS_FORMAT : int; 212 enum class DIM_TEXT_POSITION : int; 213 enum class DIM_UNITS_MODE : int; 214 215 class PAD; 216 217 /** 218 * Container for design settings for a #BOARD object. 219 */ 220 class BOARD_DESIGN_SETTINGS : public NESTED_SETTINGS 221 { 222 public: 223 BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath ); 224 225 virtual ~BOARD_DESIGN_SETTINGS(); 226 227 BOARD_DESIGN_SETTINGS( const BOARD_DESIGN_SETTINGS& aOther); 228 229 BOARD_DESIGN_SETTINGS& operator=( const BOARD_DESIGN_SETTINGS& aOther ); 230 231 bool LoadFromFile( const wxString& aDirectory = "" ) override; 232 GetStackupDescriptor()233 BOARD_STACKUP& GetStackupDescriptor() { return m_stackup; } GetStackupDescriptor()234 const BOARD_STACKUP& GetStackupDescriptor() const { return m_stackup; } 235 236 SEVERITY GetSeverity( int aDRCErrorCode ); 237 238 /** 239 * Return true if the DRC error code's severity is SEVERITY_IGNORE. 240 */ 241 bool Ignore( int aDRCErrorCode ); 242 GetNetClasses()243 NETCLASSES& GetNetClasses() const 244 { 245 return *m_netClasses; 246 } 247 SetNetClasses(NETCLASSES * aNetClasses)248 void SetNetClasses( NETCLASSES* aNetClasses ) 249 { 250 if( aNetClasses ) 251 m_netClasses = aNetClasses; 252 else 253 m_netClasses = &m_internalNetClasses; 254 } 255 GetDefaultZoneSettings()256 ZONE_SETTINGS& GetDefaultZoneSettings() 257 { 258 return m_defaultZoneSettings; 259 } 260 SetDefaultZoneSettings(const ZONE_SETTINGS & aSettings)261 void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings ) 262 { 263 m_defaultZoneSettings = aSettings; 264 } 265 266 /** 267 * @return the default netclass. 268 */ GetDefault()269 inline NETCLASS* GetDefault() const 270 { 271 return GetNetClasses().GetDefaultPtr(); 272 } 273 274 /** 275 * @return the current net class name. 276 */ GetCurrentNetClassName()277 inline const wxString& GetCurrentNetClassName() const 278 { 279 return m_currentNetClassName; 280 } 281 282 /** 283 * Return true if netclass values should be used to obtain appropriate track width. 284 */ UseNetClassTrack()285 inline bool UseNetClassTrack() const 286 { 287 return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia ); 288 } 289 290 /** 291 * Return true if netclass values should be used to obtain appropriate via size. 292 */ UseNetClassVia()293 inline bool UseNetClassVia() const 294 { 295 return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia ); 296 } 297 298 /** 299 * Return true if netclass values should be used to obtain appropriate diff pair dimensions. 300 */ UseNetClassDiffPair()301 inline bool UseNetClassDiffPair() const 302 { 303 return ( m_diffPairIndex == 0 && !m_useCustomDiffPair ); 304 } 305 306 /** 307 * @return the biggest clearance value found in NetClasses list. 308 */ 309 int GetBiggestClearanceValue() const; 310 311 /** 312 * @return the smallest clearance value found in NetClasses list. 313 */ 314 int GetSmallestClearanceValue() const; 315 316 /** 317 * @return the current micro via size that is the current netclass value. 318 */ 319 int GetCurrentMicroViaSize(); 320 321 /** 322 * @return the current micro via drill that is the current netclass value. 323 */ 324 int GetCurrentMicroViaDrill(); 325 326 /** 327 * @return the current track width list index. 328 */ GetTrackWidthIndex()329 inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; } 330 331 /** 332 * Set the current track width list index to \a aIndex. 333 * 334 * @param aIndex is the track width list index. 335 */ 336 void SetTrackWidthIndex( unsigned aIndex ); 337 338 /** 339 * @return the current track width according to the selected options 340 * ( using the default netclass value or a preset/custom value ) 341 * the default netclass is always in m_TrackWidthList[0] 342 */ 343 int GetCurrentTrackWidth() const; 344 345 /** 346 * Sets custom width for track (i.e. not available in netclasses or preset list). 347 * 348 * To have it returned with GetCurrentTrackWidth() you need to enable custom track & 349 * via sizes with #UseCustomTrackViaSize(). 350 * 351 * @param aWidth is the new track width. 352 */ SetCustomTrackWidth(int aWidth)353 inline void SetCustomTrackWidth( int aWidth ) 354 { 355 m_customTrackWidth = aWidth; 356 } 357 358 /** 359 * @return Current custom width for a track. 360 */ GetCustomTrackWidth()361 inline int GetCustomTrackWidth() const 362 { 363 return m_customTrackWidth; 364 } 365 366 /** 367 * @return the current via size list index. 368 */ GetViaSizeIndex()369 inline unsigned GetViaSizeIndex() const 370 { 371 return m_viaSizeIndex; 372 } 373 374 /** 375 * Set the current via size list index to \a aIndex. 376 * 377 * @param aIndex is the via size list index. 378 */ 379 void SetViaSizeIndex( unsigned aIndex ); 380 381 /** 382 * @return the current via size, according to the selected options 383 * ( using the default netclass value or a preset/custom value ) 384 * the default netclass is always in m_TrackWidthList[0] 385 */ 386 int GetCurrentViaSize() const; 387 388 /** 389 * Set custom size for via diameter (i.e. not available in netclasses or preset list). 390 * 391 * To have it returned with GetCurrentViaSize() you need to enable custom track & via sizes 392 * with #UseCustomTrackViaSize(). 393 * 394 * @param aSize is the new drill diameter. 395 */ SetCustomViaSize(int aSize)396 inline void SetCustomViaSize( int aSize ) 397 { 398 m_customViaSize.m_Diameter = aSize; 399 } 400 401 /** 402 * @return Current custom size for the via diameter. 403 */ GetCustomViaSize()404 inline int GetCustomViaSize() const 405 { 406 return m_customViaSize.m_Diameter; 407 } 408 409 /** 410 * @return the current via size, according to the selected options 411 * ( using the default netclass value or a preset/custom value ) 412 * the default netclass is always in m_TrackWidthList[0]. 413 */ 414 int GetCurrentViaDrill() const; 415 416 /** 417 * Sets custom size for via drill (i.e. not available in netclasses or preset list). 418 * 419 * To have it returned with GetCurrentViaDrill() you need to enable custom track & via 420 * sizes with #UseCustomTrackViaSize(). 421 * 422 * @param aDrill is the new drill size. 423 */ SetCustomViaDrill(int aDrill)424 inline void SetCustomViaDrill( int aDrill ) 425 { 426 m_customViaSize.m_Drill = aDrill; 427 } 428 429 /** 430 * @return Current custom size for the via drill. 431 */ GetCustomViaDrill()432 inline int GetCustomViaDrill() const 433 { 434 return m_customViaSize.m_Drill; 435 } 436 437 /** 438 * Enables/disables custom track/via size settings. 439 * 440 * If enabled, values set with #SetCustomTrackWidth(), #SetCustomViaSize(), 441 * and #SetCustomViaDrill() are used for newly created tracks and vias. 442 * 443 * @param aEnabled decides if custom settings should be used for new tracks/vias. 444 */ UseCustomTrackViaSize(bool aEnabled)445 inline void UseCustomTrackViaSize( bool aEnabled ) 446 { 447 m_useCustomTrackVia = aEnabled; 448 } 449 450 /** 451 * @return True if custom sizes of tracks & vias are enabled, false otherwise. 452 */ UseCustomTrackViaSize()453 inline bool UseCustomTrackViaSize() const 454 { 455 return m_useCustomTrackVia; 456 } 457 458 /** 459 * @return the current diff pair dimension list index. 460 */ GetDiffPairIndex()461 inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; } 462 463 /** 464 * @param aIndex is the diff pair dimensions list index to set. 465 */ 466 void SetDiffPairIndex( unsigned aIndex ); 467 468 /** 469 * Sets custom track width for differential pairs (i.e. not available in netclasses or 470 * preset list). 471 * 472 * @param aDrill is the new track wdith. 473 */ SetCustomDiffPairWidth(int aWidth)474 inline void SetCustomDiffPairWidth( int aWidth ) 475 { 476 m_customDiffPair.m_Width = aWidth; 477 } 478 479 /** 480 * @return Current custom track width for differential pairs. 481 */ GetCustomDiffPairWidth()482 inline int GetCustomDiffPairWidth() 483 { 484 return m_customDiffPair.m_Width; 485 } 486 487 /** 488 * Sets custom gap for differential pairs (i.e. not available in netclasses or preset 489 * list). 490 * @param aGap is the new gap. 491 */ SetCustomDiffPairGap(int aGap)492 inline void SetCustomDiffPairGap( int aGap ) 493 { 494 m_customDiffPair.m_Gap = aGap; 495 } 496 497 /** 498 * Function GetCustomDiffPairGap 499 * @return Current custom gap width for differential pairs. 500 */ GetCustomDiffPairGap()501 inline int GetCustomDiffPairGap() 502 { 503 return m_customDiffPair.m_Gap; 504 } 505 506 /** 507 * Sets custom via gap for differential pairs (i.e. not available in netclasses or 508 * preset list). 509 * 510 * @param aGap is the new gap. Specify 0 to use the DiffPairGap for vias as well. 511 */ SetCustomDiffPairViaGap(int aGap)512 inline void SetCustomDiffPairViaGap( int aGap ) 513 { 514 m_customDiffPair.m_ViaGap = aGap; 515 } 516 517 /** 518 * @return Current custom via gap width for differential pairs. 519 */ GetCustomDiffPairViaGap()520 inline int GetCustomDiffPairViaGap() 521 { 522 return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap; 523 } 524 525 /** 526 * Enables/disables custom differential pair dimensions. 527 * 528 * @param aEnabled decides if custom settings should be used for new differential pairs. 529 */ UseCustomDiffPairDimensions(bool aEnabled)530 inline void UseCustomDiffPairDimensions( bool aEnabled ) 531 { 532 m_useCustomDiffPair = aEnabled; 533 } 534 535 /** 536 * @return True if custom sizes of diff pairs are enabled, false otherwise. 537 */ UseCustomDiffPairDimensions()538 inline bool UseCustomDiffPairDimensions() const 539 { 540 return m_useCustomDiffPair; 541 } 542 543 /** 544 * @return the current diff pair track width, according to the selected options 545 * ( using the default netclass value or a preset/custom value ) 546 */ 547 int GetCurrentDiffPairWidth() const; 548 549 /** 550 * @return the current diff pair gap, according to the selected options 551 * ( using the default netclass value or a preset/custom value ) 552 */ 553 int GetCurrentDiffPairGap() const; 554 555 /** 556 * @return the current diff pair via gap, according to the selected options 557 * ( using the default netclass value or a preset/custom value ) 558 * the default netclass is always in m_DiffPairDimensionsList[0]. 559 */ 560 int GetCurrentDiffPairViaGap() const; 561 562 /** 563 * @param aValue The minimum distance between the edges of two holes or 0 to disable 564 * hole-to-hole separation checking. 565 */ 566 void SetMinHoleSeparation( int aDistance ); 567 568 /** 569 * @param aValue The minimum distance between copper items and board edges. 570 */ 571 void SetCopperEdgeClearance( int aDistance ); 572 573 /** 574 * Set the minimum distance between silk items to \a aValue. 575 * 576 * @note Compound graphics within a single footprint or on the board are not checked, 577 * but distances between text and between graphics from different footprints are. 578 * 579 * @param aValue The minimum distance between silk items. 580 */ 581 void SetSilkClearance( int aDistance ); 582 583 /** 584 * Return a bit-mask of all the layers that are enabled. 585 * 586 * @return the enabled layers in bit-mapped form. 587 */ GetEnabledLayers()588 inline LSET GetEnabledLayers() const 589 { 590 return m_enabledLayers; 591 } 592 593 /** 594 * Change the bit-mask of enabled layers to \a aMask. 595 * 596 * @param aMask = The new bit-mask of enabled layers. 597 */ 598 void SetEnabledLayers( LSET aMask ); 599 600 /** 601 * Test whether a given layer \a aLayerId is enabled. 602 * 603 * @param aLayerId The layer to be tested. 604 * @return true if the layer is enabled. 605 */ IsLayerEnabled(PCB_LAYER_ID aLayerId)606 inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const 607 { 608 if( aLayerId >= 0 && aLayerId < PCB_LAYER_ID_COUNT ) 609 return m_enabledLayers[aLayerId]; 610 611 return false; 612 } 613 614 /** 615 * @return the number of enabled copper layers. 616 */ GetCopperLayerCount()617 inline int GetCopperLayerCount() const 618 { 619 return m_copperLayerCount; 620 } 621 622 /** 623 * Set the copper layer count to \a aNewLayerCount. 624 * 625 * @param aNewLayerCount The new number of enabled copper layers. 626 */ 627 void SetCopperLayerCount( int aNewLayerCount ); 628 GetBoardThickness()629 inline int GetBoardThickness() const { return m_boardThickness; } SetBoardThickness(int aThickness)630 inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; } 631 632 /* 633 * Return an epsilon which accounts for rounding errors, etc. 634 * 635 * While currently an advanced cfg, going through this API allows us to easily change 636 * it to board-specific if so desired. 637 */ 638 int GetDRCEpsilon() const; 639 640 /** 641 * Pad & via drills are finish size. 642 * 643 * Adding the hole plating thickness gives you the actual hole size. 644 */ 645 int GetHolePlatingThickness() const; 646 647 /** 648 * Return the default graphic segment thickness from the layer class for the given layer. 649 */ 650 int GetLineThickness( PCB_LAYER_ID aLayer ) const; 651 652 /** 653 * Return the default text size from the layer class for the given layer. 654 */ 655 wxSize GetTextSize( PCB_LAYER_ID aLayer ) const; 656 657 /** 658 * Return the default text thickness from the layer class for the given layer. 659 */ 660 int GetTextThickness( PCB_LAYER_ID aLayer ) const; 661 662 bool GetTextItalic( PCB_LAYER_ID aLayer ) const; 663 bool GetTextUpright( PCB_LAYER_ID aLayer ) const; 664 665 int GetLayerClass( PCB_LAYER_ID aLayer ) const; 666 SetAuxOrigin(const wxPoint & aOrigin)667 void SetAuxOrigin( const wxPoint& aOrigin ) { m_auxOrigin = aOrigin; } GetAuxOrigin()668 const wxPoint& GetAuxOrigin() { return m_auxOrigin; } 669 SetGridOrigin(const wxPoint & aOrigin)670 void SetGridOrigin( const wxPoint& aOrigin ) { m_gridOrigin = aOrigin; } GetGridOrigin()671 const wxPoint& GetGridOrigin() { return m_gridOrigin; } 672 673 private: 674 void initFromOther( const BOARD_DESIGN_SETTINGS& aOther ); 675 676 bool migrateSchema0to1(); 677 678 public: 679 // Note: the first value in each dimensions list is the current netclass value 680 std::vector<int> m_TrackWidthList; 681 std::vector<VIA_DIMENSION> m_ViasDimensionsList; 682 std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList; 683 684 bool m_MicroViasAllowed; ///< true to allow micro vias 685 bool m_BlindBuriedViaAllowed; ///< true to allow blind/buried vias 686 VIATYPE m_CurrentViaType; ///< (VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA) 687 688 bool m_UseConnectedTrackWidth; // use width of existing track when creating a new, 689 // connected track 690 bool m_TempOverrideTrackWidth; // use selected track width temporarily even when 691 // using connected track width 692 int m_MinClearance; // overall min clearance 693 int m_TrackMinWidth; // overall min track width 694 int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring 695 int m_ViasMinSize; // overall vias (not micro vias) min diameter 696 int m_MinThroughDrill; // through hole (not micro vias) min drill diameter 697 int m_MicroViasMinSize; // micro vias min diameter 698 int m_MicroViasMinDrill; // micro vias min drill diameter 699 int m_CopperEdgeClearance; 700 int m_HoleClearance; // Hole to copper clearance 701 int m_HoleToHoleMin; // Min width of web between two drilled holes 702 int m_SilkClearance; 703 704 std::shared_ptr<DRC_ENGINE> m_DRCEngine; 705 std::map<int, SEVERITY> m_DRCSeverities; // Map from DRCErrorCode to SEVERITY 706 std::set<wxString> m_DrcExclusions; 707 708 /** 709 * Option to select different fill algorithms. 710 * 711 * There are currently two supported values: 712 * 5: 713 * - Use thick outlines around filled polygons (gives smoothest shape but at the expense 714 * of processing time and slight infidelity when exporting) 715 * - Use zone outline when knocking out higher-priority zones (just wrong, but mimics 716 * legacy behavior. 717 * 6: 718 * - No thick outline. 719 * - Use filled areas when knocking out higher-priority zones. 720 */ 721 int m_ZoneFillVersion; 722 723 // When smoothing the zone's outline there's the question of external fillets (that is, those 724 // applied to concave corners). While it seems safer to never have copper extend outside the 725 // zone outline, 5.1.x and prior did indeed fill them so we leave the mode available. 726 bool m_ZoneKeepExternalFillets; 727 728 // Maximum error allowed when approximating circles and arcs to segments 729 int m_MaxError; 730 731 // Global mask margins: 732 int m_SolderMaskMargin; // Solder mask margin 733 int m_SolderMaskMinWidth; // Solder mask min width (2 areas closer than this 734 // width are merged) 735 int m_SolderPasteMargin; // Solder paste margin absolute value 736 double m_SolderPasteMarginRatio; // Solder mask margin ratio value of pad size 737 // The final margin is the sum of these 2 values 738 739 // Variables used in footprint editing (default value in item/footprint creation) 740 std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems; 741 742 // Arrays of default values for the various layer classes. 743 int m_LineThickness[ LAYER_CLASS_COUNT ]; 744 wxSize m_TextSize[ LAYER_CLASS_COUNT ]; 745 int m_TextThickness[ LAYER_CLASS_COUNT ]; 746 bool m_TextItalic[ LAYER_CLASS_COUNT ]; 747 bool m_TextUpright[ LAYER_CLASS_COUNT ]; 748 749 // Default values for dimension objects 750 DIM_UNITS_MODE m_DimensionUnitsMode; 751 int m_DimensionPrecision; ///< Number of digits after the decimal 752 DIM_UNITS_FORMAT m_DimensionUnitsFormat; 753 bool m_DimensionSuppressZeroes; 754 DIM_TEXT_POSITION m_DimensionTextPosition; 755 bool m_DimensionKeepTextAligned; 756 int m_DimensionArrowLength; 757 int m_DimensionExtensionOffset; 758 759 // Miscellaneous 760 std::unique_ptr<PAD> m_Pad_Master; // A dummy pad to store all default parameters 761 // when importing values or creating a new pad 762 763 // Set to true if the board has a stackup management. 764 // If not set a default basic stackup will be used to generate the gbrjob file. 765 // Could be removed later, or at least always set to true 766 bool m_HasStackup; 767 768 /// Enable inclusion of stackup height in track length measurements and length tuning 769 bool m_UseHeightForLengthCalcs; 770 771 private: 772 wxPoint m_auxOrigin; ///< origin for plot exports 773 wxPoint m_gridOrigin; ///< origin for grid offsets 774 775 // Indices into the trackWidth, viaSizes and diffPairDimensions lists. 776 // The 0 index is always the current netclass value(s) 777 unsigned m_trackWidthIndex; 778 unsigned m_viaSizeIndex; 779 unsigned m_diffPairIndex; 780 781 // Custom values for track/via sizes (specified via dialog instead of netclass or lists) 782 bool m_useCustomTrackVia; 783 int m_customTrackWidth; 784 VIA_DIMENSION m_customViaSize; 785 786 // Custom values for differential pairs (specified via dialog instead of netclass/lists) 787 bool m_useCustomDiffPair; 788 DIFF_PAIR_DIMENSION m_customDiffPair; 789 790 int m_copperLayerCount; ///< Number of copper layers for this design 791 792 LSET m_enabledLayers; ///< Bit-mask for layer enabling 793 794 int m_boardThickness; ///< Board thickness for 3D viewer 795 796 /// Current net class name used to display netclass info. 797 /// This is also the last used netclass after starting a track. 798 wxString m_currentNetClassName; 799 800 /** the description of layers stackup, for board fabrication 801 * only physical layers are in layers stackup. 802 * It includes not only layers enabled for the board edition, but also dielectric layers 803 */ 804 BOARD_STACKUP m_stackup; 805 806 /// Net classes that are loaded from the board file before these were stored in the project 807 NETCLASSES m_internalNetClasses; 808 809 /// This will point to m_internalNetClasses until it is repointed to the project after load 810 NETCLASSES* m_netClasses; 811 812 /// The default settings that will be used for new zones 813 ZONE_SETTINGS m_defaultZoneSettings; 814 }; 815 816 #endif // BOARD_DESIGN_SETTINGS_H_ 817