1 /* Definitions of target machine for GNU compiler. 2 Sun 68000/68020 version. 3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 4 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 /* We need to have MOTOROLA always defined (either 0 or 1) because we use 24 if-statements and ?: on it. This way we have compile-time error checking 25 for both the MOTOROLA and MIT code paths. We do rely on the host compiler 26 to optimize away all constant tests. */ 27 #ifdef MOTOROLA 28 # undef MOTOROLA 29 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */ 30 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") 31 #else 32 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") 33 # define MOTOROLA 0 /* Use the MIT assembly syntax. */ 34 #endif 35 36 /* Note that some other tm.h files include this one and then override 37 many of the definitions that relate to assembler syntax. */ 38 39 /* Target CPU builtins. */ 40 #define TARGET_CPU_CPP_BUILTINS() \ 41 do \ 42 { \ 43 builtin_define ("__m68k__"); \ 44 builtin_define_std ("mc68000"); \ 45 if (TARGET_68040_ONLY) \ 46 { \ 47 if (TARGET_68060) \ 48 builtin_define_std ("mc68060"); \ 49 else \ 50 builtin_define_std ("mc68040"); \ 51 } \ 52 else if (TARGET_68060) /* -m68020-60 */ \ 53 { \ 54 builtin_define_std ("mc68060"); \ 55 builtin_define_std ("mc68040"); \ 56 builtin_define_std ("mc68030"); \ 57 builtin_define_std ("mc68020"); \ 58 } \ 59 else if (TARGET_68040) /* -m68020-40 */ \ 60 { \ 61 builtin_define_std ("mc68040"); \ 62 builtin_define_std ("mc68030"); \ 63 builtin_define_std ("mc68020"); \ 64 } \ 65 else if (TARGET_68030) \ 66 builtin_define_std ("mc68030"); \ 67 else if (TARGET_68020) \ 68 builtin_define_std ("mc68020"); \ 69 if (TARGET_68881) \ 70 builtin_define ("__HAVE_68881__"); \ 71 if (TARGET_CPU32) \ 72 { \ 73 builtin_define_std ("mc68332"); \ 74 builtin_define_std ("mcpu32"); \ 75 } \ 76 if (TARGET_COLDFIRE) \ 77 builtin_define ("__mcoldfire__"); \ 78 if (TARGET_5200) \ 79 builtin_define ("__mcf5200__"); \ 80 if (TARGET_528x) \ 81 { \ 82 builtin_define ("__mcf528x__"); \ 83 builtin_define ("__mcf5200__"); \ 84 } \ 85 if (TARGET_CFV3) \ 86 { \ 87 builtin_define ("__mcf5300__"); \ 88 builtin_define ("__mcf5307__"); \ 89 } \ 90 if (TARGET_CFV4) \ 91 { \ 92 builtin_define ("__mcf5400__"); \ 93 builtin_define ("__mcf5407__"); \ 94 } \ 95 if (TARGET_CF_HWDIV) \ 96 builtin_define ("__mcfhwdiv__"); \ 97 if (flag_pic) \ 98 { \ 99 builtin_define ("__pic__"); \ 100 if (flag_pic > 1) \ 101 builtin_define ("__PIC__"); \ 102 } \ 103 builtin_assert ("cpu=m68k"); \ 104 builtin_assert ("machine=m68k"); \ 105 } \ 106 while (0) 107 108 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 109 quantities. */ 110 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 111 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 112 #define INT_OP_NO_DOT 2 /* byte, short, long */ 113 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 114 115 /* Set the default */ 116 #define INT_OP_GROUP INT_OP_DOT_WORD 117 118 /* Run-time compilation parameters selecting different hardware subsets. */ 119 120 extern int target_flags; 121 122 /* Macros used in the machine description to test the flags. */ 123 124 /* Compile for a 68020 (not a 68000 or 68010). */ 125 #define MASK_68020 (1<<0) 126 #define TARGET_68020 (target_flags & MASK_68020) 127 128 /* Compile for a 68030. This does not really make a difference in GCC, 129 it just enables the __mc68030__ predefine. */ 130 #define MASK_68030 (1<<1) 131 #define TARGET_68030 (target_flags & MASK_68030) 132 133 /* Optimize for 68040, but still allow execution on 68020 134 (-m68020-40 or -m68040). 135 The 68040 will execute all 68030 and 68881/2 instructions, but some 136 of them must be emulated in software by the OS. When TARGET_68040 is 137 turned on, these instructions won't be used. This code will still 138 run on a 68030 and 68881/2. */ 139 #define MASK_68040 (1<<2) 140 #define TARGET_68040 (target_flags & MASK_68040) 141 142 /* Use the 68040-only fp instructions (-m68040 or -m68060). */ 143 #define MASK_68040_ONLY (1<<3) 144 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY) 145 146 /* Optimize for 68060, but still allow execution on 68020 147 (-m68020-60 or -m68060). 148 The 68060 will execute all 68030 and 68881/2 instructions, but some 149 of them must be emulated in software by the OS. When TARGET_68060 is 150 turned on, these instructions won't be used. This code will still 151 run on a 68030 and 68881/2. */ 152 #define MASK_68060 (1<<4) 153 #define TARGET_68060 (target_flags & MASK_68060) 154 155 /* Compile for mcf5200 */ 156 #define MASK_5200 (1<<5) 157 #define TARGET_5200 (target_flags & MASK_5200) 158 159 /* Build for ColdFire v3 */ 160 #define MASK_CFV3 (1<<6) 161 #define TARGET_CFV3 (target_flags & MASK_CFV3) 162 163 /* Build for ColdFire v4 */ 164 #define MASK_CFV4 (1<<7) 165 #define TARGET_CFV4 (target_flags & MASK_CFV4) 166 167 /* Compile for ColdFire 528x */ 168 #define MASK_528x (1<<8) 169 #define TARGET_528x (target_flags & MASK_528x) 170 171 /* Divide support for ColdFire */ 172 #define MASK_CF_HWDIV (1<<9) 173 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV) 174 175 /* Compile 68881 insns for floating point (not library calls). */ 176 #define MASK_68881 (1<<10) 177 #define TARGET_68881 (target_flags & MASK_68881) 178 179 /* Compile using 68020 bit-field insns. */ 180 #define MASK_BITFIELD (1<<11) 181 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD) 182 183 /* Compile with 16-bit `int'. */ 184 #define MASK_SHORT (1<<12) 185 #define TARGET_SHORT (target_flags & MASK_SHORT) 186 187 /* Align ints to a word boundary. This breaks compatibility with the 188 published ABI's for structures containing ints, but produces faster 189 code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire). 190 It's required for ColdFire cpus without a misalignment module. */ 191 #define MASK_ALIGN_INT (1<<13) 192 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT) 193 194 /* Use PC-relative addressing modes (without using a global offset table). 195 The m68000 supports 16-bit PC-relative addressing. 196 The m68020 supports 32-bit PC-relative addressing 197 (using outer displacements). 198 199 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are 200 treated as all containing an implicit PC-relative component, and hence 201 cannot be used directly as addresses for memory writes. See the comments 202 in m68k.c for more information. */ 203 #define MASK_PCREL (1<<14) 204 #define TARGET_PCREL (target_flags & MASK_PCREL) 205 206 /* Relax strict alignment. */ 207 #define MASK_NO_STRICT_ALIGNMENT (1<<15) 208 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) 209 210 /* Compile using rtd insn calling sequence. 211 This will not work unless you use prototypes at least 212 for all functions that can take varying numbers of args. */ 213 #define MASK_RTD (1<<16) 214 #define TARGET_RTD (target_flags & MASK_RTD) 215 216 /* Support A5 relative data separate from text. 217 * This option implies -fPIC, however it inhibits the generation of the 218 * A5 save/restore in functions and the loading of a5 with a got pointer. 219 */ 220 #define MASK_SEP_DATA (1<<17) 221 #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA) 222 223 /* Compile using library ID based shared libraries. 224 * Set a specific ID using the -mshared-library-id=xxx option. 225 */ 226 #define MASK_ID_SHARED_LIBRARY (1<<18) 227 #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY) 228 229 /* Compile for a CPU32. A 68020 without bitfields is a good 230 heuristic for a CPU32. */ 231 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) 232 233 /* Is the target a ColdFire? */ 234 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4) 235 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE) 236 237 /* Which bits can be set by specifying a ColdFire */ 238 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV) 239 240 /* Macro to define tables used to set the flags. 241 This is a list in braces of pairs in braces, 242 each pair being { "NAME", VALUE } 243 where VALUE is the bits to set or minus the bits to clear. 244 An empty string NAME is used to identify the default VALUE. */ 245 246 #define TARGET_SWITCHES \ 247 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 248 N_("Generate code for a 68020") }, \ 249 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 250 N_("Generate code for a 68020") }, \ 251 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ 252 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ 253 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ 254 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 255 N_("Generate code for a 68000") }, \ 256 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ 257 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 258 N_("Generate code for a 68000") }, \ 259 { "bitfield", MASK_BITFIELD, \ 260 N_("Use the bit-field instructions") }, \ 261 { "nobitfield", - MASK_BITFIELD, \ 262 N_("Do not use the bit-field instructions") }, \ 263 { "short", MASK_SHORT, \ 264 N_("Consider type `int' to be 16 bits wide") }, \ 265 { "noshort", - MASK_SHORT, \ 266 N_("Consider type `int' to be 32 bits wide") }, \ 267 { "68881", MASK_68881, "" }, \ 268 { "soft-float", - MASK_68881, \ 269 N_("Generate code with library calls for floating point") }, \ 270 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \ 271 N_("Generate code for a 68040, without any new instructions") }, \ 272 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ 273 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \ 274 N_("Generate code for a 68060, without any new instructions") }, \ 275 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ 276 |MASK_68060), "" }, \ 277 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ 278 N_("Generate code for a 68030") }, \ 279 { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \ 280 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \ 281 N_("Generate code for a 68040") }, \ 282 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ 283 |MASK_68040_ONLY|MASK_68040), "" }, \ 284 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \ 285 N_("Generate code for a 68060") }, \ 286 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ 287 |MASK_68040_ONLY|MASK_68060), "" }, \ 288 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 289 |MASK_BITFIELD|MASK_68881), \ 290 N_("Generate code for a 520X") }, \ 291 { "5200", (MASK_5200), "" }, \ 292 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 293 |MASK_BITFIELD|MASK_68881), \ 294 N_("Generate code for a 5206e") }, \ 295 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \ 296 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 297 |MASK_BITFIELD|MASK_68881), \ 298 N_("Generate code for a 528x") }, \ 299 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \ 300 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 301 |MASK_BITFIELD|MASK_68881), \ 302 N_("Generate code for a 5307") }, \ 303 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \ 304 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ 305 |MASK_BITFIELD|MASK_68881), \ 306 N_("Generate code for a 5407") }, \ 307 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \ 308 { "68851", 0, \ 309 N_("Generate code for a 68851") }, \ 310 { "no-68851", 0, \ 311 N_("Do no generate code for a 68851") }, \ 312 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ 313 |MASK_68020|MASK_BITFIELD|MASK_68881), \ 314 N_("Generate code for a 68302") }, \ 315 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ 316 |MASK_BITFIELD|MASK_68881), \ 317 N_("Generate code for a 68332") }, \ 318 { "68332", MASK_68020, "" }, \ 319 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ 320 |MASK_BITFIELD|MASK_68881), \ 321 N_("Generate code for a cpu32") }, \ 322 { "cpu32", MASK_68020, "" }, \ 323 { "align-int", MASK_ALIGN_INT, \ 324 N_("Align variables on a 32-bit boundary") }, \ 325 { "no-align-int", -MASK_ALIGN_INT, \ 326 N_("Align variables on a 16-bit boundary") }, \ 327 { "sep-data", MASK_SEP_DATA, \ 328 N_("Enable separate data segment") }, \ 329 { "no-sep-data", -MASK_SEP_DATA, \ 330 N_("Disable separate data segment") }, \ 331 { "id-shared-library", MASK_ID_SHARED_LIBRARY, \ 332 N_("Enable ID based shared library") }, \ 333 { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \ 334 N_("Disable ID based shared library") }, \ 335 { "pcrel", MASK_PCREL, \ 336 N_("Generate pc-relative code") }, \ 337 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \ 338 N_("Do not use unaligned memory references") }, \ 339 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \ 340 N_("Use unaligned memory references") }, \ 341 { "rtd", MASK_RTD, \ 342 N_("Use different calling convention using 'rtd'") }, \ 343 { "nortd", - MASK_RTD, \ 344 N_("Use normal calling convention") }, \ 345 SUBTARGET_SWITCHES \ 346 { "", TARGET_DEFAULT, "" }} 347 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */ 348 349 /* This macro is similar to `TARGET_SWITCHES' but defines names of 350 command options that have values. Its definition is an 351 initializer with a subgrouping for each command option. 352 353 Each subgrouping contains a string constant, that defines the 354 fixed part of the option name, and the address of a variable. The 355 variable, type `char *', is set to the variable part of the given 356 option if the fixed part matches. The actual option name is made 357 by appending `-m' to the specified name. */ 358 #define TARGET_OPTIONS \ 359 { { "align-loops=", &m68k_align_loops_string, \ 360 N_("Loop code aligned to this power of 2"), 0}, \ 361 { "align-jumps=", &m68k_align_jumps_string, \ 362 N_("Jump targets are aligned to this power of 2"), 0}, \ 363 { "align-functions=", &m68k_align_funcs_string, \ 364 N_("Function starts are aligned to this power of 2"), 0}, \ 365 { "shared-library-id=", &m68k_library_id_string, \ 366 N_("ID of shared library to build"), 0}, \ 367 SUBTARGET_OPTIONS \ 368 } 369 370 /* Sometimes certain combinations of command options do not make 371 sense on a particular target machine. You can define a macro 372 `OVERRIDE_OPTIONS' to take account of this. This macro, if 373 defined, is executed once just after all the command options have 374 been parsed. 375 376 Don't use this macro to turn on various extra optimizations for 377 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 378 379 #define OVERRIDE_OPTIONS override_options() 380 381 /* These are meant to be redefined in the host dependent files */ 382 #define SUBTARGET_SWITCHES 383 #define SUBTARGET_OPTIONS 384 #define SUBTARGET_OVERRIDE_OPTIONS 385 386 /* target machine storage layout */ 387 388 /* Define for XFmode extended real floating point support. */ 389 #define LONG_DOUBLE_TYPE_SIZE 96 390 391 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 392 instructions, we get proper intermediate rounding, otherwise we 393 get extended precision results. */ 394 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2) 395 396 /* Define this if most significant bit is lowest numbered 397 in instructions that operate on numbered bit-fields. 398 This is true for 68020 insns such as bfins and bfexts. 399 We make it true always by avoiding using the single-bit insns 400 except in special cases with constant bit numbers. */ 401 #define BITS_BIG_ENDIAN 1 402 403 /* Define this if most significant byte of a word is the lowest numbered. */ 404 /* That is true on the 68000. */ 405 #define BYTES_BIG_ENDIAN 1 406 407 /* Define this if most significant word of a multiword number is the lowest 408 numbered. */ 409 /* For 68000 we can decide arbitrarily 410 since there are no machine instructions for them. 411 So let's be consistent. */ 412 #define WORDS_BIG_ENDIAN 1 413 414 /* Width of a word, in units (bytes). */ 415 #define UNITS_PER_WORD 4 416 417 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 418 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 419 420 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 421 #define STACK_BOUNDARY 16 422 423 /* Allocation boundary (in *bits*) for the code of a function. */ 424 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3)) 425 426 /* Alignment of field after `int : 0' in a structure. */ 427 #define EMPTY_FIELD_BOUNDARY 16 428 429 /* No data type wants to be aligned rounder than this. 430 Most published ABIs say that ints should be aligned on 16 bit 431 boundaries, but cpus with 32-bit busses get better performance 432 aligned on 32-bit boundaries. ColdFires without a misalignment 433 module require 32-bit alignment. */ 434 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 435 436 /* Set this nonzero if move instructions will actually fail to work 437 when given unaligned data. */ 438 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 439 440 /* Maximum power of 2 that code can be aligned to. */ 441 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */ 442 443 /* Maximum number of library ids we permit */ 444 #define MAX_LIBRARY_ID 255 445 446 /* Align loop starts for optimal branching. */ 447 #define LOOP_ALIGN(LABEL) (m68k_align_loops) 448 449 /* This is how to align an instruction for optimal branching. */ 450 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps) 451 452 /* Define number of bits in most basic integer type. 453 (If undefined, default is BITS_PER_WORD). */ 454 455 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 456 457 /* Define these to avoid dependence on meaning of `int'. */ 458 459 #define WCHAR_TYPE "long int" 460 #define WCHAR_TYPE_SIZE 32 461 462 /* Standard register usage. */ 463 464 /* Number of actual hardware registers. 465 The hardware registers are assigned numbers for the compiler 466 from 0 to just below FIRST_PSEUDO_REGISTER. 467 All registers that the compiler knows about must be given numbers, 468 even those that are not normally considered general registers. 469 For the 68000, we give the data registers numbers 0-7, 470 the address registers numbers 010-017, 471 and the 68881 floating point registers numbers 020-027. */ 472 #define FIRST_PSEUDO_REGISTER 25 473 474 /* This defines the register which is used to hold the offset table for PIC. */ 475 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) 476 477 /* 1 for registers that have pervasive standard uses 478 and are not available for the register allocator. 479 On the 68000, only the stack pointer is such. */ 480 481 #define FIXED_REGISTERS \ 482 {/* Data registers. */ \ 483 0, 0, 0, 0, 0, 0, 0, 0, \ 484 \ 485 /* Address registers. */ \ 486 0, 0, 0, 0, 0, 0, 0, 1, \ 487 \ 488 /* Floating point registers \ 489 (if available). */ \ 490 0, 0, 0, 0, 0, 0, 0, 0, \ 491 \ 492 /* Arg pointer. */ \ 493 1 } 494 495 /* 1 for registers not available across function calls. 496 These must include the FIXED_REGISTERS and also any 497 registers that can be used without being saved. 498 The latter must include the registers where values are returned 499 and the register where structure-value addresses are passed. 500 Aside from that, you can include as many other registers as you like. */ 501 #define CALL_USED_REGISTERS \ 502 {1, 1, 0, 0, 0, 0, 0, 0, \ 503 1, 1, 0, 0, 0, 0, 0, 1, \ 504 1, 1, 0, 0, 0, 0, 0, 0, 1 } 505 506 #define REG_ALLOC_ORDER \ 507 { /* d0/d1/a0/a1 */ \ 508 0, 1, 8, 9, \ 509 /* d2-d7 */ \ 510 2, 3, 4, 5, 6, 7, \ 511 /* a2-a7/arg */ \ 512 10, 11, 12, 13, 14, 15, 24, \ 513 /* fp0-fp7 */ \ 514 16, 17, 18, 19, 20, 21, 22, 23\ 515 } 516 517 518 /* Make sure everything's fine if we *don't* have a given processor. 519 This assumes that putting a register in fixed_regs will keep the 520 compiler's mitts completely off it. We don't bother to zero it out 521 of register classes. */ 522 523 #define CONDITIONAL_REGISTER_USAGE \ 524 { \ 525 int i; \ 526 HARD_REG_SET x; \ 527 if (! TARGET_68881) \ 528 { \ 529 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 530 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 531 if (TEST_HARD_REG_BIT (x, i)) \ 532 fixed_regs[i] = call_used_regs[i] = 1; \ 533 } \ 534 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 535 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ 536 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 537 } 538 539 /* Return number of consecutive hard regs needed starting at reg REGNO 540 to hold something of mode MODE. 541 This is ordinarily the length in words of a value of mode MODE 542 but can be less for certain modes in special long registers. 543 544 On the 68000, ordinary registers hold 32 bits worth; 545 for the 68881 registers, a single register is always enough for 546 anything that can be stored in them at all. */ 547 #define HARD_REGNO_NREGS(REGNO, MODE) \ 548 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 549 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 550 551 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 552 On the 68000, the cpu registers can hold any mode but the 68881 registers 553 can hold only SFmode or DFmode. */ 554 555 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 556 (((REGNO) < 16 \ 557 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \ 558 || ((REGNO) >= 16 && (REGNO) < 24 \ 559 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 560 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 561 && GET_MODE_UNIT_SIZE (MODE) <= 12)) 562 563 564 /* Value is 1 if it is a good idea to tie two pseudo registers 565 when one has mode MODE1 and one has mode MODE2. 566 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 567 for any hard reg, then this must be 0 for correct output. */ 568 #define MODES_TIEABLE_P(MODE1, MODE2) \ 569 (! TARGET_68881 \ 570 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 571 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 572 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 573 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 574 575 /* Specify the registers used for certain standard purposes. 576 The values of these macros are register numbers. */ 577 578 /* m68000 pc isn't overloaded on a register. */ 579 /* #define PC_REGNUM */ 580 581 /* Register to use for pushing function arguments. */ 582 #define STACK_POINTER_REGNUM 15 583 584 /* Base register for access to local variables of the function. */ 585 #define FRAME_POINTER_REGNUM 14 586 587 /* Value should be nonzero if functions must have frame pointers. 588 Zero means the frame pointer need not be set up (and parms 589 may be accessed via the stack pointer) in functions that seem suitable. 590 This is computed in `reload', in reload1.c. */ 591 #define FRAME_POINTER_REQUIRED 0 592 593 /* Base register for access to arguments of the function. 594 * This isn't a hardware register. It will be eliminated to the 595 * stack pointer or frame pointer. 596 */ 597 #define ARG_POINTER_REGNUM 24 598 599 /* Register in which static-chain is passed to a function. */ 600 #define STATIC_CHAIN_REGNUM 8 601 602 /* Register in which address to store a structure value 603 is passed to a function. */ 604 #define STRUCT_VALUE_REGNUM 9 605 606 /* Define the classes of registers for register constraints in the 607 machine description. Also define ranges of constants. 608 609 One of the classes must always be named ALL_REGS and include all hard regs. 610 If there is more than one class, another class must be named NO_REGS 611 and contain no registers. 612 613 The name GENERAL_REGS must be the name of a class (or an alias for 614 another name such as ALL_REGS). This is the class of registers 615 that is allowed by "g" or "r" in a register constraint. 616 Also, registers outside this class are allocated only when 617 instructions express preferences for them. 618 619 The classes must be numbered in nondecreasing order; that is, 620 a larger-numbered class must never be contained completely 621 in a smaller-numbered class. 622 623 For any two classes, it is very desirable that there be another 624 class that represents their union. */ 625 626 /* The 68000 has three kinds of registers, so eight classes would be 627 a complete set. One of them is not needed. */ 628 629 enum reg_class { 630 NO_REGS, DATA_REGS, 631 ADDR_REGS, FP_REGS, 632 GENERAL_REGS, DATA_OR_FP_REGS, 633 ADDR_OR_FP_REGS, ALL_REGS, 634 LIM_REG_CLASSES }; 635 636 #define N_REG_CLASSES (int) LIM_REG_CLASSES 637 638 /* Give names of register classes as strings for dump file. */ 639 640 #define REG_CLASS_NAMES \ 641 { "NO_REGS", "DATA_REGS", \ 642 "ADDR_REGS", "FP_REGS", \ 643 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 644 "ADDR_OR_FP_REGS", "ALL_REGS" } 645 646 /* Define which registers fit in which classes. 647 This is an initializer for a vector of HARD_REG_SET 648 of length N_REG_CLASSES. */ 649 650 #define REG_CLASS_CONTENTS \ 651 { \ 652 {0x00000000}, /* NO_REGS */ \ 653 {0x000000ff}, /* DATA_REGS */ \ 654 {0x0100ff00}, /* ADDR_REGS */ \ 655 {0x00ff0000}, /* FP_REGS */ \ 656 {0x0100ffff}, /* GENERAL_REGS */ \ 657 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 658 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ 659 {0x01ffffff}, /* ALL_REGS */ \ 660 } 661 662 /* The same information, inverted: 663 Return the class number of the smallest class containing 664 reg number REGNO. This could be a conditional expression 665 or could index an array. */ 666 667 extern enum reg_class regno_reg_class[]; 668 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) 669 670 /* The class value for index registers, and the one for base regs. */ 671 672 #define INDEX_REG_CLASS GENERAL_REGS 673 #define BASE_REG_CLASS ADDR_REGS 674 675 /* Get reg_class from a letter such as appears in the machine description. 676 We do a trick here to modify the effective constraints on the 677 machine description; we zorch the constraint letters that aren't 678 appropriate for a specific target. This allows us to guarantee 679 that a specific kind of register will not be used for a given target 680 without fiddling with the register classes above. */ 681 682 #define REG_CLASS_FROM_LETTER(C) \ 683 ((C) == 'a' ? ADDR_REGS : \ 684 ((C) == 'd' ? DATA_REGS : \ 685 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 686 NO_REGS) : \ 687 NO_REGS))) 688 689 /* The letters I, J, K, L and M in a register constraint string 690 can be used to stand for particular ranges of immediate operands. 691 This macro defines what the ranges are. 692 C is the letter, and VALUE is a constant value. 693 Return 1 if VALUE is in the range specified by C. 694 695 For the 68000, `I' is used for the range 1 to 8 696 allowed as immediate shift counts and in addq. 697 `J' is used for the range of signed numbers that fit in 16 bits. 698 `K' is for numbers that moveq can't handle. 699 `L' is for range -8 to -1, range of values that can be added with subq. 700 `M' is for numbers that moveq+notb can't handle. 701 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. 702 'O' is for 16 (for rotate using swap). 703 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ 704 705 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 706 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 707 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 708 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 709 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ 710 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ 711 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ 712 (C) == 'O' ? (VALUE) == 16 : \ 713 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) 714 715 /* 716 * A small bit of explanation: 717 * "G" defines all of the floating constants that are *NOT* 68881 718 * constants. this is so 68881 constants get reloaded and the 719 * fpmovecr is used. 720 */ 721 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 722 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) 723 724 /* A C expression that defines the optional machine-dependent constraint 725 letters that can be used to segregate specific types of operands, 726 usually memory references, for the target machine. It should return 1 if 727 VALUE corresponds to the operand type represented by the constraint letter 728 C. If C is not defined as an extra constraint, the value returned should 729 be 0 regardless of VALUE. */ 730 731 /* Letters in the range `Q' through `U' may be defined in a 732 machine-dependent fashion to stand for arbitrary operand types. 733 The machine description macro `EXTRA_CONSTRAINT' is passed the 734 operand as its first argument and the constraint letter as its 735 second operand. 736 737 `Q' means address register indirect addressing mode. 738 `S' is for operands that satisfy 'm' when -mpcrel is in effect. 739 `T' is for operands that satisfy 's' when -mpcrel is not in effect. 740 `U' is for register offset addressing. */ 741 742 #define EXTRA_CONSTRAINT(OP,CODE) \ 743 (((CODE) == 'S') \ 744 ? (TARGET_PCREL \ 745 && GET_CODE (OP) == MEM \ 746 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 747 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ 748 || GET_CODE (XEXP (OP, 0)) == CONST)) \ 749 : \ 750 (((CODE) == 'T') \ 751 ? ( !TARGET_PCREL \ 752 && (GET_CODE (OP) == SYMBOL_REF \ 753 || GET_CODE (OP) == LABEL_REF \ 754 || GET_CODE (OP) == CONST)) \ 755 : \ 756 (((CODE) == 'Q') \ 757 ? (GET_CODE (OP) == MEM \ 758 && GET_CODE (XEXP (OP, 0)) == REG) \ 759 : \ 760 (((CODE) == 'U') \ 761 ? (GET_CODE (OP) == MEM \ 762 && GET_CODE (XEXP (OP, 0)) == PLUS \ 763 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ 764 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ 765 : \ 766 0)))) 767 768 /* Given an rtx X being reloaded into a reg required to be 769 in class CLASS, return the class of reg to actually use. 770 In general this is just CLASS; but on some machines 771 in some cases it is preferable to use a more restrictive class. 772 On the 68000 series, use a data reg if possible when the 773 value is a constant in the range where moveq could be used 774 and we ensure that QImodes are reloaded into data regs. */ 775 776 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 777 ((GET_CODE (X) == CONST_INT \ 778 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 779 && (CLASS) != ADDR_REGS) \ 780 ? DATA_REGS \ 781 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ 782 ? DATA_REGS \ 783 : (GET_CODE (X) == CONST_DOUBLE \ 784 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 785 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ 786 ? FP_REGS : NO_REGS) \ 787 : (TARGET_PCREL \ 788 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 789 || GET_CODE (X) == LABEL_REF)) \ 790 ? ADDR_REGS \ 791 : (CLASS)) 792 793 /* Force QImode output reloads from subregs to be allocated to data regs, 794 since QImode stores from address regs are not supported. We make the 795 assumption that if the class is not ADDR_REGS, then it must be a superset 796 of DATA_REGS. */ 797 798 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 799 (((MODE) == QImode && (CLASS) != ADDR_REGS) \ 800 ? DATA_REGS \ 801 : (CLASS)) 802 803 /* Return the maximum number of consecutive registers 804 needed to represent mode MODE in a register of class CLASS. */ 805 /* On the 68000, this is the size of MODE in words, 806 except in the FP regs, where a single reg is always enough. */ 807 #define CLASS_MAX_NREGS(CLASS, MODE) \ 808 ((CLASS) == FP_REGS ? 1 \ 809 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 810 811 /* Moves between fp regs and other regs are two insns. */ 812 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 813 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 814 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 815 ? 4 : 2) 816 817 /* Stack layout; function entry, exit and calling. */ 818 819 /* Define this if pushing a word on the stack 820 makes the stack pointer a smaller address. */ 821 #define STACK_GROWS_DOWNWARD 822 823 /* Define this if the nominal address of the stack frame 824 is at the high-address end of the local variables; 825 that is, each additional local variable allocated 826 goes at a more negative offset in the frame. */ 827 #define FRAME_GROWS_DOWNWARD 828 829 /* Offset within stack frame to start allocating local variables at. 830 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 831 first local allocated. Otherwise, it is the offset to the BEGINNING 832 of the first local allocated. */ 833 #define STARTING_FRAME_OFFSET 0 834 835 /* If we generate an insn to push BYTES bytes, 836 this says how many the stack pointer really advances by. 837 On the 68000, sp@- in a byte insn really pushes a word. 838 On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */ 839 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) 840 841 /* We want to avoid trying to push bytes. */ 842 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 843 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ 844 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE))) 845 846 /* Offset of first parameter from the argument pointer register value. */ 847 #define FIRST_PARM_OFFSET(FNDECL) 8 848 849 /* Value is the number of byte of arguments automatically 850 popped when returning from a subroutine call. 851 FUNDECL is the declaration node of the function (as a tree), 852 FUNTYPE is the data type of the function (as a tree), 853 or for a library call it is an identifier node for the subroutine name. 854 SIZE is the number of bytes of arguments passed on the stack. 855 856 On the 68000, the RTS insn cannot pop anything. 857 On the 68010, the RTD insn may be used to pop them if the number 858 of args is fixed, but if the number is variable then the caller 859 must pop them all. RTD can't be used for library calls now 860 because the library is compiled with the Unix compiler. 861 Use of RTD is a selectable option, since it is incompatible with 862 standard Unix calling sequences. If the option is not selected, 863 the caller must always pop the args. */ 864 865 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 866 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ 867 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 868 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ 869 == void_type_node))) \ 870 ? (SIZE) : 0) 871 872 /* Define how to find the value returned by a function. 873 VALTYPE is the data type of the value (as a tree). 874 If the precise function being called is known, FUNC is its FUNCTION_DECL; 875 otherwise, FUNC is 0. */ 876 877 /* On the 68000 the return value is in D0 regardless. */ 878 879 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 880 gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 881 882 /* Define how to find the value returned by a library function 883 assuming the value has mode MODE. */ 884 885 /* On the 68000 the return value is in D0 regardless. */ 886 887 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 888 889 /* 1 if N is a possible register number for a function value. 890 On the 68000, d0 is the only register thus used. */ 891 892 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 893 894 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 895 more than one register. */ 896 897 #define NEEDS_UNTYPED_CALL 0 898 899 /* Define this if PCC uses the nonreentrant convention for returning 900 structure and union values. */ 901 902 #define PCC_STATIC_STRUCT_RETURN 903 904 /* 1 if N is a possible register number for function argument passing. 905 On the 68000, no registers are used in this way. */ 906 907 #define FUNCTION_ARG_REGNO_P(N) 0 908 909 /* Define a data type for recording info about an argument list 910 during the scan of that argument list. This data type should 911 hold all necessary information about the function itself 912 and about the args processed so far, enough to enable macros 913 such as FUNCTION_ARG to determine where the next arg should go. 914 915 On the m68k, this is a single integer, which is a number of bytes 916 of arguments scanned so far. */ 917 918 #define CUMULATIVE_ARGS int 919 920 /* Initialize a variable CUM of type CUMULATIVE_ARGS 921 for a call to a function whose data type is FNTYPE. 922 For a library call, FNTYPE is 0. 923 924 On the m68k, the offset starts at 0. */ 925 926 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 927 ((CUM) = 0) 928 929 /* Update the data in CUM to advance over an argument 930 of mode MODE and data type TYPE. 931 (TYPE is null for libcalls where that information may not be available.) */ 932 933 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 934 ((CUM) += ((MODE) != BLKmode \ 935 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 936 : (int_size_in_bytes (TYPE) + 3) & ~3)) 937 938 /* Define where to put the arguments to a function. 939 Value is zero to push the argument on the stack, 940 or a hard register in which to store the argument. 941 942 MODE is the argument's machine mode. 943 TYPE is the data type of the argument (as a tree). 944 This is null for libcalls where that information may 945 not be available. 946 CUM is a variable of type CUMULATIVE_ARGS which gives info about 947 the preceding args and about the function being called. 948 NAMED is nonzero if this argument is a named parameter 949 (otherwise it is an extra parameter matching an ellipsis). 950 951 On the m68k all args are always pushed. */ 952 953 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 954 955 /* For an arg passed partly in registers and partly in memory, 956 this is the number of registers used. 957 For args passed entirely in registers or entirely in memory, zero. */ 958 959 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 960 961 /* Output assembler code to FILE to increment profiler label # LABELNO 962 for profiling a function entry. */ 963 964 #define FUNCTION_PROFILER(FILE, LABELNO) \ 965 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 966 967 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 968 the stack pointer does not matter. The value is tested only in 969 functions that have frame pointers. 970 No definition is equivalent to always zero. */ 971 972 #define EXIT_IGNORE_STACK 1 973 974 /* This is a hook for other tm files to change. */ 975 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ 976 977 /* Determine if the epilogue should be output as RTL. 978 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 979 #define USE_RETURN_INSN use_return_insn () 980 981 /* Output assembler code for a block containing the constant parts 982 of a trampoline, leaving space for the variable parts. */ 983 984 /* On the 68k, the trampoline looks like this: 985 movl #STATIC,a0 986 jmp FUNCTION 987 988 WARNING: Targets that may run on 68040+ cpus must arrange for 989 the instruction cache to be flushed. Previous incarnations of 990 the m68k trampoline code attempted to get around this by either 991 using an out-of-line transfer function or pc-relative data, but 992 the fact remains that the code to jump to the transfer function 993 or the code to load the pc-relative data needs to be flushed 994 just as much as the "variable" portion of the trampoline. 995 Recognizing that a cache flush is going to be required anyway, 996 dispense with such notions and build a smaller trampoline. */ 997 998 /* Since more instructions are required to move a template into 999 place than to create it on the spot, don't use a template. */ 1000 1001 /* Length in units of the trampoline for entering a nested function. */ 1002 1003 #define TRAMPOLINE_SIZE 12 1004 1005 /* Alignment required for a trampoline in bits. */ 1006 1007 #define TRAMPOLINE_ALIGNMENT 16 1008 1009 /* Targets redefine this to invoke code to either flush the cache, 1010 or enable stack execution (or both). */ 1011 1012 #ifndef FINALIZE_TRAMPOLINE 1013 #define FINALIZE_TRAMPOLINE(TRAMP) 1014 #endif 1015 1016 /* Emit RTL insns to initialize the variable parts of a trampoline. 1017 FNADDR is an RTX for the address of the function's pure code. 1018 CXT is an RTX for the static chain value for the function. 1019 1020 We generate a two-instructions program at address TRAMP : 1021 movea.l &CXT,%a0 1022 jmp FNADDR */ 1023 1024 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1025 { \ 1026 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ 1027 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ 1028 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ 1029 GEN_INT(0x4EF9)); \ 1030 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ 1031 FINALIZE_TRAMPOLINE(TRAMP); \ 1032 } 1033 1034 /* This is the library routine that is used 1035 to transfer control from the trampoline 1036 to the actual nested function. 1037 It is defined for backward compatibility, 1038 for linking with object code that used the old 1039 trampoline definition. */ 1040 1041 /* A colon is used with no explicit operands 1042 to cause the template string to be scanned for %-constructs. */ 1043 /* The function name __transfer_from_trampoline is not actually used. 1044 The function definition just permits use of "asm with operands" 1045 (though the operand list is empty). */ 1046 #define TRANSFER_FROM_TRAMPOLINE \ 1047 void \ 1048 __transfer_from_trampoline () \ 1049 { \ 1050 register char *a0 asm ("%a0"); \ 1051 asm (GLOBAL_ASM_OP "___trampoline"); \ 1052 asm ("___trampoline:"); \ 1053 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 1054 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 1055 asm ("rts":); \ 1056 } 1057 1058 /* Definitions for register eliminations. 1059 1060 This is an array of structures. Each structure initializes one pair 1061 of eliminable registers. The "from" register number is given first, 1062 followed by "to". Eliminations of the same "from" register are listed 1063 in order of preference. 1064 1065 There are two registers that can always be eliminated on the m68k. 1066 The frame pointer and the arg pointer can be replaced by either the 1067 hard frame pointer or to the stack pointer, depending upon the 1068 circumstances. The hard frame pointer is not used before reload and 1069 so it is not eligible for elimination. */ 1070 1071 #define ELIMINABLE_REGS \ 1072 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 1073 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 1074 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 1075 1076 /* Given FROM and TO register numbers, say whether this elimination is 1077 allowed. Frame pointer elimination is automatically handled. 1078 1079 All other eliminations are valid. */ 1080 1081 #define CAN_ELIMINATE(FROM, TO) \ 1082 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1083 1084 /* Define the offset between two registers, one to be eliminated, and the other 1085 its replacement, at the start of a routine. */ 1086 1087 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1088 (OFFSET) = m68k_initial_elimination_offset(FROM, TO) 1089 1090 /* Addressing modes, and classification of registers for them. */ 1091 1092 #define HAVE_POST_INCREMENT 1 1093 1094 #define HAVE_PRE_DECREMENT 1 1095 1096 /* Macros to check register numbers against specific register classes. */ 1097 1098 /* These assume that REGNO is a hard or pseudo reg number. 1099 They give nonzero only if REGNO is a hard reg of the suitable class 1100 or a pseudo reg currently allocated to a suitable hard reg. 1101 Since they use reg_renumber, they are safe only once reg_renumber 1102 has been allocated, which happens in local-alloc.c. */ 1103 1104 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1105 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 1106 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1107 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 1108 #define REGNO_OK_FOR_DATA_P(REGNO) \ 1109 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 1110 #define REGNO_OK_FOR_FP_P(REGNO) \ 1111 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 1112 1113 /* Now macros that check whether X is a register and also, 1114 strictly, whether it is in a specified class. 1115 1116 These macros are specific to the 68000, and may be used only 1117 in code for printing assembler insns and in conditions for 1118 define_optimization. */ 1119 1120 /* 1 if X is a data register. */ 1121 1122 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 1123 1124 /* 1 if X is an fp register. */ 1125 1126 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1127 1128 /* 1 if X is an address register */ 1129 1130 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 1131 1132 /* Maximum number of registers that can appear in a valid memory address. */ 1133 1134 #define MAX_REGS_PER_ADDRESS 2 1135 1136 /* Recognize any constant value that is a valid address. */ 1137 1138 #define CONSTANT_ADDRESS_P(X) \ 1139 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1140 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1141 || GET_CODE (X) == HIGH) 1142 1143 /* Nonzero if the constant value X is a legitimate general operand. 1144 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1145 1146 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode) 1147 1148 /* Nonzero if the constant value X is a legitimate general operand 1149 when generating PIC code. It is given that flag_pic is on and 1150 that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1151 1152 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are 1153 accepted by insn predicates, but which would otherwise fail the 1154 `general_operand' test. */ 1155 1156 #ifndef REG_OK_STRICT 1157 #define PCREL_GENERAL_OPERAND_OK 0 1158 #else 1159 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) 1160 #endif 1161 1162 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1163 (! symbolic_operand (X, VOIDmode) \ 1164 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ 1165 || PCREL_GENERAL_OPERAND_OK) 1166 1167 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1168 and check its validity for a certain class. 1169 We have two alternate definitions for each of them. 1170 The usual definition accepts all pseudo regs; the other rejects 1171 them unless they have been allocated suitable hard regs. 1172 The symbol REG_OK_STRICT causes the latter definition to be used. 1173 1174 Most source files want to accept pseudo regs in the hope that 1175 they will get allocated to the class that the insn wants them to be in. 1176 Source files for reload pass need to be strict. 1177 After reload, it makes no difference, since pseudo regs have 1178 been eliminated by then. */ 1179 1180 #ifndef REG_OK_STRICT 1181 1182 /* Nonzero if X is a hard reg that can be used as an index 1183 or if it is a pseudo reg. */ 1184 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 1185 /* Nonzero if X is a hard reg that can be used as a base reg 1186 or if it is a pseudo reg. */ 1187 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 1188 1189 #else 1190 1191 /* Nonzero if X is a hard reg that can be used as an index. */ 1192 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1193 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1194 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1195 1196 #endif 1197 1198 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1199 that is a valid memory address for an instruction. 1200 The MODE argument is the machine mode for the MEM expression 1201 that wants to use this address. 1202 1203 When generating PIC, an address involving a SYMBOL_REF is legitimate 1204 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. 1205 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, 1206 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. 1207 1208 Likewise for a LABEL_REF when generating PIC. 1209 1210 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1211 1212 /* Allow SUBREG everywhere we allow REG. This results in better code. It 1213 also makes function inlining work when inline functions are called with 1214 arguments that are SUBREGs. */ 1215 1216 #define LEGITIMATE_BASE_REG_P(X) \ 1217 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1218 || (GET_CODE (X) == SUBREG \ 1219 && GET_CODE (SUBREG_REG (X)) == REG \ 1220 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1221 1222 #define INDIRECTABLE_1_ADDRESS_P(X) \ 1223 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ 1224 || LEGITIMATE_BASE_REG_P (X) \ 1225 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 1226 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ 1227 || (GET_CODE (X) == PLUS \ 1228 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ 1229 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1230 && (TARGET_68020 \ 1231 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ 1232 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1233 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ 1234 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1235 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) 1236 1237 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 1238 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 1239 1240 /* Only labels on dispatch tables are valid for indexing from. */ 1241 #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 1242 { rtx temp; \ 1243 if (GET_CODE (X) == LABEL_REF \ 1244 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ 1245 && GET_CODE (temp) == JUMP_INSN \ 1246 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ 1247 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ 1248 goto ADDR; \ 1249 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } 1250 1251 #define GO_IF_INDEXING(X, ADDR) \ 1252 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 1253 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 1254 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 1255 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 1256 1257 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 1258 { GO_IF_INDEXING (X, ADDR); \ 1259 if (GET_CODE (X) == PLUS) \ 1260 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1261 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ 1262 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 1263 if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 1264 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ 1265 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 1266 1267 /* ColdFire/5200 does not allow HImode index registers. */ 1268 #define LEGITIMATE_INDEX_REG_P(X) \ 1269 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1270 || (! TARGET_COLDFIRE \ 1271 && GET_CODE (X) == SIGN_EXTEND \ 1272 && GET_CODE (XEXP (X, 0)) == REG \ 1273 && GET_MODE (XEXP (X, 0)) == HImode \ 1274 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 1275 || (GET_CODE (X) == SUBREG \ 1276 && GET_CODE (SUBREG_REG (X)) == REG \ 1277 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1278 1279 #define LEGITIMATE_INDEX_P(X) \ 1280 (LEGITIMATE_INDEX_REG_P (X) \ 1281 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \ 1282 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 1283 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1284 && (INTVAL (XEXP (X, 1)) == 2 \ 1285 || INTVAL (XEXP (X, 1)) == 4 \ 1286 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE)))) 1287 1288 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ 1289 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1290 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 1291 GO_IF_INDEXED_ADDRESS (X, ADDR); \ 1292 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ 1293 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ 1294 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ 1295 goto ADDR; } 1296 1297 /* Don't call memory_address_noforce for the address to fetch 1298 the switch offset. This address is ok as it stands (see above), 1299 but memory_address_noforce would alter it. */ 1300 #define PIC_CASE_VECTOR_ADDRESS(index) index 1301 1302 /* Try machine-dependent ways of modifying an illegitimate address 1303 to be legitimate. If we find one, return the new, valid address. 1304 This macro is used in only one place: `memory_address' in explow.c. 1305 1306 OLDX is the address as it was before break_out_memory_refs was called. 1307 In some cases it is useful to look at this to decide what needs to be done. 1308 1309 MODE and WIN are passed so that this macro can use 1310 GO_IF_LEGITIMATE_ADDRESS. 1311 1312 It is always safe for this macro to do nothing. It exists to recognize 1313 opportunities to optimize the output. 1314 1315 For the 68000, we handle X+REG by loading X into a register R and 1316 using R+REG. R will go in an address reg and indexing will be used. 1317 However, if REG is a broken-out memory address or multiplication, 1318 nothing needs to be done because REG can certainly go in an address reg. */ 1319 1320 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } 1321 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1322 { register int ch = (X) != (OLDX); \ 1323 if (GET_CODE (X) == PLUS) \ 1324 { int copied = 0; \ 1325 if (GET_CODE (XEXP (X, 0)) == MULT) \ 1326 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ 1327 if (GET_CODE (XEXP (X, 1)) == MULT) \ 1328 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ 1329 if (ch && GET_CODE (XEXP (X, 1)) == REG \ 1330 && GET_CODE (XEXP (X, 0)) == REG) \ 1331 goto WIN; \ 1332 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 1333 if (GET_CODE (XEXP (X, 0)) == REG \ 1334 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 1335 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1336 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 1337 { register rtx temp = gen_reg_rtx (Pmode); \ 1338 register rtx val = force_operand (XEXP (X, 1), 0); \ 1339 emit_move_insn (temp, val); \ 1340 COPY_ONCE (X); \ 1341 XEXP (X, 1) = temp; \ 1342 goto WIN; } \ 1343 else if (GET_CODE (XEXP (X, 1)) == REG \ 1344 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 1345 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 1346 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 1347 { register rtx temp = gen_reg_rtx (Pmode); \ 1348 register rtx val = force_operand (XEXP (X, 0), 0); \ 1349 emit_move_insn (temp, val); \ 1350 COPY_ONCE (X); \ 1351 XEXP (X, 0) = temp; \ 1352 goto WIN; }}} 1353 1354 /* Go to LABEL if ADDR (a legitimate address expression) 1355 has an effect that depends on the machine mode it is used for. 1356 On the 68000, only predecrement and postincrement address depend thus 1357 (the amount of decrement or increment being the length of the operand). */ 1358 1359 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1360 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 1361 1362 /* Specify the machine mode that this machine uses 1363 for the index in the tablejump instruction. */ 1364 #define CASE_VECTOR_MODE HImode 1365 1366 /* Define as C expression which evaluates to nonzero if the tablejump 1367 instruction expects the table to contain offsets from the address of the 1368 table. 1369 Do not define this if the table should contain absolute addresses. */ 1370 #define CASE_VECTOR_PC_RELATIVE 1 1371 1372 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1373 #define DEFAULT_SIGNED_CHAR 1 1374 1375 /* Don't cse the address of the function being compiled. */ 1376 #define NO_RECURSIVE_FUNCTION_CSE 1377 1378 /* Max number of bytes we can move from memory to memory 1379 in one reasonably fast instruction. */ 1380 #define MOVE_MAX 4 1381 1382 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1383 #define SLOW_BYTE_ACCESS 0 1384 1385 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1386 is done just by pretending it is already truncated. */ 1387 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1388 1389 /* We assume that the store-condition-codes instructions store 0 for false 1390 and some other value for true. This is the value stored for true. */ 1391 1392 #define STORE_FLAG_VALUE (-1) 1393 1394 /* When a prototype says `char' or `short', really pass an `int'. */ 1395 #define PROMOTE_PROTOTYPES 1 1396 1397 /* Specify the machine mode that pointers have. 1398 After generation of rtl, the compiler makes no further distinction 1399 between pointers and any other objects of this machine mode. */ 1400 #define Pmode SImode 1401 1402 /* A function address in a call instruction 1403 is a byte address (for indexing purposes) 1404 so give the MEM rtx a byte's mode. */ 1405 #define FUNCTION_MODE QImode 1406 1407 1408 /* Tell final.c how to eliminate redundant test instructions. */ 1409 1410 /* Here we define machine-dependent flags and fields in cc_status 1411 (see `conditions.h'). */ 1412 1413 /* Set if the cc value is actually in the 68881, so a floating point 1414 conditional branch must be output. */ 1415 #define CC_IN_68881 04000 1416 1417 /* Store in cc_status the expressions that the condition codes will 1418 describe after execution of an instruction whose pattern is EXP. 1419 Do not alter them if the instruction would not alter the cc's. */ 1420 1421 /* On the 68000, all the insns to store in an address register fail to 1422 set the cc's. However, in some cases these instructions can make it 1423 possibly invalid to use the saved cc's. In those cases we clear out 1424 some or all of the saved cc's so they won't be used. */ 1425 1426 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 1427 1428 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 1429 do { if (cc_prev_status.flags & CC_IN_68881) \ 1430 return FLOAT; \ 1431 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 1432 return NO_OV; \ 1433 return NORMAL; } while (0) 1434 1435 /* Control the assembler format that we output. */ 1436 1437 /* Output to assembler file text saying following lines 1438 may contain character constants, extra white space, comments, etc. */ 1439 1440 #define ASM_APP_ON "#APP\n" 1441 1442 /* Output to assembler file text saying following lines 1443 no longer contain unusual constructs. */ 1444 1445 #define ASM_APP_OFF "#NO_APP\n" 1446 1447 /* Output before read-only data. */ 1448 1449 #define TEXT_SECTION_ASM_OP "\t.text" 1450 1451 /* Output before writable data. */ 1452 1453 #define DATA_SECTION_ASM_OP "\t.data" 1454 1455 #define GLOBAL_ASM_OP "\t.globl\t" 1456 1457 /* Here are four prefixes that are used by asm_fprintf to 1458 facilitate customization for alternate assembler syntaxes. 1459 Machines with no likelihood of an alternate syntax need not 1460 define these and need not use asm_fprintf. */ 1461 1462 /* The prefix for register names. Note that REGISTER_NAMES 1463 is supposed to include this prefix. */ 1464 1465 #define REGISTER_PREFIX "" 1466 1467 /* The prefix for local labels. You should be able to define this as 1468 an empty string, or any arbitrary string (such as ".", ".L%", etc) 1469 without having to make any other changes to account for the specific 1470 definition. Note it is a string literal, not interpreted by printf 1471 and friends. */ 1472 1473 #define LOCAL_LABEL_PREFIX "" 1474 1475 /* The prefix to add to user-visible assembler symbols. */ 1476 1477 #define USER_LABEL_PREFIX "_" 1478 1479 /* The prefix for immediate operands. */ 1480 1481 #define IMMEDIATE_PREFIX "#" 1482 1483 /* How to refer to registers in assembler output. 1484 This sequence is indexed by compiler's hard-register-number (see above). */ 1485 1486 #define REGISTER_NAMES \ 1487 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1488 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1489 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" } 1490 1491 /* How to renumber registers for dbx and gdb. 1492 On the Sun-3, the floating point registers have numbers 1493 18 to 25, not 16 to 23 as they do in the compiler. */ 1494 1495 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 1496 1497 /* Before the prologue, RA is at 0(%sp). */ 1498 #define INCOMING_RETURN_ADDR_RTX \ 1499 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1500 1501 /* We must not use the DBX register numbers for the DWARF 2 CFA column 1502 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 1503 Instead use the identity mapping. */ 1504 #define DWARF_FRAME_REGNUM(REG) REG 1505 1506 /* Before the prologue, the top of the frame is at 4(%sp). */ 1507 #define INCOMING_FRAME_SP_OFFSET 4 1508 1509 /* Describe how we implement __builtin_eh_return. */ 1510 #define EH_RETURN_DATA_REGNO(N) \ 1511 ((N) < 2 ? (N) : INVALID_REGNUM) 1512 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) 1513 #define EH_RETURN_HANDLER_RTX \ 1514 gen_rtx_MEM (Pmode, \ 1515 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 1516 plus_constant (EH_RETURN_STACKADJ_RTX, \ 1517 UNITS_PER_WORD))) 1518 1519 /* Select a format to encode pointers in exception handling data. CODE 1520 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1521 true if the symbol may be affected by dynamic relocations. */ 1522 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1523 (flag_pic \ 1524 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 1525 : DW_EH_PE_absptr) 1526 1527 /* This is how to output a reference to a user-level label named NAME. 1528 `assemble_name' uses this. */ 1529 1530 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1531 asm_fprintf (FILE, "%U%s", NAME) 1532 1533 /* This is how to store into the string LABEL 1534 the symbol_ref name of an internal numbered label where 1535 PREFIX is the class of label and NUM is the number within the class. 1536 This is suitable for output with `assemble_name'. */ 1537 1538 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1539 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 1540 1541 /* This is how to output an insn to push a register on the stack. 1542 It need not be very fast code. */ 1543 1544 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1545 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) 1546 1547 /* This is how to output an insn to pop a register from the stack. 1548 It need not be very fast code. */ 1549 1550 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1551 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) 1552 1553 /* This is how to output an element of a case-vector that is absolute. 1554 (The 68000 does not use such vectors, 1555 but we must define this macro anyway.) */ 1556 1557 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1558 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 1559 1560 /* This is how to output an element of a case-vector that is relative. */ 1561 1562 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1563 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 1564 1565 /* This is how to output an assembler line 1566 that says to advance the location counter 1567 to a multiple of 2**LOG bytes. */ 1568 1569 /* We don't have a way to align to more than a two-byte boundary, so do the 1570 best we can and don't complain. */ 1571 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1572 if ((LOG) >= 1) \ 1573 fprintf (FILE, "\t.even\n"); 1574 1575 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1576 fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) 1577 1578 /* This says how to output an assembler line 1579 to define a global common symbol. */ 1580 1581 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1582 ( fputs (".comm ", (FILE)), \ 1583 assemble_name ((FILE), (NAME)), \ 1584 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 1585 1586 /* This says how to output an assembler line 1587 to define a local common symbol. */ 1588 1589 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1590 ( fputs (".lcomm ", (FILE)), \ 1591 assemble_name ((FILE), (NAME)), \ 1592 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 1593 1594 /* Output a float value (represented as a C double) as an immediate operand. 1595 This macro is a 68k-specific macro. */ 1596 1597 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ 1598 do { \ 1599 if (CODE == 'f') \ 1600 { \ 1601 char dstr[30]; \ 1602 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ 1603 asm_fprintf ((FILE), "%I0r%s", dstr); \ 1604 } \ 1605 else \ 1606 { \ 1607 long l; \ 1608 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1609 asm_fprintf ((FILE), "%I0x%lx", l); \ 1610 } \ 1611 } while (0) 1612 1613 /* Output a double value (represented as a C double) as an immediate operand. 1614 This macro is a 68k-specific macro. */ 1615 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ 1616 do { char dstr[30]; \ 1617 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1618 asm_fprintf (FILE, "%I0r%s", dstr); \ 1619 } while (0) 1620 1621 /* Note, long double immediate operands are not actually 1622 generated by m68k.md. */ 1623 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ 1624 do { char dstr[30]; \ 1625 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1626 asm_fprintf (FILE, "%I0r%s", dstr); \ 1627 } while (0) 1628 1629 /* Print operand X (an rtx) in assembler syntax to file FILE. 1630 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1631 For `%' followed by punctuation, CODE is the punctuation and X is null. 1632 1633 On the 68000, we use several CODE characters: 1634 '.' for dot needed in Motorola-style opcode names. 1635 '-' for an operand pushing on the stack: 1636 sp@-, -(sp) or -(%sp) depending on the style of syntax. 1637 '+' for an operand pushing on the stack: 1638 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1639 '@' for a reference to the top word on the stack: 1640 sp@, (sp) or (%sp) depending on the style of syntax. 1641 '#' for an immediate operand prefix (# in MIT and Motorola syntax 1642 but & in SGS syntax). 1643 '!' for the fpcr register (used in some float-to-fixed conversions). 1644 '$' for the letter `s' in an op code, but only on the 68040. 1645 '&' for the letter `d' in an op code, but only on the 68040. 1646 '/' for register prefix needed by longlong.h. 1647 1648 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1649 'd' to force memory addressing to be absolute, not relative. 1650 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1651 'o' for operands to go directly to output_operand_address (bypassing 1652 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 1653 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1654 or print pair of registers as rx:ry. */ 1655 1656 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1657 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 1658 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 1659 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') 1660 1661 /* A C compound statement to output to stdio stream STREAM the 1662 assembler syntax for an instruction operand X. X is an RTL 1663 expression. 1664 1665 CODE is a value that can be used to specify one of several ways 1666 of printing the operand. It is used when identical operands 1667 must be printed differently depending on the context. CODE 1668 comes from the `%' specification that was used to request 1669 printing of the operand. If the specification was just `%DIGIT' 1670 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 1671 is the ASCII code for LTR. 1672 1673 If X is a register, this macro should print the register's name. 1674 The names can be found in an array `reg_names' whose type is 1675 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 1676 1677 When the machine description has a specification `%PUNCT' (a `%' 1678 followed by a punctuation character), this macro is called with 1679 a null pointer for X and the punctuation character for CODE. 1680 1681 See m68k.c for the m68k specific codes. */ 1682 1683 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1684 1685 /* A C compound statement to output to stdio stream STREAM the 1686 assembler syntax for an instruction operand that is a memory 1687 reference whose address is ADDR. ADDR is an RTL expression. */ 1688 1689 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 1690 1691 /* Variables in m68k.c */ 1692 extern const char *m68k_align_loops_string; 1693 extern const char *m68k_align_jumps_string; 1694 extern const char *m68k_align_funcs_string; 1695 extern const char *m68k_library_id_string; 1696 extern int m68k_align_loops; 1697 extern int m68k_align_jumps; 1698 extern int m68k_align_funcs; 1699 extern int m68k_last_compare_had_fp_operands; 1700 1701 1702 /* Define the codes that are matched by predicates in m68k.c. */ 1703 1704 #define PREDICATE_CODES \ 1705 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 1706 LABEL_REF, SUBREG, REG, MEM}}, \ 1707 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \ 1708 {"memory_src_operand", {SUBREG, MEM}}, \ 1709 {"not_sp_operand", {SUBREG, REG, MEM}}, \ 1710 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \ 1711 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \ 1712 {"const_sint32_operand", {CONST_INT}}, \ 1713 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \ 1714 GT, LT, GE, LE}}, \ 1715 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}}, 1716 1717 /* 1718 Local variables: 1719 version-control: t 1720 End: 1721 */ 1722