1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH. 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3 Free Software Foundation, Inc. 4 Contributed by Steve Chamberlain (sac@cygnus.com). 5 Improved by Jim Wilson (wilson@cygnus.com). 6 7 This file is part of GNU CC. 8 9 GNU CC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 GNU CC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GNU CC; see the file COPYING. If not, write to 21 the Free Software Foundation, 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. */ 23 24 #ifndef GCC_SH_H 25 #define GCC_SH_H 26 27 #define TARGET_VERSION \ 28 fputs (" (Hitachi SH)", stderr); 29 30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't 31 include it here, because hconfig.h is also included by gencodes.c . */ 32 /* ??? No longer true. */ 33 extern int code_for_indirect_jump_scratch; 34 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do { \ 37 builtin_define ("__sh__"); \ 38 builtin_assert ("cpu=sh"); \ 39 builtin_assert ("machine=sh"); \ 40 switch ((int) sh_cpu) \ 41 { \ 42 case PROCESSOR_SH1: \ 43 builtin_define ("__sh1__"); \ 44 break; \ 45 case PROCESSOR_SH2: \ 46 builtin_define ("__sh2__"); \ 47 break; \ 48 case PROCESSOR_SH3: \ 49 builtin_define ("__sh3__"); \ 50 builtin_define ("__SH3__"); \ 51 if (TARGET_HARD_SH4) \ 52 builtin_define ("__SH4_NOFPU__"); \ 53 break; \ 54 case PROCESSOR_SH3E: \ 55 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \ 56 break; \ 57 case PROCESSOR_SH4: \ 58 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \ 59 break; \ 60 case PROCESSOR_SH5: \ 61 { \ 62 builtin_define_with_value ("__SH5__", \ 63 TARGET_SHMEDIA64 ? "64" : "32", 0); \ 64 builtin_define_with_value ("__SHMEDIA__", \ 65 TARGET_SHMEDIA ? "1" : "0", 0); \ 66 if (! TARGET_FPU_DOUBLE) \ 67 builtin_define ("__SH4_NOFPU__"); \ 68 } \ 69 } \ 70 if (TARGET_HITACHI) \ 71 builtin_define ("__HITACHI__"); \ 72 builtin_define (TARGET_LITTLE_ENDIAN \ 73 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \ 74 if (flag_pic) \ 75 { \ 76 builtin_define ("__pic__"); \ 77 builtin_define ("__PIC__"); \ 78 } \ 79 TARGET_OBJFMT_CPP_BUILTINS (); \ 80 } while (0) 81 82 /* We can not debug without a frame pointer. */ 83 /* #define CAN_DEBUG_WITHOUT_FP */ 84 85 #define CONDITIONAL_REGISTER_USAGE do \ 86 { \ 87 int regno; \ 88 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \ 89 if (! VALID_REGISTER_P (regno)) \ 90 fixed_regs[regno] = call_used_regs[regno] = 1; \ 91 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \ 92 if (TARGET_SH5) \ 93 call_used_regs[FIRST_GENERAL_REG + 8] \ 94 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \ 95 if (TARGET_SHMEDIA) \ 96 { \ 97 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \ 98 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \ 99 regno_reg_class[FIRST_FP_REG] = FP_REGS; \ 100 } \ 101 if (flag_pic) \ 102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 103 /* Hitachi saves and restores mac registers on call. */ \ 104 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \ 105 { \ 106 call_used_regs[MACH_REG] = 0; \ 107 call_used_regs[MACL_REG] = 0; \ 108 } \ 109 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \ 110 regno <= LAST_FP_REG; regno += 2) \ 111 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \ 112 if (TARGET_SHMEDIA) \ 113 { \ 114 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\ 115 if (! fixed_regs[regno] && call_used_regs[regno]) \ 116 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ 117 } \ 118 else \ 119 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \ 120 if (! fixed_regs[regno] && call_used_regs[regno]) \ 121 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \ 122 } while (0) 123 124 /* ??? Need to write documentation for all SH options and add it to the 125 invoke.texi file. */ 126 127 /* Run-time compilation parameters selecting different hardware subsets. */ 128 129 extern int target_flags; 130 #define ISIZE_BIT (1<<1) 131 #define DALIGN_BIT (1<<6) 132 #define SH1_BIT (1<<8) 133 #define SH2_BIT (1<<9) 134 #define SH3_BIT (1<<10) 135 #define SH3E_BIT (1<<11) 136 #define HARD_SH4_BIT (1<<5) 137 #define FPU_SINGLE_BIT (1<<7) 138 #define SH4_BIT (1<<12) 139 #define FMOVD_BIT (1<<4) 140 #define SH5_BIT (1<<0) 141 #define SPACE_BIT (1<<13) 142 #define BIGTABLE_BIT (1<<14) 143 #define RELAX_BIT (1<<15) 144 #define USERMODE_BIT (1<<16) 145 #define HITACHI_BIT (1<<22) 146 #define NOMACSAVE_BIT (1<<23) 147 #define PREFERGOT_BIT (1<<24) 148 #define PADSTRUCT_BIT (1<<28) 149 #define LITTLE_ENDIAN_BIT (1<<29) 150 #define IEEE_BIT (1<<30) 151 152 /* Nonzero if we should dump out instruction size info. */ 153 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) 154 155 /* Nonzero to align doubles on 64 bit boundaries. */ 156 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) 157 158 /* Nonzero if we should generate code using type 1 insns. */ 159 #define TARGET_SH1 (target_flags & SH1_BIT) 160 161 /* Nonzero if we should generate code using type 2 insns. */ 162 #define TARGET_SH2 (target_flags & SH2_BIT) 163 164 /* Nonzero if we should generate code using type 3 insns. */ 165 #define TARGET_SH3 (target_flags & SH3_BIT) 166 167 /* Nonzero if we should generate code using type 3E insns. */ 168 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT)) 169 170 /* Nonzero if the cache line size is 32. */ 171 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5) 172 173 /* Nonzero if we schedule for a superscalar implementation. */ 174 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT) 175 176 /* Nonzero if the target has separate instruction and data caches. */ 177 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT) 178 179 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */ 180 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT) 181 182 /* Nonzero if the default precision of th FPU is single */ 183 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT) 184 185 /* Nonzero if a double-precision FPU is available. */ 186 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT) 187 188 /* Nonzero if an FPU is available. */ 189 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE) 190 191 /* Nonzero if we should generate code using type 4 insns. */ 192 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT)) 193 194 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */ 195 #define TARGET_SH5 (target_flags & SH5_BIT) 196 197 /* Nonzero if we should generate code using the SHcompact instruction 198 set and 32-bit ABI. */ 199 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1) 200 201 /* Nonzero if we should generate code using the SHmedia instruction 202 set and ABI. */ 203 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1) 204 205 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit 206 ABI. */ 207 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \ 208 && (target_flags & SH3E_BIT)) 209 210 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit 211 ABI. */ 212 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \ 213 && ! (target_flags & SH3E_BIT)) 214 215 /* Nonzero if we should generate code using SHmedia FPU instructions. */ 216 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE) 217 /* Nonzero if we should generate fmovd. */ 218 #define TARGET_FMOVD (target_flags & FMOVD_BIT) 219 220 /* Nonzero if we respect NANs. */ 221 #define TARGET_IEEE (target_flags & IEEE_BIT) 222 223 /* Nonzero if we should generate smaller code rather than faster code. */ 224 #define TARGET_SMALLCODE (target_flags & SPACE_BIT) 225 226 /* Nonzero to use long jump tables. */ 227 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) 228 229 /* Nonzero to generate pseudo-ops needed by the assembler and linker 230 to do function call relaxing. */ 231 #define TARGET_RELAX (target_flags & RELAX_BIT) 232 233 /* Nonzero if using Hitachi's calling convention. */ 234 #define TARGET_HITACHI (target_flags & HITACHI_BIT) 235 236 /* Nonzero if not saving macl/mach when using -mhitachi */ 237 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT) 238 239 /* Nonzero if padding structures to a multiple of 4 bytes. This is 240 incompatible with Hitachi's compiler, and gives unusual structure layouts 241 which confuse programmers. 242 ??? This option is not useful, but is retained in case there are people 243 who are still relying on it. It may be deleted in the future. */ 244 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT) 245 246 /* Nonzero if generating code for a little endian SH. */ 247 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) 248 249 /* Nonzero if we should do everything in userland. */ 250 #define TARGET_USERMODE (target_flags & USERMODE_BIT) 251 252 /* Nonzero if we should prefer @GOT calls when generating PIC. */ 253 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT) 254 255 #define SELECT_SH1 (SH1_BIT) 256 #define SELECT_SH2 (SH2_BIT | SELECT_SH1) 257 #define SELECT_SH3 (SH3_BIT | SELECT_SH2) 258 #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3) 259 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3) 260 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E) 261 #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3) 262 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4) 263 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT) 264 #define SELECT_SH5_64_NOFPU (SH5_BIT) 265 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT) 266 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT) 267 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E) 268 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3) 269 270 /* Reset all target-selection flags. */ 271 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \ 272 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT) 273 274 #define TARGET_SWITCHES \ 275 { {"1", TARGET_NONE, "" }, \ 276 {"1", SELECT_SH1, "" }, \ 277 {"2", TARGET_NONE, "" }, \ 278 {"2", SELECT_SH2, "" }, \ 279 {"3", TARGET_NONE, "" }, \ 280 {"3", SELECT_SH3, "" }, \ 281 {"3e", TARGET_NONE, "" }, \ 282 {"3e", SELECT_SH3E, "" }, \ 283 {"4-single-only", TARGET_NONE, "" }, \ 284 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \ 285 {"4-single", TARGET_NONE, "" }, \ 286 {"4-single", SELECT_SH4_SINGLE, "" },\ 287 {"4-nofpu", TARGET_NONE, "" }, \ 288 {"4-nofpu", SELECT_SH4_NOFPU, "" },\ 289 {"4", TARGET_NONE, "" }, \ 290 {"4", SELECT_SH4, "" }, \ 291 {"5-64media", TARGET_NONE, "" }, \ 292 {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \ 293 {"5-64media-nofpu", TARGET_NONE, "" }, \ 294 {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \ 295 {"5-32media", TARGET_NONE, "" }, \ 296 {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \ 297 {"5-32media-nofpu", TARGET_NONE, "" }, \ 298 {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \ 299 {"5-compact", TARGET_NONE, "" }, \ 300 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \ 301 {"5-compact-nofpu", TARGET_NONE, "" }, \ 302 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \ 303 {"b", -LITTLE_ENDIAN_BIT, "" }, \ 304 {"bigtable", BIGTABLE_BIT, "" }, \ 305 {"dalign", DALIGN_BIT, "" }, \ 306 {"fmovd", FMOVD_BIT, "" }, \ 307 {"hitachi", HITACHI_BIT, "" }, \ 308 {"nomacsave", NOMACSAVE_BIT, "" }, \ 309 {"ieee", IEEE_BIT, "" }, \ 310 {"isize", ISIZE_BIT, "" }, \ 311 {"l", LITTLE_ENDIAN_BIT, "" }, \ 312 {"no-ieee", -IEEE_BIT, "" }, \ 313 {"padstruct", PADSTRUCT_BIT, "" }, \ 314 {"prefergot", PREFERGOT_BIT, "" }, \ 315 {"relax", RELAX_BIT, "" }, \ 316 {"space", SPACE_BIT, "" }, \ 317 {"usermode", USERMODE_BIT, "" }, \ 318 SUBTARGET_SWITCHES \ 319 {"", TARGET_DEFAULT, "" } \ 320 } 321 322 /* This are meant to be redefined in the host dependent files */ 323 #define SUBTARGET_SWITCHES 324 325 /* This defaults us to big-endian. */ 326 #ifndef TARGET_ENDIAN_DEFAULT 327 #define TARGET_ENDIAN_DEFAULT 0 328 #endif 329 330 #ifndef TARGET_CPU_DEFAULT 331 #define TARGET_CPU_DEFAULT SELECT_SH1 332 #endif 333 334 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT) 335 336 #define CPP_SPEC " %(subtarget_cpp_spec) " 337 338 #ifndef SUBTARGET_CPP_SPEC 339 #define SUBTARGET_CPP_SPEC "" 340 #endif 341 342 #ifndef SUBTARGET_EXTRA_SPECS 343 #define SUBTARGET_EXTRA_SPECS 344 #endif 345 346 #define EXTRA_SPECS \ 347 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 348 { "link_emul_prefix", LINK_EMUL_PREFIX }, \ 349 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ 350 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ 351 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ 352 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ 353 SUBTARGET_EXTRA_SPECS 354 355 #define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}" 356 357 #ifndef SUBTARGET_ASM_ENDIAN_SPEC 358 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT 359 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" 360 #else 361 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" 362 #endif 363 #endif 364 365 #define LINK_EMUL_PREFIX "sh%{ml:l}" 366 367 #if TARGET_CPU_DEFAULT & SH5_BIT 368 #if TARGET_CPU_DEFAULT & SH3E_BIT 369 #define LINK_DEFAULT_CPU_EMUL "32" 370 #else 371 #define LINK_DEFAULT_CPU_EMUL "64" 372 #endif /* SH3E_BIT */ 373 #else 374 #define LINK_DEFAULT_CPU_EMUL "" 375 #endif /* SH5_BIT */ 376 377 #define SUBTARGET_LINK_EMUL_SUFFIX "" 378 #define SUBTARGET_LINK_SPEC "" 379 380 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC, 381 so that we can undo the damage without code replication. */ 382 #define LINK_SPEC SH_LINK_SPEC 383 384 #define SH_LINK_SPEC "\ 385 -m %(link_emul_prefix)\ 386 %{m5-compact*|m5-32media*:32}\ 387 %{m5-64media*:64}\ 388 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\ 389 %(subtarget_link_emul_suffix) \ 390 %{mrelax:-relax} %(subtarget_link_spec)" 391 392 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 393 do { \ 394 if (LEVEL) \ 395 flag_omit_frame_pointer = -1; \ 396 if (SIZE) \ 397 target_flags |= SPACE_BIT; \ 398 } while (0) 399 400 #define ASSEMBLER_DIALECT assembler_dialect 401 402 extern int assembler_dialect; 403 404 #define OVERRIDE_OPTIONS sh_override_options () 405 406 /* Target machine storage layout. */ 407 408 /* Define this if most significant bit is lowest numbered 409 in instructions that operate on numbered bit-fields. */ 410 411 #define BITS_BIG_ENDIAN 0 412 413 /* Define this if most significant byte of a word is the lowest numbered. */ 414 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 415 416 /* Define this if most significant word of a multiword number is the lowest 417 numbered. */ 418 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 419 420 /* Define this to set the endianness to use in libgcc2.c, which can 421 not depend on target_flags. */ 422 #if defined(__LITTLE_ENDIAN__) 423 #define LIBGCC2_WORDS_BIG_ENDIAN 0 424 #else 425 #define LIBGCC2_WORDS_BIG_ENDIAN 1 426 #endif 427 428 #define MAX_BITS_PER_WORD 64 429 430 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD 431 432 /* Width in bits of an `int'. We want just 32-bits, even if words are 433 longer. */ 434 #define INT_TYPE_SIZE 32 435 436 /* Width in bits of a `long'. */ 437 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32) 438 439 /* Width in bits of a `long long'. */ 440 #define LONG_LONG_TYPE_SIZE 64 441 442 /* Width in bits of a `long double'. */ 443 #define LONG_DOUBLE_TYPE_SIZE 64 444 445 /* Width of a word, in units (bytes). */ 446 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4) 447 #define MIN_UNITS_PER_WORD 4 448 449 /* Width in bits of a pointer. 450 See also the macro `Pmode' defined below. */ 451 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32) 452 453 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 454 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32) 455 456 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 457 #define STACK_BOUNDARY BIGGEST_ALIGNMENT 458 459 /* The log (base 2) of the cache line size, in bytes. Processors prior to 460 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. 461 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ 462 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2) 463 464 /* ABI given & required minimum allocation boundary (in *bits*) for the 465 code of a function. */ 466 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA) 467 468 /* On SH5, the lowest bit is used to indicate SHmedia functions, so 469 the vbit must go into the delta field of 470 pointers-to-member-functions. */ 471 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ 472 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn) 473 474 /* Alignment of field after `int : 0' in a structure. */ 475 #define EMPTY_FIELD_BOUNDARY 32 476 477 /* No data type wants to be aligned rounder than this. */ 478 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 479 480 /* The best alignment to use in cases where we have a choice. */ 481 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32) 482 483 /* Make strings word-aligned so strcpy from constants will be faster. */ 484 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 485 ((TREE_CODE (EXP) == STRING_CST \ 486 && (ALIGN) < FASTEST_ALIGNMENT) \ 487 ? FASTEST_ALIGNMENT : (ALIGN)) 488 489 /* Make arrays of chars word-aligned for the same reasons. */ 490 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 491 (TREE_CODE (TYPE) == ARRAY_TYPE \ 492 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 493 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 494 495 /* Number of bits which any structure or union's size must be a 496 multiple of. Each structure or union's size is rounded up to a 497 multiple of this. */ 498 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) 499 500 /* Set this nonzero if move instructions will actually fail to work 501 when given unaligned data. */ 502 #define STRICT_ALIGNMENT 1 503 504 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 505 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 506 barrier_align (LABEL_AFTER_BARRIER) 507 508 #define LOOP_ALIGN(A_LABEL) \ 509 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \ 510 ? 0 : sh_loop_align (A_LABEL)) 511 512 #define LABEL_ALIGN(A_LABEL) \ 513 ( \ 514 (PREV_INSN (A_LABEL) \ 515 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \ 516 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 517 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ 518 /* explicit alignment insn in constant tables. */ \ 519 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 520 : 0) 521 522 /* Jump tables must be 32 bit aligned, no matter the size of the element. */ 523 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 524 525 /* The base two logarithm of the known minimum alignment of an insn length. */ 526 #define INSN_LENGTH_ALIGNMENT(A_INSN) \ 527 (GET_CODE (A_INSN) == INSN \ 528 ? 1 << TARGET_SHMEDIA \ 529 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ 530 ? 1 << TARGET_SHMEDIA \ 531 : CACHE_LOG) 532 533 /* Standard register usage. */ 534 535 /* Register allocation for the Hitachi calling convention: 536 537 r0 arg return 538 r1..r3 scratch 539 r4..r7 args in 540 r8..r13 call saved 541 r14 frame pointer/call saved 542 r15 stack pointer 543 ap arg pointer (doesn't really exist, always eliminated) 544 pr subroutine return address 545 t t bit 546 mach multiply/accumulate result, high part 547 macl multiply/accumulate result, low part. 548 fpul fp/int communication register 549 rap return address pointer register 550 fr0 fp arg return 551 fr1..fr3 scratch floating point registers 552 fr4..fr11 fp args in 553 fr12..fr15 call saved floating point registers */ 554 555 #define MAX_REGISTER_NAME_LENGTH 5 556 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; 557 558 #define SH_REGISTER_NAMES_INITIALIZER \ 559 { \ 560 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 561 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 562 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 563 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 564 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 565 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 566 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 567 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 568 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ 569 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ 570 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ 571 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ 572 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ 573 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ 574 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ 575 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ 576 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ 577 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ 578 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ 579 "rap" \ 580 } 581 582 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER 583 584 #define REGNAMES_ARR_INDEX_1(index) \ 585 (sh_register_names[index]) 586 #define REGNAMES_ARR_INDEX_2(index) \ 587 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) 588 #define REGNAMES_ARR_INDEX_4(index) \ 589 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) 590 #define REGNAMES_ARR_INDEX_8(index) \ 591 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) 592 #define REGNAMES_ARR_INDEX_16(index) \ 593 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) 594 #define REGNAMES_ARR_INDEX_32(index) \ 595 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) 596 #define REGNAMES_ARR_INDEX_64(index) \ 597 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) 598 599 #define REGISTER_NAMES \ 600 { \ 601 REGNAMES_ARR_INDEX_64 (0), \ 602 REGNAMES_ARR_INDEX_64 (64), \ 603 REGNAMES_ARR_INDEX_8 (128), \ 604 REGNAMES_ARR_INDEX_8 (136), \ 605 REGNAMES_ARR_INDEX_8 (144), \ 606 REGNAMES_ARR_INDEX_1 (152) \ 607 } 608 609 #define ADDREGNAMES_SIZE 32 610 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 611 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ 612 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; 613 614 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ 615 { \ 616 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ 617 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ 618 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ 619 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ 620 } 621 622 #define ADDREGNAMES_REGNO(index) \ 623 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ 624 : (-1)) 625 626 #define ADDREGNAMES_ARR_INDEX_1(index) \ 627 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } 628 #define ADDREGNAMES_ARR_INDEX_2(index) \ 629 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) 630 #define ADDREGNAMES_ARR_INDEX_4(index) \ 631 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) 632 #define ADDREGNAMES_ARR_INDEX_8(index) \ 633 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) 634 #define ADDREGNAMES_ARR_INDEX_16(index) \ 635 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) 636 #define ADDREGNAMES_ARR_INDEX_32(index) \ 637 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) 638 639 #define ADDITIONAL_REGISTER_NAMES \ 640 { \ 641 ADDREGNAMES_ARR_INDEX_32 (0) \ 642 } 643 644 /* Number of actual hardware registers. 645 The hardware registers are assigned numbers for the compiler 646 from 0 to just below FIRST_PSEUDO_REGISTER. 647 All registers that the compiler knows about must be given numbers, 648 even those that are not normally considered general registers. */ 649 650 /* There are many other relevant definitions in sh.md's md_constants. */ 651 652 #define FIRST_GENERAL_REG R0_REG 653 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15)) 654 #define FIRST_FP_REG DR0_REG 655 #define LAST_FP_REG (FIRST_FP_REG + \ 656 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1)) 657 #define FIRST_XD_REG XD0_REG 658 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) 659 #define FIRST_TARGET_REG TR0_REG 660 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) 661 662 #define GENERAL_REGISTER_P(REGNO) \ 663 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG) 664 665 #define GENERAL_OR_AP_REGISTER_P(REGNO) \ 666 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG)) 667 668 #define FP_REGISTER_P(REGNO) \ 669 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG) 670 671 #define XD_REGISTER_P(REGNO) \ 672 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG) 673 674 #define FP_OR_XD_REGISTER_P(REGNO) \ 675 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) 676 677 #define FP_ANY_REGISTER_P(REGNO) \ 678 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) 679 680 #define SPECIAL_REGISTER_P(REGNO) \ 681 ((REGNO) == GBR_REG || (REGNO) == T_REG \ 682 || (REGNO) == MACH_REG || (REGNO) == MACL_REG) 683 684 #define TARGET_REGISTER_P(REGNO) \ 685 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG) 686 687 #define SHMEDIA_REGISTER_P(REGNO) \ 688 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ 689 || TARGET_REGISTER_P (REGNO)) 690 691 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers 692 that should be fixed. */ 693 #define VALID_REGISTER_P(REGNO) \ 694 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ 695 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ 696 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ 697 || (TARGET_SH3E && (REGNO) == FPUL_REG)) 698 699 /* The mode that should be generally used to store a register by 700 itself in the stack, or to load it back. */ 701 #define REGISTER_NATURAL_MODE(REGNO) \ 702 (FP_REGISTER_P (REGNO) ? SFmode \ 703 : XD_REGISTER_P (REGNO) ? DFmode \ 704 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \ 705 ? DImode \ 706 : SImode) 707 708 #define FIRST_PSEUDO_REGISTER 153 709 710 /* 1 for registers that have pervasive standard uses 711 and are not available for the register allocator. 712 713 Mach register is fixed 'cause it's only 10 bits wide for SH1. 714 It is 32 bits wide for SH2. */ 715 716 #define FIXED_REGISTERS \ 717 { \ 718 /* Regular registers. */ \ 719 0, 0, 0, 0, 0, 0, 0, 0, \ 720 0, 0, 0, 0, 0, 0, 0, 1, \ 721 /* r16 is reserved, r18 is the former pr. */ \ 722 1, 0, 0, 0, 0, 0, 0, 0, \ 723 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ 724 /* r26 is a global variable data pointer; r27 is for constants. */ \ 725 1, 1, 1, 1, 0, 0, 0, 0, \ 726 0, 0, 0, 0, 0, 0, 0, 0, \ 727 0, 0, 0, 0, 0, 0, 0, 0, \ 728 0, 0, 0, 0, 0, 0, 0, 0, \ 729 0, 0, 0, 0, 0, 0, 0, 1, \ 730 /* FP registers. */ \ 731 0, 0, 0, 0, 0, 0, 0, 0, \ 732 0, 0, 0, 0, 0, 0, 0, 0, \ 733 0, 0, 0, 0, 0, 0, 0, 0, \ 734 0, 0, 0, 0, 0, 0, 0, 0, \ 735 0, 0, 0, 0, 0, 0, 0, 0, \ 736 0, 0, 0, 0, 0, 0, 0, 0, \ 737 0, 0, 0, 0, 0, 0, 0, 0, \ 738 0, 0, 0, 0, 0, 0, 0, 0, \ 739 /* Branch target registers. */ \ 740 0, 0, 0, 0, 0, 0, 0, 0, \ 741 /* XD registers. */ \ 742 0, 0, 0, 0, 0, 0, 0, 0, \ 743 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 744 1, 1, 1, 1, 1, 1, 0, 1, \ 745 /*"rap" */ \ 746 1, \ 747 } 748 749 /* 1 for registers not available across function calls. 750 These must include the FIXED_REGISTERS and also any 751 registers that can be used without being saved. 752 The latter must include the registers where values are returned 753 and the register where structure-value addresses are passed. 754 Aside from that, you can include as many other registers as you like. */ 755 756 #define CALL_USED_REGISTERS \ 757 { \ 758 /* Regular registers. */ \ 759 1, 1, 1, 1, 1, 1, 1, 1, \ 760 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ 761 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ 762 across SH5 function calls. */ \ 763 0, 0, 0, 0, 0, 0, 0, 1, \ 764 1, 1, 0, 1, 1, 1, 1, 1, \ 765 1, 1, 1, 1, 0, 0, 0, 0, \ 766 0, 0, 0, 0, 1, 1, 1, 1, \ 767 1, 1, 1, 1, 0, 0, 0, 0, \ 768 0, 0, 0, 0, 0, 0, 0, 0, \ 769 0, 0, 0, 0, 1, 1, 1, 1, \ 770 /* FP registers. */ \ 771 1, 1, 1, 1, 1, 1, 1, 1, \ 772 1, 1, 1, 1, 0, 0, 0, 0, \ 773 1, 1, 1, 1, 1, 1, 1, 1, \ 774 1, 1, 1, 1, 1, 1, 1, 1, \ 775 1, 1, 1, 1, 0, 0, 0, 0, \ 776 0, 0, 0, 0, 0, 0, 0, 0, \ 777 0, 0, 0, 0, 0, 0, 0, 0, \ 778 0, 0, 0, 0, 0, 0, 0, 0, \ 779 /* Branch target registers. */ \ 780 1, 1, 1, 1, 1, 0, 0, 0, \ 781 /* XD registers. */ \ 782 1, 1, 1, 1, 1, 1, 0, 0, \ 783 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 784 1, 1, 0, 1, 1, 1, 1, 1, \ 785 /*"rap" */ \ 786 1, \ 787 } 788 789 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved 790 across SHcompact function calls. We can't tell whether a called 791 function is SHmedia or SHcompact, so we assume it may be when 792 compiling SHmedia code with the 32-bit ABI, since that's the only 793 ABI that can be linked with SHcompact code. */ 794 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \ 795 (TARGET_SHMEDIA32 \ 796 && GET_MODE_SIZE (MODE) > 4 \ 797 && (((REGNO) >= FIRST_GENERAL_REG + 10 \ 798 && (REGNO) <= FIRST_GENERAL_REG + 14) \ 799 || (REGNO) == PR_MEDIA_REG)) 800 801 /* Return number of consecutive hard regs needed starting at reg REGNO 802 to hold something of mode MODE. 803 This is ordinarily the length in words of a value of mode MODE 804 but can be less for certain modes in special long registers. 805 806 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */ 807 808 #define HARD_REGNO_NREGS(REGNO, MODE) \ 809 (XD_REGISTER_P (REGNO) \ 810 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \ 811 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \ 812 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \ 813 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ 814 815 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 816 We can allow any mode in any general register. The special registers 817 only allow SImode. Don't allow any mode in the PR. */ 818 819 /* We cannot hold DCmode values in the XD registers because alter_reg 820 handles subregs of them incorrectly. We could work around this by 821 spacing the XD registers like the DR registers, but this would require 822 additional memory in every compilation to hold larger register vectors. 823 We could hold SFmode / SCmode values in XD registers, but that 824 would require a tertiary reload when reloading from / to memory, 825 and a secondary reload to reload from / to general regs; that 826 seems to be a loosing proposition. */ 827 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode, 828 it won't be ferried through GP registers first. */ 829 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 830 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \ 831 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \ 832 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \ 833 ? 1 \ 834 : (MODE) == V2SFmode \ 835 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \ 836 || GENERAL_REGISTER_P (REGNO)) \ 837 : (MODE) == V4SFmode \ 838 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \ 839 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \ 840 : (MODE) == V16SFmode \ 841 ? (TARGET_SHMEDIA \ 842 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \ 843 : (REGNO) == FIRST_XD_REG) \ 844 : FP_REGISTER_P (REGNO) \ 845 ? ((MODE) == SFmode || (MODE) == SImode \ 846 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \ 847 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \ 848 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \ 849 || (MODE) == V2SFmode || (MODE) == TImode))) \ 850 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \ 851 : XD_REGISTER_P (REGNO) \ 852 ? (MODE) == DFmode \ 853 : TARGET_REGISTER_P (REGNO) \ 854 ? ((MODE) == DImode || (MODE) == SImode) \ 855 : (REGNO) == PR_REG ? 0 \ 856 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \ 857 : 1) 858 859 /* Value is 1 if MODE is a supported vector mode. */ 860 #define VECTOR_MODE_SUPPORTED_P(MODE) \ 861 ((TARGET_FPU_ANY \ 862 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \ 863 || (TARGET_SHMEDIA \ 864 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \ 865 || (MODE) == V2SImode))) 866 867 /* Value is 1 if it is a good idea to tie two pseudo registers 868 when one has mode MODE1 and one has mode MODE2. 869 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 870 for any hard reg, then this must be 0 for correct output. 871 That's the case for xd registers: we don't hold SFmode values in 872 them, so we can't tie an SFmode pseudos with one in another 873 floating-point mode. */ 874 875 #define MODES_TIEABLE_P(MODE1, MODE2) \ 876 ((MODE1) == (MODE2) \ 877 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 878 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \ 879 && (GET_MODE_SIZE (MODE2) <= 4)) \ 880 : ((MODE1) != SFmode && (MODE2) != SFmode)))) 881 882 /* A C expression that is nonzero if hard register NEW_REG can be 883 considered for use as a rename register for OLD_REG register */ 884 885 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 886 sh_hard_regno_rename_ok (OLD_REG, NEW_REG) 887 888 /* Specify the registers used for certain standard purposes. 889 The values of these macros are register numbers. */ 890 891 /* Define this if the program counter is overloaded on a register. */ 892 /* #define PC_REGNUM 15*/ 893 894 /* Register to use for pushing function arguments. */ 895 #define STACK_POINTER_REGNUM SP_REG 896 897 /* Base register for access to local variables of the function. */ 898 #define FRAME_POINTER_REGNUM FP_REG 899 900 /* Fake register that holds the address on the stack of the 901 current function's return address. */ 902 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG 903 904 /* Register to hold the addressing base for position independent 905 code access to data items. */ 906 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) 907 908 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 909 910 /* Value should be nonzero if functions must have frame pointers. 911 Zero means the frame pointer need not be set up (and parms may be accessed 912 via the stack pointer) in functions that seem suitable. */ 913 914 #define FRAME_POINTER_REQUIRED 0 915 916 /* Definitions for register eliminations. 917 918 We have three registers that can be eliminated on the SH. First, the 919 frame pointer register can often be eliminated in favor of the stack 920 pointer register. Secondly, the argument pointer register can always be 921 eliminated; it is replaced with either the stack or frame pointer. 922 Third, there is the return address pointer, which can also be replaced 923 with either the stack or the frame pointer. */ 924 925 /* This is an array of structures. Each structure initializes one pair 926 of eliminable registers. The "from" register number is given first, 927 followed by "to". Eliminations of the same "from" register are listed 928 in order of preference. */ 929 930 /* If you add any registers here that are not actually hard registers, 931 and that have any alternative of elimination that doesn't always 932 apply, you need to amend calc_live_regs to exclude it, because 933 reload spills all eliminable registers where it sees an 934 can_eliminate == 0 entry, thus making them 'live' . 935 If you add any hard registers that can be eliminated in different 936 ways, you have to patch reload to spill them only when all alternatives 937 of elimination fail. */ 938 939 #define ELIMINABLE_REGS \ 940 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 941 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 942 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 943 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 944 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} 945 946 /* Given FROM and TO register numbers, say whether this elimination 947 is allowed. */ 948 #define CAN_ELIMINATE(FROM, TO) \ 949 (!((FROM) == FRAME_POINTER_REGNUM && ! frame_pointer_needed)) 950 951 /* Define the offset between two registers, one to be eliminated, and the other 952 its replacement, at the start of a routine. */ 953 954 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 955 OFFSET = initial_elimination_offset ((FROM), (TO)) 956 957 /* Base register for access to arguments of the function. */ 958 #define ARG_POINTER_REGNUM AP_REG 959 960 /* Register in which the static-chain is passed to a function. */ 961 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3) 962 963 /* The register in which a struct value address is passed. */ 964 965 #define STRUCT_VALUE_REGNUM 2 966 967 /* If the structure value address is not passed in a register, define 968 `STRUCT_VALUE' as an expression returning an RTX for the place 969 where the address is passed. If it returns 0, the address is 970 passed as an "invisible" first argument. */ 971 972 /* The Hitachi calling convention doesn't quite fit into this scheme since 973 the address is passed like an invisible argument, but one that is always 974 passed in memory. */ 975 #define STRUCT_VALUE \ 976 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM)) 977 978 #define RETURN_IN_MEMORY(TYPE) \ 979 (TARGET_SH5 \ 980 ? ((TYPE_MODE (TYPE) == BLKmode \ 981 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \ 982 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \ 983 : (TYPE_MODE (TYPE) == BLKmode \ 984 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE)) 985 986 /* Don't default to pcc-struct-return, because we have already specified 987 exactly how to return structures in the RETURN_IN_MEMORY macro. */ 988 989 #define DEFAULT_PCC_STRUCT_RETURN 0 990 991 #define SHMEDIA_REGS_STACK_ADJUST() \ 992 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \ 993 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \ 994 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \ 995 : 0) 996 997 998 /* Define the classes of registers for register constraints in the 999 machine description. Also define ranges of constants. 1000 1001 One of the classes must always be named ALL_REGS and include all hard regs. 1002 If there is more than one class, another class must be named NO_REGS 1003 and contain no registers. 1004 1005 The name GENERAL_REGS must be the name of a class (or an alias for 1006 another name such as ALL_REGS). This is the class of registers 1007 that is allowed by "g" or "r" in a register constraint. 1008 Also, registers outside this class are allocated only when 1009 instructions express preferences for them. 1010 1011 The classes must be numbered in nondecreasing order; that is, 1012 a larger-numbered class must never be contained completely 1013 in a smaller-numbered class. 1014 1015 For any two classes, it is very desirable that there be another 1016 class that represents their union. */ 1017 1018 /* The SH has two sorts of general registers, R0 and the rest. R0 can 1019 be used as the destination of some of the arithmetic ops. There are 1020 also some special purpose registers; the T bit register, the 1021 Procedure Return Register and the Multiply Accumulate Registers. */ 1022 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by 1023 reg_class_subunion. We don't want to have an actual union class 1024 of these, because it would only be used when both classes are calculated 1025 to give the same cost, but there is only one FPUL register. 1026 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS 1027 applying to the actual instruction alternative considered. E.g., the 1028 y/r alternative of movsi_ie is considered to have no more cost that 1029 the r/r alternative, which is patently untrue. */ 1030 1031 enum reg_class 1032 { 1033 NO_REGS, 1034 R0_REGS, 1035 PR_REGS, 1036 T_REGS, 1037 MAC_REGS, 1038 FPUL_REGS, 1039 SIBCALL_REGS, 1040 GENERAL_REGS, 1041 FP0_REGS, 1042 FP_REGS, 1043 DF_HI_REGS, 1044 DF_REGS, 1045 FPSCR_REGS, 1046 GENERAL_FP_REGS, 1047 TARGET_REGS, 1048 ALL_REGS, 1049 LIM_REG_CLASSES 1050 }; 1051 1052 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1053 1054 /* Give names of register classes as strings for dump file. */ 1055 #define REG_CLASS_NAMES \ 1056 { \ 1057 "NO_REGS", \ 1058 "R0_REGS", \ 1059 "PR_REGS", \ 1060 "T_REGS", \ 1061 "MAC_REGS", \ 1062 "FPUL_REGS", \ 1063 "SIBCALL_REGS", \ 1064 "GENERAL_REGS", \ 1065 "FP0_REGS", \ 1066 "FP_REGS", \ 1067 "DF_HI_REGS", \ 1068 "DF_REGS", \ 1069 "FPSCR_REGS", \ 1070 "GENERAL_FP_REGS", \ 1071 "TARGET_REGS", \ 1072 "ALL_REGS", \ 1073 } 1074 1075 /* Define which registers fit in which classes. 1076 This is an initializer for a vector of HARD_REG_SET 1077 of length N_REG_CLASSES. */ 1078 1079 #define REG_CLASS_CONTENTS \ 1080 { \ 1081 /* NO_REGS: */ \ 1082 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1083 /* R0_REGS: */ \ 1084 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1085 /* PR_REGS: */ \ 1086 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ 1087 /* T_REGS: */ \ 1088 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ 1089 /* MAC_REGS: */ \ 1090 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ 1091 /* FPUL_REGS: */ \ 1092 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \ 1093 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1094 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1095 /* GENERAL_REGS: */ \ 1096 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \ 1097 /* FP0_REGS: */ \ 1098 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ 1099 /* FP_REGS: */ \ 1100 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1101 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \ 1102 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1103 /* DF_REGS: */ \ 1104 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1105 /* FPSCR_REGS: */ \ 1106 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ 1107 /* GENERAL_FP_REGS: */ \ 1108 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \ 1109 /* TARGET_REGS: */ \ 1110 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ 1111 /* ALL_REGS: */ \ 1112 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \ 1113 } 1114 1115 /* The same information, inverted: 1116 Return the class number of the smallest class containing 1117 reg number REGNO. This could be a conditional expression 1118 or could index an array. */ 1119 1120 extern int regno_reg_class[FIRST_PSEUDO_REGISTER]; 1121 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] 1122 1123 /* When defined, the compiler allows registers explicitly used in the 1124 rtl to be used as spill registers but prevents the compiler from 1125 extending the lifetime of these registers. */ 1126 1127 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA) 1128 1129 /* The order in which register should be allocated. */ 1130 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, 1131 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be 1132 spilled or used otherwise, we better have the FP_REGS allocated first. */ 1133 #define REG_ALLOC_ORDER \ 1134 { 65, 66, 67, 68, 69, 70, 71, 64, \ 1135 72, 73, 74, 75, 76, 77, 78, 79, \ 1136 136,137,138,139,140,141,142,143, \ 1137 80, 81, 82, 83, 84, 85, 86, 87, \ 1138 88, 89, 90, 91, 92, 93, 94, 95, \ 1139 96, 97, 98, 99,100,101,102,103, \ 1140 104,105,106,107,108,109,110,111, \ 1141 112,113,114,115,116,117,118,119, \ 1142 120,121,122,123,124,125,126,127, \ 1143 151, 1, 2, 3, 7, 6, 5, 4, \ 1144 0, 8, 9, 10, 11, 12, 13, 14, \ 1145 16, 17, 18, 19, 20, 21, 22, 23, \ 1146 24, 25, 26, 27, 28, 29, 30, 31, \ 1147 32, 33, 34, 35, 36, 37, 38, 39, \ 1148 40, 41, 42, 43, 44, 45, 46, 47, \ 1149 48, 49, 50, 51, 52, 53, 54, 55, \ 1150 56, 57, 58, 59, 60, 61, 62, 63, \ 1151 150, 15,145,146,147,144,148,149, \ 1152 128,129,130,131,132,133,134,135, \ 1153 152 } 1154 1155 /* The class value for index registers, and the one for base regs. */ 1156 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS) 1157 #define BASE_REG_CLASS GENERAL_REGS 1158 1159 /* Get reg_class from a letter such as appears in the machine 1160 description. */ 1161 extern enum reg_class reg_class_from_letter[]; 1162 1163 #define REG_CLASS_FROM_LETTER(C) \ 1164 ( ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS ) 1165 1166 /* The letters I, J, K, L and M in a register constraint string 1167 can be used to stand for particular ranges of immediate operands. 1168 This macro defines what the ranges are. 1169 C is the letter, and VALUE is a constant value. 1170 Return 1 if VALUE is in the range specified by C. 1171 I: arithmetic operand -127..128, as used in add, sub, etc 1172 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori 1173 K: shift operand 1,2,8 or 16 1174 L: logical operand 0..255, as used in and, or, etc. 1175 M: constant 1 1176 N: constant 0 1177 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori 1178 P: arithmetic operand -512..511, as used in SHmedia andi, ori 1179 */ 1180 1181 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ 1182 && ((HOST_WIDE_INT)(VALUE)) <= 127) 1183 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ 1184 && ((HOST_WIDE_INT)(VALUE)) <= 32767) 1185 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) 1186 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1187 && ((HOST_WIDE_INT)(VALUE)) <= 255) 1188 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) 1189 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) 1190 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \ 1191 && ((HOST_WIDE_INT)(VALUE)) <= 31) 1192 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ 1193 && ((HOST_WIDE_INT)(VALUE)) <= 511) 1194 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1195 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ 1196 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ 1197 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ 1198 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ 1199 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 1200 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ 1201 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ 1202 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ 1203 : 0) 1204 1205 /* Similar, but for floating constants, and defining letters G and H. 1206 Here VALUE is the CONST_DOUBLE rtx itself. */ 1207 1208 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1209 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \ 1210 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \ 1211 : (C) == 'F') 1212 1213 /* Given an rtx X being reloaded into a reg required to be 1214 in class CLASS, return the class of reg to actually use. 1215 In general this is just CLASS; but on some machines 1216 in some cases it is preferable to use a more restrictive class. */ 1217 1218 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1219 ((CLASS) == NO_REGS && TARGET_SHMEDIA \ 1220 && (GET_CODE (X) == CONST_DOUBLE \ 1221 || GET_CODE (X) == SYMBOL_REF) \ 1222 ? GENERAL_REGS \ 1223 : (CLASS)) \ 1224 1225 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 1226 ((((REGCLASS_HAS_FP_REG (CLASS) \ 1227 && (GET_CODE (X) == REG \ 1228 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1229 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \ 1230 && TARGET_FMOVD)))) \ 1231 || (REGCLASS_HAS_GENERAL_REG (CLASS) \ 1232 && GET_CODE (X) == REG \ 1233 && FP_REGISTER_P (REGNO (X)))) \ 1234 && ! TARGET_SHMEDIA \ 1235 && ((MODE) == SFmode || (MODE) == SImode)) \ 1236 ? FPUL_REGS \ 1237 : (((CLASS) == FPUL_REGS \ 1238 || (REGCLASS_HAS_FP_REG (CLASS) \ 1239 && ! TARGET_SHMEDIA && MODE == SImode)) \ 1240 && (GET_CODE (X) == MEM \ 1241 || (GET_CODE (X) == REG \ 1242 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1243 || REGNO (X) == T_REG \ 1244 || system_reg_operand (X, VOIDmode))))) \ 1245 ? GENERAL_REGS \ 1246 : ((CLASS) == TARGET_REGS \ 1247 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ 1248 ? ((target_operand ((X), (MODE)) \ 1249 && ! target_reg_operand ((X), (MODE))) \ 1250 ? NO_REGS : GENERAL_REGS) \ 1251 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ 1252 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \ 1253 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ 1254 ? GENERAL_REGS \ 1255 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \ 1256 && TARGET_REGISTER_P (REGNO (X))) \ 1257 ? GENERAL_REGS : NO_REGS) 1258 1259 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ 1260 ((REGCLASS_HAS_FP_REG (CLASS) \ 1261 && ! TARGET_SHMEDIA \ 1262 && immediate_operand ((X), (MODE)) \ 1263 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \ 1264 && (MODE) == SFmode && fldi_ok ())) \ 1265 ? R0_REGS \ 1266 : (CLASS == FPUL_REGS \ 1267 && ((GET_CODE (X) == REG \ 1268 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \ 1269 || REGNO (X) == T_REG)) \ 1270 || GET_CODE (X) == PLUS)) \ 1271 ? GENERAL_REGS \ 1272 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \ 1273 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \ 1274 ? GENERAL_REGS \ 1275 : R0_REGS) \ 1276 : (CLASS == FPSCR_REGS \ 1277 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1278 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\ 1279 ? GENERAL_REGS \ 1280 : (REGCLASS_HAS_FP_REG (CLASS) \ 1281 && TARGET_SHMEDIA \ 1282 && immediate_operand ((X), (MODE)) \ 1283 && (X) != CONST0_RTX (GET_MODE (X)) \ 1284 && GET_MODE (X) != V4SFmode) \ 1285 ? GENERAL_REGS \ 1286 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X))) 1287 1288 /* Return the maximum number of consecutive registers 1289 needed to represent mode MODE in a register of class CLASS. 1290 1291 On SH this is the size of MODE in words. */ 1292 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1293 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1294 1295 /* If defined, gives a class of registers that cannot be used as the 1296 operand of a SUBREG that changes the mode of the object illegally. */ 1297 /* ??? We need to renumber the internal numbers for the frnn registers 1298 when in little endian in order to allow mode size changes. */ 1299 1300 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1301 sh_cannot_change_mode_class (FROM, TO, CLASS) 1302 1303 /* Stack layout; function entry, exit and calling. */ 1304 1305 /* Define the number of registers that can hold parameters. 1306 These macros are used only in other macro definitions below. */ 1307 1308 #define NPARM_REGS(MODE) \ 1309 (TARGET_FPU_ANY && (MODE) == SFmode \ 1310 ? (TARGET_SH5 ? 12 : 8) \ 1311 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1312 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1313 ? (TARGET_SH5 ? 12 : 8) \ 1314 : (TARGET_SH5 ? 8 : 4)) 1315 1316 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4)) 1317 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0)) 1318 1319 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4)) 1320 #define FIRST_FP_RET_REG FIRST_FP_REG 1321 1322 /* Define this if pushing a word on the stack 1323 makes the stack pointer a smaller address. */ 1324 #define STACK_GROWS_DOWNWARD 1325 1326 /* Define this macro if the addresses of local variable slots are at 1327 negative offsets from the frame pointer. 1328 1329 The SH only has positive indexes, so grow the frame up. */ 1330 /* #define FRAME_GROWS_DOWNWARD */ 1331 1332 /* Offset from the frame pointer to the first local variable slot to 1333 be allocated. */ 1334 #define STARTING_FRAME_OFFSET 0 1335 1336 /* If we generate an insn to push BYTES bytes, 1337 this says how many the stack pointer really advances by. */ 1338 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. 1339 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to 1340 do correct alignment. */ 1341 #if 0 1342 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 1343 #endif 1344 1345 /* Offset of first parameter from the argument pointer register value. */ 1346 #define FIRST_PARM_OFFSET(FNDECL) 0 1347 1348 /* Value is the number of byte of arguments automatically 1349 popped when returning from a subroutine call. 1350 FUNDECL is the declaration node of the function (as a tree), 1351 FUNTYPE is the data type of the function (as a tree), 1352 or for a library call it is an identifier node for the subroutine name. 1353 SIZE is the number of bytes of arguments passed on the stack. 1354 1355 On the SH, the caller does not pop any of its arguments that were passed 1356 on the stack. */ 1357 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1358 1359 /* Value is the number of bytes of arguments automatically popped when 1360 calling a subroutine. 1361 CUM is the accumulated argument list. 1362 1363 On SHcompact, the call trampoline pops arguments off the stack. */ 1364 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0) 1365 1366 /* Nonzero if we do not know how to pass TYPE solely in registers. 1367 Values that come in registers with inconvenient padding are stored 1368 to memory at the function start. */ 1369 1370 #define MUST_PASS_IN_STACK(MODE,TYPE) \ 1371 ((TYPE) != 0 \ 1372 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1373 || TREE_ADDRESSABLE (TYPE))) 1374 /* Some subroutine macros specific to this machine. */ 1375 1376 #define BASE_RETURN_VALUE_REG(MODE) \ 1377 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ 1378 ? FIRST_FP_RET_REG \ 1379 : TARGET_FPU_ANY && (MODE) == SCmode \ 1380 ? FIRST_FP_RET_REG \ 1381 : (TARGET_FPU_DOUBLE \ 1382 && ((MODE) == DFmode || (MODE) == SFmode \ 1383 || (MODE) == DCmode || (MODE) == SCmode )) \ 1384 ? FIRST_FP_RET_REG \ 1385 : FIRST_RET_REG) 1386 1387 #define BASE_ARG_REG(MODE) \ 1388 ((TARGET_SH3E && ((MODE) == SFmode)) \ 1389 ? FIRST_FP_PARM_REG \ 1390 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1391 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1392 ? FIRST_FP_PARM_REG \ 1393 : FIRST_PARM_REG) 1394 1395 /* Define how to find the value returned by a function. 1396 VALTYPE is the data type of the value (as a tree). 1397 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1398 otherwise, FUNC is 0. 1399 For the SH, this is like LIBCALL_VALUE, except that we must change the 1400 mode like PROMOTE_MODE does. 1401 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types 1402 tested here has to be kept in sync with the one in explow.c:promote_mode. */ 1403 1404 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1405 gen_rtx (REG, \ 1406 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \ 1407 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \ 1408 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \ 1409 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \ 1410 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \ 1411 || TREE_CODE (VALTYPE) == CHAR_TYPE \ 1412 || TREE_CODE (VALTYPE) == REAL_TYPE \ 1413 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \ 1414 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \ 1415 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) 1416 1417 /* Define how to find the value returned by a library function 1418 assuming the value has mode MODE. */ 1419 #define LIBCALL_VALUE(MODE) \ 1420 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE)); 1421 1422 /* 1 if N is a possible register number for a function value. */ 1423 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1424 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \ 1425 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG)) 1426 1427 /* 1 if N is a possible register number for function argument passing. */ 1428 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1429 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \ 1430 + NPARM_REGS (SImode))) \ 1431 || (TARGET_FPU_ANY \ 1432 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \ 1433 + NPARM_REGS (SFmode)))) 1434 1435 /* Define a data type for recording info about an argument list 1436 during the scan of that argument list. This data type should 1437 hold all necessary information about the function itself 1438 and about the args processed so far, enough to enable macros 1439 such as FUNCTION_ARG to determine where the next arg should go. 1440 1441 On SH, this is a single integer, which is a number of words 1442 of arguments scanned so far (including the invisible argument, 1443 if any, which holds the structure-value-address). 1444 Thus NARGREGS or more means all following args should go on the stack. */ 1445 1446 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; 1447 struct sh_args { 1448 int arg_count[2]; 1449 int force_mem; 1450 /* Nonzero if a prototype is available for the function. */ 1451 int prototype_p; 1452 /* The number of an odd floating-point register, that should be used 1453 for the next argument of type float. */ 1454 int free_single_fp_reg; 1455 /* Whether we're processing an outgoing function call. */ 1456 int outgoing; 1457 /* The number of general-purpose registers that should have been 1458 used to pass partial arguments, that are passed totally on the 1459 stack. On SHcompact, a call trampoline will pop them off the 1460 stack before calling the actual function, and, if the called 1461 function is implemented in SHcompact mode, the incoming arguments 1462 decoder will push such arguments back onto the stack. For 1463 incoming arguments, STACK_REGS also takes into account other 1464 arguments passed by reference, that the decoder will also push 1465 onto the stack. */ 1466 int stack_regs; 1467 /* The number of general-purpose registers that should have been 1468 used to pass arguments, if the arguments didn't have to be passed 1469 by reference. */ 1470 int byref_regs; 1471 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by 1472 reference. */ 1473 int byref; 1474 1475 /* call_cookie is a bitmask used by call expanders, as well as 1476 function prologue and epilogues, to allow SHcompact to comply 1477 with the SH5 32-bit ABI, that requires 64-bit registers to be 1478 used even though only the lower 32-bit half is visible in 1479 SHcompact mode. The strategy is to call SHmedia trampolines. 1480 1481 The alternatives for each of the argument-passing registers are 1482 (a) leave it unchanged; (b) pop it off the stack; (c) load its 1483 contents from the address in it; (d) add 8 to it, storing the 1484 result in the next register, then (c); (e) copy it from some 1485 floating-point register, 1486 1487 Regarding copies from floating-point registers, r2 may only be 1488 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe 1489 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2, 1490 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8. 1491 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or 1492 dr10. 1493 1494 The bit mask is structured as follows: 1495 1496 - 1 bit to tell whether to set up a return trampoline. 1497 1498 - 3 bits to count the number consecutive registers to pop off the 1499 stack. 1500 1501 - 4 bits for each of r9, r8, r7 and r6. 1502 1503 - 3 bits for each of r5, r4, r3 and r2. 1504 1505 - 3 bits set to 0 (the most significant ones) 1506 1507 3 2 1 0 1508 1098 7654 3210 9876 5432 1098 7654 3210 1509 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST 1510 2223 3344 4555 6666 7777 8888 9999 SSS- 1511 1512 - If F is set, the register must be copied from an FP register, 1513 whose number is encoded in the remaining bits. 1514 1515 - Else, if L is set, the register must be loaded from the address 1516 contained in it. If the P bit is *not* set, the address of the 1517 following dword should be computed first, and stored in the 1518 following register. 1519 1520 - Else, if P is set, the register alone should be popped off the 1521 stack. 1522 1523 - After all this processing, the number of registers represented 1524 in SSS will be popped off the stack. This is an optimization 1525 for pushing/popping consecutive registers, typically used for 1526 varargs and large arguments partially passed in registers. 1527 1528 - If T is set, a return trampoline will be set up for 64-bit 1529 return values to be split into 2 32-bit registers. */ 1530 #define CALL_COOKIE_RET_TRAMP_SHIFT 0 1531 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT) 1532 #define CALL_COOKIE_STACKSEQ_SHIFT 1 1533 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT) 1534 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \ 1535 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7) 1536 #define CALL_COOKIE_INT_REG_SHIFT(REG) \ 1537 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3) 1538 #define CALL_COOKIE_INT_REG(REG, VAL) \ 1539 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG)) 1540 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \ 1541 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15)) 1542 long call_cookie; 1543 }; 1544 1545 #define CUMULATIVE_ARGS struct sh_args 1546 1547 #define GET_SH_ARG_CLASS(MODE) \ 1548 ((TARGET_FPU_ANY && (MODE) == SFmode) \ 1549 ? SH_ARG_FLOAT \ 1550 /* There's no mention of complex float types in the SH5 ABI, so we 1551 should presumably handle them as aggregate types. */ \ 1552 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ 1553 ? SH_ARG_INT \ 1554 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1555 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1556 ? SH_ARG_FLOAT : SH_ARG_INT) 1557 1558 #define ROUND_ADVANCE(SIZE) \ 1559 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1560 1561 /* Round a register number up to a proper boundary for an arg of mode 1562 MODE. 1563 1564 The SH doesn't care about double alignment, so we only 1565 round doubles to even regs when asked to explicitly. */ 1566 1567 #define ROUND_REG(CUM, MODE) \ 1568 (((TARGET_ALIGN_DOUBLE \ 1569 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \ 1570 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\ 1571 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ 1572 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ 1573 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \ 1574 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]) 1575 1576 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1577 for a call to a function whose data type is FNTYPE. 1578 For a library call, FNTYPE is 0. 1579 1580 On SH, the offset always starts at 0: the first parm reg is always 1581 the same reg for a given argument class. 1582 1583 For TARGET_HITACHI, the structure value pointer is passed in memory. */ 1584 1585 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1586 do { \ 1587 (CUM).arg_count[(int) SH_ARG_INT] = 0; \ 1588 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \ 1589 (CUM).force_mem \ 1590 = (TARGET_HITACHI && FNTYPE \ 1591 && aggregate_value_p (TREE_TYPE (FNTYPE))); \ 1592 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \ 1593 (CUM).arg_count[(int) SH_ARG_INT] \ 1594 = (TARGET_SH5 && (FNTYPE) \ 1595 && aggregate_value_p (TREE_TYPE (FNTYPE))); \ 1596 (CUM).free_single_fp_reg = 0; \ 1597 (CUM).outgoing = 1; \ 1598 (CUM).stack_regs = 0; \ 1599 (CUM).byref_regs = 0; \ 1600 (CUM).byref = 0; \ 1601 (CUM).call_cookie \ 1602 = (CALL_COOKIE_RET_TRAMP \ 1603 (TARGET_SHCOMPACT && (FNTYPE) \ 1604 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \ 1605 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \ 1606 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \ 1607 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \ 1608 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \ 1609 (FNTYPE))) \ 1610 == FIRST_RET_REG))); \ 1611 } while (0) 1612 1613 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1614 do { \ 1615 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \ 1616 (CUM).call_cookie \ 1617 = (CALL_COOKIE_RET_TRAMP \ 1618 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \ 1619 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \ 1620 } while (0) 1621 1622 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1623 do { \ 1624 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \ 1625 (CUM).outgoing = 0; \ 1626 } while (0) 1627 1628 /* FIXME: This is overly conservative. A SHcompact function that 1629 receives arguments ``by reference'' will have them stored in its 1630 own stack frame, so it must not pass pointers or references to 1631 these arguments to other functions by means of sibling calls. */ 1632 #define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1633 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0) 1634 1635 /* Update the data in CUM to advance over an argument 1636 of mode MODE and data type TYPE. 1637 (TYPE is null for libcalls where that information may not be 1638 available.) */ 1639 1640 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1641 if ((CUM).force_mem) \ 1642 (CUM).force_mem = 0; \ 1643 else if (TARGET_SH5) \ 1644 { \ 1645 tree TYPE_ = ((CUM).byref && (TYPE) \ 1646 ? TREE_TYPE (TYPE) \ 1647 : (TYPE)); \ 1648 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \ 1649 ? TYPE_MODE (TYPE_) \ 1650 : (MODE)); \ 1651 int dwords = (((CUM).byref \ 1652 ? (CUM).byref \ 1653 : (MODE_) == BLKmode \ 1654 ? int_size_in_bytes (TYPE_) \ 1655 : GET_MODE_SIZE (MODE_)) + 7) / 8; \ 1656 int numregs = MIN (dwords, NPARM_REGS (SImode) \ 1657 - (CUM).arg_count[(int) SH_ARG_INT]); \ 1658 \ 1659 if (numregs) \ 1660 { \ 1661 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \ 1662 if (TARGET_SHCOMPACT \ 1663 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \ 1664 { \ 1665 (CUM).call_cookie \ 1666 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \ 1667 - numregs), 1); \ 1668 /* N.B. We want this also for outgoing. */\ 1669 (CUM).stack_regs += numregs; \ 1670 } \ 1671 else if ((CUM).byref) \ 1672 { \ 1673 if (! (CUM).outgoing) \ 1674 (CUM).stack_regs += numregs; \ 1675 (CUM).byref_regs += numregs; \ 1676 (CUM).byref = 0; \ 1677 do \ 1678 (CUM).call_cookie \ 1679 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \ 1680 - numregs), 2); \ 1681 while (--numregs); \ 1682 (CUM).call_cookie \ 1683 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \ 1684 - 1), 1); \ 1685 } \ 1686 else if (dwords > numregs) \ 1687 { \ 1688 int pushregs = numregs; \ 1689 \ 1690 if (TARGET_SHCOMPACT) \ 1691 (CUM).stack_regs += numregs; \ 1692 while (pushregs < NPARM_REGS (SImode) - 1 \ 1693 && (CALL_COOKIE_INT_REG_GET \ 1694 ((CUM).call_cookie, \ 1695 NPARM_REGS (SImode) - pushregs) \ 1696 == 1)) \ 1697 { \ 1698 (CUM).call_cookie \ 1699 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \ 1700 - pushregs, 1); \ 1701 pushregs++; \ 1702 } \ 1703 if (numregs == NPARM_REGS (SImode)) \ 1704 (CUM).call_cookie \ 1705 |= CALL_COOKIE_INT_REG (0, 1) \ 1706 | CALL_COOKIE_STACKSEQ (numregs - 1); \ 1707 else \ 1708 (CUM).call_cookie \ 1709 |= CALL_COOKIE_STACKSEQ (numregs); \ 1710 } \ 1711 } \ 1712 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \ 1713 && ((NAMED) || ! (CUM).prototype_p)) \ 1714 { \ 1715 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \ 1716 (CUM).free_single_fp_reg = 0; \ 1717 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \ 1718 < NPARM_REGS (SFmode)) \ 1719 { \ 1720 int numfpregs \ 1721 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \ 1722 NPARM_REGS (SFmode) \ 1723 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \ 1724 \ 1725 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \ 1726 \ 1727 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \ 1728 { \ 1729 if ((CUM).outgoing && numregs > 0) \ 1730 do \ 1731 { \ 1732 (CUM).call_cookie \ 1733 |= (CALL_COOKIE_INT_REG \ 1734 ((CUM).arg_count[(int) SH_ARG_INT] \ 1735 - numregs + ((numfpregs - 2) / 2), \ 1736 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \ 1737 - numfpregs) / 2)); \ 1738 } \ 1739 while (numfpregs -= 2); \ 1740 } \ 1741 else if ((MODE_) == SFmode && (NAMED) \ 1742 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \ 1743 < NPARM_REGS (SFmode))) \ 1744 (CUM).free_single_fp_reg \ 1745 = FIRST_FP_PARM_REG - numfpregs \ 1746 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \ 1747 } \ 1748 } \ 1749 } \ 1750 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \ 1751 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \ 1752 = (ROUND_REG ((CUM), (MODE)) \ 1753 + ((MODE) == BLKmode \ 1754 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ 1755 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))))) 1756 1757 /* Return boolean indicating arg of mode MODE will be passed in a reg. 1758 This macro is only used in this file. */ 1759 1760 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1761 (((TYPE) == 0 \ 1762 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \ 1763 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \ 1764 && ! (CUM).force_mem \ 1765 && (TARGET_SH3E \ 1766 ? ((MODE) == BLKmode \ 1767 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \ 1768 + int_size_in_bytes (TYPE)) \ 1769 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \ 1770 : ((ROUND_REG((CUM), (MODE)) \ 1771 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \ 1772 <= NPARM_REGS (MODE))) \ 1773 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE))) 1774 1775 /* Define where to put the arguments to a function. 1776 Value is zero to push the argument on the stack, 1777 or a hard register in which to store the argument. 1778 1779 MODE is the argument's machine mode. 1780 TYPE is the data type of the argument (as a tree). 1781 This is null for libcalls where that information may 1782 not be available. 1783 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1784 the preceding args and about the function being called. 1785 NAMED is nonzero if this argument is a named parameter 1786 (otherwise it is an extra parameter matching an ellipsis). 1787 1788 On SH the first args are normally in registers 1789 and the rest are pushed. Any arg that starts within the first 1790 NPARM_REGS words is at least partially passed in a register unless 1791 its data type forbids. */ 1792 1793 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1794 ((! TARGET_SH5 \ 1795 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1796 && ((NAMED) || !TARGET_HITACHI)) \ 1797 ? gen_rtx_REG ((MODE), \ 1798 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \ 1799 ^ ((MODE) == SFmode && TARGET_SH4 \ 1800 && TARGET_LITTLE_ENDIAN != 0))) \ 1801 : TARGET_SH5 \ 1802 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \ 1803 ? GEN_INT ((CUM).call_cookie) \ 1804 /* The following test assumes unnamed arguments are promoted to \ 1805 DFmode. */ \ 1806 : (MODE) == SFmode && (CUM).free_single_fp_reg \ 1807 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \ 1808 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \ 1809 && ((NAMED) || ! (CUM).prototype_p) \ 1810 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \ 1811 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \ 1812 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \ 1813 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \ 1814 FIRST_FP_PARM_REG \ 1815 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \ 1816 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1817 && (! TARGET_SHCOMPACT \ 1818 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \ 1819 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \ 1820 (TYPE), (NAMED))))) \ 1821 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \ 1822 + (CUM).arg_count[(int) SH_ARG_INT])) \ 1823 : 0) \ 1824 : 0) 1825 1826 /* Whether an argument must be passed by reference. On SHcompact, we 1827 pretend arguments wider than 32-bits that would have been passed in 1828 registers are passed by reference, so that an SHmedia trampoline 1829 loads them into the full 64-bits registers. */ 1830 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \ 1831 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \ 1832 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED))) 1833 1834 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \ 1835 ((CUM).byref \ 1836 = (TARGET_SHCOMPACT \ 1837 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1838 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \ 1839 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \ 1840 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \ 1841 >= NPARM_REGS (SFmode)))) \ 1842 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ 1843 : GET_MODE_SIZE (MODE)) > 4 \ 1844 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \ 1845 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \ 1846 (TYPE), (NAMED))) \ 1847 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ 1848 : GET_MODE_SIZE (MODE)) \ 1849 : 0) 1850 1851 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit 1852 register in SHcompact mode, it must be padded in the most 1853 significant end. This means that passing it by reference wouldn't 1854 pad properly on a big-endian machine. In this particular case, we 1855 pass this argument on the stack, in a way that the call trampoline 1856 will load its value into the appropriate register. */ 1857 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \ 1858 ((MODE) == BLKmode \ 1859 && TARGET_SHCOMPACT \ 1860 && ! TARGET_LITTLE_ENDIAN \ 1861 && int_size_in_bytes (TYPE) > 4 \ 1862 && int_size_in_bytes (TYPE) < 8) 1863 1864 /* Minimum alignment for an argument to be passed by callee-copy 1865 reference. We need such arguments to be aligned to 8 byte 1866 boundaries, because they'll be loaded using quad loads. */ 1867 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) 1868 1869 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \ 1870 ((CUM).outgoing \ 1871 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \ 1872 : GET_MODE_ALIGNMENT (MODE)) \ 1873 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0)) 1874 1875 /* The SH5 ABI requires floating-point arguments to be passed to 1876 functions without a prototype in both an FP register and a regular 1877 register or the stack. When passing the argument in both FP and 1878 general-purpose registers, list the FP register first. */ 1879 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \ 1880 (gen_rtx_PARALLEL \ 1881 ((MODE), \ 1882 gen_rtvec (2, \ 1883 gen_rtx_EXPR_LIST \ 1884 (VOIDmode, \ 1885 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1886 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ 1887 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \ 1888 : NULL_RTX), \ 1889 const0_rtx), \ 1890 gen_rtx_EXPR_LIST \ 1891 (VOIDmode, \ 1892 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1893 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \ 1894 + (CUM).arg_count[(int) SH_ARG_INT]) \ 1895 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ 1896 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \ 1897 const0_rtx)))) 1898 1899 /* The SH5 ABI requires regular registers or stack slots to be 1900 reserved for floating-point arguments. Registers are taken care of 1901 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here. 1902 Unfortunately, there's no way to just reserve a stack slot, so 1903 we'll end up needlessly storing a copy of the argument in the 1904 stack. For incoming arguments, however, the PARALLEL will be 1905 optimized to the register-only form, and the value in the stack 1906 slot won't be used at all. */ 1907 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \ 1908 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ 1909 ? gen_rtx_REG ((MODE), (REG)) \ 1910 : gen_rtx_PARALLEL ((MODE), \ 1911 gen_rtvec (2, \ 1912 gen_rtx_EXPR_LIST \ 1913 (VOIDmode, NULL_RTX, \ 1914 const0_rtx), \ 1915 gen_rtx_EXPR_LIST \ 1916 (VOIDmode, gen_rtx_REG ((MODE), \ 1917 (REG)), \ 1918 const0_rtx)))) 1919 1920 #define STRICT_ARGUMENT_NAMING TARGET_SH5 1921 1922 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5) 1923 1924 /* For an arg passed partly in registers and partly in memory, 1925 this is the number of registers used. 1926 For args passed entirely in registers or entirely in memory, zero. 1927 1928 We sometimes split args. */ 1929 1930 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1931 ((! TARGET_SH5 \ 1932 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1933 && ! TARGET_SH4 \ 1934 && (ROUND_REG ((CUM), (MODE)) \ 1935 + ((MODE) != BLKmode \ 1936 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ 1937 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \ 1938 > NPARM_REGS (MODE))) \ 1939 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \ 1940 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \ 1941 && ! TARGET_SHCOMPACT) \ 1942 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \ 1943 : 0) 1944 1945 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1946 (TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \ 1947 && ((CUM).arg_count[(int) SH_ARG_INT] \ 1948 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode)) 1949 1950 /* Perform any needed actions needed for a function that is receiving a 1951 variable number of arguments. */ 1952 1953 /* We actually emit the code in sh_expand_prologue. We used to use 1954 a static variable to flag that we need to emit this code, but that 1955 doesn't when inlining, when functions are deferred and then emitted 1956 later. Fortunately, we already have two flags that are part of struct 1957 function that tell if a function uses varargs or stdarg. */ 1958 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \ 1959 if (! current_function_stdarg) \ 1960 abort (); \ 1961 while (0) 1962 1963 /* Define the `__builtin_va_list' type for the ABI. */ 1964 #define BUILD_VA_LIST_TYPE(VALIST) \ 1965 (VALIST) = sh_build_va_list () 1966 1967 /* Implement `va_start' for varargs and stdarg. */ 1968 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1969 sh_va_start (valist, nextarg) 1970 1971 /* Implement `va_arg'. */ 1972 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1973 sh_va_arg (valist, type) 1974 1975 /* Call the function profiler with a given profile label. 1976 We use two .aligns, so as to make sure that both the .long is aligned 1977 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) 1978 from the trapa instruction. */ 1979 1980 #define FUNCTION_PROFILER(STREAM,LABELNO) \ 1981 { \ 1982 fprintf((STREAM), "\t.align\t2\n"); \ 1983 fprintf((STREAM), "\ttrapa\t#33\n"); \ 1984 fprintf((STREAM), "\t.align\t2\n"); \ 1985 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1986 } 1987 1988 /* Define this macro if the code for function profiling should come 1989 before the function prologue. Normally, the profiling code comes 1990 after. */ 1991 1992 #define PROFILE_BEFORE_PROLOGUE 1993 1994 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1995 the stack pointer does not matter. The value is tested only in 1996 functions that have frame pointers. 1997 No definition is equivalent to always zero. */ 1998 1999 #define EXIT_IGNORE_STACK 1 2000 2001 /* 2002 On the SH, the trampoline looks like 2003 2 0002 D202 mov.l l2,r2 2004 1 0000 D301 mov.l l1,r3 2005 3 0004 422B jmp @r2 2006 4 0006 0009 nop 2007 5 0008 00000000 l1: .long area 2008 6 000c 00000000 l2: .long function */ 2009 2010 /* Length in units of the trampoline for entering a nested function. */ 2011 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16) 2012 2013 /* Alignment required for a trampoline in bits . */ 2014 #define TRAMPOLINE_ALIGNMENT \ 2015 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \ 2016 : TARGET_SHMEDIA ? 256 : 64) 2017 2018 /* Emit RTL insns to initialize the variable parts of a trampoline. 2019 FNADDR is an RTX for the address of the function's pure code. 2020 CXT is an RTX for the static chain value for the function. */ 2021 2022 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 2023 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 2024 2025 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */ 2026 2027 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \ 2028 { \ 2029 if (TARGET_SHMEDIA) \ 2030 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \ 2031 gen_reg_rtx (Pmode), 0, \ 2032 OPTAB_LIB_WIDEN); \ 2033 } while (0) 2034 2035 /* A C expression whose value is RTL representing the value of the return 2036 address for the frame COUNT steps up from the current frame. 2037 FRAMEADDR is already the frame pointer of the COUNT frame, so we 2038 can ignore COUNT. */ 2039 2040 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2041 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0) 2042 2043 /* A C expression whose value is RTL representing the location of the 2044 incoming return address at the beginning of any function, before the 2045 prologue. This RTL is either a REG, indicating that the return 2046 value is saved in REG, or a MEM representing a location in 2047 the stack. */ 2048 #define INCOMING_RETURN_ADDR_RTX \ 2049 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) 2050 2051 /* Generate necessary RTL for __builtin_saveregs(). */ 2052 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs () 2053 2054 /* Addressing modes, and classification of registers for them. */ 2055 #define HAVE_POST_INCREMENT TARGET_SH1 2056 /*#define HAVE_PRE_INCREMENT 1*/ 2057 /*#define HAVE_POST_DECREMENT 1*/ 2058 #define HAVE_PRE_DECREMENT TARGET_SH1 2059 2060 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \ 2061 ? 0 : TARGET_SH1) 2062 #define USE_LOAD_PRE_DECREMENT(mode) 0 2063 #define USE_STORE_POST_INCREMENT(mode) 0 2064 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \ 2065 ? 0 : TARGET_SH1) 2066 2067 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \ 2068 < (TARGET_SMALLCODE ? 2 : \ 2069 ((ALIGN >= 32) ? 16 : 2))) 2070 2071 /* Macros to check register numbers against specific register classes. */ 2072 2073 /* These assume that REGNO is a hard or pseudo reg number. 2074 They give nonzero only if REGNO is a hard reg of the suitable class 2075 or a pseudo reg currently allocated to a suitable hard reg. 2076 Since they use reg_renumber, they are safe only once reg_renumber 2077 has been allocated, which happens in local-alloc.c. */ 2078 2079 #define REGNO_OK_FOR_BASE_P(REGNO) \ 2080 (GENERAL_OR_AP_REGISTER_P (REGNO) \ 2081 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) 2082 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 2083 (TARGET_SHMEDIA \ 2084 ? (GENERAL_REGISTER_P (REGNO) \ 2085 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ 2086 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) 2087 2088 /* Maximum number of registers that can appear in a valid memory 2089 address. */ 2090 2091 #define MAX_REGS_PER_ADDRESS 2 2092 2093 /* Recognize any constant value that is a valid address. */ 2094 2095 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 2096 2097 /* Nonzero if the constant value X is a legitimate general operand. */ 2098 2099 #define LEGITIMATE_CONSTANT_P(X) \ 2100 (TARGET_SHMEDIA \ 2101 ? ((GET_MODE (X) != DFmode \ 2102 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \ 2103 || (X) == CONST0_RTX (GET_MODE (X)) \ 2104 || ! TARGET_SHMEDIA_FPU \ 2105 || TARGET_SHMEDIA64) \ 2106 : (GET_CODE (X) != CONST_DOUBLE \ 2107 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \ 2108 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))) 2109 2110 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2111 and check its validity for a certain class. 2112 We have two alternate definitions for each of them. 2113 The usual definition accepts all pseudo regs; the other rejects 2114 them unless they have been allocated suitable hard regs. 2115 The symbol REG_OK_STRICT causes the latter definition to be used. */ 2116 2117 #ifndef REG_OK_STRICT 2118 2119 /* Nonzero if X is a hard reg that can be used as a base reg 2120 or if it is a pseudo reg. */ 2121 #define REG_OK_FOR_BASE_P(X) \ 2122 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2123 2124 /* Nonzero if X is a hard reg that can be used as an index 2125 or if it is a pseudo reg. */ 2126 #define REG_OK_FOR_INDEX_P(X) \ 2127 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ 2128 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2129 2130 /* Nonzero if X/OFFSET is a hard reg that can be used as an index 2131 or if X is a pseudo reg. */ 2132 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 2133 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ 2134 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2135 2136 #else 2137 2138 /* Nonzero if X is a hard reg that can be used as a base reg. */ 2139 #define REG_OK_FOR_BASE_P(X) \ 2140 REGNO_OK_FOR_BASE_P (REGNO (X)) 2141 2142 /* Nonzero if X is a hard reg that can be used as an index. */ 2143 #define REG_OK_FOR_INDEX_P(X) \ 2144 REGNO_OK_FOR_INDEX_P (REGNO (X)) 2145 2146 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */ 2147 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \ 2148 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0) 2149 2150 #endif 2151 2152 /* The 'Q' constraint is a pc relative load operand. */ 2153 #define EXTRA_CONSTRAINT_Q(OP) \ 2154 (GET_CODE (OP) == MEM \ 2155 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \ 2156 || (GET_CODE (XEXP ((OP), 0)) == CONST \ 2157 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \ 2158 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \ 2159 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT))) 2160 2161 /* The `S' constraint is a 16-bit constant, literal or symbolic. */ 2162 #define EXTRA_CONSTRAINT_S(OP) \ 2163 (GET_CODE (OP) == CONST \ 2164 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \ 2165 && GET_MODE (XEXP ((OP), 0)) == DImode \ 2166 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \ 2167 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \ 2168 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \ 2169 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \ 2170 && (MOVI_SHORI_BASE_OPERAND_P \ 2171 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \ 2172 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \ 2173 1)) == CONST_INT))) 2174 2175 /* Check whether OP is a datalabel unspec. */ 2176 #define DATALABEL_REF_NO_CONST_P(OP) \ 2177 (GET_CODE (OP) == UNSPEC \ 2178 && XINT ((OP), 1) == UNSPEC_DATALABEL \ 2179 && XVECLEN ((OP), 0) == 1 \ 2180 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \ 2181 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)) 2182 2183 /* Check whether OP is a datalabel unspec, possibly enclosed within a 2184 CONST. */ 2185 #define DATALABEL_REF_P(OP) \ 2186 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \ 2187 || DATALABEL_REF_NO_CONST_P (OP)) 2188 2189 #define GOT_ENTRY_P(OP) \ 2190 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2191 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) 2192 2193 #define GOTPLT_ENTRY_P(OP) \ 2194 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2195 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) 2196 2197 #define UNSPEC_GOTOFF_P(OP) \ 2198 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) 2199 2200 #define GOTOFF_P(OP) \ 2201 (GET_CODE (OP) == CONST \ 2202 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ 2203 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ 2204 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ 2205 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))) 2206 2207 #define PIC_ADDR_P(OP) \ 2208 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 2209 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) 2210 2211 #define NON_PIC_REFERENCE_P(OP) \ 2212 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ 2213 || DATALABEL_REF_P (OP) \ 2214 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ 2215 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ 2216 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \ 2217 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) 2218 2219 #define PIC_REFERENCE_P(OP) \ 2220 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ 2221 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) 2222 2223 #define MOVI_SHORI_BASE_OPERAND_P(OP) \ 2224 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP)) 2225 2226 /* The `T' constraint is a label or a symbol. */ 2227 #define EXTRA_CONSTRAINT_T(OP) \ 2228 (NON_PIC_REFERENCE_P (OP)) 2229 2230 /* A zero in any shape or form. */ 2231 #define EXTRA_CONSTRAINT_U(OP) \ 2232 ((OP) == CONST0_RTX (GET_MODE (OP))) 2233 2234 /* Any vector constant we can handle. */ 2235 #define EXTRA_CONSTRAINT_W(OP) \ 2236 (GET_CODE (OP) == CONST_VECTOR \ 2237 && (sh_rep_vec ((OP), VOIDmode) \ 2238 || (HOST_BITS_PER_WIDE_INT >= 64 \ 2239 ? sh_const_vec ((OP), VOIDmode) \ 2240 : sh_1el_vec ((OP), VOIDmode)))) 2241 2242 #define EXTRA_CONSTRAINT(OP, C) \ 2243 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ 2244 : (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \ 2245 : (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \ 2246 : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \ 2247 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \ 2248 : 0) 2249 2250 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2251 that is a valid memory address for an instruction. 2252 The MODE argument is the machine mode for the MEM expression 2253 that wants to use this address. */ 2254 2255 #define MODE_DISP_OK_4(X,MODE) \ 2256 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \ 2257 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode)) 2258 2259 #define MODE_DISP_OK_8(X,MODE) \ 2260 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \ 2261 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode)) 2262 2263 #define BASE_REGISTER_RTX_P(X) \ 2264 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 2265 || (GET_CODE (X) == SUBREG \ 2266 && GET_CODE (SUBREG_REG (X)) == REG \ 2267 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 2268 2269 /* Since this must be r0, which is a single register class, we must check 2270 SUBREGs more carefully, to be sure that we don't accept one that extends 2271 outside the class. */ 2272 #define INDEX_REGISTER_RTX_P(X) \ 2273 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 2274 || (GET_CODE (X) == SUBREG \ 2275 && GET_CODE (SUBREG_REG (X)) == REG \ 2276 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X)))) 2277 2278 /* Jump to LABEL if X is a valid address RTX. This must also take 2279 REG_OK_STRICT into account when deciding about valid registers, but it uses 2280 the above macros so we are in luck. 2281 2282 Allow REG 2283 REG+disp 2284 REG+r0 2285 REG++ 2286 --REG */ 2287 2288 /* ??? The SH3e does not have the REG+disp addressing mode when loading values 2289 into the FRx registers. We implement this by setting the maximum offset 2290 to zero when the value is SFmode. This also restricts loading of SFmode 2291 values into the integer registers, but that can't be helped. */ 2292 2293 /* The SH allows a displacement in a QI or HI amode, but only when the 2294 other operand is R0. GCC doesn't handle this very well, so we forgo 2295 all of that. 2296 2297 A legitimate index for a QI or HI is 0, SI can be any number 0..63, 2298 DI can be any number 0..60. */ 2299 2300 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ 2301 do { \ 2302 if (GET_CODE (OP) == CONST_INT) \ 2303 { \ 2304 if (TARGET_SHMEDIA) \ 2305 { \ 2306 int MODE_SIZE = GET_MODE_SIZE (MODE); \ 2307 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \ 2308 && INTVAL (OP) >= -512 * MODE_SIZE \ 2309 && INTVAL (OP) < 512 * MODE_SIZE) \ 2310 goto LABEL; \ 2311 else \ 2312 break; \ 2313 } \ 2314 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \ 2315 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \ 2316 } \ 2317 } while(0) 2318 2319 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 2320 { \ 2321 if (BASE_REGISTER_RTX_P (X)) \ 2322 goto LABEL; \ 2323 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 2324 && ! TARGET_SHMEDIA \ 2325 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \ 2326 goto LABEL; \ 2327 else if (GET_CODE (X) == PLUS \ 2328 && ((MODE) != PSImode || reload_completed)) \ 2329 { \ 2330 rtx xop0 = XEXP ((X), 0); \ 2331 rtx xop1 = XEXP ((X), 1); \ 2332 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ 2333 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \ 2334 if (GET_MODE_SIZE (MODE) <= 4 \ 2335 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \ 2336 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \ 2337 { \ 2338 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ 2339 goto LABEL; \ 2340 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ 2341 goto LABEL; \ 2342 } \ 2343 } \ 2344 } 2345 2346 /* Try machine-dependent ways of modifying an illegitimate address 2347 to be legitimate. If we find one, return the new, valid address. 2348 This macro is used in only one place: `memory_address' in explow.c. 2349 2350 OLDX is the address as it was before break_out_memory_refs was called. 2351 In some cases it is useful to look at this to decide what needs to be done. 2352 2353 MODE and WIN are passed so that this macro can use 2354 GO_IF_LEGITIMATE_ADDRESS. 2355 2356 It is always safe for this macro to do nothing. It exists to recognize 2357 opportunities to optimize the output. 2358 2359 For the SH, if X is almost suitable for indexing, but the offset is 2360 out of range, convert it into a normal form so that cse has a chance 2361 of reducing the number of address registers used. */ 2362 2363 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2364 { \ 2365 if (flag_pic) \ 2366 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 2367 if (GET_CODE (X) == PLUS \ 2368 && (GET_MODE_SIZE (MODE) == 4 \ 2369 || GET_MODE_SIZE (MODE) == 8) \ 2370 && GET_CODE (XEXP ((X), 1)) == CONST_INT \ 2371 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \ 2372 && ! TARGET_SHMEDIA \ 2373 && ! (TARGET_SH4 && (MODE) == DFmode) \ 2374 && ! (TARGET_SH3E && (MODE) == SFmode)) \ 2375 { \ 2376 rtx index_rtx = XEXP ((X), 1); \ 2377 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 2378 rtx sum; \ 2379 \ 2380 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \ 2381 /* On rare occasions, we might get an unaligned pointer \ 2382 that is indexed in a way to give an aligned address. \ 2383 Therefore, keep the lower two bits in offset_base. */ \ 2384 /* Instead of offset_base 128..131 use 124..127, so that \ 2385 simple add suffices. */ \ 2386 if (offset > 127) \ 2387 { \ 2388 offset_base = ((offset + 4) & ~60) - 4; \ 2389 } \ 2390 else \ 2391 offset_base = offset & ~60; \ 2392 /* Sometimes the normal form does not suit DImode. We \ 2393 could avoid that by using smaller ranges, but that \ 2394 would give less optimized code when SImode is \ 2395 prevalent. */ \ 2396 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 2397 { \ 2398 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \ 2399 GEN_INT (offset_base), NULL_RTX, 0, \ 2400 OPTAB_LIB_WIDEN); \ 2401 \ 2402 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \ 2403 goto WIN; \ 2404 } \ 2405 } \ 2406 } 2407 2408 /* A C compound statement that attempts to replace X, which is an address 2409 that needs reloading, with a valid memory address for an operand of 2410 mode MODE. WIN is a C statement label elsewhere in the code. 2411 2412 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form 2413 of the address. That will allow inheritance of the address reloads. */ 2414 2415 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2416 { \ 2417 if (GET_CODE (X) == PLUS \ 2418 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2419 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2420 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 2421 && ! TARGET_SHMEDIA \ 2422 && ! (TARGET_SH4 && (MODE) == DFmode) \ 2423 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \ 2424 { \ 2425 rtx index_rtx = XEXP (X, 1); \ 2426 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \ 2427 rtx sum; \ 2428 \ 2429 if (TARGET_SH3E && MODE == SFmode) \ 2430 { \ 2431 X = copy_rtx (X); \ 2432 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \ 2433 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 2434 (TYPE)); \ 2435 goto WIN; \ 2436 } \ 2437 /* Instead of offset_base 128..131 use 124..127, so that \ 2438 simple add suffices. */ \ 2439 if (offset > 127) \ 2440 { \ 2441 offset_base = ((offset + 4) & ~60) - 4; \ 2442 } \ 2443 else \ 2444 offset_base = offset & ~60; \ 2445 /* Sometimes the normal form does not suit DImode. We \ 2446 could avoid that by using smaller ranges, but that \ 2447 would give less optimized code when SImode is \ 2448 prevalent. */ \ 2449 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \ 2450 { \ 2451 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ 2452 GEN_INT (offset_base)); \ 2453 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\ 2454 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \ 2455 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \ 2456 (TYPE)); \ 2457 goto WIN; \ 2458 } \ 2459 } \ 2460 /* We must re-recognize what we created before. */ \ 2461 else if (GET_CODE (X) == PLUS \ 2462 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ 2463 && GET_CODE (XEXP (X, 0)) == PLUS \ 2464 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 2465 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ 2466 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2467 && ! TARGET_SHMEDIA \ 2468 && ! (TARGET_SH3E && MODE == SFmode)) \ 2469 { \ 2470 /* Because this address is so complex, we know it must have \ 2471 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \ 2472 it is already unshared, and needs no further unsharing. */ \ 2473 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \ 2474 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\ 2475 goto WIN; \ 2476 } \ 2477 } 2478 2479 /* Go to LABEL if ADDR (a legitimate address expression) 2480 has an effect that depends on the machine mode it is used for. 2481 2482 ??? Strictly speaking, we should also include all indexed addressing, 2483 because the index scale factor is the length of the operand. 2484 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to 2485 high if we did that. So we rely on reload to fix things up. */ 2486 2487 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 2488 { \ 2489 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ 2490 goto LABEL; \ 2491 } 2492 2493 /* Specify the machine mode that this machine uses 2494 for the index in the tablejump instruction. */ 2495 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) 2496 2497 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 2498 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ 2499 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 2500 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 2501 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 2502 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ 2503 : SImode) 2504 2505 /* Define as C expression which evaluates to nonzero if the tablejump 2506 instruction expects the table to contain offsets from the address of the 2507 table. 2508 Do not define this if the table should contain absolute addresses. */ 2509 #define CASE_VECTOR_PC_RELATIVE 1 2510 2511 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ 2512 #define FLOAT_TYPE_SIZE 32 2513 2514 /* Since the SH3e has only `float' support, it is desirable to make all 2515 floating point types equivalent to `float'. */ 2516 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64) 2517 2518 /* 'char' is signed by default. */ 2519 #define DEFAULT_SIGNED_CHAR 1 2520 2521 /* The type of size_t unsigned int. */ 2522 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") 2523 2524 #undef PTRDIFF_TYPE 2525 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") 2526 2527 #define WCHAR_TYPE "short unsigned int" 2528 #define WCHAR_TYPE_SIZE 16 2529 2530 #define SH_ELF_WCHAR_TYPE "long int" 2531 2532 /* Don't cse the address of the function being compiled. */ 2533 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/ 2534 2535 /* Max number of bytes we can move from memory to memory 2536 in one reasonably fast instruction. */ 2537 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4) 2538 2539 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever 2540 MOVE_MAX is not a compile-time constant. */ 2541 #define MAX_MOVE_MAX 8 2542 2543 /* Max number of bytes we want move_by_pieces to be able to copy 2544 efficiently. */ 2545 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4) 2546 2547 /* Define if operations between registers always perform the operation 2548 on the full register even if a narrower mode is specified. */ 2549 #define WORD_REGISTER_OPERATIONS 2550 2551 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2552 will either zero-extend or sign-extend. The value of this macro should 2553 be the code that says which one of the two operations is implicitly 2554 done, NIL if none. */ 2555 /* For SHmedia, we can truncate to QImode easier using zero extension. */ 2556 /* FP registers can load SImode values, but don't implicitly sign-extend 2557 them to DImode. */ 2558 #define LOAD_EXTEND_OP(MODE) \ 2559 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ 2560 : (MODE) != SImode ? SIGN_EXTEND : NIL) 2561 2562 /* Define if loading short immediate values into registers sign extends. */ 2563 #define SHORT_IMMEDIATES_SIGN_EXTEND 2564 2565 /* Nonzero if access to memory by bytes is no faster than for words. */ 2566 #define SLOW_BYTE_ACCESS 1 2567 2568 /* We assume that the store-condition-codes instructions store 0 for false 2569 and some other value for true. This is the value stored for true. */ 2570 2571 #define STORE_FLAG_VALUE 1 2572 2573 /* Immediate shift counts are truncated by the output routines (or was it 2574 the assembler?). Shift counts in a register are truncated by SH. Note 2575 that the native compiler puts too large (> 32) immediate shift counts 2576 into a register and shifts by the register, letting the SH decide what 2577 to do instead of doing that itself. */ 2578 /* ??? The library routines in lib1funcs.asm truncate the shift count. 2579 However, the SH3 has hardware shifts that do not truncate exactly as gcc 2580 expects - the sign bit is significant - so it appears that we need to 2581 leave this zero for correct SH3 code. */ 2582 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3) 2583 2584 /* All integers have the same format so truncation is easy. */ 2585 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 2586 2587 /* Define this if addresses of constant functions 2588 shouldn't be put through pseudo regs where they can be cse'd. 2589 Desirable on machines where ordinary constants are expensive 2590 but a CALL with constant address is cheap. */ 2591 /*#define NO_FUNCTION_CSE 1*/ 2592 2593 /* Chars and shorts should be passed as ints. */ 2594 #define PROMOTE_PROTOTYPES 1 2595 2596 /* The machine modes of pointers and functions. */ 2597 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode) 2598 #define FUNCTION_MODE Pmode 2599 2600 /* The relative costs of various types of constants. */ 2601 2602 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2603 case CONST_INT: \ 2604 if (TARGET_SHMEDIA) \ 2605 { \ 2606 if (INTVAL (RTX) == 0) \ 2607 return 0; \ 2608 if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \ 2609 return 0; \ 2610 if (((OUTER_CODE) == IOR || (OUTER_CODE) == XOR \ 2611 || (OUTER_CODE) == PLUS) \ 2612 && CONST_OK_FOR_P (INTVAL (RTX))) \ 2613 return 0; \ 2614 if (CONST_OK_FOR_J (INTVAL (RTX))) \ 2615 return COSTS_N_INSNS ((OUTER_CODE) != SET); \ 2616 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \ 2617 return COSTS_N_INSNS (2); \ 2618 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \ 2619 return COSTS_N_INSNS (3); \ 2620 else \ 2621 return COSTS_N_INSNS (4); \ 2622 } \ 2623 if (CONST_OK_FOR_I (INTVAL (RTX))) \ 2624 return 0; \ 2625 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \ 2626 && CONST_OK_FOR_L (INTVAL (RTX))) \ 2627 return 1; \ 2628 else \ 2629 return 8; \ 2630 case CONST: \ 2631 case LABEL_REF: \ 2632 case SYMBOL_REF: \ 2633 if (TARGET_SHMEDIA64) \ 2634 return COSTS_N_INSNS (4); \ 2635 if (TARGET_SHMEDIA32) \ 2636 return COSTS_N_INSNS (2); \ 2637 return 5; \ 2638 case CONST_DOUBLE: \ 2639 if (TARGET_SHMEDIA) \ 2640 return COSTS_N_INSNS (4); \ 2641 else \ 2642 return 10; 2643 2644 #define RTX_COSTS(X, CODE, OUTER_CODE) \ 2645 case PLUS: \ 2646 return COSTS_N_INSNS (addsubcosts (X)); \ 2647 case AND: \ 2648 return COSTS_N_INSNS (andcosts (X)); \ 2649 case MULT: \ 2650 return COSTS_N_INSNS (multcosts (X)); \ 2651 case ASHIFT: \ 2652 case ASHIFTRT: \ 2653 case LSHIFTRT: \ 2654 return COSTS_N_INSNS (shiftcosts (X)); \ 2655 case DIV: \ 2656 case UDIV: \ 2657 case MOD: \ 2658 case UMOD: \ 2659 return COSTS_N_INSNS (20); \ 2660 case FLOAT: \ 2661 case FIX: \ 2662 return 100; 2663 2664 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 2665 are actually function calls with some special constraints on arguments 2666 and register usage. 2667 2668 These macros tell reorg that the references to arguments and 2669 register clobbers for insns of type sfunc do not appear to happen 2670 until after the millicode call. This allows reorg to put insns 2671 which set the argument registers into the delay slot of the millicode 2672 call -- thus they act more like traditional CALL_INSNs. 2673 2674 get_attr_is_sfunc will try to recognize the given insn, so make sure to 2675 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 2676 in particular. */ 2677 2678 #define INSN_SETS_ARE_DELAYED(X) \ 2679 ((GET_CODE (X) == INSN \ 2680 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2681 && GET_CODE (PATTERN (X)) != USE \ 2682 && GET_CODE (PATTERN (X)) != CLOBBER \ 2683 && get_attr_is_sfunc (X))) 2684 2685 #define INSN_REFERENCES_ARE_DELAYED(X) \ 2686 ((GET_CODE (X) == INSN \ 2687 && GET_CODE (PATTERN (X)) != SEQUENCE \ 2688 && GET_CODE (PATTERN (X)) != USE \ 2689 && GET_CODE (PATTERN (X)) != CLOBBER \ 2690 && get_attr_is_sfunc (X))) 2691 2692 2693 /* Position Independent Code. */ 2694 2695 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */ 2696 #define SH_DATALABEL_ENCODING "#" 2697 2698 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */ 2699 #define DATALABEL_SYMNAME_P(SYM_NAME) \ 2700 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \ 2701 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0]) 2702 2703 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of 2704 SYM_NAME. Then, remove a leading *, like the default definition in 2705 output.h. */ 2706 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \ 2707 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \ 2708 ? strlen (SH_DATALABEL_ENCODING) : 0) 2709 2710 /* We can't directly access anything that contains a symbol, 2711 nor can we indirect via the constant pool. */ 2712 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2713 (! nonpic_symbol_mentioned_p (X) \ 2714 && (GET_CODE (X) != SYMBOL_REF \ 2715 || ! CONSTANT_POOL_ADDRESS_P (X) \ 2716 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) 2717 2718 #define SYMBOLIC_CONST_P(X) \ 2719 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ 2720 && nonpic_symbol_mentioned_p (X)) 2721 2722 /* Compute the cost of an address. For the SH, all valid addresses are 2723 the same cost. Use a slightly higher cost for reg + reg addressing, 2724 since it increases pressure on r0. */ 2725 2726 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \ 2727 && ! TARGET_SHMEDIA \ 2728 ? 1 : 0) 2729 2730 /* Compute extra cost of moving data between one register class 2731 and another. */ 2732 2733 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass 2734 uses this information. Hence, the general register <-> floating point 2735 register information here is not used for SFmode. */ 2736 2737 #define REGCLASS_HAS_GENERAL_REG(CLASS) \ 2738 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \ 2739 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) 2740 2741 #define REGCLASS_HAS_FP_REG(CLASS) \ 2742 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ 2743 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) 2744 2745 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \ 2746 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS)) 2747 2748 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 2749 would be so that people with slow memory systems could generate 2750 different code that does fewer memory accesses. */ 2751 2752 /* A C expression for the cost of a branch instruction. A value of 1 2753 is the default; other values are interpreted relative to that. 2754 The SH1 does not have delay slots, hence we get a pipeline stall 2755 at every branch. The SH4 is superscalar, so the single delay slot 2756 is not sufficient to keep both pipelines filled. */ 2757 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1) 2758 2759 /* Assembler output control. */ 2760 2761 /* A C string constant describing how to begin a comment in the target 2762 assembler language. The compiler assumes that the comment will end at 2763 the end of the line. */ 2764 #define ASM_COMMENT_START "!" 2765 2766 /* The text to go at the start of the assembler file. */ 2767 #define ASM_FILE_START(STREAM) \ 2768 output_file_start (STREAM) 2769 2770 #define ASM_APP_ON "" 2771 #define ASM_APP_OFF "" 2772 #define FILE_ASM_OP "\t.file\n" 2773 #define SET_ASM_OP "\t.set\t" 2774 2775 /* How to change between sections. */ 2776 2777 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text") 2778 #define DATA_SECTION_ASM_OP "\t.data" 2779 2780 #if defined CRT_BEGIN || defined CRT_END 2781 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ 2782 # undef TEXT_SECTION_ASM_OP 2783 # if __SHMEDIA__ == 1 && __SH5__ == 32 2784 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\"" 2785 # else 2786 # define TEXT_SECTION_ASM_OP "\t.text" 2787 # endif 2788 #endif 2789 2790 2791 /* If defined, a C expression whose value is a string containing the 2792 assembler operation to identify the following data as 2793 uninitialized global data. If not defined, and neither 2794 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, 2795 uninitialized global data will be output in the data section if 2796 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be 2797 used. */ 2798 #ifndef BSS_SECTION_ASM_OP 2799 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 2800 #endif 2801 2802 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a 2803 separate, explicit argument. If you define this macro, it is used 2804 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in 2805 handling the required alignment of the variable. The alignment is 2806 specified as the number of bits. 2807 2808 Try to use function `asm_output_aligned_bss' defined in file 2809 `varasm.c' when defining this macro. */ 2810 #ifndef ASM_OUTPUT_ALIGNED_BSS 2811 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2812 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 2813 #endif 2814 2815 /* Define this so that jump tables go in same section as the current function, 2816 which could be text or it could be a user defined section. */ 2817 #define JUMP_TABLES_IN_TEXT_SECTION 1 2818 2819 #undef DO_GLOBAL_CTORS_BODY 2820 #define DO_GLOBAL_CTORS_BODY \ 2821 { \ 2822 typedef (*pfunc)(); \ 2823 extern pfunc __ctors[]; \ 2824 extern pfunc __ctors_end[]; \ 2825 pfunc *p; \ 2826 for (p = __ctors_end; p > __ctors; ) \ 2827 { \ 2828 (*--p)(); \ 2829 } \ 2830 } 2831 2832 #undef DO_GLOBAL_DTORS_BODY 2833 #define DO_GLOBAL_DTORS_BODY \ 2834 { \ 2835 typedef (*pfunc)(); \ 2836 extern pfunc __dtors[]; \ 2837 extern pfunc __dtors_end[]; \ 2838 pfunc *p; \ 2839 for (p = __dtors; p < __dtors_end; p++) \ 2840 { \ 2841 (*p)(); \ 2842 } \ 2843 } 2844 2845 #define ASM_OUTPUT_REG_PUSH(file, v) \ 2846 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); 2847 2848 #define ASM_OUTPUT_REG_POP(file, v) \ 2849 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); 2850 2851 /* DBX register number for a given compiler register number. */ 2852 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 2853 to match gdb. */ 2854 /* svr4.h undefines this macro, yet we really want to use the same numbers 2855 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */ 2856 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) 2857 2858 #define SH_DBX_REGISTER_NUMBER(REGNO) \ 2859 (GENERAL_REGISTER_P (REGNO) \ 2860 ? ((REGNO) - FIRST_GENERAL_REG) \ 2861 : FP_REGISTER_P (REGNO) \ 2862 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \ 2863 : 77) : 25)) \ 2864 : XD_REGISTER_P (REGNO) \ 2865 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \ 2866 : TARGET_REGISTER_P (REGNO) \ 2867 ? ((REGNO) - FIRST_TARGET_REG + 68) \ 2868 : (REGNO) == PR_REG \ 2869 ? (TARGET_SH5 ? 241 : 17) \ 2870 : (REGNO) == PR_MEDIA_REG \ 2871 ? (TARGET_SH5 ? 18 : -1) \ 2872 : (REGNO) == T_REG \ 2873 ? (TARGET_SH5 ? 242 : 18) \ 2874 : (REGNO) == GBR_REG \ 2875 ? (TARGET_SH5 ? 238 : 19) \ 2876 : (REGNO) == MACH_REG \ 2877 ? (TARGET_SH5 ? 239 : 20) \ 2878 : (REGNO) == MACL_REG \ 2879 ? (TARGET_SH5 ? 240 : 21) \ 2880 : (REGNO) == FPUL_REG \ 2881 ? (TARGET_SH5 ? 244 : 23) \ 2882 : (abort(), -1)) 2883 2884 /* This is how to output a reference to a user-level label named NAME. */ 2885 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 2886 do \ 2887 { \ 2888 const char * lname; \ 2889 \ 2890 STRIP_DATALABEL_ENCODING (lname, (NAME)); \ 2891 if (lname[0] == '*') \ 2892 fputs (lname + 1, (FILE)); \ 2893 else \ 2894 asm_fprintf ((FILE), "%U%s", lname); \ 2895 } \ 2896 while (0) 2897 2898 /* This is how to output a reference to a symbol_ref. On SH5, 2899 references to non-code symbols must be preceded by `datalabel'. */ 2900 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ 2901 do \ 2902 { \ 2903 if (TARGET_SH5 \ 2904 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \ 2905 || CONSTANT_POOL_ADDRESS_P (SYM))) \ 2906 fputs ("datalabel ", (FILE)); \ 2907 assemble_name ((FILE), XSTR ((SYM), 0)); \ 2908 } \ 2909 while (0) 2910 2911 /* This is how to output an assembler line 2912 that says to advance the location counter 2913 to a multiple of 2**LOG bytes. */ 2914 2915 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2916 if ((LOG) != 0) \ 2917 fprintf ((FILE), "\t.align %d\n", (LOG)) 2918 2919 /* Globalizing directive for a label. */ 2920 #define GLOBAL_ASM_OP "\t.global\t" 2921 2922 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 2923 2924 /* Construct a private name. */ 2925 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 2926 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 2927 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 2928 2929 /* Output a relative address table. */ 2930 2931 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 2932 switch (GET_MODE (BODY)) \ 2933 { \ 2934 case SImode: \ 2935 if (TARGET_SH5) \ 2936 { \ 2937 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \ 2938 (VALUE), (REL)); \ 2939 break; \ 2940 } \ 2941 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2942 break; \ 2943 case HImode: \ 2944 if (TARGET_SH5) \ 2945 { \ 2946 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \ 2947 (VALUE), (REL)); \ 2948 break; \ 2949 } \ 2950 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2951 break; \ 2952 case QImode: \ 2953 if (TARGET_SH5) \ 2954 { \ 2955 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \ 2956 (VALUE), (REL)); \ 2957 break; \ 2958 } \ 2959 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 2960 break; \ 2961 default: \ 2962 break; \ 2963 } 2964 2965 /* Output an absolute table element. */ 2966 2967 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 2968 if (! optimize || TARGET_BIGTABLE) \ 2969 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ 2970 else \ 2971 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); 2972 2973 2974 /* A C statement to be executed just prior to the output of 2975 assembler code for INSN, to modify the extracted operands so 2976 they will be output differently. 2977 2978 Here the argument OPVEC is the vector containing the operands 2979 extracted from INSN, and NOPERANDS is the number of elements of 2980 the vector which contain meaningful data for this insn. 2981 The contents of this vector are what will be used to convert the insn 2982 template into assembler code, so you can change the assembler output 2983 by changing the contents of the vector. */ 2984 2985 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2986 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 2987 2988 /* Print operand X (an rtx) in assembler syntax to file FILE. 2989 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2990 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2991 2992 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE)) 2993 2994 /* Print a memory address as an operand to reference that memory location. */ 2995 2996 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X)) 2997 2998 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2999 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \ 3000 || (CHAR) == '$'|| (CHAR) == '\'') 3001 3002 /* Recognize machine-specific patterns that may appear within 3003 constants. Used for PIC-specific UNSPECs. */ 3004 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 3005 do \ 3006 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \ 3007 { \ 3008 switch (XINT ((X), 1)) \ 3009 { \ 3010 case UNSPEC_DATALABEL: \ 3011 fputs ("datalabel ", (STREAM)); \ 3012 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3013 break; \ 3014 case UNSPEC_PIC: \ 3015 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \ 3016 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3017 break; \ 3018 case UNSPEC_GOT: \ 3019 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3020 fputs ("@GOT", (STREAM)); \ 3021 break; \ 3022 case UNSPEC_GOTOFF: \ 3023 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3024 fputs ("@GOTOFF", (STREAM)); \ 3025 break; \ 3026 case UNSPEC_PLT: \ 3027 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3028 fputs ("@PLT", (STREAM)); \ 3029 break; \ 3030 case UNSPEC_GOTPLT: \ 3031 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 3032 fputs ("@GOTPLT", (STREAM)); \ 3033 break; \ 3034 case UNSPEC_CALLER: \ 3035 { \ 3036 char name[32]; \ 3037 /* LPCS stands for Label for PIC Call Site. */ \ 3038 ASM_GENERATE_INTERNAL_LABEL \ 3039 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \ 3040 assemble_name ((STREAM), name); \ 3041 } \ 3042 break; \ 3043 default: \ 3044 goto FAIL; \ 3045 } \ 3046 break; \ 3047 } \ 3048 else \ 3049 goto FAIL; \ 3050 while (0) 3051 3052 3053 extern struct rtx_def *sh_compare_op0; 3054 extern struct rtx_def *sh_compare_op1; 3055 3056 /* Which processor to schedule for. The elements of the enumeration must 3057 match exactly the cpu attribute in the sh.md file. */ 3058 3059 enum processor_type { 3060 PROCESSOR_SH1, 3061 PROCESSOR_SH2, 3062 PROCESSOR_SH3, 3063 PROCESSOR_SH3E, 3064 PROCESSOR_SH4, 3065 PROCESSOR_SH5 3066 }; 3067 3068 #define sh_cpu_attr ((enum attr_cpu)sh_cpu) 3069 extern enum processor_type sh_cpu; 3070 3071 extern int optimize; /* needed for gen_casesi. */ 3072 3073 enum mdep_reorg_phase_e 3074 { 3075 SH_BEFORE_MDEP_REORG, 3076 SH_INSERT_USES_LABELS, 3077 SH_SHORTEN_BRANCHES0, 3078 SH_FIXUP_PCLOAD, 3079 SH_SHORTEN_BRANCHES1, 3080 SH_AFTER_MDEP_REORG 3081 }; 3082 3083 extern enum mdep_reorg_phase_e mdep_reorg_phase; 3084 3085 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) 3086 3087 /* Generate calls to memcpy, memcmp and memset. */ 3088 3089 #define TARGET_MEM_FUNCTIONS 3090 3091 /* Handle Hitachi compiler's pragmas. */ 3092 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ 3093 cpp_register_pragma (PFILE, 0, "interrupt", sh_pr_interrupt); \ 3094 cpp_register_pragma (PFILE, 0, "trapa", sh_pr_trapa); \ 3095 cpp_register_pragma (PFILE, 0, "nosave_low_regs", sh_pr_nosave_low_regs); \ 3096 } while (0) 3097 3098 /* Set when processing a function with pragma interrupt turned on. */ 3099 3100 extern int pragma_interrupt; 3101 3102 /* Set when processing a function with interrupt attribute. */ 3103 3104 extern int current_function_interrupt; 3105 3106 /* Set to an RTX containing the address of the stack to switch to 3107 for interrupt functions. */ 3108 extern struct rtx_def *sp_switch; 3109 3110 extern int rtx_equal_function_value_matters; 3111 3112 3113 /* Instructions with unfilled delay slots take up an 3114 extra two bytes for the nop in the delay slot. 3115 sh-dsp parallel processing insns are four bytes long. */ 3116 3117 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 3118 (LENGTH) += sh_insn_length_adjustment (X); 3119 3120 /* Define the codes that are matched by predicates in sh.c. */ 3121 #define PREDICATE_CODES \ 3122 {"and_operand", {SUBREG, REG, CONST_INT}}, \ 3123 {"any_register_operand", {SUBREG, REG}}, \ 3124 {"arith_operand", {SUBREG, REG, CONST_INT}}, \ 3125 {"arith_reg_dest", {SUBREG, REG}}, \ 3126 {"arith_reg_operand", {SUBREG, REG}}, \ 3127 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \ 3128 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \ 3129 {"binary_logical_operator", {AND, IOR, XOR}}, \ 3130 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \ 3131 {"commutative_float_operator", {PLUS, MULT}}, \ 3132 {"equality_comparison_operator", {EQ,NE}}, \ 3133 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \ 3134 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \ 3135 {"fp_arith_reg_operand", {SUBREG, REG}}, \ 3136 {"fpscr_operand", {REG}}, \ 3137 {"fpul_operand", {REG}}, \ 3138 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \ 3139 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 3140 {"general_movdst_operand", {SUBREG, REG, MEM}}, \ 3141 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \ 3142 {"int_gpr_dest", {SUBREG, REG}}, \ 3143 {"inqhi_operand", {TRUNCATE}}, \ 3144 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \ 3145 {"logical_operand", {SUBREG, REG, CONST_INT}}, \ 3146 {"mextr_bit_offset", {CONST_INT}}, \ 3147 {"noncommutative_float_operator", {MINUS, DIV}}, \ 3148 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \ 3149 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \ 3150 {"target_reg_operand", {SUBREG, REG}}, \ 3151 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\ 3152 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \ 3153 {"register_operand", {SUBREG, REG}}, \ 3154 {"sh_const_vec", {CONST_VECTOR}}, \ 3155 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \ 3156 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \ 3157 {"symbol_ref_operand", {SYMBOL_REF}}, \ 3158 {"unary_float_operator", {ABS, NEG, SQRT}}, \ 3159 3160 #define SPECIAL_MODE_PREDICATES \ 3161 "any_register_operand", \ 3162 "int_gpr_dest", \ 3163 "trunc_hi_operand", \ 3164 /* This line intentionally left blank. */ 3165 3166 #define any_register_operand register_operand 3167 3168 /* Define this macro if it is advisable to hold scalars in registers 3169 in a wider mode than that declared by the program. In such cases, 3170 the value is constrained to be within the bounds of the declared 3171 type, but kept valid in the wider mode. The signedness of the 3172 extension may differ from that of the type. 3173 3174 Leaving the unsignedp unchanged gives better code than always setting it 3175 to 0. This is despite the fact that we have only signed char and short 3176 load instructions. */ 3177 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 3178 if (GET_MODE_CLASS (MODE) == MODE_INT \ 3179 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 3180 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ 3181 (MODE) = (TARGET_SH1 ? SImode : DImode); 3182 3183 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign 3184 extensions applied to char/short functions arguments. Defining 3185 PROMOTE_FUNCTION_RETURN does the same for function returns. */ 3186 3187 #define PROMOTE_FUNCTION_ARGS 3188 #define PROMOTE_FUNCTION_RETURN 3189 3190 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64) 3191 3192 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing 3193 and poping arguments. However, we do have push/pop instructions, and 3194 rather limited offsets (4 bits) in load/store instructions, so it isn't 3195 clear if this would give better code. If implemented, should check for 3196 compatibility problems. */ 3197 3198 #define SH_DYNAMIC_SHIFT_COST \ 3199 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20) 3200 3201 3202 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } 3203 3204 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4 3205 3206 #define NORMAL_MODE(ENTITY) \ 3207 (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \ 3208 : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \ 3209 : FP_MODE_DOUBLE) 3210 3211 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \ 3212 && (REGNO) == FPSCR_REG) 3213 3214 #define MODE_NEEDED(ENTITY, INSN) \ 3215 (recog_memoized (INSN) >= 0 \ 3216 ? get_attr_fp_mode (INSN) \ 3217 : FP_MODE_NONE) 3218 3219 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \ 3220 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE) 3221 3222 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3223 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE)) 3224 3225 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \ 3226 sh_can_redirect_branch ((INSN), (SEQ)) 3227 3228 #define DWARF_FRAME_RETURN_COLUMN \ 3229 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG)) 3230 3231 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ 3232 /* SH constant pool breaks the devices in crtstuff.c to control section 3233 in where code resides. We have to write it as asm code. */ 3234 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 3235 asm (SECTION_OP "\n\ 3236 mov.l 1f,r1\n\ 3237 mova 2f,r0\n\ 3238 braf r1\n\ 3239 lds r0,pr\n\ 3240 0: .p2align 2\n\ 3241 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ 3242 2:\n" TEXT_SECTION_ASM_OP); 3243 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */ 3244 3245 #define ALLOCATE_INITIAL_VALUE(hard_reg) \ 3246 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \ 3247 ? (current_function_is_leaf && ! sh_pr_n_sets () \ 3248 ? (hard_reg) \ 3249 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \ 3250 : NULL_RTX) 3251 3252 #endif /* ! GCC_SH_H */ 3253