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Searched defs:TCG_TARGET_REG_BITS (Results 1 – 25 of 79) sorted by relevance

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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/sparc/
H A Dtcg-target.h27 #define TCG_TARGET_REG_BITS 64 macro
29 #define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/i386/
H A Dtcg-target.h30 # define TCG_TARGET_REG_BITS 64 macro
33 # define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/ppc/
H A Dtcg-target.h28 # define TCG_TARGET_REG_BITS 64 macro
30 # define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/i386/
H A Dtcg-target.h30 # define TCG_TARGET_REG_BITS 64 macro
33 # define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/ppc/
H A Dtcg-target.h28 # define TCG_TARGET_REG_BITS 64 macro
30 # define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/i386/
H A Dtcg-target.h26 #define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/s390/
H A Dtcg-target.h26 #define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu60/qemu-6.0.0/tcg/tci/
H A Dtcg-target.h48 # define TCG_TARGET_REG_BITS 32 macro
50 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/arm/
H A Dtcg-target.h27 #define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/ppc/
H A Dtcg-target.h29 # define TCG_TARGET_REG_BITS 64 macro
31 # define TCG_TARGET_REG_BITS 32 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/tci/
H A Dtcg-target.h49 # define TCG_TARGET_REG_BITS 32 macro
51 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu/qemu-6.2.0/tcg/tci/
H A Dtcg-target.h49 # define TCG_TARGET_REG_BITS 32 macro
51 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/mips/
H A Dtcg-target.h31 # define TCG_TARGET_REG_BITS 32 macro
33 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/riscv/
H A Dtcg-target.h29 # define TCG_TARGET_REG_BITS 32 macro
31 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/tci/
H A Dtcg-target.h48 # define TCG_TARGET_REG_BITS 32 macro
50 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu5/qemu-5.2.0/tcg/riscv/
H A Dtcg-target.h29 # define TCG_TARGET_REG_BITS 32 macro
31 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu5/qemu-5.2.0/tcg/tci/
H A Dtcg-target.h48 # define TCG_TARGET_REG_BITS 32 macro
50 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu5/qemu-5.2.0/tcg/mips/
H A Dtcg-target.h31 # define TCG_TARGET_REG_BITS 32 macro
33 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/riscv/
H A Dtcg-target.h29 # define TCG_TARGET_REG_BITS 32 macro
31 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/mips/
H A Dtcg-target.h31 # define TCG_TARGET_REG_BITS 32 macro
33 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/tci/
H A Dtcg-target.h48 # define TCG_TARGET_REG_BITS 32 macro
50 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu42/qemu-4.2.1/tcg/riscv/
H A Dtcg-target.h29 # define TCG_TARGET_REG_BITS 32 macro
31 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu42/qemu-4.2.1/tcg/tci/
H A Dtcg-target.h48 # define TCG_TARGET_REG_BITS 32 macro
50 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu42/qemu-4.2.1/tcg/mips/
H A Dtcg-target.h31 # define TCG_TARGET_REG_BITS 32 macro
33 # define TCG_TARGET_REG_BITS 64 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/mips/
H A Dtcg-target.h31 # define TCG_TARGET_REG_BITS 32 macro
33 # define TCG_TARGET_REG_BITS 64 macro

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