1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _MACHINE_HYPERVISOR_H_ 31 #define _MACHINE_HYPERVISOR_H_ 32 33 /* 34 * These registers are only useful when in hypervisor context, 35 * e.g. specific to EL2, or controlling the hypervisor. 36 */ 37 38 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 39 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 40 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 41 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 42 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 43 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 44 45 /* CPTR_EL2 - Architecture feature trap register */ 46 /* Valid if HCR_EL2.E2H == 0 */ 47 #define CPTR_RES0 0x7fefc800 48 #define CPTR_RES1 0x000033ff 49 #define CPTR_TFP 0x00000400 50 /* Valid if HCR_EL2.E2H == 1 */ 51 #define CPTR_FPEN 0x00300000 52 /* Unconditionally valid */ 53 #define CPTR_TTA 0x00100000 54 #define CPTR_TCPAC 0x80000000 55 56 /* HCR_EL2 - Hypervisor Config Register */ 57 #define HCR_VM (UL(0x1) << 0) 58 #define HCR_SWIO (UL(0x1) << 1) 59 #define HCR_PTW (UL(0x1) << 2) 60 #define HCR_FMO (UL(0x1) << 3) 61 #define HCR_IMO (UL(0x1) << 4) 62 #define HCR_AMO (UL(0x1) << 5) 63 #define HCR_VF (UL(0x1) << 6) 64 #define HCR_VI (UL(0x1) << 7) 65 #define HCR_VSE (UL(0x1) << 8) 66 #define HCR_FB (UL(0x1) << 9) 67 #define HCR_BSU_MASK (UL(0x3) << 10) 68 #define HCR_BSU_IS (UL(0x1) << 10) 69 #define HCR_BSU_OS (UL(0x2) << 10) 70 #define HCR_BSU_FS (UL(0x3) << 10) 71 #define HCR_DC (UL(0x1) << 12) 72 #define HCR_TWI (UL(0x1) << 13) 73 #define HCR_TWE (UL(0x1) << 14) 74 #define HCR_TID0 (UL(0x1) << 15) 75 #define HCR_TID1 (UL(0x1) << 16) 76 #define HCR_TID2 (UL(0x1) << 17) 77 #define HCR_TID3 (UL(0x1) << 18) 78 #define HCR_TSC (UL(0x1) << 19) 79 #define HCR_TIDCP (UL(0x1) << 20) 80 #define HCR_TACR (UL(0x1) << 21) 81 #define HCR_TSW (UL(0x1) << 22) 82 #define HCR_TPCP (UL(0x1) << 23) 83 #define HCR_TPU (UL(0x1) << 24) 84 #define HCR_TTLB (UL(0x1) << 25) 85 #define HCR_TVM (UL(0x1) << 26) 86 #define HCR_TGE (UL(0x1) << 27) 87 #define HCR_TDZ (UL(0x1) << 28) 88 #define HCR_HCD (UL(0x1) << 29) 89 #define HCR_TRVM (UL(0x1) << 30) 90 #define HCR_RW (UL(0x1) << 31) 91 #define HCR_CD (UL(0x1) << 32) 92 #define HCR_ID (UL(0x1) << 33) 93 #define HCR_E2H (UL(0x1) << 34) 94 #define HCR_TLOR (UL(0x1) << 35) 95 #define HCR_TERR (UL(0x1) << 36) 96 #define HCR_TEA (UL(0x1) << 37) 97 #define HCR_MIOCNCE (UL(0x1) << 38) 98 /* Bit 39 is reserved */ 99 #define HCR_APK (UL(0x1) << 40) 100 #define HCR_API (UL(0x1) << 41) 101 #define HCR_NV (UL(0x1) << 42) 102 #define HCR_NV1 (UL(0x1) << 43) 103 #define HCR_AT (UL(0x1) << 44) 104 #define HCR_NV2 (UL(0x1) << 45) 105 #define HCR_FWB (UL(0x1) << 46) 106 #define HCR_FIEN (UL(0x1) << 47) 107 /* Bit 48 is reserved */ 108 #define HCR_TID4 (UL(0x1) << 49) 109 #define HCR_TICAB (UL(0x1) << 50) 110 #define HCR_AMVOFFEN (UL(0x1) << 51) 111 #define HCR_TOCU (UL(0x1) << 52) 112 #define HCR_EnSCXT (UL(0x1) << 53) 113 #define HCR_TTLBIS (UL(0x1) << 54) 114 #define HCR_TTLBOS (UL(0x1) << 55) 115 #define HCR_ATA (UL(0x1) << 56) 116 #define HCR_DCT (UL(0x1) << 57) 117 #define HCR_TID5 (UL(0x1) << 58) 118 #define HCR_TWEDEn (UL(0x1) << 59) 119 #define HCR_TWEDEL_MASK (UL(0xf) << 60) 120 121 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ 122 #define HPFAR_EL2_FIPA_SHIFT 4 123 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 124 #define HPFAR_EL2_FIPA_GET(x) \ 125 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT) 126 /* HPFAR_EL2_FIPA holds the 4k page address */ 127 #define HPFAR_EL2_FIPA_ADDR(x) \ 128 (HPFAR_EL2_FIPA_GET(x) << 12) 129 /* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */ 130 #define FAR_EL2_HPFAR_PAGE_MASK (0xffful) 131 132 /* ICC_SRE_EL2 */ 133 #define ICC_SRE_EL2_SRE (1UL << 0) 134 #define ICC_SRE_EL2_EN (1UL << 3) 135 136 /* SCTLR_EL2 - System Control Register */ 137 #define SCTLR_EL2_RES1 0x30c50830 138 #define SCTLR_EL2_M_SHIFT 0 139 #define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) 140 #define SCTLR_EL2_A_SHIFT 1 141 #define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) 142 #define SCTLR_EL2_C_SHIFT 2 143 #define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) 144 #define SCTLR_EL2_SA_SHIFT 3 145 #define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) 146 #define SCTLR_EL2_I_SHIFT 12 147 #define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) 148 #define SCTLR_EL2_WXN_SHIFT 19 149 #define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) 150 #define SCTLR_EL2_EE_SHIFT 25 151 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) 152 153 /* TCR_EL2 - Translation Control Register */ 154 #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) 155 #define TCR_EL2_T0SZ_SHIFT 0 156 #define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) 157 #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) 158 /* Bits 7:6 are reserved */ 159 #define TCR_EL2_IRGN0_SHIFT 8 160 #define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) 161 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT) 162 #define TCR_EL2_ORGN0_SHIFT 10 163 #define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) 164 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT) 165 #define TCR_EL2_SH0_SHIFT 12 166 #define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) 167 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT) 168 #define TCR_EL2_TG0_SHIFT 14 169 #define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) 170 #define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT) 171 #define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT) 172 #define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT) 173 #define TCR_EL2_PS_SHIFT 16 174 #define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT) 175 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) 176 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) 177 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) 178 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) 179 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) 180 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) 181 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) 182 #define TCR_EL2_HPD_SHIFT 24 183 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT) 184 #define TCR_EL2_HWU59_SHIFT 25 185 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT) 186 #define TCR_EL2_HWU60_SHIFT 26 187 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT) 188 #define TCR_EL2_HWU61_SHIFT 27 189 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT) 190 #define TCR_EL2_HWU62_SHIFT 28 191 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) 192 #define TCR_EL2_HWU \ 193 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) 194 195 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ 196 #define VMPIDR_EL2_U 0x0000000040000000 197 #define VMPIDR_EL2_MT 0x0000000001000000 198 #define VMPIDR_EL2_RES1 0x0000000080000000 199 200 /* VTCR_EL2 - Virtualization Translation Control Register */ 201 #define VTCR_EL2_RES1 (0x1UL << 31) 202 #define VTCR_EL2_T0SZ_SHIFT 0 203 #define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT) 204 #define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT) 205 #define VTCR_EL2_SL0_SHIFT 6 206 #define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) 207 #define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) 208 #define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) 209 #define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT) 210 #define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT) 211 #define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT) 212 #define VTCR_EL2_IRGN0_SHIFT 8 213 #define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) 214 #define VTCR_EL2_ORGN0_SHIFT 10 215 #define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) 216 #define VTCR_EL2_SH0_SHIFT 12 217 #define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) 218 #define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) 219 #define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) 220 #define VTCR_EL2_TG0_SHIFT 14 221 #define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) 222 #define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) 223 #define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) 224 #define VTCR_EL2_PS_SHIFT 16 225 #define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) 226 #define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) 227 #define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) 228 #define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) 229 #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) 230 #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) 231 232 /* VTTBR_EL2 - Virtualization Translation Table Base Register */ 233 #define VTTBR_VMID_MASK 0xffff000000000000 234 #define VTTBR_VMID_SHIFT 48 235 /* Assumed to be 0 by locore.S */ 236 #define VTTBR_HOST 0x0000000000000000 237 238 /* MDCR_EL2 - Hyp Debug Control Register */ 239 #define MDCR_EL2_HPMN_MASK 0x1f 240 #define MDCR_EL2_HPMN_SHIFT 0 241 #define MDCR_EL2_TPMCR_SHIFT 5 242 #define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) 243 #define MDCR_EL2_TPM_SHIFT 6 244 #define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) 245 #define MDCR_EL2_HPME_SHIFT 7 246 #define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) 247 #define MDCR_EL2_TDE_SHIFT 8 248 #define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) 249 #define MDCR_EL2_TDA_SHIFT 9 250 #define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) 251 #define MDCR_EL2_TDOSA_SHIFT 10 252 #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) 253 #define MDCR_EL2_TDRA_SHIFT 11 254 #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) 255 256 #endif /* !_MACHINE_HYPERVISOR_H_ */ 257