1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2005-2014, 2018-2021, 2023 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
5 */
6 #ifndef __iwl_fh_h__
7 #define __iwl_fh_h__
8
9 #include <linux/types.h>
10 #include <linux/bitfield.h>
11
12 #include "iwl-trans.h"
13
14 /****************************/
15 /* Flow Handler Definitions */
16 /****************************/
17
18 /**
19 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
20 * Addresses are offsets from device's PCI hardware base address.
21 */
22 #define FH_MEM_LOWER_BOUND (0x1000)
23 #define FH_MEM_UPPER_BOUND (0x2000)
24 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000)
25 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000)
26
27 /**
28 * Keep-Warm (KW) buffer base address.
29 *
30 * Driver must allocate a 4KByte buffer that is for keeping the
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
32 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
35 *
36 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
37 * of the buffer, which must be 4K aligned. Once this is set up, the device
38 * automatically invokes keep-warm accesses when normal accesses might not
39 * be sufficient to maintain fast DRAM response.
40 *
41 * Bit fields:
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
43 */
44 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
45
46
47 /**
48 * TFD Circular Buffers Base (CBBC) addresses
49 *
50 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
51 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
52 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
53 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
54 * aligned (address bits 0-7 must be 0).
55 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
56 * for them are in different places.
57 *
58 * Bit fields in each pointer register:
59 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
60 */
61 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
62 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
63 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0)
64 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
65 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20)
66 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80)
67 /* 22000 TFD table address, 64 bit */
68 #define TFH_TFDQ_CBB_TABLE (0x1C00)
69
70 /* Find TFD CB base pointer for given queue */
FH_MEM_CBBC_QUEUE(struct iwl_trans * trans,unsigned int chnl)71 static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans,
72 unsigned int chnl)
73 {
74 if (trans->trans_cfg->gen2) {
75 WARN_ON_ONCE(chnl >= 64);
76 return TFH_TFDQ_CBB_TABLE + 8 * chnl;
77 }
78 if (chnl < 16)
79 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
80 if (chnl < 20)
81 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
82 WARN_ON_ONCE(chnl >= 32);
83 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
84 }
85
86 /* 22000 configuration registers */
87
88 /*
89 * TFH Configuration register.
90 *
91 * BIT fields:
92 *
93 * Bits 3:0:
94 * Define the maximum number of pending read requests.
95 * Maximum configuration value allowed is 0xC
96 * Bits 9:8:
97 * Define the maximum transfer size. (64 / 128 / 256)
98 * Bit 10:
99 * When bit is set and transfer size is set to 128B, the TFH will enable
100 * reading chunks of more than 64B only if the read address is aligned to 128B.
101 * In case of DRAM read address which is not aligned to 128B, the TFH will
102 * enable transfer size which doesn't cross 64B DRAM address boundary.
103 */
104 #define TFH_TRANSFER_MODE (0x1F40)
105 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc
106 #define TFH_CHUNK_SIZE_128 BIT(8)
107 #define TFH_CHUNK_SPLIT_MODE BIT(10)
108 /*
109 * Defines the offset address in dwords referring from the beginning of the
110 * Tx CMD which will be updated in DRAM.
111 * Note that the TFH offset address for Tx CMD update is always referring to
112 * the start of the TFD first TB.
113 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
114 */
115 #define TFH_TXCMD_UPDATE_CFG (0x1F48)
116 /*
117 * Controls TX DMA operation
118 *
119 * BIT fields:
120 *
121 * Bits 31:30: Enable the SRAM DMA channel.
122 * Turning on bit 31 will kick the SRAM2DRAM DMA.
123 * Note that the sram2dram may be enabled only after configuring the DRAM and
124 * SRAM addresses registers and the byte count register.
125 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When
126 * set to 1 - interrupt is sent to the driver
127 * Bit 0: Indicates the snoop configuration
128 */
129 #define TFH_SRV_DMA_CHNL0_CTRL (0x1F60)
130 #define TFH_SRV_DMA_SNOOP BIT(0)
131 #define TFH_SRV_DMA_TO_DRIVER BIT(24)
132 #define TFH_SRV_DMA_START BIT(31)
133
134 /* Defines the DMA SRAM write start address to transfer a data block */
135 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64)
136
137 /* Defines the 64bits DRAM start address to read the DMA data block from */
138 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68)
139
140 /*
141 * Defines the number of bytes to transfer from DRAM to SRAM.
142 * Note that this register may be configured with non-dword aligned size.
143 */
144 #define TFH_SRV_DMA_CHNL0_BC (0x1F70)
145
146 /**
147 * Rx SRAM Control and Status Registers (RSCSR)
148 *
149 * These registers provide handshake between driver and device for the Rx queue
150 * (this queue handles *all* command responses, notifications, Rx data, etc.
151 * sent from uCode to host driver). Unlike Tx, there is only one Rx
152 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
153 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
154 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
155 * mapping between RBDs and RBs.
156 *
157 * Driver must allocate host DRAM memory for the following, and set the
158 * physical address of each into device registers:
159 *
160 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
161 * entries (although any power of 2, up to 4096, is selectable by driver).
162 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
163 * (typically 4K, although 8K or 16K are also selectable by driver).
164 * Driver sets up RB size and number of RBDs in the CB via Rx config
165 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
166 *
167 * Bit fields within one RBD:
168 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
169 *
170 * Driver sets physical address [35:8] of base of RBD circular buffer
171 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
172 *
173 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
174 * (RBs) have been filled, via a "write pointer", actually the index of
175 * the RB's corresponding RBD within the circular buffer. Driver sets
176 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
177 *
178 * Bit fields in lower dword of Rx status buffer (upper dword not used
179 * by driver:
180 * 31-12: Not used by driver
181 * 11- 0: Index of last filled Rx buffer descriptor
182 * (device writes, driver reads this value)
183 *
184 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
185 * enter pointers to these RBs into contiguous RBD circular buffer entries,
186 * and update the device's "write" index register,
187 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
188 *
189 * This "write" index corresponds to the *next* RBD that the driver will make
190 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
191 * the circular buffer. This value should initially be 0 (before preparing any
192 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
193 * wrap back to 0 at the end of the circular buffer (but don't wrap before
194 * "read" index has advanced past 1! See below).
195 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
196 *
197 * As the device fills RBs (referenced from contiguous RBDs within the circular
198 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
199 * to tell the driver the index of the latest filled RBD. The driver must
200 * read this "read" index from DRAM after receiving an Rx interrupt from device
201 *
202 * The driver must also internally keep track of a third index, which is the
203 * next RBD to process. When receiving an Rx interrupt, driver should process
204 * all filled but unprocessed RBs up to, but not including, the RB
205 * corresponding to the "read" index. For example, if "read" index becomes "1",
206 * driver may process the RB pointed to by RBD 0. Depending on volume of
207 * traffic, there may be many RBs to process.
208 *
209 * If read index == write index, device thinks there is no room to put new data.
210 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
211 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
212 * and "read" indexes; that is, make sure that there are no more than 254
213 * buffers waiting to be filled.
214 */
215 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
216 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
217 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
218
219 /**
220 * Physical base address of 8-byte Rx Status buffer.
221 * Bit fields:
222 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
223 */
224 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
225
226 /**
227 * Physical base address of Rx Buffer Descriptor Circular Buffer.
228 * Bit fields:
229 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
230 */
231 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
232
233 /**
234 * Rx write pointer (index, really!).
235 * Bit fields:
236 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
237 * NOTE: For 256-entry circular buffer, use only bits [7:0].
238 */
239 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
240 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
241
242 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c)
243 #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
244
245 /**
246 * Rx Config/Status Registers (RCSR)
247 * Rx Config Reg for channel 0 (only channel used)
248 *
249 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
250 * normal operation (see bit fields).
251 *
252 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
253 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
254 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
255 *
256 * Bit fields:
257 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
258 * '10' operate normally
259 * 29-24: reserved
260 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
261 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
262 * 19-18: reserved
263 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
264 * '10' 12K, '11' 16K.
265 * 15-14: reserved
266 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
267 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
268 * typical value 0x10 (about 1/2 msec)
269 * 3- 0: reserved
270 */
271 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
272 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
273 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
274
275 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
276 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8)
277 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10)
278
279 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
280 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
281 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
282 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
283 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
284 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
285
286 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
287 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
288 #define RX_RB_TIMEOUT (0x11)
289
290 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
291 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
292 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
293
294 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
295 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
296 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
297 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
298
299 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
300 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
301 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
302
303 /**
304 * Rx Shared Status Registers (RSSR)
305 *
306 * After stopping Rx DMA channel (writing 0 to
307 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
308 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
309 *
310 * Bit fields:
311 * 24: 1 = Channel 0 is idle
312 *
313 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
314 * contain default values that should not be altered by the driver.
315 */
316 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
317 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
318
319 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
320 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
321 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
322 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
323
324 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
325
326 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
327 #define FH_MEM_TB_MAX_LENGTH (0x00020000)
328
329 /* 9000 rx series registers */
330
331 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
332 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
333 /* Write index table */
334 #define RFH_Q0_FRBDCB_WIDX 0xA08080
335 #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4)
336 /* Write index table - shadow registers */
337 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
338 #define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
339 /* Read index table */
340 #define RFH_Q0_FRBDCB_RIDX 0xA080C0
341 #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4)
342 /* Used list table */
343 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
344 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8)
345 /* Write index table */
346 #define RFH_Q0_URBDCB_WIDX 0xA08180
347 #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4)
348 #define RFH_Q0_URBDCB_VAID 0xA081C0
349 #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4)
350 /* stts */
351 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
352 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
353
354 #define RFH_Q0_ORB_WPTR_LSB 0xA08280
355 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8)
356 #define RFH_RBDBUF_RBD0_LSB 0xA08300
357 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8)
358
359 /**
360 * RFH Status Register
361 *
362 * Bit fields:
363 *
364 * Bit 29: RBD_FETCH_IDLE
365 * This status flag is set by the RFH when there is no active RBD fetch from
366 * DRAM.
367 * Once the RFH RBD controller starts fetching (or when there is a pending
368 * RBD read response from DRAM), this flag is immediately turned off.
369 *
370 * Bit 30: SRAM_DMA_IDLE
371 * This status flag is set by the RFH when there is no active transaction from
372 * SRAM to DRAM.
373 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
374 *
375 * Bit 31: RXF_DMA_IDLE
376 * This status flag is set by the RFH when there is no active transaction from
377 * RXF to DRAM.
378 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
379 */
380 #define RFH_GEN_STATUS 0xA09808
381 #define RFH_GEN_STATUS_GEN3 0xA07824
382 #define RBD_FETCH_IDLE BIT(29)
383 #define SRAM_DMA_IDLE BIT(30)
384 #define RXF_DMA_IDLE BIT(31)
385
386 /* DMA configuration */
387 #define RFH_RXF_DMA_CFG 0xA09820
388 #define RFH_RXF_DMA_CFG_GEN3 0xA07880
389 /* RB size */
390 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
391 #define RFH_RXF_DMA_RB_SIZE_POS 16
392 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS)
393 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS)
394 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS)
395 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS)
396 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS)
397 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS)
398 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS)
399 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS)
400 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS)
401 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS)
402 /* RB Circular Buffer size:defines the table sizes in RBD units */
403 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
404 #define RFH_RXF_DMA_RBDCB_SIZE_POS 20
405 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS)
406 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS)
407 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS)
408 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
409 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
410 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS)
411 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS)
412 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS)
413 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS)
414 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
415 #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24
416 #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)
417 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
418 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
419 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
420 #define RFH_DMA_EN_ENABLE_VAL BIT(31)
421
422 #define RFH_RXF_RXQ_ACTIVE 0xA0980C
423
424 #define RFH_GEN_CFG 0xA09800
425 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
426 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
427 #define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4)
428 #define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1
429 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0
430 /* the driver assumes everywhere that the default RXQ is 0 */
431 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
432 #define RFH_GEN_CFG_VAL(_n, _v) FIELD_PREP(RFH_GEN_CFG_ ## _n, _v)
433
434 /* end of 9000 rx series registers */
435
436 /* TFDB Area - TFDs buffer table */
437 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
438 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
439 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
440 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
441 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
442
443 /**
444 * Transmit DMA Channel Control/Status Registers (TCSR)
445 *
446 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
447 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
449 *
450 * To use a Tx DMA channel, driver must initialize its
451 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
452 *
453 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
454 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
455 *
456 * All other bits should be 0.
457 *
458 * Bit fields:
459 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
460 * '10' operate normally
461 * 29- 4: Reserved, set to "0"
462 * 3: Enable internal DMA requests (1, normal operation), disable (0)
463 * 2- 0: Reserved, set to "0"
464 */
465 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
466 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
467
468 /* Find Control/Status reg for given Tx DMA/FIFO channel */
469 #define FH_TCSR_CHNL_NUM (8)
470
471 /* TCSR: tx_config register values */
472 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
473 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
474 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
475 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
476 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
477 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
478
479 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
480 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
481
482 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
483 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
484
485 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
486 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
487 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
488
489 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
490 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
491 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
492
493 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
494 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
495 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
496
497 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
498 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
499 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
500
501 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
502 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
503
504 /**
505 * Tx Shared Status Registers (TSSR)
506 *
507 * After stopping Tx DMA channel (writing 0 to
508 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
509 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
510 * (channel's buffers empty | no pending requests).
511 *
512 * Bit fields:
513 * 31-24: 1 = Channel buffers empty (channel 7:0)
514 * 23-16: 1 = No pending requests (channel 7:0)
515 */
516 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
517 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
518
519 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
520
521 /**
522 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
523 * 31: Indicates an address error when accessed to internal memory
524 * uCode/driver must write "1" in order to clear this flag
525 * 30: Indicates that Host did not send the expected number of dwords to FH
526 * uCode/driver must write "1" in order to clear this flag
527 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
528 * command was received from the scheduler while the TRB was already full
529 * with previous command
530 * uCode/driver must write "1" in order to clear this flag
531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
532 * bit is set, it indicates that the FH has received a full indication
533 * from the RTC TxFIFO and the current value of the TxCredit counter was
534 * not equal to zero. This mean that the credit mechanism was not
535 * synchronized to the TxFIFO status
536 * uCode/driver must write "1" in order to clear this flag
537 */
538 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
539 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008)
540
541 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
542
543 /* Tx service channels */
544 #define FH_SRVC_CHNL (9)
545 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
546 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
547 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
548 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
549
550 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
551 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4)
552
553 /* Instruct FH to increment the retry count of a packet when
554 * it is brought from the memory to TX-FIFO
555 */
556 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
557
558 #define RX_POOL_SIZE(rbds) ((rbds) - 1 + \
559 IWL_MAX_RX_HW_QUEUES * \
560 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
561 /* cb size is the exponent */
562 #define RX_QUEUE_CB_SIZE(x) ilog2(x)
563
564 #define RX_QUEUE_SIZE 256
565 #define RX_QUEUE_MASK 255
566 #define RX_QUEUE_SIZE_LOG 8
567
568 /**
569 * struct iwl_rb_status - reserve buffer status
570 * host memory mapped FH registers
571 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
572 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
573 * @finished_rb_num [0:11] - Indicates the index of the current RB
574 * in which the last frame was written to
575 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
576 * which was transferred
577 */
578 struct iwl_rb_status {
579 __le16 closed_rb_num;
580 __le16 closed_fr_num;
581 __le16 finished_rb_num;
582 __le16 finished_fr_nam;
583 __le32 __spare;
584 } __packed;
585
586
587 #define TFD_QUEUE_SIZE_MAX (256)
588 #define TFD_QUEUE_SIZE_MAX_GEN3 (65536)
589 /* cb size is the exponent - 3 */
590 #define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3)
591 #define TFD_QUEUE_SIZE_BC_DUP (64)
592 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
593 #define TFD_QUEUE_BC_SIZE_GEN3_AX210 1024
594 #define TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4)
595 #define IWL_TX_DMA_MASK DMA_BIT_MASK(36)
596 #define IWL_NUM_OF_TBS 20
597 #define IWL_TFH_NUM_TBS 25
598
599 /* IMR DMA registers */
600 #define IMR_TFH_SRV_DMA_CHNL0_CTRL 0x00a0a51c
601 #define IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR 0x00a0a520
602 #define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB 0x00a0a524
603 #define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB 0x00a0a528
604 #define IMR_TFH_SRV_DMA_CHNL0_BC 0x00a0a52c
605 #define TFH_SRV_DMA_CHNL0_LEFT_BC 0x00a0a530
606
607 /* RFH S2D DMA registers */
608 #define IMR_RFH_GEN_CFG_SERVICE_DMA_RS_MSK 0x0000000c
609 #define IMR_RFH_GEN_CFG_SERVICE_DMA_SNOOP_MSK 0x00000002
610
611 /* TFH D2S DMA registers */
612 #define IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK 0x80000000
613 #define IMR_UREG_CHICK 0x00d05c00
614 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS 0x00800000
615 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK 0x00000030
616 #define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS 0x80000000
617
iwl_get_dma_hi_addr(dma_addr_t addr)618 static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr)
619 {
620 return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF;
621 }
622
623 /**
624 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits
625 * @TB_HI_N_LEN_ADDR_HI_MSK: high 4 bits (to make it 36) of DMA address
626 * @TB_HI_N_LEN_LEN_MSK: length of the TB
627 */
628 enum iwl_tfd_tb_hi_n_len {
629 TB_HI_N_LEN_ADDR_HI_MSK = 0xf,
630 TB_HI_N_LEN_LEN_MSK = 0xfff0,
631 };
632
633 /**
634 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor
635 *
636 * This structure contains dma address and length of transmission address
637 *
638 * @lo: low [31:0] portion of the dma address of TX buffer
639 * every even is unaligned on 16 bit boundary
640 * @hi_n_len: &enum iwl_tfd_tb_hi_n_len
641 */
642 struct iwl_tfd_tb {
643 __le32 lo;
644 __le16 hi_n_len;
645 } __packed;
646
647 /**
648 * struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor
649 *
650 * This structure contains dma address and length of transmission address
651 *
652 * @tb_len length of the tx buffer
653 * @addr 64 bits dma address
654 */
655 struct iwl_tfh_tb {
656 __le16 tb_len;
657 __le64 addr;
658 } __packed;
659
660 /**
661 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
662 * Both driver and device share these circular buffers, each of which must be
663 * contiguous 256 TFDs.
664 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
665 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
666 *
667 * Driver must indicate the physical address of the base of each
668 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
669 *
670 * Each TFD contains pointer/size information for up to 20 / 25 data buffers
671 * in host DRAM. These buffers collectively contain the (one) frame described
672 * by the TFD. Each buffer must be a single contiguous block of memory within
673 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
674 * of (4K - 4). The concatenates all of a TFD's buffers into a single
675 * Tx frame, up to 8 KBytes in size.
676 *
677 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
678 */
679
680 /**
681 * struct iwl_tfd - Transmit Frame Descriptor (TFD)
682 * @ __reserved1[3] reserved
683 * @ num_tbs 0-4 number of active tbs
684 * 5 reserved
685 * 6-7 padding (not used)
686 * @ tbs[20] transmit frame buffer descriptors
687 * @ __pad padding
688 */
689 struct iwl_tfd {
690 u8 __reserved1[3];
691 u8 num_tbs;
692 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS];
693 __le32 __pad;
694 } __packed;
695
696 /**
697 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD)
698 * @ num_tbs 0-4 number of active tbs
699 * 5 -15 reserved
700 * @ tbs[25] transmit frame buffer descriptors
701 * @ __pad padding
702 */
703 struct iwl_tfh_tfd {
704 __le16 num_tbs;
705 struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS];
706 __le32 __pad;
707 } __packed;
708
709 /* Keep Warm Size */
710 #define IWL_KW_SIZE 0x1000 /* 4k */
711
712 /* Fixed (non-configurable) rx data from phy */
713
714 /**
715 * struct iwlagn_schedq_bc_tbl scheduler byte count table
716 * base physical address provided by SCD_DRAM_BASE_ADDR
717 * For devices up to 22000:
718 * @tfd_offset 0-12 - tx command byte count
719 * 12-16 - station index
720 * For 22000:
721 * @tfd_offset 0-12 - tx command byte count
722 * 12-13 - number of 64 byte chunks
723 * 14-16 - reserved
724 */
725 struct iwlagn_scd_bc_tbl {
726 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
727 } __packed;
728
729 /**
730 * struct iwl_gen3_bc_tbl_entry scheduler byte count table entry gen3
731 * For AX210 and on:
732 * @tfd_offset: 0-12 - tx command byte count
733 * 12-13 - number of 64 byte chunks
734 * 14-16 - reserved
735 */
736 struct iwl_gen3_bc_tbl_entry {
737 __le16 tfd_offset;
738 } __packed;
739
740 #endif /* !__iwl_fh_h__ */
741