1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SMU_13_0_6_DRIVER_IF_H 24 #define SMU_13_0_6_DRIVER_IF_H 25 26 // *** IMPORTANT *** 27 // PMFW TEAM: Always increment the interface version if 28 // anything is changed in this file 29 #define SMU13_0_6_DRIVER_IF_VERSION 0x08042024 30 31 //I2C Interface 32 #define NUM_I2C_CONTROLLERS 8 33 #define I2C_CONTROLLER_ENABLED 1 34 #define I2C_CONTROLLER_DISABLED 0 35 36 #define MAX_SW_I2C_COMMANDS 24 37 38 typedef enum { 39 I2C_CONTROLLER_PORT_0, //CKSVII2C0 40 I2C_CONTROLLER_PORT_1, //CKSVII2C1 41 I2C_CONTROLLER_PORT_COUNT, 42 } I2cControllerPort_e; 43 44 typedef enum { 45 UNSUPPORTED_1, //50 Kbits/s not supported anymore! 46 I2C_SPEED_STANDARD_100K, //100 Kbits/s 47 I2C_SPEED_FAST_400K, //400 Kbits/s 48 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 49 UNSUPPORTED_2, //1 Mbits/s (in high speed mode) not supported anymore! 50 UNSUPPORTED_3, //2.3 Mbits/s not supported anymore! 51 I2C_SPEED_COUNT, 52 } I2cSpeed_e; 53 54 typedef enum { 55 I2C_CMD_READ, 56 I2C_CMD_WRITE, 57 I2C_CMD_COUNT, 58 } I2cCmdType_e; 59 60 #define CMDCONFIG_STOP_BIT 0 61 #define CMDCONFIG_RESTART_BIT 1 62 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 63 64 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 65 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 66 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 67 68 typedef struct { 69 uint8_t ReadWriteData; //Return data for read. Data to send for write 70 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 71 } SwI2cCmd_t; //SW I2C Command Table 72 73 typedef struct { 74 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 75 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 76 uint8_t SlaveAddress; //Slave address of device 77 uint8_t NumCmds; //Number of commands 78 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 79 } SwI2cRequest_t; // SW I2C Request Table 80 81 typedef struct { 82 SwI2cRequest_t SwI2cRequest; 83 uint32_t Spare[8]; 84 uint32_t MmHubPadding[8]; // SMU internal use 85 } SwI2cRequestExternal_t; 86 87 typedef enum { 88 PPCLK_VCLK, 89 PPCLK_DCLK, 90 PPCLK_SOCCLK, 91 PPCLK_UCLK, 92 PPCLK_FCLK, 93 PPCLK_LCLK, 94 PPCLK_COUNT, 95 } PPCLK_e; 96 97 typedef enum { 98 GPIO_INT_POLARITY_ACTIVE_LOW, 99 GPIO_INT_POLARITY_ACTIVE_HIGH, 100 } GpioIntPolarity_e; 101 102 //TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode 103 typedef enum { 104 UCLK_DPM_MODE_BANDWIDTH, 105 UCLK_DPM_MODE_LATENCY, 106 } UCLK_DPM_MODE_e; 107 108 typedef struct { 109 //0-23 SOC, 24-26 SOCIO, 27-29 SOC 110 uint16_t avgPsmCount[30]; 111 uint16_t minPsmCount[30]; 112 float avgPsmVoltage[30]; 113 float minPsmVoltage[30]; 114 } AvfsDebugTableAid_t; 115 116 typedef struct { 117 //0-27 GFX, 28-29 SOC 118 uint16_t avgPsmCount[30]; 119 uint16_t minPsmCount[30]; 120 float avgPsmVoltage[30]; 121 float minPsmVoltage[30]; 122 } AvfsDebugTableXcd_t; 123 124 // Defines used for IH-based thermal interrupts to GFX driver - A/X only 125 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 126 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 127 128 //thermal over-temp mask defines for IH interrupt to host 129 #define THROTTLER_PROCHOT_BIT 0 130 #define THROTTLER_PPT_BIT 1 131 #define THROTTLER_THERMAL_SOCKET_BIT 2//AID, XCD, CCD throttling 132 #define THROTTLER_THERMAL_VR_BIT 3//VRHOT 133 #define THROTTLER_THERMAL_HBM_BIT 4 134 135 // These defines are used with the following messages: 136 // SMC_MSG_TransferTableDram2Smu 137 // SMC_MSG_TransferTableSmu2Dram 138 // #define TABLE_PPTABLE 0 139 // #define TABLE_AVFS_PSM_DEBUG 1 140 // #define TABLE_AVFS_FUSE_OVERRIDE 2 141 // #define TABLE_PMSTATUSLOG 3 142 // #define TABLE_SMU_METRICS 4 143 // #define TABLE_DRIVER_SMU_CONFIG 5 144 // #define TABLE_I2C_COMMANDS 6 145 // #define TABLE_COUNT 7 146 147 // // Table transfer status 148 // #define TABLE_TRANSFER_OK 0x0 149 // #define TABLE_TRANSFER_FAILED 0xFF 150 // #define TABLE_TRANSFER_PENDING 0xAB 151 152 #endif 153