xref: /dragonfly/sys/dev/netif/ti/if_tireg.h (revision 86d7f5d3)
1 /*
2  * Copyright (c) 1997, 1998, 1999
3  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * $FreeBSD: src/sys/pci/if_tireg.h,v 1.13.2.4 2001/04/26 16:41:15 wpaul Exp $
33  * $DragonFly: src/sys/dev/netif/ti/if_tireg.h,v 1.8 2007/04/08 12:03:18 sephe Exp $
34  */
35 
36 /*
37  * Tigon register offsets. These are memory mapped registers
38  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
39  * Each register must be accessed using 32 bit operations.
40  *
41  * All reegisters are accessed through a 16K shared memory block.
42  * The first group of registers are actually copies of the PCI
43  * configuration space registers.
44  */
45 
46 #define TI_PCI_ID			0x000 /* PCI device/vendor ID */
47 #define TI_PCI_CMDSTAT			0x004
48 #define TI_PCI_CLASSCODE		0x008
49 #define TI_PCI_BIST			0x00C
50 #define TI_PCI_LOMEM			0x010 /* Shared memory base address */
51 #define TI_PCI_SUBSYS			0x02C
52 #define TI_PCI_ROMBASE			0x030
53 #define TI_PCI_INT			0x03C
54 
55 #ifndef PCIM_CMD_MWIEN
56 #define PCIM_CMD_MWIEN			0x0010
57 #endif
58 
59 /*
60  * Alteon AceNIC PCI vendor/device ID.
61  */
62 #define ALT_VENDORID			0x12AE
63 #define ALT_DEVICEID_ACENIC		0x0001
64 #define ALT_DEVICEID_ACENIC_COPPER	0x0002
65 
66 /*
67  * 3Com 3c985 PCI vendor/device ID.
68  */
69 #define TC_VENDORID			0x10B7
70 #define TC_DEVICEID_3C985		0x0001
71 
72 /*
73  * Netgear GA620 PCI vendor/device ID.
74  */
75 #define NG_VENDORID			0x1385
76 #define NG_DEVICEID_GA620		0x620A
77 #define NG_DEVICEID_GA620T		0x630A
78 
79 /*
80  * SGI device/vendor ID.
81  */
82 #define SGI_VENDORID			0x10A9
83 #define SGI_DEVICEID_TIGON		0x0009
84 
85 /*
86  * DEC vendor ID, Farallon device ID. Apparently, Farallon used
87  * the DEC vendor ID in their cards by mistake.
88  */
89 #define DEC_VENDORID			0x1011
90 #define DEC_DEVICEID_FARALLON_PN9000SX	0x001a
91 
92 /*
93  * Tigon configuration and control registers.
94  */
95 #define TI_MISC_HOST_CTL		0x040
96 #define TI_MISC_LOCAL_CTL		0x044
97 #define TI_SEM_AB			0x048 /* Tigon 2 only */
98 #define TI_MISC_CONF			0x050 /* Tigon 2 only */
99 #define TI_TIMER_BITS			0x054
100 #define TI_TIMERREF			0x058
101 #define TI_PCI_STATE			0x05C
102 #define TI_MAIN_EVENT_A			0x060
103 #define TI_MAILBOX_EVENT_A		0x064
104 #define TI_WINBASE			0x068
105 #define TI_WINDATA			0x06C
106 #define TI_MAIN_EVENT_B			0x070 /* Tigon 2 only */
107 #define TI_MAILBOX_EVENT_B		0x074 /* Tigon 2 only */
108 #define TI_TIMERREF_B			0x078 /* Tigon 2 only */
109 #define TI_SERIAL			0x07C
110 
111 /*
112  * Misc host control bits.
113  */
114 #define TI_MHC_INTSTATE			0x00000001
115 #define TI_MHC_CLEARINT			0x00000002
116 #define TI_MHC_RESET			0x00000008
117 #define TI_MHC_BYTE_SWAP_ENB		0x00000010
118 #define TI_MHC_WORD_SWAP_ENB		0x00000020
119 #define TI_MHC_MASK_INTS		0x00000040
120 #define TI_MHC_CHIP_REV_MASK		0xF0000000
121 
122 #define TI_MHC_BIGENDIAN_INIT	\
123 	(TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
124 
125 #define TI_MHC_LITTLEENDIAN_INIT	\
126 	(TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
127 
128 /*
129  * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
130  * Rev 5 is also the Tigon 2, but is a broken version which was never
131  * used in any actual hardware, so we ignore it.
132  */
133 #define TI_REV_TIGON_I			0x40000000
134 #define TI_REV_TIGON_II			0x60000000
135 
136 /*
137  * Firmware revision that we want.
138  */
139 #define TI_FIRMWARE_MAJOR		0xc
140 #define TI_FIRMWARE_MINOR		0x4
141 #define TI_FIRMWARE_FIX			0xd
142 
143 /*
144  * Miscelaneous Local Control register.
145  */
146 #define TI_MLC_EE_WRITE_ENB		0x00000010
147 #define TI_MLC_SRAM_BANK_SIZE		0x00000300 /* Tigon 2 only */
148 #define TI_MLC_LOCALADDR_21		0x00004000
149 #define TI_MLC_LOCALADDR_22		0x00008000
150 #define TI_MLC_SBUS_WRITEERR		0x00080000
151 #define TI_MLC_EE_CLK			0x00100000
152 #define TI_MLC_EE_TXEN			0x00200000
153 #define TI_MLC_EE_DOUT			0x00400000
154 #define TI_MLC_EE_DIN			0x00800000
155 
156 /* Possible memory sizes. */
157 #define TI_MLC_SRAM_BANK_DISA		0x00000000
158 #define TI_MLC_SRAM_BANK_1024K		0x00000100
159 #define TI_MLC_SRAM_BANK_512K		0x00000200
160 #define TI_MLC_SRAM_BANK_256K		0x00000300
161 
162 /*
163  * Offset of MAC address inside EEPROM.
164  */
165 #define TI_EE_MAC_OFFSET		0x8c
166 
167 #define TI_DMA_ASSIST			0x11C
168 #define TI_CPU_STATE			0x140
169 #define TI_CPU_PROGRAM_COUNTER		0x144
170 #define TI_SRAM_ADDR			0x154
171 #define TI_SRAM_DATA			0x158
172 #define TI_GEN_0			0x180
173 #define TI_GEN_X			0x1FC
174 #define TI_MAC_TX_STATE			0x200
175 #define TI_MAC_RX_STATE			0x220
176 #define TI_CPU_CTL_B			0x240 /* Tigon 2 only */
177 #define TI_CPU_PROGRAM_COUNTER_B	0x244 /* Tigon 2 only */
178 #define TI_SRAM_ADDR_B			0x254 /* Tigon 2 only */
179 #define TI_SRAM_DATA_B			0x258 /* Tigon 2 only */
180 #define TI_GEN_B_0			0x280 /* Tigon 2 only */
181 #define TI_GEN_B_X			0x2FC /* Tigon 2 only */
182 
183 /*
184  * Misc config register.
185  */
186 #define TI_MCR_SRAM_SYNCHRONOUS		0x00100000 /* Tigon 2 only */
187 
188 /*
189  * PCI state register.
190  */
191 #define TI_PCISTATE_FORCE_RESET		0x00000001
192 #define TI_PCISTATE_PROVIDE_LEN		0x00000002
193 #define TI_PCISTATE_READ_MAXDMA		0x0000001C
194 #define TI_PCISTATE_WRITE_MAXDMA	0x000000E0
195 #define TI_PCISTATE_MINDMA		0x0000FF00
196 #define TI_PCISTATE_FIFO_RETRY_ENB	0x00010000
197 #define TI_PCISTATE_USE_MEM_RD_MULT	0x00020000
198 #define TI_PCISTATE_NO_SWAP_READ_DMA	0x00040000
199 #define TI_PCISTATE_NO_SWAP_WRITE_DMA	0x00080000
200 #define TI_PCISTATE_66MHZ_BUS		0x00080000 /* Tigon 2 only */
201 #define TI_PCISTATE_32BIT_BUS		0x00100000 /* Tigon 2 only */
202 #define TI_PCISTATE_ENB_BYTE_ENABLES	0x00800000 /* Tigon 2 only */
203 #define TI_PCISTATE_READ_CMD		0x0F000000
204 #define TI_PCISTATE_WRITE_CMD		0xF0000000
205 
206 #define TI_PCI_READMAX_4		0x04
207 #define TI_PCI_READMAX_16		0x08
208 #define TI_PCI_READMAX_32		0x0C
209 #define TI_PCI_READMAX_64		0x10
210 #define TI_PCI_READMAX_128		0x14
211 #define TI_PCI_READMAX_256		0x18
212 #define TI_PCI_READMAX_1024		0x1C
213 
214 #define TI_PCI_WRITEMAX_4		0x20
215 #define TI_PCI_WRITEMAX_16		0x40
216 #define TI_PCI_WRITEMAX_32		0x60
217 #define TI_PCI_WRITEMAX_64		0x80
218 #define TI_PCI_WRITEMAX_128		0xA0
219 #define TI_PCI_WRITEMAX_256		0xC0
220 #define TI_PCI_WRITEMAX_1024		0xE0
221 
222 #define TI_PCI_READ_CMD			0x06000000
223 #define TI_PCI_WRITE_CMD		0x70000000
224 
225 /*
226  * DMA state register.
227  */
228 #define TI_DMASTATE_ENABLE		0x00000001
229 #define TI_DMASTATE_PAUSE		0x00000002
230 
231 /*
232  * CPU state register.
233  */
234 #define TI_CPUSTATE_RESET		0x00000001
235 #define TI_CPUSTATE_STEP		0x00000002
236 #define TI_CPUSTATE_ROMFAIL		0x00000010
237 #define TI_CPUSTATE_HALT		0x00010000
238 /*
239  * MAC TX state register
240  */
241 #define TI_TXSTATE_RESET		0x00000001
242 #define TI_TXSTATE_ENB			0x00000002
243 #define TI_TXSTATE_STOP			0x00000004
244 
245 /*
246  * MAC RX state register
247  */
248 #define TI_RXSTATE_RESET		0x00000001
249 #define TI_RXSTATE_ENB			0x00000002
250 #define TI_RXSTATE_STOP			0x00000004
251 
252 /*
253  * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
254  * split into 64 bit registers. Only the lower 32 bits of each mailbox
255  * are used.
256  */
257 #define TI_MB_HOSTINTR_HI		0x500
258 #define TI_MB_HOSTINTR_LO		0x504
259 #define TI_MB_HOSTINTR			TI_MB_HOSTINTR_LO
260 #define TI_MB_CMDPROD_IDX_HI		0x508
261 #define TI_MB_CMDPROD_IDX_LO		0x50C
262 #define TI_MB_CMDPROD_IDX		TI_MB_CMDPROD_IDX_LO
263 #define TI_MB_SENDPROD_IDX_HI		0x510
264 #define TI_MB_SENDPROD_IDX_LO		0x514
265 #define TI_MB_SENDPROD_IDX		TI_MB_SENDPROD_IDX_LO
266 #define TI_MB_STDRXPROD_IDX_HI		0x518 /* Tigon 2 only */
267 #define TI_MB_STDRXPROD_IDX_LO		0x51C /* Tigon 2 only */
268 #define TI_MB_STDRXPROD_IDX		TI_MB_STDRXPROD_IDX_LO
269 #define TI_MB_JUMBORXPROD_IDX_HI	0x520 /* Tigon 2 only */
270 #define TI_MB_JUMBORXPROD_IDX_LO	0x524 /* Tigon 2 only */
271 #define TI_MB_JUMBORXPROD_IDX		TI_MB_JUMBORXPROD_IDX_LO
272 #define TI_MB_MINIRXPROD_IDX_HI		0x528 /* Tigon 2 only */
273 #define TI_MB_MINIRXPROD_IDX_LO		0x52C /* Tigon 2 only */
274 #define TI_MB_MINIRXPROD_IDX		TI_MB_MINIRXPROD_IDX_LO
275 #define TI_MB_RSVD			0x530
276 
277 /*
278  * Tigon 2 general communication registers. These are 64 and 32 bit
279  * registers which are only valid after the firmware has been
280  * loaded and started. They actually exist in NIC memory but are
281  * mapped into the host memory via the shared memory region.
282  *
283  * The NIC internally maps these registers starting at address 0,
284  * so to determine the NIC address of any of these registers, we
285  * subtract 0x600 (the address of the first register).
286  */
287 
288 #define TI_GCR_BASE			0x600
289 #define TI_GCR_MACADDR			0x600
290 #define TI_GCR_PAR0			0x600
291 #define TI_GCR_PAR1			0x604
292 #define TI_GCR_GENINFO_HI		0x608
293 #define TI_GCR_GENINFO_LO		0x60C
294 #define TI_GCR_MCASTADDR		0x610 /* obsolete */
295 #define TI_GCR_MAR0			0x610 /* obsolete */
296 #define TI_GCR_MAR1			0x614 /* obsolete */
297 #define TI_GCR_OPMODE			0x618
298 #define TI_GCR_DMA_READCFG		0x61C
299 #define TI_GCR_DMA_WRITECFG		0x620
300 #define TI_GCR_TX_BUFFER_RATIO		0x624
301 #define TI_GCR_EVENTCONS_IDX		0x628
302 #define TI_GCR_CMDCONS_IDX		0x62C
303 #define TI_GCR_TUNEPARMS		0x630
304 #define TI_GCR_RX_COAL_TICKS		0x630
305 #define TI_GCR_TX_COAL_TICKS		0x634
306 #define TI_GCR_STAT_TICKS		0x638
307 #define TI_GCR_TX_MAX_COAL_BD		0x63C
308 #define TI_GCR_RX_MAX_COAL_BD		0x640
309 #define TI_GCR_NIC_TRACING		0x644
310 #define TI_GCR_GLINK			0x648
311 #define TI_GCR_LINK			0x64C
312 #define TI_GCR_NICTRACE_PTR		0x650
313 #define TI_GCR_NICTRACE_START		0x654
314 #define TI_GCR_NICTRACE_LEN		0x658
315 #define TI_GCR_IFINDEX			0x65C
316 #define TI_GCR_IFMTU			0x660
317 #define TI_GCR_MASK_INTRS		0x664
318 #define TI_GCR_GLINK_STAT		0x668
319 #define TI_GCR_LINK_STAT		0x66C
320 #define TI_GCR_RXRETURNCONS_IDX		0x680
321 #define TI_GCR_CMDRING			0x700
322 
323 #define TI_GCR_NIC_ADDR(x)		(x - TI_GCR_BASE);
324 
325 /*
326  * Local memory window. The local memory window is a 2K shared
327  * memory region which can be used to access the NIC's internal
328  * SRAM. The window can be mapped to a given 2K region using
329  * the TI_WINDOW_BASE register.
330  */
331 #define TI_WINDOW			0x800
332 #define TI_WINLEN			0x800
333 
334 #define TI_TICKS_PER_SEC		1000000
335 
336 /*
337  * Operation mode register.
338  */
339 #define TI_OPMODE_BYTESWAP_BD		0x00000002
340 #define TI_OPMODE_WORDSWAP_BD		0x00000004
341 #define TI_OPMODE_WARN_ENB		0x00000008 /* not yet implimented */
342 #define TI_OPMODE_BYTESWAP_DATA		0x00000010
343 #define TI_OPMODE_1_DMA_ACTIVE		0x00000040
344 #define TI_OPMODE_SBUS			0x00000100
345 #define TI_OPMODE_DONT_FRAG_JUMBO	0x00000200
346 #define TI_OPMODE_INCLUDE_CRC		0x00000400
347 #define TI_OPMODE_RX_BADFRAMES		0x00000800
348 #define TI_OPMODE_NO_EVENT_INTRS	0x00001000
349 #define TI_OPMODE_NO_TX_INTRS		0x00002000
350 #define TI_OPMODE_NO_RX_INTRS		0x00004000
351 #define TI_OPMODE_FATAL_ENB		0x40000000 /* not yet implimented */
352 
353 /*
354  * DMA configuration thresholds.
355  */
356 #define TI_DMA_STATE_THRESH_16W		0x00000100
357 #define TI_DMA_STATE_THRESH_8W		0x00000080
358 #define TI_DMA_STATE_THRESH_4W		0x00000040
359 #define TI_DMA_STATE_THRESH_2W		0x00000020
360 #define TI_DMA_STATE_THRESH_1W		0x00000010
361 
362 #define TI_DMA_STATE_FORCE_32_BIT	0x00000008
363 
364 /*
365  * Gigabit link status bits.
366  */
367 #define TI_GLNK_SENSE_NO_BEG		0x00002000
368 #define TI_GLNK_LOOPBACK		0x00004000
369 #define TI_GLNK_PREF			0x00008000
370 #define TI_GLNK_1000MB			0x00040000
371 #define TI_GLNK_FULL_DUPLEX		0x00080000
372 #define TI_GLNK_TX_FLOWCTL_Y		0x00200000 /* Tigon 2 only */
373 #define TI_GLNK_RX_FLOWCTL_Y		0x00800000
374 #define TI_GLNK_AUTONEGENB		0x20000000
375 #define TI_GLNK_ENB			0x40000000
376 
377 /*
378  * Link status bits.
379  */
380 #define TI_LNK_LOOPBACK			0x00004000
381 #define TI_LNK_PREF			0x00008000
382 #define TI_LNK_10MB			0x00010000
383 #define TI_LNK_100MB			0x00020000
384 #define TI_LNK_1000MB			0x00040000
385 #define TI_LNK_FULL_DUPLEX		0x00080000
386 #define TI_LNK_HALF_DUPLEX		0x00100000
387 #define TI_LNK_TX_FLOWCTL_Y		0x00200000 /* Tigon 2 only */
388 #define TI_LNK_RX_FLOWCTL_Y		0x00800000
389 #define TI_LNK_AUTONEGENB		0x20000000
390 #define TI_LNK_ENB			0x40000000
391 
392 /*
393  * Ring size constants.
394  */
395 #define TI_EVENT_RING_CNT	256
396 #define TI_CMD_RING_CNT		64
397 #define TI_STD_RX_RING_CNT	512
398 #define TI_JUMBO_RX_RING_CNT	256
399 #define TI_MINI_RX_RING_CNT	1024
400 #define TI_RETURN_RING_CNT	2048
401 
402 /*
403  * Possible TX ring sizes.
404  */
405 #define TI_TX_RING_CNT_128	128
406 #define TI_TX_RING_BASE_128	0x3800
407 
408 #define TI_TX_RING_CNT_256	256
409 #define TI_TX_RING_BASE_256	0x3000
410 
411 #define TI_TX_RING_CNT_512	512
412 #define TI_TX_RING_BASE_512	0x2000
413 
414 #define TI_TX_RING_CNT		TI_TX_RING_CNT_512
415 #define TI_TX_RING_BASE		TI_TX_RING_BASE_512
416 
417 /*
418  * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
419  * is limited to 2MB total, and in general I think most adapters have
420  * around 1MB. We use this value for zeroing the NIC's SRAM, so to
421  * be safe we use the largest possible value (zeroing memory that
422  * isn't there doesn't hurt anything).
423  */
424 #define TI_MEM_MAX		0x7FFFFF
425 
426 /*
427  * Even on the alpha, pci addresses are 32-bit quantities
428  */
429 
430 #ifdef __64_bit_pci_addressing__
431 typedef struct {
432 	uint64_t		ti_addr;
433 } ti_hostaddr;
434 #define TI_HOSTADDR(x)	x.ti_addr
435 #else
436 typedef struct {
437 	uint32_t		ti_addr_hi;
438 	uint32_t		ti_addr_lo;
439 } ti_hostaddr;
440 #define TI_HOSTADDR(x)	x.ti_addr_lo
441 #endif
442 
443 /*
444  * Ring control block structure. The rules for the max_len field
445  * are as follows:
446  *
447  * For the send ring, max_len indicates the number of entries in the
448  * ring (128, 256 or 512).
449  *
450  * For the standard receive ring, max_len indicates the threshold
451  * used to decide when a frame should be put in the jumbo receive ring
452  * instead of the standard one.
453  *
454  * For the mini ring, max_len indicates the size of the buffers in the
455  * ring. This is the value used to decide when a frame is small enough
456  * to be placed in the mini ring.
457  *
458  * For the return receive ring, max_len indicates the number of entries
459  * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
460  * 2048 for backwards compatibility). The value 1024 can only be used
461  * if the mini ring is disabled.
462  */
463 struct ti_rcb {
464 	ti_hostaddr		ti_hostaddr;
465 #if BYTE_ORDER == BIG_ENDIAN
466 	uint16_t		ti_max_len;
467 	uint16_t		ti_flags;
468 #else
469 	uint16_t		ti_flags;
470 	uint16_t		ti_max_len;
471 #endif
472 	uint32_t		ti_unused;
473 };
474 
475 #define TI_RCB_FLAG_TCP_UDP_CKSUM	0x00000001
476 #define TI_RCB_FLAG_IP_CKSUM		0x00000002
477 #define TI_RCB_FLAG_NO_PHDR_CKSUM	0x00000008
478 #define TI_RCB_FLAG_VLAN_ASSIST		0x00000010
479 #define TI_RCB_FLAG_COAL_UPD_ONLY	0x00000020
480 #define TI_RCB_FLAG_HOST_RING		0x00000040
481 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM	0x00000080
482 #define TI_RCB_FLAG_USE_EXT_RX_BD	0x00000100
483 #define TI_RCB_FLAG_RING_DISABLED	0x00000200
484 
485 struct ti_producer {
486 	uint32_t		ti_idx;
487 	uint32_t		ti_unused;
488 };
489 
490 /*
491  * Tigon statistics counters.
492  */
493 struct ti_stats {
494 	/*
495 	 * MAC stats, taken from RFC 1643, ethernet-like MIB
496 	 */
497 	volatile uint32_t dot3StatsAlignmentErrors;		/* 0 */
498 	volatile uint32_t dot3StatsFCSErrors;			/* 1 */
499 	volatile uint32_t dot3StatsSingleCollisionFrames;	/* 2 */
500 	volatile uint32_t dot3StatsMultipleCollisionFrames;	/* 3 */
501 	volatile uint32_t dot3StatsSQETestErrors;		/* 4 */
502 	volatile uint32_t dot3StatsDeferredTransmissions;	/* 5 */
503 	volatile uint32_t dot3StatsLateCollisions;		/* 6 */
504 	volatile uint32_t dot3StatsExcessiveCollisions;	/* 7 */
505 	volatile uint32_t dot3StatsInternalMacTransmitErrors;	/* 8 */
506 	volatile uint32_t dot3StatsCarrierSenseErrors;		/* 9 */
507 	volatile uint32_t dot3StatsFrameTooLongs;		/* 10 */
508 	volatile uint32_t dot3StatsInternalMacReceiveErrors;	/* 11 */
509 	/*
510 	 * interface stats, taken from RFC 1213, MIB-II, interfaces group
511 	 */
512 	volatile uint32_t ifIndex;				/* 12 */
513 	volatile uint32_t ifType;				/* 13 */
514 	volatile uint32_t ifMtu;				/* 14 */
515 	volatile uint32_t ifSpeed;				/* 15 */
516 	volatile uint32_t ifAdminStatus;			/* 16 */
517 #define IF_ADMIN_STATUS_UP      1
518 #define IF_ADMIN_STATUS_DOWN    2
519 #define IF_ADMIN_STATUS_TESTING 3
520 	volatile uint32_t ifOperStatus;			/* 17 */
521 #define IF_OPER_STATUS_UP       1
522 #define IF_OPER_STATUS_DOWN     2
523 #define IF_OPER_STATUS_TESTING  3
524 #define IF_OPER_STATUS_UNKNOWN  4
525 #define IF_OPER_STATUS_DORMANT  5
526 	volatile uint32_t ifLastChange;			/* 18 */
527 	volatile uint32_t ifInDiscards;			/* 19 */
528 	volatile uint32_t ifInErrors;				/* 20 */
529 	volatile uint32_t ifInUnknownProtos;			/* 21 */
530 	volatile uint32_t ifOutDiscards;			/* 22 */
531 	volatile uint32_t ifOutErrors;				/* 23 */
532 	volatile uint32_t ifOutQLen;     /* deprecated */	/* 24 */
533 	volatile uint8_t  ifPhysAddress[8]; /* 8 bytes */	/* 25 - 26 */
534 	volatile uint8_t  ifDescr[32];				/* 27 - 34 */
535 	uint32_t alignIt;      /* align to 64 bit for uint64_ts following */
536 	/*
537 	 * more interface stats, taken from RFC 1573, MIB-IIupdate,
538 	 * interfaces group
539 	 */
540 	volatile uint64_t ifHCInOctets;			/* 36 - 37 */
541 	volatile uint64_t ifHCInUcastPkts;			/* 38 - 39 */
542 	volatile uint64_t ifHCInMulticastPkts;			/* 40 - 41 */
543 	volatile uint64_t ifHCInBroadcastPkts;			/* 42 - 43 */
544 	volatile uint64_t ifHCOutOctets;			/* 44 - 45 */
545 	volatile uint64_t ifHCOutUcastPkts;			/* 46 - 47 */
546 	volatile uint64_t ifHCOutMulticastPkts;		/* 48 - 49 */
547 	volatile uint64_t ifHCOutBroadcastPkts;		/* 50 - 51 */
548 	volatile uint32_t ifLinkUpDownTrapEnable;		/* 52 */
549 	volatile uint32_t ifHighSpeed;				/* 53 */
550 	volatile uint32_t ifPromiscuousMode; 			/* 54 */
551 	volatile uint32_t ifConnectorPresent; /* follow link state 55 */
552 	/*
553 	 * Host Commands
554 	 */
555 	volatile uint32_t nicCmdsHostState;			/* 56 */
556 	volatile uint32_t nicCmdsFDRFiltering;			/* 57 */
557 	volatile uint32_t nicCmdsSetRecvProdIndex;		/* 58 */
558 	volatile uint32_t nicCmdsUpdateGencommStats;		/* 59 */
559 	volatile uint32_t nicCmdsResetJumboRing;		/* 60 */
560 	volatile uint32_t nicCmdsAddMCastAddr;			/* 61 */
561 	volatile uint32_t nicCmdsDelMCastAddr;			/* 62 */
562 	volatile uint32_t nicCmdsSetPromiscMode;		/* 63 */
563 	volatile uint32_t nicCmdsLinkNegotiate;		/* 64 */
564 	volatile uint32_t nicCmdsSetMACAddr;			/* 65 */
565 	volatile uint32_t nicCmdsClearProfile;			/* 66 */
566 	volatile uint32_t nicCmdsSetMulticastMode;		/* 67 */
567 	volatile uint32_t nicCmdsClearStats;			/* 68 */
568 	volatile uint32_t nicCmdsSetRecvJumboProdIndex;	/* 69 */
569 	volatile uint32_t nicCmdsSetRecvMiniProdIndex;		/* 70 */
570 	volatile uint32_t nicCmdsRefreshStats;			/* 71 */
571 	volatile uint32_t nicCmdsUnknown;			/* 72 */
572 	/*
573 	 * NIC Events
574 	 */
575 	volatile uint32_t nicEventsNICFirmwareOperational;	/* 73 */
576 	volatile uint32_t nicEventsStatsUpdated;		/* 74 */
577 	volatile uint32_t nicEventsLinkStateChanged;		/* 75 */
578 	volatile uint32_t nicEventsError;			/* 76 */
579 	volatile uint32_t nicEventsMCastListUpdated;		/* 77 */
580 	volatile uint32_t nicEventsResetJumboRing;		/* 78 */
581 	/*
582 	 * Ring manipulation
583 	 */
584 	volatile uint32_t nicRingSetSendProdIndex;		/* 79 */
585 	volatile uint32_t nicRingSetSendConsIndex;		/* 80 */
586 	volatile uint32_t nicRingSetRecvReturnProdIndex;	/* 81 */
587 	/*
588 	 * Interrupts
589 	 */
590 	volatile uint32_t nicInterrupts;			/* 82 */
591 	volatile uint32_t nicAvoidedInterrupts;		/* 83 */
592 	/*
593 	 * BD Coalessing Thresholds
594 	 */
595 	volatile uint32_t nicEventThresholdHit;		/* 84 */
596 	volatile uint32_t nicSendThresholdHit;			/* 85 */
597 	volatile uint32_t nicRecvThresholdHit;			/* 86 */
598 	/*
599 	 * DMA Attentions
600 	 */
601 	volatile uint32_t nicDmaRdOverrun;			/* 87 */
602 	volatile uint32_t nicDmaRdUnderrun;			/* 88 */
603 	volatile uint32_t nicDmaWrOverrun;			/* 89 */
604 	volatile uint32_t nicDmaWrUnderrun;			/* 90 */
605 	volatile uint32_t nicDmaWrMasterAborts;		/* 91 */
606 	volatile uint32_t nicDmaRdMasterAborts;		/* 92 */
607 	/*
608 	 * NIC Resources
609 	 */
610 	volatile uint32_t nicDmaWriteRingFull;			/* 93 */
611 	volatile uint32_t nicDmaReadRingFull;			/* 94 */
612 	volatile uint32_t nicEventRingFull;			/* 95 */
613 	volatile uint32_t nicEventProducerRingFull;		/* 96 */
614 	volatile uint32_t nicTxMacDescrRingFull;		/* 97 */
615 	volatile uint32_t nicOutOfTxBufSpaceFrameRetry;	/* 98 */
616 	volatile uint32_t nicNoMoreWrDMADescriptors;		/* 99 */
617 	volatile uint32_t nicNoMoreRxBDs;			/* 100 */
618 	volatile uint32_t nicNoSpaceInReturnRing;		/* 101 */
619 	volatile uint32_t nicSendBDs;            /* current count 102 */
620 	volatile uint32_t nicRecvBDs;            /* current count 103 */
621 	volatile uint32_t nicJumboRecvBDs;       /* current count 104 */
622 	volatile uint32_t nicMiniRecvBDs;        /* current count 105 */
623 	volatile uint32_t nicTotalRecvBDs;       /* current count 106 */
624 	volatile uint32_t nicTotalSendBDs;       /* current count 107 */
625 	volatile uint32_t nicJumboSpillOver;			/* 108 */
626 	volatile uint32_t nicSbusHangCleared;			/* 109 */
627 	volatile uint32_t nicEnqEventDelayed;			/* 110 */
628 	/*
629 	 * Stats from MAC rx completion
630 	 */
631 	volatile uint32_t nicMacRxLateColls;			/* 111 */
632 	volatile uint32_t nicMacRxLinkLostDuringPkt;		/* 112 */
633 	volatile uint32_t nicMacRxPhyDecodeErr;		/* 113 */
634 	volatile uint32_t nicMacRxMacAbort;			/* 114 */
635 	volatile uint32_t nicMacRxTruncNoResources;		/* 115 */
636 	/*
637 	 * Stats from the mac_stats area
638 	 */
639 	volatile uint32_t nicMacRxDropUla;			/* 116 */
640 	volatile uint32_t nicMacRxDropMcast;			/* 117 */
641 	volatile uint32_t nicMacRxFlowControl;			/* 118 */
642 	volatile uint32_t nicMacRxDropSpace;			/* 119 */
643 	volatile uint32_t nicMacRxColls;			/* 120 */
644 	/*
645  	 * MAC RX Attentions
646 	 */
647 	volatile uint32_t nicMacRxTotalAttns;			/* 121 */
648 	volatile uint32_t nicMacRxLinkAttns;			/* 122 */
649 	volatile uint32_t nicMacRxSyncAttns;			/* 123 */
650 	volatile uint32_t nicMacRxConfigAttns;			/* 124 */
651 	volatile uint32_t nicMacReset;				/* 125 */
652 	volatile uint32_t nicMacRxBufDescrAttns;		/* 126 */
653 	volatile uint32_t nicMacRxBufAttns;			/* 127 */
654 	volatile uint32_t nicMacRxZeroFrameCleanup;		/* 128 */
655 	volatile uint32_t nicMacRxOneFrameCleanup;		/* 129 */
656 	volatile uint32_t nicMacRxMultipleFrameCleanup;	/* 130 */
657 	volatile uint32_t nicMacRxTimerCleanup;		/* 131 */
658 	volatile uint32_t nicMacRxDmaCleanup;			/* 132 */
659 	/*
660 	 * Stats from the mac_stats area
661 	 */
662 	volatile uint32_t nicMacTxCollisionHistogram[15];	/* 133 */
663 	/*
664 	 * MAC TX Attentions
665 	 */
666 	volatile uint32_t nicMacTxTotalAttns;			/* 134 */
667 	/*
668 	 * NIC Profile
669 	 */
670 	volatile uint32_t nicProfile[32];			/* 135 */
671 	/*
672 	 * Pat to 1024 bytes.
673 	 */
674 	uint32_t		pad[75];
675 };
676 /*
677  * Tigon general information block. This resides in host memory
678  * and contains the status counters, ring control blocks and
679  * producer pointers.
680  */
681 
682 struct ti_gib {
683 	struct ti_stats		ti_stats;
684 	struct ti_rcb		ti_ev_rcb;
685 	struct ti_rcb		ti_cmd_rcb;
686 	struct ti_rcb		ti_tx_rcb;
687 	struct ti_rcb		ti_std_rx_rcb;
688 	struct ti_rcb		ti_jumbo_rx_rcb;
689 	struct ti_rcb		ti_mini_rx_rcb;
690 	struct ti_rcb		ti_return_rcb;
691 	ti_hostaddr		ti_ev_prodidx_ptr;
692 	ti_hostaddr		ti_return_prodidx_ptr;
693 	ti_hostaddr		ti_tx_considx_ptr;
694 	ti_hostaddr		ti_refresh_stats_ptr;
695 };
696 
697 /*
698  * Buffer descriptor structures. There are basically three types
699  * of structures: normal receive descriptors, extended receive
700  * descriptors and transmit descriptors. The extended receive
701  * descriptors are optionally used only for the jumbo receive ring.
702  */
703 
704 struct ti_rx_desc {
705 	ti_hostaddr		ti_addr;
706 #if BYTE_ORDER == BIG_ENDIAN
707 	uint16_t		ti_idx;
708 	uint16_t		ti_len;
709 #else
710 	uint16_t		ti_len;
711 	uint16_t		ti_idx;
712 #endif
713 #if BYTE_ORDER == BIG_ENDIAN
714 	uint16_t		ti_type;
715 	uint16_t		ti_flags;
716 #else
717 	uint16_t		ti_flags;
718 	uint16_t		ti_type;
719 #endif
720 #if BYTE_ORDER == BIG_ENDIAN
721 	uint16_t		ti_ip_cksum;
722 	uint16_t		ti_tcp_udp_cksum;
723 #else
724 	uint16_t		ti_tcp_udp_cksum;
725 	uint16_t		ti_ip_cksum;
726 #endif
727 #if BYTE_ORDER == BIG_ENDIAN
728 	uint16_t		ti_error_flags;
729 	uint16_t		ti_vlan_tag;
730 #else
731 	uint16_t		ti_vlan_tag;
732 	uint16_t		ti_error_flags;
733 #endif
734 	uint32_t		ti_rsvd;
735 	uint32_t		ti_opaque;
736 };
737 
738 struct ti_rx_desc_ext {
739 	ti_hostaddr		ti_addr1;
740 	ti_hostaddr		ti_addr2;
741 	ti_hostaddr		ti_addr3;
742 #if BYTE_ORDER == BIG_ENDIAN
743 	uint16_t		ti_len1;
744 	uint16_t		ti_len2;
745 #else
746 	uint16_t		ti_len2;
747 	uint16_t		ti_len1;
748 #endif
749 #if BYTE_ORDER == BIG_ENDIAN
750 	uint16_t		ti_len3;
751 	uint16_t		ti_rsvd0;
752 #else
753 	uint16_t		ti_rsvd0;
754 	uint16_t		ti_len3;
755 #endif
756 	ti_hostaddr		ti_addr0;
757 #if BYTE_ORDER == BIG_ENDIAN
758 	uint16_t		ti_idx;
759 	uint16_t		ti_len0;
760 #else
761 	uint16_t		ti_len0;
762 	uint16_t		ti_idx;
763 #endif
764 #if BYTE_ORDER == BIG_ENDIAN
765 	uint16_t		ti_type;
766 	uint16_t		ti_flags;
767 #else
768 	uint16_t		ti_flags;
769 	uint16_t		ti_type;
770 #endif
771 #if BYTE_ORDER == BIG_ENDIAN
772 	uint16_t		ti_ip_cksum;
773 	uint16_t		ti_tcp_udp_cksum;
774 #else
775 	uint16_t		ti_tcp_udp_cksum;
776 	uint16_t		ti_ip_cksum;
777 #endif
778 #if BYTE_ORDER == BIG_ENDIAN
779 	uint16_t		ti_error_flags;
780 	uint16_t		ti_vlan_tag;
781 #else
782 	uint16_t		ti_vlan_tag;
783 	uint16_t		ti_error_flags;
784 #endif
785 	uint32_t		ti_rsvd1;
786 	uint32_t		ti_opaque;
787 };
788 
789 /*
790  * Transmit descriptors are, mercifully, very small.
791  */
792 struct ti_tx_desc {
793 	ti_hostaddr		ti_addr;
794 #if BYTE_ORDER == BIG_ENDIAN
795 	uint16_t		ti_len;
796 	uint16_t		ti_flags;
797 #else
798 	uint16_t		ti_flags;
799 	uint16_t		ti_len;
800 #endif
801 #if BYTE_ORDER == BIG_ENDIAN
802 	uint16_t		ti_rsvd;
803 	uint16_t		ti_vlan_tag;
804 #else
805 	uint16_t		ti_vlan_tag;
806 	uint16_t		ti_rsvd;
807 #endif
808 };
809 
810 /*
811  * NOTE!  On the Alpha, we have an alignment constraint.
812  * The first thing in the packet is a 14-byte Ethernet header.
813  * This means that the packet is misaligned.  To compensate,
814  * we actually offset the data 2 bytes into the cluster.  This
815  * alignes the packet after the Ethernet header at a 32-bit
816  * boundary.
817  */
818 
819 #define ETHER_ALIGN 2
820 
821 #define TI_FRAMELEN		1518
822 #define TI_JUMBO_FRAMELEN	9018
823 #define TI_JUMBO_MTU		(TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
824 #define TI_PAGE_SIZE		PAGE_SIZE
825 #define TI_MIN_FRAMELEN		60
826 
827 /*
828  * Buffer descriptor error flags.
829  */
830 #define TI_BDERR_CRC			0x0001
831 #define TI_BDERR_COLLDETECT		0x0002
832 #define TI_BDERR_LINKLOST		0x0004
833 #define TI_BDERR_DECODE			0x0008
834 #define TI_BDERR_ODD_NIBBLES		0x0010
835 #define TI_BDERR_MAC_ABRT		0x0020
836 #define TI_BDERR_RUNT			0x0040
837 #define TI_BDERR_TRUNC			0x0080
838 #define TI_BDERR_GIANT			0x0100
839 
840 /*
841  * Buffer descriptor flags.
842  */
843 #define TI_BDFLAG_TCP_UDP_CKSUM		0x0001
844 #define TI_BDFLAG_IP_CKSUM		0x0002
845 #define TI_BDFLAG_END			0x0004
846 #define TI_BDFLAG_MORE			0x0008
847 #define TI_BDFLAG_JUMBO_RING		0x0010
848 #define TI_BDFLAG_UCAST_PKT		0x0020
849 #define TI_BDFLAG_MCAST_PKT		0x0040
850 #define TI_BDFLAG_BCAST_PKT		0x0060
851 #define TI_BDFLAG_IP_FRAG		0x0080
852 #define TI_BDFLAG_IP_FRAG_END		0x0100
853 #define TI_BDFLAG_VLAN_TAG		0x0200
854 #define TI_BDFLAG_ERROR			0x0400
855 #define TI_BDFLAG_COAL_NOW		0x0800
856 #define	TI_BDFLAG_MINI_RING		0x1000
857 
858 /*
859  * Descriptor type flags. I think these only have meaning for
860  * the Tigon 1. I had to extract them from the sample driver source
861  * since they aren't in the manual.
862  */
863 #define TI_BDTYPE_TYPE_NULL			0x0000
864 #define TI_BDTYPE_SEND_BD			0x0001
865 #define TI_BDTYPE_RECV_BD			0x0002
866 #define TI_BDTYPE_RECV_JUMBO_BD			0x0003
867 #define TI_BDTYPE_RECV_BD_LAST			0x0004
868 #define TI_BDTYPE_SEND_DATA			0x0005
869 #define TI_BDTYPE_SEND_DATA_LAST		0x0006
870 #define TI_BDTYPE_RECV_DATA			0x0007
871 #define TI_BDTYPE_RECV_DATA_LAST		0x000b
872 #define TI_BDTYPE_EVENT_RUPT			0x000c
873 #define TI_BDTYPE_EVENT_NO_RUPT			0x000d
874 #define TI_BDTYPE_ODD_START			0x000e
875 #define TI_BDTYPE_UPDATE_STATS			0x000f
876 #define TI_BDTYPE_SEND_DUMMY_DMA		0x0010
877 #define TI_BDTYPE_EVENT_PROD			0x0011
878 #define TI_BDTYPE_TX_CONS			0x0012
879 #define TI_BDTYPE_RX_PROD			0x0013
880 #define TI_BDTYPE_REFRESH_STATS			0x0014
881 #define TI_BDTYPE_SEND_DATA_LAST_VLAN		0x0015
882 #define TI_BDTYPE_SEND_DATA_COAL		0x0016
883 #define TI_BDTYPE_SEND_DATA_LAST_COAL		0x0017
884 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL	0x0018
885 #define TI_BDTYPE_TX_CONS_NO_INTR		0x0019
886 
887 /*
888  * Tigon command structure.
889  */
890 struct ti_cmd_desc {
891 #if BYTE_ORDER == BIG_ENDIAN
892 	uint32_t		ti_cmd:8;
893 	uint32_t		ti_code:12;
894 	uint32_t		ti_idx:12;
895 #else
896 	uint32_t		ti_idx:12;
897 	uint32_t		ti_code:12;
898 	uint32_t		ti_cmd:8;
899 #endif
900 };
901 
902 #define TI_CMD_HOST_STATE		0x01
903 #define TI_CMD_CODE_STACK_UP		0x01
904 #define TI_CMD_CODE_STACK_DOWN		0x02
905 
906 /*
907  * This command enables software address filtering. It's a workaround
908  * for a bug in the Tigon 1 and not implemented for the Tigon 2.
909  */
910 #define TI_CMD_FDR_FILTERING		0x02
911 #define TI_CMD_CODE_FILT_ENB		0x01
912 #define TI_CMD_CODE_FILT_DIS		0x02
913 
914 #define TI_CMD_SET_RX_PROD_IDX		0x03 /* obsolete */
915 #define TI_CMD_UPDATE_GENCOM		0x04
916 #define TI_CMD_RESET_JUMBO_RING		0x05
917 #define TI_CMD_SET_PARTIAL_RX_CNT	0x06
918 #define TI_CMD_ADD_MCAST_ADDR		0x08 /* obsolete */
919 #define TI_CMD_DEL_MCAST_ADDR		0x09 /* obsolete */
920 
921 #define TI_CMD_SET_PROMISC_MODE		0x0A
922 #define TI_CMD_CODE_PROMISC_ENB		0x01
923 #define TI_CMD_CODE_PROMISC_DIS		0x02
924 
925 #define TI_CMD_LINK_NEGOTIATION		0x0B
926 #define TI_CMD_CODE_NEGOTIATE_BOTH	0x00
927 #define TI_CMD_CODE_NEGOTIATE_GIGABIT	0x01
928 #define TI_CMD_CODE_NEGOTIATE_10_100	0x02
929 
930 #define TI_CMD_SET_MAC_ADDR		0x0C
931 #define TI_CMD_CLR_PROFILE		0x0D
932 
933 #define TI_CMD_SET_ALLMULTI		0x0E
934 #define TI_CMD_CODE_ALLMULTI_ENB	0x01
935 #define TI_CMD_CODE_ALLMULTI_DIS	0x02
936 
937 #define TI_CMD_CLR_STATS		0x0F
938 #define TI_CMD_SET_RX_JUMBO_PROD_IDX	0x10 /* obsolete */
939 #define TI_CMD_RFRSH_STATS		0x11
940 
941 #define TI_CMD_EXT_ADD_MCAST		0x12
942 #define TI_CMD_EXT_DEL_MCAST		0x13
943 
944 /*
945  * Utility macros to make issuing commands a little simpler. Assumes
946  * that 'sc' and 'cmd' are in local scope.
947  */
948 #define TI_DO_CMD(x, y, z)		do {		\
949 	cmd.ti_cmd = x;					\
950 	cmd.ti_code = y;				\
951 	cmd.ti_idx = z;					\
952 	ti_cmd(sc, &cmd);				\
953 } while(0)
954 
955 #define TI_DO_CMD_EXT(x, y, z, v, w)	do {		\
956 	cmd.ti_cmd = x;					\
957 	cmd.ti_code = y;				\
958 	cmd.ti_idx = z;					\
959 	ti_cmd_ext(sc, &cmd, v, w);			\
960 } while(0)
961 
962 /*
963  * Other utility macros.
964  */
965 #define TI_INC(x, y)	(x) = (x + 1) % y
966 
967 #define TI_UPDATE_JUMBOPROD(x, y)					\
968 	if (x->ti_hwrev == TI_HWREV_TIGON) {				\
969 		TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y);	\
970 	} else {							\
971 		CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y);		\
972 	}
973 
974 #define TI_UPDATE_MINIPROD(x, y)					\
975 		CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y);
976 
977 #define TI_UPDATE_STDPROD(x, y)						\
978 	if (x->ti_hwrev == TI_HWREV_TIGON) {				\
979 		TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y);		\
980 	} else {							\
981 		CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y);			\
982 	}
983 
984 
985 /*
986  * Tigon event structure.
987  */
988 struct ti_event_desc {
989 #if BYTE_ORDER == BIG_ENDIAN
990 	uint32_t		ti_event:8;
991 	uint32_t		ti_code:12;
992 	uint32_t		ti_idx:12;
993 #else
994 	uint32_t		ti_idx:12;
995 	uint32_t		ti_code:12;
996 	uint32_t		ti_event:8;
997 #endif
998 	uint32_t		ti_rsvd;
999 };
1000 
1001 /*
1002  * Tigon events.
1003  */
1004 #define TI_EV_FIRMWARE_UP		0x01
1005 #define TI_EV_STATS_UPDATED		0x04
1006 
1007 #define TI_EV_LINKSTAT_CHANGED		0x06
1008 #define TI_EV_CODE_GIG_LINK_UP		0x01
1009 #define TI_EV_CODE_LINK_DOWN		0x02
1010 #define TI_EV_CODE_LINK_UP		0x03
1011 
1012 #define TI_EV_ERROR			0x07
1013 #define TI_EV_CODE_ERR_INVAL_CMD	0x01
1014 #define TI_EV_CODE_ERR_UNIMP_CMD	0x02
1015 #define TI_EV_CODE_ERR_BADCFG		0x03
1016 
1017 #define TI_EV_MCAST_UPDATED		0x08
1018 #define TI_EV_CODE_MCAST_ADD		0x01
1019 #define TI_EV_CODE_MCAST_DEL		0x02
1020 
1021 #define TI_EV_RESET_JUMBO_RING		0x09
1022 /*
1023  * Register access macros. The Tigon always uses memory mapped register
1024  * accesses and all registers must be accessed with 32 bit operations.
1025  */
1026 
1027 #define CSR_WRITE_4(sc, reg, val)	\
1028 	bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val)
1029 
1030 #define CSR_READ_4(sc, reg)		\
1031 	bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg)
1032 
1033 #define TI_SETBIT(sc, reg, x)	\
1034 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
1035 #define TI_CLRBIT(sc, reg, x)	\
1036 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
1037 
1038 /*
1039  * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
1040  * values are tuneable. They control the actual amount of buffers
1041  * allocated for the standard, mini and jumbo receive rings.
1042  */
1043 
1044 #define TI_SSLOTS	256
1045 #define TI_MSLOTS	256
1046 #define TI_JSLOTS	384
1047 
1048 #define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN)
1049 #define TI_JLEN (TI_JRAWLEN + (sizeof(uint64_t) - \
1050 	(TI_JRAWLEN % sizeof(uint64_t))))
1051 #define TI_JPAGESZ PAGE_SIZE
1052 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ)
1053 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID)
1054 
1055 struct ti_softc;
1056 
1057 struct ti_jslot {
1058 	struct ti_softc		*ti_sc;
1059 	void			*ti_buf;
1060         int			ti_inuse;
1061 	int			ti_slot;
1062 	SLIST_ENTRY(ti_jslot)	jslot_link;
1063 };
1064 
1065 /*
1066  * Ring structures. Most of these reside in host memory and we tell
1067  * the NIC where they are via the ring control blocks. The exceptions
1068  * are the tx and command rings, which live in NIC memory and which
1069  * we access via the shared memory window.
1070  */
1071 struct ti_ring_data {
1072 	struct ti_rx_desc	ti_rx_std_ring[TI_STD_RX_RING_CNT];
1073 	struct ti_rx_desc	ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
1074 	struct ti_rx_desc	ti_rx_mini_ring[TI_MINI_RX_RING_CNT];
1075 	struct ti_rx_desc	ti_rx_return_ring[TI_RETURN_RING_CNT];
1076 	struct ti_event_desc	ti_event_ring[TI_EVENT_RING_CNT];
1077 	struct ti_tx_desc	ti_tx_ring[TI_TX_RING_CNT];
1078 	/*
1079 	 * Make sure producer structures are aligned on 32-byte cache
1080 	 * line boundaries.
1081 	 */
1082 	struct ti_producer	ti_ev_prodidx_r;
1083 	uint32_t		ti_pad0[6];
1084 	struct ti_producer	ti_return_prodidx_r;
1085 	uint32_t		ti_pad1[6];
1086 	struct ti_producer	ti_tx_considx_r;
1087 	uint32_t		ti_pad2[6];
1088 	struct ti_tx_desc	*ti_tx_ring_nic;/* pointer to shared mem */
1089 	struct ti_cmd_desc	*ti_cmd_ring;	/* pointer to shared mem */
1090 	struct ti_gib		ti_info;
1091 };
1092 
1093 /*
1094  * Mbuf pointers. We need these to keep track of the virtual addresses
1095  * of our mbuf chains since we can only convert from physical to virtual,
1096  * not the other way around.
1097  */
1098 struct ti_chain_data {
1099 	struct mbuf		*ti_tx_chain[TI_TX_RING_CNT];
1100 	struct mbuf		*ti_rx_std_chain[TI_STD_RX_RING_CNT];
1101 	struct mbuf		*ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
1102 	struct mbuf		*ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
1103 	/* Stick the jumbo mem management stuff here too. */
1104 	struct ti_jslot		ti_jslots[TI_JSLOTS];
1105 	void			*ti_jumbo_buf;
1106 };
1107 
1108 struct ti_type {
1109 	uint16_t		ti_vid;
1110 	uint16_t		ti_did;
1111 	char			*ti_name;
1112 };
1113 
1114 #define TI_HWREV_TIGON		0x01
1115 #define TI_HWREV_TIGON_II	0x02
1116 #define TI_TIMEOUT		1000
1117 #define TI_TXCONS_UNSET		0xFFFF	/* impossible value */
1118 
1119 struct ti_mc_entry {
1120 	struct ether_addr		mc_addr;
1121 	SLIST_ENTRY(ti_mc_entry)	mc_entries;
1122 };
1123 
1124 struct ti_softc {
1125 	struct arpcom		arpcom;		/* interface info */
1126 	bus_space_handle_t	ti_bhandle;
1127 	vm_offset_t		ti_vhandle;
1128 	bus_space_tag_t		ti_btag;
1129 	void			*ti_intrhand;
1130 	struct resource		*ti_irq;
1131 	struct resource		*ti_res;
1132 	struct ifmedia		ifmedia;	/* media info */
1133 	uint8_t			ti_hwrev;	/* Tigon rev (1 or 2) */
1134 	uint8_t			ti_copper;	/* 1000baseT card */
1135 	uint8_t			ti_linkstat;	/* Link state */
1136 	struct ti_ring_data	*ti_rdata;	/* rings */
1137 	struct ti_chain_data	ti_cdata;	/* mbufs */
1138 #define ti_ev_prodidx		ti_rdata->ti_ev_prodidx_r
1139 #define ti_return_prodidx	ti_rdata->ti_return_prodidx_r
1140 #define ti_tx_considx		ti_rdata->ti_tx_considx_r
1141 	uint16_t		ti_tx_saved_considx;
1142 	uint16_t		ti_rx_saved_considx;
1143 	uint16_t		ti_ev_saved_considx;
1144 	uint16_t		ti_cmd_saved_prodidx;
1145 	uint16_t		ti_std;		/* current std ring head */
1146 	uint16_t		ti_mini;	/* current mini ring head */
1147 	uint16_t		ti_jumbo;	/* current jumo ring head */
1148 	SLIST_HEAD(__ti_mchead, ti_mc_entry)	ti_mc_listhead;
1149 	SLIST_HEAD(__ti_jfreehead, ti_jslot)	ti_jfree_listhead;
1150 	struct lwkt_serialize	ti_jslot_serializer;
1151 	uint32_t		ti_stat_ticks;
1152 	uint32_t		ti_rx_coal_ticks;
1153 	uint32_t		ti_tx_coal_ticks;
1154 	uint32_t		ti_rx_max_coal_bds;
1155 	uint32_t		ti_tx_max_coal_bds;
1156 	uint32_t		ti_tx_buf_ratio;
1157 	int			ti_if_flags;
1158 	int			ti_txcnt;
1159 };
1160 
1161 /*
1162  * Microchip Technology 24Cxx EEPROM control bytes
1163  */
1164 #define EEPROM_CTL_READ			0xA1	/* 0101 0001 */
1165 #define EEPROM_CTL_WRITE		0xA0	/* 0101 0000 */
1166 
1167 /*
1168  * Note that EEPROM_START leaves transmission enabled.
1169  */
1170 #define EEPROM_START							\
1171 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
1172 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */	\
1173 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
1174 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
1175 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
1176 
1177 /*
1178  * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
1179  * that no further data can be written to the EEPROM I/O pin.
1180  */
1181 #define EEPROM_STOP							\
1182 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */	\
1183 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */	\
1184 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */	\
1185 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */	\
1186 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */	\
1187 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */	\
1188 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */
1189