1 /* $OpenBSD: tireg.h,v 1.6 2022/01/09 05:42:42 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_tireg.h,v 1.12 2000/01/18 00:26:29 wpaul Exp $ 35 */ 36 37 /* 38 * Tigon register offsets. These are memory mapped registers 39 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 40 * Each register must be accessed using 32 bit operations. 41 * 42 * All registers are accessed through a 16K shared memory block. 43 * The first group of registers are actually copies of the PCI 44 * configuration space registers. 45 */ 46 47 #define TI_PCI_ID PCI_ID_REG /* PCI device/vendor ID */ 48 #define TI_PCI_CMDSTAT PCI_COMMAND_STATUS_REG 49 #define TI_PCI_CLASSCODE PCI_CLASS_REG 50 #define TI_PCI_BIST PCI_BHLC_REG 51 #define TI_PCI_LOMEM PCI_MAPS /* Shared memory base address */ 52 #define TI_PCI_SUBSYS PCI_SUBVEND_0 53 #define TI_PCI_ROMBASE 0x030 54 #define TI_PCI_INT PCI_INTLINE 55 56 /* 57 * Tigon configuration and control registers. 58 */ 59 #define TI_MISC_HOST_CTL 0x040 60 #define TI_MISC_LOCAL_CTL 0x044 61 #define TI_SEM_AB 0x048 /* Tigon 2 only */ 62 #define TI_MISC_CONF 0x050 /* Tigon 2 only */ 63 #define TI_TIMER_BITS 0x054 64 #define TI_TIMERREF 0x058 65 #define TI_PCI_STATE 0x05C 66 #define TI_MAIN_EVENT_A 0x060 67 #define TI_MAILBOX_EVENT_A 0x064 68 #define TI_WINBASE 0x068 69 #define TI_WINDATA 0x06C 70 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 71 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 72 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 73 #define TI_SERIAL 0x07C 74 75 /* 76 * Misc host control bits. 77 */ 78 #define TI_MHC_INTSTATE 0x00000001 79 #define TI_MHC_CLEARINT 0x00000002 80 #define TI_MHC_RESET 0x00000008 81 #define TI_MHC_BYTE_SWAP_ENB 0x00000010 82 #define TI_MHC_WORD_SWAP_ENB 0x00000020 83 #define TI_MHC_MASK_INTS 0x00000040 84 #define TI_MHC_CHIP_REV_MASK 0xF0000000 85 86 #define TI_MHC_BIGENDIAN_INIT \ 87 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 88 89 #define TI_MHC_LITTLEENDIAN_INIT \ 90 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 91 92 /* 93 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 94 * Rev 5 is also the Tigon 2, but is a broken version which was never 95 * used in any actual hardware, so we ignore it. 96 */ 97 #define TI_REV_TIGON_I 0x40000000 98 #define TI_REV_TIGON_II 0x60000000 99 100 /* 101 * Firmware revision that we want. 102 */ 103 #define TI_FIRMWARE_MAJOR 0xc 104 #define TI_FIRMWARE_MINOR 0x4 105 #define TI_FIRMWARE_FIX 0xd 106 107 /* 108 * Miscellaneous Local Control registers. 109 */ 110 #define TI_MLC_EE_WRITE_ENB 0x00000010 111 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 112 #define TI_MLC_LOCALADDR_21 0x00004000 113 #define TI_MLC_LOCALADDR_22 0x00008000 114 #define TI_MLC_SBUS_WRITEERR 0x00080000 115 #define TI_MLC_EE_CLK 0x00100000 116 #define TI_MLC_EE_TXEN 0x00200000 117 #define TI_MLC_EE_DOUT 0x00400000 118 #define TI_MLC_EE_DIN 0x00800000 119 120 /* Possible memory sizes. */ 121 #define TI_MLC_SRAM_BANK_DISA 0x00000000 122 #define TI_MLC_SRAM_BANK_1024K 0x00000100 123 #define TI_MLC_SRAM_BANK_512K 0x00000200 124 #define TI_MLC_SRAM_BANK_256K 0x00000300 125 126 /* 127 * Offset of MAC address inside EEPROM. 128 */ 129 #define TI_EE_MAC_OFFSET 0x8c 130 131 #define TI_DMA_ASSIST 0x11C 132 #define TI_CPU_STATE 0x140 133 #define TI_CPU_PROGRAM_COUNTER 0x144 134 #define TI_SRAM_ADDR 0x154 135 #define TI_SRAM_DATA 0x158 136 #define TI_GEN_0 0x180 137 #define TI_GEN_X 0x1FC 138 #define TI_MAC_TX_STATE 0x200 139 #define TI_MAC_RX_STATE 0x220 140 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 141 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 142 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 143 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 144 #define TI_GEN_B_0 0x280 /* Tigon 2 only */ 145 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 146 147 /* 148 * Misc config register. 149 */ 150 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 151 152 /* 153 * PCI state register. 154 */ 155 #define TI_PCISTATE_FORCE_RESET 0x00000001 156 #define TI_PCISTATE_PROVIDE_LEN 0x00000002 157 #define TI_PCISTATE_READ_MAXDMA 0x0000001C 158 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 159 #define TI_PCISTATE_MINDMA 0x0000FF00 160 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 161 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 162 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 163 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 164 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 165 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 166 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 167 #define TI_PCISTATE_READ_CMD 0x0F000000 168 #define TI_PCISTATE_WRITE_CMD 0xF0000000 169 170 #define TI_PCI_READMAX_4 0x04 171 #define TI_PCI_READMAX_16 0x08 172 #define TI_PCI_READMAX_32 0x0C 173 #define TI_PCI_READMAX_64 0x10 174 #define TI_PCI_READMAX_128 0x14 175 #define TI_PCI_READMAX_256 0x18 176 #define TI_PCI_READMAX_1024 0x1C 177 178 #define TI_PCI_WRITEMAX_4 0x20 179 #define TI_PCI_WRITEMAX_16 0x40 180 #define TI_PCI_WRITEMAX_32 0x60 181 #define TI_PCI_WRITEMAX_64 0x80 182 #define TI_PCI_WRITEMAX_128 0xA0 183 #define TI_PCI_WRITEMAX_256 0xC0 184 #define TI_PCI_WRITEMAX_1024 0xE0 185 186 #define TI_PCI_READ_CMD 0x06000000 187 #define TI_PCI_WRITE_CMD 0x70000000 188 189 /* 190 * DMA state register. 191 */ 192 #define TI_DMASTATE_ENABLE 0x00000001 193 #define TI_DMASTATE_PAUSE 0x00000002 194 195 /* 196 * CPU state register. 197 */ 198 #define TI_CPUSTATE_RESET 0x00000001 199 #define TI_CPUSTATE_STEP 0x00000002 200 #define TI_CPUSTATE_ROMFAIL 0x00000010 201 #define TI_CPUSTATE_HALT 0x00010000 202 /* 203 * MAC TX state register 204 */ 205 #define TI_TXSTATE_RESET 0x00000001 206 #define TI_TXSTATE_ENB 0x00000002 207 #define TI_TXSTATE_STOP 0x00000004 208 209 /* 210 * MAC RX state register 211 */ 212 #define TI_RXSTATE_RESET 0x00000001 213 #define TI_RXSTATE_ENB 0x00000002 214 #define TI_RXSTATE_STOP 0x00000004 215 216 /* 217 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 218 * split into 64 bit registers. Only the lower 32 bits of each mailbox 219 * are used. 220 */ 221 #define TI_MB_HOSTINTR_HI 0x500 222 #define TI_MB_HOSTINTR_LO 0x504 223 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 224 #define TI_MB_CMDPROD_IDX_HI 0x508 225 #define TI_MB_CMDPROD_IDX_LO 0x50C 226 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 227 #define TI_MB_SENDPROD_IDX_HI 0x510 228 #define TI_MB_SENDPROD_IDX_LO 0x514 229 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 230 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 231 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 232 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 233 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 234 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 235 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 236 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 237 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 238 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 239 #define TI_MB_RSVD 0x530 240 241 /* 242 * Tigon 2 general communication registers. These are 64 and 32 bit 243 * registers which are only valid after the firmware has been 244 * loaded and started. They actually exist in NIC memory but are 245 * mapped into the host memory via the shared memory region. 246 * 247 * The NIC internally maps these registers starting at address 0, 248 * so to determine the NIC address of any of these registers, we 249 * subtract 0x600 (the address of the first register). 250 */ 251 252 #define TI_GCR_BASE 0x600 253 #define TI_GCR_MACADDR 0x600 254 #define TI_GCR_PAR0 0x600 255 #define TI_GCR_PAR1 0x604 256 #define TI_GCR_GENINFO_HI 0x608 257 #define TI_GCR_GENINFO_LO 0x60C 258 #define TI_GCR_MCASTADDR 0x610 /* obsolete */ 259 #define TI_GCR_MAR0 0x610 /* obsolete */ 260 #define TI_GCR_MAR1 0x614 /* obsolete */ 261 #define TI_GCR_OPMODE 0x618 262 #define TI_GCR_DMA_READCFG 0x61C 263 #define TI_GCR_DMA_WRITECFG 0x620 264 #define TI_GCR_TX_BUFFER_RATIO 0x624 265 #define TI_GCR_EVENTCONS_IDX 0x628 266 #define TI_GCR_CMDCONS_IDX 0x62C 267 #define TI_GCR_TUNEPARMS 0x630 268 #define TI_GCR_RX_COAL_TICKS 0x630 269 #define TI_GCR_TX_COAL_TICKS 0x634 270 #define TI_GCR_STAT_TICKS 0x638 271 #define TI_GCR_TX_MAX_COAL_BD 0x63C 272 #define TI_GCR_RX_MAX_COAL_BD 0x640 273 #define TI_GCR_NIC_TRACING 0x644 274 #define TI_GCR_GLINK 0x648 275 #define TI_GCR_LINK 0x64C 276 #define TI_GCR_NICTRACE_PTR 0x650 277 #define TI_GCR_NICTRACE_START 0x654 278 #define TI_GCR_NICTRACE_LEN 0x658 279 #define TI_GCR_IFINDEX 0x65C 280 #define TI_GCR_IFMTU 0x660 281 #define TI_GCR_MASK_INTRS 0x664 282 #define TI_GCR_GLINK_STAT 0x668 283 #define TI_GCR_LINK_STAT 0x66C 284 #define TI_GCR_RXRETURNCONS_IDX 0x680 285 #define TI_GCR_CMDRING 0x700 286 287 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE) 288 289 /* 290 * Local memory window. The local memory window is a 2K shared 291 * memory region which can be used to access the NIC's internal 292 * SRAM. The window can be mapped to a given 2K region using 293 * the TI_WINDOW_BASE register. 294 */ 295 #define TI_WINDOW 0x800 296 #define TI_WINLEN 0x800 297 298 #define TI_TICKS_PER_SEC 1000000 299 300 /* 301 * Operation mode register. 302 */ 303 #define TI_OPMODE_BYTESWAP_BD 0x00000002 304 #define TI_OPMODE_WORDSWAP_BD 0x00000004 305 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implemented */ 306 #define TI_OPMODE_BYTESWAP_DATA 0x00000010 307 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040 308 #define TI_OPMODE_SBUS 0x00000100 309 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 310 #define TI_OPMODE_INCLUDE_CRC 0x00000400 311 #define TI_OPMODE_RX_BADFRAMES 0x00000800 312 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000 313 #define TI_OPMODE_NO_TX_INTRS 0x00002000 314 #define TI_OPMODE_NO_RX_INTRS 0x00004000 315 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implemented */ 316 317 #if BYTE_ORDER == BIG_ENDIAN 318 #define TI_DMA_SWAP_OPTIONS \ 319 TI_OPMODE_BYTESWAP_DATA| \ 320 TI_OPMODE_BYTESWAP_BD|TI_OPMODE_WORDSWAP_BD 321 #else 322 #define TI_DMA_SWAP_OPTIONS \ 323 TI_OPMODE_BYTESWAP_DATA 324 #endif 325 326 /* 327 * DMA configuration thresholds. 328 */ 329 #define TI_DMA_STATE_THRESH_16W 0x00000100 330 #define TI_DMA_STATE_THRESH_8W 0x00000080 331 #define TI_DMA_STATE_THRESH_4W 0x00000040 332 #define TI_DMA_STATE_THRESH_2W 0x00000020 333 #define TI_DMA_STATE_THRESH_1W 0x00000010 334 335 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008 336 337 /* 338 * Gigabit link status bits. 339 */ 340 #define TI_GLNK_SENSE_NO_BEG 0x00002000 341 #define TI_GLNK_LOOPBACK 0x00004000 342 #define TI_GLNK_PREF 0x00008000 343 #define TI_GLNK_1000MB 0x00040000 344 #define TI_GLNK_FULL_DUPLEX 0x00080000 345 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 346 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000 347 #define TI_GLNK_AUTONEGENB 0x20000000 348 #define TI_GLNK_ENB 0x40000000 349 350 /* 351 * Link status bits. 352 */ 353 #define TI_LNK_LOOPBACK 0x00004000 354 #define TI_LNK_PREF 0x00008000 355 #define TI_LNK_10MB 0x00010000 356 #define TI_LNK_100MB 0x00020000 357 #define TI_LNK_1000MB 0x00040000 358 #define TI_LNK_FULL_DUPLEX 0x00080000 359 #define TI_LNK_HALF_DUPLEX 0x00100000 360 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 361 #define TI_LNK_RX_FLOWCTL_Y 0x00800000 362 #define TI_LNK_AUTONEGENB 0x20000000 363 #define TI_LNK_ENB 0x40000000 364 365 /* 366 * Ring size constants. 367 */ 368 #define TI_EVENT_RING_CNT 256 369 #define TI_CMD_RING_CNT 64 370 #define TI_STD_RX_RING_CNT 512 371 #define TI_JUMBO_RX_RING_CNT 256 372 #define TI_MINI_RX_RING_CNT 1024 373 #define TI_RETURN_RING_CNT 2048 374 375 /* 376 * Possible TX ring sizes. 377 */ 378 #define TI_TX_RING_CNT_128 128 379 #define TI_TX_RING_BASE_128 0x3800 380 381 #define TI_TX_RING_CNT_256 256 382 #define TI_TX_RING_BASE_256 0x3000 383 384 #define TI_TX_RING_CNT_512 512 385 #define TI_TX_RING_BASE_512 0x2000 386 387 #define TI_TX_RING_CNT TI_TX_RING_CNT_512 388 #define TI_TX_RING_BASE TI_TX_RING_BASE_512 389 390 /* 391 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 392 * is limited to 2MB total, and in general I think most adapters have 393 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 394 * be safe we use the largest possible value (zeroing memory that 395 * isn't there doesn't hurt anything). 396 */ 397 #define TI_MEM_MAX 0x7FFFFF 398 399 /* 400 * Even on the alpha, pci addresses are 32-bit quantities 401 */ 402 403 typedef struct { 404 u_int32_t ti_addr_hi; 405 u_int32_t ti_addr_lo; 406 } ti_hostaddr; 407 #define TI_HOSTADDR(x) x.ti_addr_lo 408 409 /* 410 * Ring control block structure. The rules for the max_len field 411 * are as follows: 412 * 413 * For the send ring, max_len indicates the number of entries in the 414 * ring (128, 256 or 512). 415 * 416 * For the standard receive ring, max_len indicates the threshold 417 * used to decide when a frame should be put in the jumbo receive ring 418 * instead of the standard one. 419 * 420 * For the mini ring, max_len indicates the size of the buffers in the 421 * ring. This is the value used to decide when a frame is small enough 422 * to be placed in the mini ring. 423 * 424 * For the return receive ring, max_len indicates the number of entries 425 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 426 * 2048 for backwards compatibility). The value 1024 can only be used 427 * if the mini ring is disabled. 428 */ 429 struct ti_rcb { 430 ti_hostaddr ti_hostaddr; 431 #if BYTE_ORDER == BIG_ENDIAN 432 u_int16_t ti_max_len; 433 u_int16_t ti_flags; 434 #else 435 u_int16_t ti_flags; 436 u_int16_t ti_max_len; 437 #endif 438 u_int32_t ti_unused; 439 }; 440 441 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 442 #define TI_RCB_FLAG_IP_CKSUM 0x00000002 443 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 444 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 445 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 446 #define TI_RCB_FLAG_HOST_RING 0x00000040 447 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 448 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 449 #define TI_RCB_FLAG_RING_DISABLED 0x00000200 450 451 struct ti_producer { 452 u_int32_t ti_idx; 453 u_int32_t ti_unused; 454 }; 455 456 /* 457 * Tigon statistics counters. 458 */ 459 struct ti_stats { 460 /* 461 * MAC stats, taken from RFC 1643, ethernet-like MIB 462 */ 463 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 464 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 465 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 466 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 467 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 468 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 469 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 470 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 471 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 472 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 473 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 474 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 475 /* 476 * interface stats, taken from RFC 1213, MIB-II, interfaces group 477 */ 478 volatile u_int32_t ifIndex; /* 12 */ 479 volatile u_int32_t ifType; /* 13 */ 480 volatile u_int32_t ifMtu; /* 14 */ 481 volatile u_int32_t ifSpeed; /* 15 */ 482 volatile u_int32_t ifAdminStatus; /* 16 */ 483 #define IF_ADMIN_STATUS_UP 1 484 #define IF_ADMIN_STATUS_DOWN 2 485 #define IF_ADMIN_STATUS_TESTING 3 486 volatile u_int32_t ifOperStatus; /* 17 */ 487 #define IF_OPER_STATUS_UP 1 488 #define IF_OPER_STATUS_DOWN 2 489 #define IF_OPER_STATUS_TESTING 3 490 #define IF_OPER_STATUS_UNKNOWN 4 491 #define IF_OPER_STATUS_DORMANT 5 492 volatile u_int32_t ifLastChange; /* 18 */ 493 volatile u_int32_t ifInDiscards; /* 19 */ 494 volatile u_int32_t ifInErrors; /* 20 */ 495 volatile u_int32_t ifInUnknownProtos; /* 21 */ 496 volatile u_int32_t ifOutDiscards; /* 22 */ 497 volatile u_int32_t ifOutErrors; /* 23 */ 498 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 499 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 500 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 501 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 502 /* 503 * more interface stats, taken from RFC 1573, MIB-IIupdate, 504 * interfaces group 505 */ 506 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 507 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 508 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 509 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 510 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 511 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 512 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 513 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 514 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 515 volatile u_int32_t ifHighSpeed; /* 53 */ 516 volatile u_int32_t ifPromiscuousMode; /* 54 */ 517 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 518 /* 519 * Host Commands 520 */ 521 volatile u_int32_t nicCmdsHostState; /* 56 */ 522 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 523 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 524 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 525 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 526 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 527 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 528 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 529 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 530 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 531 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 532 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 533 volatile u_int32_t nicCmdsClearStats; /* 68 */ 534 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 535 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 536 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 537 volatile u_int32_t nicCmdsUnknown; /* 72 */ 538 /* 539 * NIC Events 540 */ 541 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 542 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 543 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 544 volatile u_int32_t nicEventsError; /* 76 */ 545 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 546 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 547 /* 548 * Ring manipulation 549 */ 550 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 551 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 552 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 553 /* 554 * Interrupts 555 */ 556 volatile u_int32_t nicInterrupts; /* 82 */ 557 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 558 /* 559 * BD Coalescing Thresholds 560 */ 561 volatile u_int32_t nicEventThresholdHit; /* 84 */ 562 volatile u_int32_t nicSendThresholdHit; /* 85 */ 563 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 564 /* 565 * DMA Attentions 566 */ 567 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 568 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 569 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 570 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 571 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 572 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 573 /* 574 * NIC Resources 575 */ 576 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 577 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 578 volatile u_int32_t nicEventRingFull; /* 95 */ 579 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 580 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 581 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 582 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 583 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 584 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 585 volatile u_int32_t nicSendBDs; /* current count 102 */ 586 volatile u_int32_t nicRecvBDs; /* current count 103 */ 587 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 588 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 589 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 590 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 591 volatile u_int32_t nicJumboSpillOver; /* 108 */ 592 volatile u_int32_t nicSbusHangCleared; /* 109 */ 593 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 594 /* 595 * Stats from MAC rx completion 596 */ 597 volatile u_int32_t nicMacRxLateColls; /* 111 */ 598 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 599 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 600 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 601 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 602 /* 603 * Stats from the mac_stats area 604 */ 605 volatile u_int32_t nicMacRxDropUla; /* 116 */ 606 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 607 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 608 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 609 volatile u_int32_t nicMacRxColls; /* 120 */ 610 /* 611 * MAC RX Attentions 612 */ 613 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 614 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 615 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 616 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 617 volatile u_int32_t nicMacReset; /* 125 */ 618 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 619 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 620 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 621 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 622 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 623 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 624 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 625 /* 626 * Stats from the mac_stats area 627 */ 628 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 629 /* 630 * MAC TX Attentions 631 */ 632 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 633 /* 634 * NIC Profile 635 */ 636 volatile u_int32_t nicProfile[32]; /* 135 */ 637 /* 638 * Pat to 1024 bytes. 639 */ 640 u_int32_t pad[75]; 641 }; 642 /* 643 * Tigon general information block. This resides in host memory 644 * and contains the status counters, ring control blocks and 645 * producer pointers. 646 */ 647 648 struct ti_gib { 649 struct ti_stats ti_stats; 650 struct ti_rcb ti_ev_rcb; 651 struct ti_rcb ti_cmd_rcb; 652 struct ti_rcb ti_tx_rcb; 653 struct ti_rcb ti_std_rx_rcb; 654 struct ti_rcb ti_jumbo_rx_rcb; 655 struct ti_rcb ti_mini_rx_rcb; 656 struct ti_rcb ti_return_rcb; 657 ti_hostaddr ti_ev_prodidx_ptr; 658 ti_hostaddr ti_return_prodidx_ptr; 659 ti_hostaddr ti_tx_considx_ptr; 660 ti_hostaddr ti_refresh_stats_ptr; 661 }; 662 663 /* 664 * Buffer descriptor structures. There are basically three types 665 * of structures: normal receive descriptors, extended receive 666 * descriptors and transmit descriptors. The extended receive 667 * descriptors are optionally used only for the jumbo receive ring. 668 */ 669 670 struct ti_rx_desc { 671 ti_hostaddr ti_addr; 672 #if BYTE_ORDER == BIG_ENDIAN 673 u_int16_t ti_idx; 674 u_int16_t ti_len; 675 #else 676 u_int16_t ti_len; 677 u_int16_t ti_idx; 678 #endif 679 #if BYTE_ORDER == BIG_ENDIAN 680 u_int16_t ti_type; 681 u_int16_t ti_flags; 682 #else 683 u_int16_t ti_flags; 684 u_int16_t ti_type; 685 #endif 686 #if BYTE_ORDER == BIG_ENDIAN 687 u_int16_t ti_ip_cksum; 688 u_int16_t ti_tcp_udp_cksum; 689 #else 690 u_int16_t ti_tcp_udp_cksum; 691 u_int16_t ti_ip_cksum; 692 #endif 693 #if BYTE_ORDER == BIG_ENDIAN 694 u_int16_t ti_error_flags; 695 u_int16_t ti_vlan_tag; 696 #else 697 u_int16_t ti_vlan_tag; 698 u_int16_t ti_error_flags; 699 #endif 700 u_int32_t ti_rsvd; 701 u_int32_t ti_opaque; 702 }; 703 704 struct ti_rx_desc_ext { 705 ti_hostaddr ti_addr1; 706 ti_hostaddr ti_addr2; 707 ti_hostaddr ti_addr3; 708 #if BYTE_ORDER == BIG_ENDIAN 709 u_int16_t ti_len1; 710 u_int16_t ti_len2; 711 #else 712 u_int16_t ti_len2; 713 u_int16_t ti_len1; 714 #endif 715 #if BYTE_ORDER == BIG_ENDIAN 716 u_int16_t ti_len3; 717 u_int16_t ti_rsvd0; 718 #else 719 u_int16_t ti_rsvd0; 720 u_int16_t ti_len3; 721 #endif 722 ti_hostaddr ti_addr0; 723 #if BYTE_ORDER == BIG_ENDIAN 724 u_int16_t ti_idx; 725 u_int16_t ti_len0; 726 #else 727 u_int16_t ti_len0; 728 u_int16_t ti_idx; 729 #endif 730 #if BYTE_ORDER == BIG_ENDIAN 731 u_int16_t ti_type; 732 u_int16_t ti_flags; 733 #else 734 u_int16_t ti_flags; 735 u_int16_t ti_type; 736 #endif 737 #if BYTE_ORDER == BIG_ENDIAN 738 u_int16_t ti_ip_cksum; 739 u_int16_t ti_tcp_udp_cksum; 740 #else 741 u_int16_t ti_tcp_udp_cksum; 742 u_int16_t ti_ip_cksum; 743 #endif 744 #if BYTE_ORDER == BIG_ENDIAN 745 u_int16_t ti_error_flags; 746 u_int16_t ti_vlan_tag; 747 #else 748 u_int16_t ti_vlan_tag; 749 u_int16_t ti_error_flags; 750 #endif 751 u_int32_t ti_rsvd1; 752 u_int32_t ti_opaque; 753 }; 754 755 /* 756 * Transmit descriptors are, mercifully, very small. 757 */ 758 struct ti_tx_desc { 759 ti_hostaddr ti_addr; 760 #if BYTE_ORDER == BIG_ENDIAN 761 u_int16_t ti_len; 762 u_int16_t ti_flags; 763 #else 764 u_int16_t ti_flags; 765 u_int16_t ti_len; 766 #endif 767 #if BYTE_ORDER == BIG_ENDIAN 768 u_int16_t ti_rsvd; 769 u_int16_t ti_vlan_tag; 770 #else 771 u_int16_t ti_vlan_tag; 772 u_int16_t ti_rsvd; 773 #endif 774 }; 775 776 /* 777 * NOTE! On the Alpha, we have an alignment constraint. 778 * The first thing in the packet is a 14-byte Ethernet header. 779 * This means that the packet is misaligned. To compensate, 780 * we actually offset the data 2 bytes into the cluster. This 781 * aligns the packet after the Ethernet header at a 32-bit 782 * boundary. 783 */ 784 785 #define TI_JUMBO_FRAMELEN 9018 786 #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 787 #define TI_PAGE_SIZE PAGE_SIZE 788 789 /* 790 * Buffer descriptor error flags. 791 */ 792 #define TI_BDERR_CRC 0x0001 793 #define TI_BDERR_COLLDETECT 0x0002 794 #define TI_BDERR_LINKLOST 0x0004 795 #define TI_BDERR_DECODE 0x0008 796 #define TI_BDERR_ODD_NIBBLES 0x0010 797 #define TI_BDERR_MAC_ABRT 0x0020 798 #define TI_BDERR_RUNT 0x0040 799 #define TI_BDERR_TRUNC 0x0080 800 #define TI_BDERR_GIANT 0x0100 801 802 /* 803 * Buffer descriptor flags. 804 */ 805 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 806 #define TI_BDFLAG_IP_CKSUM 0x0002 807 #define TI_BDFLAG_END 0x0004 808 #define TI_BDFLAG_MORE 0x0008 809 #define TI_BDFLAG_JUMBO_RING 0x0010 810 #define TI_BDFLAG_UCAST_PKT 0x0020 811 #define TI_BDFLAG_MCAST_PKT 0x0040 812 #define TI_BDFLAG_BCAST_PKT 0x0060 813 #define TI_BDFLAG_IP_FRAG 0x0080 814 #define TI_BDFLAG_IP_FRAG_END 0x0100 815 #define TI_BDFLAG_VLAN_TAG 0x0200 816 #define TI_BDFLAG_ERROR 0x0400 817 #define TI_BDFLAG_COAL_NOW 0x0800 818 #define TI_BDFLAG_MINI_RING 0x1000 819 820 /* 821 * Descriptor type flags. I think these only have meaning for 822 * the Tigon 1. I had to extract them from the sample driver source 823 * since they aren't in the manual. 824 */ 825 #define TI_BDTYPE_TYPE_NULL 0x0000 826 #define TI_BDTYPE_SEND_BD 0x0001 827 #define TI_BDTYPE_RECV_BD 0x0002 828 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003 829 #define TI_BDTYPE_RECV_BD_LAST 0x0004 830 #define TI_BDTYPE_SEND_DATA 0x0005 831 #define TI_BDTYPE_SEND_DATA_LAST 0x0006 832 #define TI_BDTYPE_RECV_DATA 0x0007 833 #define TI_BDTYPE_RECV_DATA_LAST 0x000b 834 #define TI_BDTYPE_EVENT_RUPT 0x000c 835 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d 836 #define TI_BDTYPE_ODD_START 0x000e 837 #define TI_BDTYPE_UPDATE_STATS 0x000f 838 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 839 #define TI_BDTYPE_EVENT_PROD 0x0011 840 #define TI_BDTYPE_TX_CONS 0x0012 841 #define TI_BDTYPE_RX_PROD 0x0013 842 #define TI_BDTYPE_REFRESH_STATS 0x0014 843 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 844 #define TI_BDTYPE_SEND_DATA_COAL 0x0016 845 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 846 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 847 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 848 849 /* 850 * Tigon command structure. 851 */ 852 struct ti_cmd_desc { 853 u_int32_t ti_cmdx; 854 }; 855 856 #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff) 857 #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff) 858 #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff) 859 860 #define TI_CMD_HOST_STATE 0x01 861 #define TI_CMD_CODE_STACK_UP 0x01 862 #define TI_CMD_CODE_STACK_DOWN 0x02 863 864 /* 865 * This command enables software address filtering. It's a workaround 866 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 867 */ 868 #define TI_CMD_FDR_FILTERING 0x02 869 #define TI_CMD_CODE_FILT_ENB 0x01 870 #define TI_CMD_CODE_FILT_DIS 0x02 871 872 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 873 #define TI_CMD_UPDATE_GENCOM 0x04 874 #define TI_CMD_RESET_JUMBO_RING 0x05 875 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06 876 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 877 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 878 879 #define TI_CMD_SET_PROMISC_MODE 0x0A 880 #define TI_CMD_CODE_PROMISC_ENB 0x01 881 #define TI_CMD_CODE_PROMISC_DIS 0x02 882 883 #define TI_CMD_LINK_NEGOTIATION 0x0B 884 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 885 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 886 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02 887 888 #define TI_CMD_SET_MAC_ADDR 0x0C 889 #define TI_CMD_CLR_PROFILE 0x0D 890 891 #define TI_CMD_SET_ALLMULTI 0x0E 892 #define TI_CMD_CODE_ALLMULTI_ENB 0x01 893 #define TI_CMD_CODE_ALLMULTI_DIS 0x02 894 895 #define TI_CMD_CLR_STATS 0x0F 896 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 897 #define TI_CMD_RFRSH_STATS 0x11 898 899 #define TI_CMD_EXT_ADD_MCAST 0x12 900 #define TI_CMD_EXT_DEL_MCAST 0x13 901 902 /* 903 * Utility macros to make issuing commands a little simpler. Assumes 904 * that 'sc' and 'cmd' are in local scope. 905 */ 906 #define TI_DO_CMD(x, y, z) \ 907 do { \ 908 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 909 ti_cmd(sc, &cmd); \ 910 } while (0) 911 912 #define TI_DO_CMD_EXT(x, y, z, v, w) \ 913 do { \ 914 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \ 915 ti_cmd_ext(sc, &cmd, v, w); \ 916 } while (0) 917 918 /* 919 * Other utility macros. 920 */ 921 #define TI_INC(x, y) \ 922 do { \ 923 (x) = (x + 1) % y; \ 924 } while (0) 925 926 #define TI_UPDATE_JUMBOPROD(x, y) \ 927 do { \ 928 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 929 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 930 } else { \ 931 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 932 } \ 933 } while (0) 934 935 #define TI_UPDATE_MINIPROD(x, y) \ 936 do { \ 937 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); \ 938 } while (0) 939 940 #define TI_UPDATE_STDPROD(x, y) \ 941 do { \ 942 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 943 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 944 } else { \ 945 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 946 } \ 947 } while (0) 948 949 950 /* 951 * Tigon event structure. 952 */ 953 struct ti_event_desc { 954 u_int32_t ti_eventx; 955 u_int32_t ti_rsvd; 956 }; 957 958 #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff) 959 #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff) 960 #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff) 961 962 /* 963 * Tigon events. 964 */ 965 #define TI_EV_FIRMWARE_UP 0x01 966 #define TI_EV_STATS_UPDATED 0x04 967 968 #define TI_EV_LINKSTAT_CHANGED 0x06 969 #define TI_EV_CODE_GIG_LINK_UP 0x01 970 #define TI_EV_CODE_LINK_DOWN 0x02 971 #define TI_EV_CODE_LINK_UP 0x03 972 973 #define TI_EV_ERROR 0x07 974 #define TI_EV_CODE_ERR_INVAL_CMD 0x01 975 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02 976 #define TI_EV_CODE_ERR_BADCFG 0x03 977 978 #define TI_EV_MCAST_UPDATED 0x08 979 #define TI_EV_CODE_MCAST_ADD 0x01 980 #define TI_EV_CODE_MCAST_DEL 0x02 981 982 #define TI_EV_RESET_JUMBO_RING 0x09 983 /* 984 * Register access macros. The Tigon always uses memory mapped register 985 * accesses and all registers must be accessed with 32 bit operations. 986 */ 987 988 #define CSR_WRITE_4(sc, reg, val) \ 989 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, (reg), (val)) 990 991 #define CSR_READ_4(sc, reg) \ 992 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, (reg)) 993 994 #define TI_SETBIT(sc, reg, x) \ 995 CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) | (x))) 996 #define TI_CLRBIT(sc, reg, x) \ 997 CSR_WRITE_4(sc, (reg), (CSR_READ_4(sc, (reg)) & ~(x))) 998 999 /* 1000 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1001 * values are tuneable. They control the actual amount of buffers 1002 * allocated for the standard, mini and jumbo receive rings. 1003 */ 1004 1005 #define TI_SSLOTS 256 1006 #define TI_MSLOTS 256 1007 #define TI_JSLOTS 384 1008 1009 #define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN) 1010 #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1011 (TI_JRAWLEN % sizeof(u_int64_t)))) 1012 #define TI_JPAGESZ PAGE_SIZE 1013 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1014 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1015 1016 struct ti_jslot { 1017 caddr_t ti_buf; 1018 int ti_inuse; 1019 }; 1020 1021 /* 1022 * Ring structures. Most of these reside in host memory and we tell 1023 * the NIC where they are via the ring control blocks. The exceptions 1024 * are the tx and command rings, which live in NIC memory and which 1025 * we access via the shared memory window. 1026 */ 1027 struct ti_ring_data { 1028 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1029 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1030 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1031 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1032 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1033 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1034 1035 /* 1036 * Make sure producer structures are aligned on 32-byte cache 1037 * line boundaries. 1038 */ 1039 struct ti_producer ti_ev_prodidx_r; 1040 u_int32_t ti_pad0[6]; 1041 struct ti_producer ti_return_prodidx_r; 1042 u_int32_t ti_pad1[6]; 1043 struct ti_producer ti_tx_considx_r; 1044 u_int32_t ti_pad2[6]; 1045 struct ti_gib ti_info; 1046 }; 1047 1048 #define TI_RING_DMA_ADDR(sc, offset) \ 1049 ((sc)->ti_ring_map->dm_segs[0].ds_addr + \ 1050 offsetof(struct ti_ring_data, offset)) 1051 1052 #define TI_RING_DMASYNC(sc, offset, op) \ 1053 bus_dmamap_sync((sc)->sc_dmatag, (sc)->ti_ring_map, \ 1054 offsetof(struct ti_ring_data, offset), \ 1055 sizeof(((struct ti_ring_data *)0)->offset), (op)) 1056 1057 /* 1058 * Number of DMA segments in a TxCB. Note that this is carefully 1059 * chosen to make the total struct size an even power of two. It's 1060 * critical that no TxCB be split across a page boundary since 1061 * no attempt is made to allocate physically contiguous memory. 1062 * 1063 */ 1064 #ifdef __LP64__ 1065 #define TI_NTXSEG 30 1066 #else 1067 #define TI_NTXSEG 31 1068 #endif 1069 1070 struct ti_txmap_entry { 1071 bus_dmamap_t dmamap; 1072 SLIST_ENTRY(ti_txmap_entry) link; 1073 }; 1074 1075 /* 1076 * Mbuf pointers. We need these to keep track of the virtual addresses 1077 * of our mbuf chains since we can only convert from physical to virtual, 1078 * not the other way around. 1079 */ 1080 struct ti_chain_data { 1081 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1082 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1083 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1084 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1085 1086 struct ti_txmap_entry *ti_tx_map[TI_TX_RING_CNT]; 1087 bus_dmamap_t ti_rx_std_map[TI_STD_RX_RING_CNT]; 1088 bus_dmamap_t ti_rx_jumbo_map[TI_JUMBO_RX_RING_CNT]; 1089 bus_dmamap_t ti_rx_mini_map[TI_MINI_RX_RING_CNT]; 1090 1091 /* Stick the jumbo mem management stuff here too. */ 1092 struct ti_jslot ti_jslots[TI_JSLOTS]; 1093 void *ti_jumbo_buf; 1094 }; 1095 1096 struct ti_type { 1097 u_int16_t ti_vid; 1098 u_int16_t ti_did; 1099 char *ti_name; 1100 }; 1101 1102 #define TI_HWREV_TIGON 0x01 1103 #define TI_HWREV_TIGON_II 0x02 1104 #define TI_TIMEOUT 1000 1105 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1106 1107 struct ti_mc_entry { 1108 struct ether_addr mc_addr; 1109 SLIST_ENTRY(ti_mc_entry) mc_entries; 1110 }; 1111 1112 struct ti_softc { 1113 struct device sc_dv; 1114 struct arpcom arpcom; /* interface info */ 1115 bus_space_handle_t ti_bhandle; 1116 bus_space_tag_t ti_btag; 1117 void * ti_intrhand; 1118 struct ifmedia ifmedia; /* media info */ 1119 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1120 u_int8_t ti_sbus; /* SBus card */ 1121 u_int8_t ti_copper; /* 1000baseTX card */ 1122 u_int8_t ti_linkstat; /* Link state */ 1123 bus_dma_tag_t sc_dmatag; 1124 struct ti_ring_data *ti_rdata; /* rings */ 1125 struct ti_chain_data ti_cdata; /* mbufs */ 1126 #define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1127 #define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1128 #define ti_tx_considx ti_rdata->ti_tx_considx_r 1129 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1130 bus_dmamap_t ti_ring_map; 1131 u_int16_t ti_tx_saved_prodidx; 1132 u_int16_t ti_tx_saved_considx; 1133 u_int16_t ti_rx_saved_considx; 1134 u_int16_t ti_ev_saved_considx; 1135 u_int16_t ti_cmd_saved_prodidx; 1136 u_int16_t ti_std; /* current std ring head */ 1137 u_int16_t ti_mini; /* current mini ring head */ 1138 u_int16_t ti_jumbo; /* current jumbo ring head */ 1139 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1140 SLIST_HEAD(__ti_txmaphead, ti_txmap_entry) ti_tx_map_listhead; 1141 u_int32_t ti_stat_ticks; 1142 u_int32_t ti_rx_coal_ticks; 1143 u_int32_t ti_tx_coal_ticks; 1144 u_int32_t ti_rx_max_coal_bds; 1145 u_int32_t ti_tx_max_coal_bds; 1146 u_int32_t ti_tx_buf_ratio; 1147 int ti_txcnt; 1148 }; 1149 1150 /* 1151 * Microchip Technology 24Cxx EEPROM control bytes 1152 */ 1153 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1154 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1155 1156 /* 1157 * Note that EEPROM_START leaves transmission enabled. 1158 */ 1159 #define EEPROM_START \ 1160 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1161 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1162 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1163 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1164 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1165 1166 /* 1167 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1168 * that no further data can be written to the EEPROM I/O pin. 1169 */ 1170 #define EEPROM_STOP \ 1171 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1172 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1173 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1174 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1175 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1176 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1177 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1178