xref: /qemu/include/hw/xen/interface/trace.h (revision 8ac98aed)
1 /* SPDX-License-Identifier: MIT */
2 /******************************************************************************
3  * include/public/trace.h
4  *
5  * Mark Williamson, (C) 2004 Intel Research Cambridge
6  * Copyright (C) 2005 Bin Ren
7  */
8 
9 #ifndef __XEN_PUBLIC_TRACE_H__
10 #define __XEN_PUBLIC_TRACE_H__
11 
12 #define TRACE_EXTRA_MAX    7
13 #define TRACE_EXTRA_SHIFT 28
14 
15 /* Trace classes */
16 #define TRC_CLS_SHIFT 16
17 #define TRC_GEN      0x0001f000    /* General trace            */
18 #define TRC_SCHED    0x0002f000    /* Xen Scheduler trace      */
19 #define TRC_DOM0OP   0x0004f000    /* Xen DOM0 operation trace */
20 #define TRC_HVM      0x0008f000    /* Xen HVM trace            */
21 #define TRC_MEM      0x0010f000    /* Xen memory trace         */
22 #define TRC_PV       0x0020f000    /* Xen PV traces            */
23 #define TRC_SHADOW   0x0040f000    /* Xen shadow tracing       */
24 #define TRC_HW       0x0080f000    /* Xen hardware-related traces */
25 #define TRC_GUEST    0x0800f000    /* Guest-generated traces   */
26 #define TRC_ALL      0x0ffff000
27 #define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff)
28 #define TRC_HD_CYCLE_FLAG (1UL<<31)
29 #define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) )
30 #define TRC_HD_EXTRA(x)    (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX)
31 
32 /* Trace subclasses */
33 #define TRC_SUBCLS_SHIFT 12
34 
35 /* trace subclasses for SVM */
36 #define TRC_HVM_ENTRYEXIT   0x00081000   /* VMENTRY and #VMEXIT       */
37 #define TRC_HVM_HANDLER     0x00082000   /* various HVM handlers      */
38 #define TRC_HVM_EMUL        0x00084000   /* emulated devices */
39 
40 #define TRC_SCHED_MIN       0x00021000   /* Just runstate changes */
41 #define TRC_SCHED_CLASS     0x00022000   /* Scheduler-specific    */
42 #define TRC_SCHED_VERBOSE   0x00028000   /* More inclusive scheduling */
43 
44 /*
45  * The highest 3 bits of the last 12 bits of TRC_SCHED_CLASS above are
46  * reserved for encoding what scheduler produced the information. The
47  * actual event is encoded in the last 9 bits.
48  *
49  * This means we have 8 scheduling IDs available (which means at most 8
50  * schedulers generating events) and, in each scheduler, up to 512
51  * different events.
52  */
53 #define TRC_SCHED_ID_BITS 3
54 #define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS)
55 #define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT)
56 #define TRC_SCHED_EVT_MASK (~(TRC_SCHED_ID_MASK))
57 
58 /* Per-scheduler IDs, to identify scheduler specific events */
59 #define TRC_SCHED_CSCHED   0
60 #define TRC_SCHED_CSCHED2  1
61 /* #define XEN_SCHEDULER_SEDF 2 (Removed) */
62 #define TRC_SCHED_ARINC653 3
63 #define TRC_SCHED_RTDS     4
64 #define TRC_SCHED_SNULL    5
65 
66 /* Per-scheduler tracing */
67 #define TRC_SCHED_CLASS_EVT(_c, _e) \
68   ( ( TRC_SCHED_CLASS | \
69       ((TRC_SCHED_##_c << TRC_SCHED_ID_SHIFT) & TRC_SCHED_ID_MASK) ) + \
70     (_e & TRC_SCHED_EVT_MASK) )
71 
72 /* Trace classes for DOM0 operations */
73 #define TRC_DOM0_DOMOPS     0x00041000   /* Domains manipulations */
74 
75 /* Trace classes for Hardware */
76 #define TRC_HW_PM           0x00801000   /* Power management traces */
77 #define TRC_HW_IRQ          0x00802000   /* Traces relating to the handling of IRQs */
78 
79 /* Trace events per class */
80 #define TRC_LOST_RECORDS        (TRC_GEN + 1)
81 #define TRC_TRACE_WRAP_BUFFER  (TRC_GEN + 2)
82 #define TRC_TRACE_CPU_CHANGE    (TRC_GEN + 3)
83 
84 #define TRC_SCHED_RUNSTATE_CHANGE   (TRC_SCHED_MIN + 1)
85 #define TRC_SCHED_CONTINUE_RUNNING  (TRC_SCHED_MIN + 2)
86 #define TRC_SCHED_DOM_ADD        (TRC_SCHED_VERBOSE +  1)
87 #define TRC_SCHED_DOM_REM        (TRC_SCHED_VERBOSE +  2)
88 #define TRC_SCHED_SLEEP          (TRC_SCHED_VERBOSE +  3)
89 #define TRC_SCHED_WAKE           (TRC_SCHED_VERBOSE +  4)
90 #define TRC_SCHED_YIELD          (TRC_SCHED_VERBOSE +  5)
91 #define TRC_SCHED_BLOCK          (TRC_SCHED_VERBOSE +  6)
92 #define TRC_SCHED_SHUTDOWN       (TRC_SCHED_VERBOSE +  7)
93 #define TRC_SCHED_CTL            (TRC_SCHED_VERBOSE +  8)
94 #define TRC_SCHED_ADJDOM         (TRC_SCHED_VERBOSE +  9)
95 #define TRC_SCHED_SWITCH         (TRC_SCHED_VERBOSE + 10)
96 #define TRC_SCHED_S_TIMER_FN     (TRC_SCHED_VERBOSE + 11)
97 #define TRC_SCHED_T_TIMER_FN     (TRC_SCHED_VERBOSE + 12)
98 #define TRC_SCHED_DOM_TIMER_FN   (TRC_SCHED_VERBOSE + 13)
99 #define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14)
100 #define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15)
101 #define TRC_SCHED_SHUTDOWN_CODE  (TRC_SCHED_VERBOSE + 16)
102 #define TRC_SCHED_SWITCH_INFCONT (TRC_SCHED_VERBOSE + 17)
103 
104 #define TRC_DOM0_DOM_ADD         (TRC_DOM0_DOMOPS + 1)
105 #define TRC_DOM0_DOM_REM         (TRC_DOM0_DOMOPS + 2)
106 
107 #define TRC_MEM_PAGE_GRANT_MAP      (TRC_MEM + 1)
108 #define TRC_MEM_PAGE_GRANT_UNMAP    (TRC_MEM + 2)
109 #define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3)
110 #define TRC_MEM_SET_P2M_ENTRY       (TRC_MEM + 4)
111 #define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5)
112 #define TRC_MEM_POD_POPULATE        (TRC_MEM + 16)
113 #define TRC_MEM_POD_ZERO_RECLAIM    (TRC_MEM + 17)
114 #define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18)
115 
116 #define TRC_PV_ENTRY   0x00201000 /* Hypervisor entry points for PV guests. */
117 #define TRC_PV_SUBCALL 0x00202000 /* Sub-call in a multicall hypercall */
118 
119 #define TRC_PV_HYPERCALL             (TRC_PV_ENTRY +  1)
120 #define TRC_PV_TRAP                  (TRC_PV_ENTRY +  3)
121 #define TRC_PV_PAGE_FAULT            (TRC_PV_ENTRY +  4)
122 #define TRC_PV_FORCED_INVALID_OP     (TRC_PV_ENTRY +  5)
123 #define TRC_PV_EMULATE_PRIVOP        (TRC_PV_ENTRY +  6)
124 #define TRC_PV_EMULATE_4GB           (TRC_PV_ENTRY +  7)
125 #define TRC_PV_MATH_STATE_RESTORE    (TRC_PV_ENTRY +  8)
126 #define TRC_PV_PAGING_FIXUP          (TRC_PV_ENTRY +  9)
127 #define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10)
128 #define TRC_PV_PTWR_EMULATION        (TRC_PV_ENTRY + 11)
129 #define TRC_PV_PTWR_EMULATION_PAE    (TRC_PV_ENTRY + 12)
130 #define TRC_PV_HYPERCALL_V2          (TRC_PV_ENTRY + 13)
131 #define TRC_PV_HYPERCALL_SUBCALL     (TRC_PV_SUBCALL + 14)
132 
133 /*
134  * TRC_PV_HYPERCALL_V2 format
135  *
136  * Only some of the hypercall argument are recorded. Bit fields A0 to
137  * A5 in the first extra word are set if the argument is present and
138  * the arguments themselves are packed sequentially in the following
139  * words.
140  *
141  * The TRC_64_FLAG bit is not set for these events (even if there are
142  * 64-bit arguments in the record).
143  *
144  * Word
145  * 0    bit 31 30|29 28|27 26|25 24|23 22|21 20|19 ... 0
146  *          A5   |A4   |A3   |A2   |A1   |A0   |Hypercall op
147  * 1    First 32 bit (or low word of first 64 bit) arg in record
148  * 2    Second 32 bit (or high word of first 64 bit) arg in record
149  * ...
150  *
151  * A0-A5 bitfield values:
152  *
153  *   00b  Argument not present
154  *   01b  32-bit argument present
155  *   10b  64-bit argument present
156  *   11b  Reserved
157  */
158 #define TRC_PV_HYPERCALL_V2_ARG_32(i) (0x1 << (20 + 2*(i)))
159 #define TRC_PV_HYPERCALL_V2_ARG_64(i) (0x2 << (20 + 2*(i)))
160 #define TRC_PV_HYPERCALL_V2_ARG_MASK  (0xfff00000)
161 
162 #define TRC_SHADOW_NOT_SHADOW                 (TRC_SHADOW +  1)
163 #define TRC_SHADOW_FAST_PROPAGATE             (TRC_SHADOW +  2)
164 #define TRC_SHADOW_FAST_MMIO                  (TRC_SHADOW +  3)
165 #define TRC_SHADOW_FALSE_FAST_PATH            (TRC_SHADOW +  4)
166 #define TRC_SHADOW_MMIO                       (TRC_SHADOW +  5)
167 #define TRC_SHADOW_FIXUP                      (TRC_SHADOW +  6)
168 #define TRC_SHADOW_DOMF_DYING                 (TRC_SHADOW +  7)
169 #define TRC_SHADOW_EMULATE                    (TRC_SHADOW +  8)
170 #define TRC_SHADOW_EMULATE_UNSHADOW_USER      (TRC_SHADOW +  9)
171 #define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ    (TRC_SHADOW + 10)
172 #define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11)
173 #define TRC_SHADOW_WRMAP_BF                   (TRC_SHADOW + 12)
174 #define TRC_SHADOW_PREALLOC_UNPIN             (TRC_SHADOW + 13)
175 #define TRC_SHADOW_RESYNC_FULL                (TRC_SHADOW + 14)
176 #define TRC_SHADOW_RESYNC_ONLY                (TRC_SHADOW + 15)
177 
178 /* trace events per subclass */
179 #define TRC_HVM_NESTEDFLAG      (0x400)
180 #define TRC_HVM_VMENTRY         (TRC_HVM_ENTRYEXIT + 0x01)
181 #define TRC_HVM_VMEXIT          (TRC_HVM_ENTRYEXIT + 0x02)
182 #define TRC_HVM_VMEXIT64        (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02)
183 #define TRC_HVM_PF_XEN          (TRC_HVM_HANDLER + 0x01)
184 #define TRC_HVM_PF_XEN64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01)
185 #define TRC_HVM_PF_INJECT       (TRC_HVM_HANDLER + 0x02)
186 #define TRC_HVM_PF_INJECT64     (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02)
187 #define TRC_HVM_INJ_EXC         (TRC_HVM_HANDLER + 0x03)
188 #define TRC_HVM_INJ_VIRQ        (TRC_HVM_HANDLER + 0x04)
189 #define TRC_HVM_REINJ_VIRQ      (TRC_HVM_HANDLER + 0x05)
190 #define TRC_HVM_IO_READ         (TRC_HVM_HANDLER + 0x06)
191 #define TRC_HVM_IO_WRITE        (TRC_HVM_HANDLER + 0x07)
192 #define TRC_HVM_CR_READ         (TRC_HVM_HANDLER + 0x08)
193 #define TRC_HVM_CR_READ64       (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08)
194 #define TRC_HVM_CR_WRITE        (TRC_HVM_HANDLER + 0x09)
195 #define TRC_HVM_CR_WRITE64      (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09)
196 #define TRC_HVM_DR_READ         (TRC_HVM_HANDLER + 0x0A)
197 #define TRC_HVM_DR_WRITE        (TRC_HVM_HANDLER + 0x0B)
198 #define TRC_HVM_MSR_READ        (TRC_HVM_HANDLER + 0x0C)
199 #define TRC_HVM_MSR_WRITE       (TRC_HVM_HANDLER + 0x0D)
200 #define TRC_HVM_CPUID           (TRC_HVM_HANDLER + 0x0E)
201 #define TRC_HVM_INTR            (TRC_HVM_HANDLER + 0x0F)
202 #define TRC_HVM_NMI             (TRC_HVM_HANDLER + 0x10)
203 #define TRC_HVM_SMI             (TRC_HVM_HANDLER + 0x11)
204 #define TRC_HVM_VMMCALL         (TRC_HVM_HANDLER + 0x12)
205 #define TRC_HVM_HLT             (TRC_HVM_HANDLER + 0x13)
206 #define TRC_HVM_INVLPG          (TRC_HVM_HANDLER + 0x14)
207 #define TRC_HVM_INVLPG64        (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14)
208 #define TRC_HVM_MCE             (TRC_HVM_HANDLER + 0x15)
209 #define TRC_HVM_IOPORT_READ     (TRC_HVM_HANDLER + 0x16)
210 #define TRC_HVM_IOMEM_READ      (TRC_HVM_HANDLER + 0x17)
211 #define TRC_HVM_CLTS            (TRC_HVM_HANDLER + 0x18)
212 #define TRC_HVM_LMSW            (TRC_HVM_HANDLER + 0x19)
213 #define TRC_HVM_LMSW64          (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19)
214 #define TRC_HVM_RDTSC           (TRC_HVM_HANDLER + 0x1a)
215 #define TRC_HVM_INTR_WINDOW     (TRC_HVM_HANDLER + 0x20)
216 #define TRC_HVM_NPF             (TRC_HVM_HANDLER + 0x21)
217 #define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22)
218 #define TRC_HVM_TRAP             (TRC_HVM_HANDLER + 0x23)
219 #define TRC_HVM_TRAP_DEBUG       (TRC_HVM_HANDLER + 0x24)
220 #define TRC_HVM_VLAPIC           (TRC_HVM_HANDLER + 0x25)
221 #define TRC_HVM_XCR_READ64      (TRC_HVM_HANDLER + TRC_64_FLAG + 0x26)
222 #define TRC_HVM_XCR_WRITE64     (TRC_HVM_HANDLER + TRC_64_FLAG + 0x27)
223 
224 #define TRC_HVM_IOPORT_WRITE    (TRC_HVM_HANDLER + 0x216)
225 #define TRC_HVM_IOMEM_WRITE     (TRC_HVM_HANDLER + 0x217)
226 
227 /* Trace events for emulated devices */
228 #define TRC_HVM_EMUL_HPET_START_TIMER  (TRC_HVM_EMUL + 0x1)
229 #define TRC_HVM_EMUL_PIT_START_TIMER   (TRC_HVM_EMUL + 0x2)
230 #define TRC_HVM_EMUL_RTC_START_TIMER   (TRC_HVM_EMUL + 0x3)
231 #define TRC_HVM_EMUL_LAPIC_START_TIMER (TRC_HVM_EMUL + 0x4)
232 #define TRC_HVM_EMUL_HPET_STOP_TIMER   (TRC_HVM_EMUL + 0x5)
233 #define TRC_HVM_EMUL_PIT_STOP_TIMER    (TRC_HVM_EMUL + 0x6)
234 #define TRC_HVM_EMUL_RTC_STOP_TIMER    (TRC_HVM_EMUL + 0x7)
235 #define TRC_HVM_EMUL_LAPIC_STOP_TIMER  (TRC_HVM_EMUL + 0x8)
236 #define TRC_HVM_EMUL_PIT_TIMER_CB      (TRC_HVM_EMUL + 0x9)
237 #define TRC_HVM_EMUL_LAPIC_TIMER_CB    (TRC_HVM_EMUL + 0xA)
238 #define TRC_HVM_EMUL_PIC_INT_OUTPUT    (TRC_HVM_EMUL + 0xB)
239 #define TRC_HVM_EMUL_PIC_KICK          (TRC_HVM_EMUL + 0xC)
240 #define TRC_HVM_EMUL_PIC_INTACK        (TRC_HVM_EMUL + 0xD)
241 #define TRC_HVM_EMUL_PIC_POSEDGE       (TRC_HVM_EMUL + 0xE)
242 #define TRC_HVM_EMUL_PIC_NEGEDGE       (TRC_HVM_EMUL + 0xF)
243 #define TRC_HVM_EMUL_PIC_PEND_IRQ_CALL (TRC_HVM_EMUL + 0x10)
244 #define TRC_HVM_EMUL_LAPIC_PIC_INTR    (TRC_HVM_EMUL + 0x11)
245 
246 /* trace events for per class */
247 #define TRC_PM_FREQ_CHANGE      (TRC_HW_PM + 0x01)
248 #define TRC_PM_IDLE_ENTRY       (TRC_HW_PM + 0x02)
249 #define TRC_PM_IDLE_EXIT        (TRC_HW_PM + 0x03)
250 
251 /* Trace events for IRQs */
252 #define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1)
253 #define TRC_HW_IRQ_MOVE_CLEANUP       (TRC_HW_IRQ + 0x2)
254 #define TRC_HW_IRQ_BIND_VECTOR        (TRC_HW_IRQ + 0x3)
255 #define TRC_HW_IRQ_CLEAR_VECTOR       (TRC_HW_IRQ + 0x4)
256 #define TRC_HW_IRQ_MOVE_FINISH        (TRC_HW_IRQ + 0x5)
257 #define TRC_HW_IRQ_ASSIGN_VECTOR      (TRC_HW_IRQ + 0x6)
258 #define TRC_HW_IRQ_UNMAPPED_VECTOR    (TRC_HW_IRQ + 0x7)
259 #define TRC_HW_IRQ_HANDLED            (TRC_HW_IRQ + 0x8)
260 
261 /*
262  * Event Flags
263  *
264  * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple
265  * record formats.  These event flags distinguish between the
266  * different formats.
267  */
268 #define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
269 
270 /* This structure represents a single trace buffer record. */
271 struct t_rec {
272     uint32_t event:28;
273     uint32_t extra_u32:3;         /* # entries in trailing extra_u32[] array */
274     uint32_t cycles_included:1;   /* u.cycles or u.no_cycles? */
275     union {
276         struct {
277             uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */
278             uint32_t extra_u32[7];         /* event data items */
279         } cycles;
280         struct {
281             uint32_t extra_u32[7];         /* event data items */
282         } nocycles;
283     } u;
284 };
285 
286 /*
287  * This structure contains the metadata for a single trace buffer.  The head
288  * field, indexes into an array of struct t_rec's.
289  */
290 struct t_buf {
291     /* Assume the data buffer size is X.  X is generally not a power of 2.
292      * CONS and PROD are incremented modulo (2*X):
293      *     0 <= cons < 2*X
294      *     0 <= prod < 2*X
295      * This is done because addition modulo X breaks at 2^32 when X is not a
296      * power of 2:
297      *     (((2^32 - 1) % X) + 1) % X != (2^32) % X
298      */
299     uint32_t cons;   /* Offset of next item to be consumed by control tools. */
300     uint32_t prod;   /* Offset of next item to be produced by Xen.           */
301     /*  Records follow immediately after the meta-data header.    */
302 };
303 
304 /* Structure used to pass MFNs to the trace buffers back to trace consumers.
305  * Offset is an offset into the mapped structure where the mfn list will be held.
306  * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]).
307  */
308 struct t_info {
309     uint16_t tbuf_size; /* Size in pages of each trace buffer */
310     uint16_t mfn_offset[];  /* Offset within t_info structure of the page list per cpu */
311     /* MFN lists immediately after the header */
312 };
313 
314 #endif /* __XEN_PUBLIC_TRACE_H__ */
315 
316 /*
317  * Local variables:
318  * mode: C
319  * c-file-style: "BSD"
320  * c-basic-offset: 4
321  * tab-width: 4
322  * indent-tabs-mode: nil
323  * End:
324  */
325