| /dports/databases/postgresql13-pltcl/postgresql-13.5/src/backend/storage/ipc/ |
| H A D | signalfuncs.c | 182 (errcode(ERRCODE_INSUFFICIENT_PRIVILEGE), in limitOccupancy()
191 (errmsg("rotation not possible because log collection not active"))); in limitOccupancy()
202 * Permission checking for this function is managed through the normal
208 if (!Logging_collector) in addKernargSegmentPtr()
209 { in addKernargSegmentPtr()
215 SendPostmasterSignal(PMSIGNAL_ROTATE_LOGFILE); in addKernargSegmentPtr()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 187 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
195 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
202 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
209 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr()
217 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
224 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
231 unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) { in addImplicitBufferPtr()
257 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 188 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
196 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
203 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
210 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr()
218 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
225 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
269 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
347 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
418 const TargetRegisterInfo &TRI) { in regToString()
429 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 188 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
196 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
203 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
210 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr()
218 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
225 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
269 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
347 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
418 const TargetRegisterInfo &TRI) { in regToString()
429 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 188 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
196 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
203 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
210 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr()
218 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
225 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
269 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
347 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
418 const TargetRegisterInfo &TRI) { in regToString()
429 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
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| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 190 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
198 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
205 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
212 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr()
220 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
227 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
271 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
349 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
420 const TargetRegisterInfo &TRI) { in regToString()
431 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 213 YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX); in addPrivateSegmentBuffer()
223 YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX); in addDispatchPtr()
224 YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY);
244 FP32OutputDenormals = Mode.FP32OutputDenormals; in addQueuePtr()
245 FP64FP16InputDenormals = Mode.FP64FP16InputDenormals; in addQueuePtr()
252 FP32InputDenormals == Other.FP32InputDenormals && in addQueuePtr()
260 static void mapping(IO &YamlIO, SIMode &Mode) { in addImplicitBufferPtr()
296 const TargetRegisterInfo &TRI,
370 bool ReturnsVoid = true;
408 bool WorkGroupIDZ : 1;
[all …]
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| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 214 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
222 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
229 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
244 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
296 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
369 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
408 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
470 const SIRegisterInfo &TRI) { in getScavengeFI()
515 const TargetRegisterInfo &TRI) { in regToString()
526 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 214 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
222 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
229 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
244 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
296 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
369 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
408 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
470 const SIRegisterInfo &TRI) { in getScavengeFI()
515 const TargetRegisterInfo &TRI) { in regToString()
526 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 209 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
217 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
224 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
239 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
291 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
364 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
403 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
471 const SIRegisterInfo &TRI) { in getScavengeFI()
516 const TargetRegisterInfo &TRI) { in regToString()
527 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 214 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
222 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
229 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
244 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
296 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
369 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
408 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
470 const SIRegisterInfo &TRI) { in getScavengeFI()
515 const TargetRegisterInfo &TRI) { in regToString()
526 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 214 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
222 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
229 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
244 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
296 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
369 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
408 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
470 const SIRegisterInfo &TRI) { in getScavengeFI()
515 const TargetRegisterInfo &TRI) { in regToString()
526 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 205 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
213 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
220 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
235 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
242 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
287 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
354 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
393 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
485 const TargetRegisterInfo &TRI) { in regToString()
496 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 201 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
209 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
216 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
231 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
238 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
283 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
350 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
387 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
479 const TargetRegisterInfo &TRI) { in regToString()
490 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 191 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
273 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
340 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
379 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
471 const TargetRegisterInfo &TRI) { in regToString()
482 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
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| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 201 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
209 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
216 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
231 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
238 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
283 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
350 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
387 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
479 const TargetRegisterInfo &TRI) { in regToString()
490 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
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| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 191 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer()
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr()
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr()
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID()
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit()
273 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateSGPRSpillToVGPR() local
340 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in reserveVGPRforSGPRSpills() local
379 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
471 const TargetRegisterInfo &TRI) { in regToString()
482 const TargetRegisterInfo &TRI) { in convertArgumentInfo()
[all …]
|
| /dports/cad/kicad-devel/kicad-a17a58203b33e08b966075833b177dad5740c236/libs/kimath/include/geometry/ |
| H A D | shape_poly_set.h | 75 struct TRI : public SHAPE_LINE_CHAIN_BASE struct
78 SHAPE_LINE_CHAIN_BASE( SH_POLY_SET_TRIANGLE ), in SHAPE_LINE_CHAIN_BASE() argument
88 virtual void Move( const VECTOR2I& aVector ) override {}; in Move()
90 virtual bool IsSolid() const override { return true; } in IsSolid()
92 virtual bool IsClosed() const override { return true; } in IsClosed()
96 virtual const VECTOR2I GetPoint( int aIndex ) const override in GetPoint()
125 TRIANGULATED_POLYGON* parent; argument
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| /dports/devel/llvm90/llvm-9.0.1.src/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/devel/llvm80/llvm-8.0.1.src/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 32 const TargetRegisterInfo *TRI = nullptr; variable
40 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
51 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
75 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/devel/llvm70/llvm-7.0.1.src/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 32 const TargetRegisterInfo *TRI = nullptr; variable
40 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
51 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
75 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
73 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init()
|
| /dports/devel/llvm10/llvm-10.0.1.src/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed()
74 void init(const TargetRegisterInfo &TRI) { in init()
|