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/qemu/target/riscv/
H A Dvector_helper.c1091 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ argument
5026 #define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \ argument