1 /*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30 #ifndef RADEON_MODE_H
31 #define RADEON_MODE_H
32
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_encoder.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_modeset_helper_vtables.h>
38 #include <linux/i2c.h>
39 #include <linux/i2c-algo-bit.h>
40
41 struct edid;
42 struct drm_edid;
43 struct radeon_bo;
44 struct radeon_device;
45
46 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
47 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
48 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
49
50 #define RADEON_MAX_HPD_PINS 7
51 #define RADEON_MAX_CRTCS 6
52 #define RADEON_MAX_AFMT_BLOCKS 7
53
54 enum radeon_rmx_type {
55 RMX_OFF,
56 RMX_FULL,
57 RMX_CENTER,
58 RMX_ASPECT
59 };
60
61 enum radeon_tv_std {
62 TV_STD_NTSC,
63 TV_STD_PAL,
64 TV_STD_PAL_M,
65 TV_STD_PAL_60,
66 TV_STD_NTSC_J,
67 TV_STD_SCART_PAL,
68 TV_STD_SECAM,
69 TV_STD_PAL_CN,
70 TV_STD_PAL_N,
71 };
72
73 enum radeon_underscan_type {
74 UNDERSCAN_OFF,
75 UNDERSCAN_ON,
76 UNDERSCAN_AUTO,
77 };
78
79 enum radeon_hpd_id {
80 RADEON_HPD_1 = 0,
81 RADEON_HPD_2,
82 RADEON_HPD_3,
83 RADEON_HPD_4,
84 RADEON_HPD_5,
85 RADEON_HPD_6,
86 RADEON_HPD_NONE = 0xff,
87 };
88
89 enum radeon_output_csc {
90 RADEON_OUTPUT_CSC_BYPASS = 0,
91 RADEON_OUTPUT_CSC_TVRGB = 1,
92 RADEON_OUTPUT_CSC_YCBCR601 = 2,
93 RADEON_OUTPUT_CSC_YCBCR709 = 3,
94 };
95
96 #define RADEON_MAX_I2C_BUS 16
97
98 /* radeon gpio-based i2c
99 * 1. "mask" reg and bits
100 * grabs the gpio pins for software use
101 * 0=not held 1=held
102 * 2. "a" reg and bits
103 * output pin value
104 * 0=low 1=high
105 * 3. "en" reg and bits
106 * sets the pin direction
107 * 0=input 1=output
108 * 4. "y" reg and bits
109 * input pin value
110 * 0=low 1=high
111 */
112 struct radeon_i2c_bus_rec {
113 bool valid;
114 /* id used by atom */
115 uint8_t i2c_id;
116 /* id used by atom */
117 enum radeon_hpd_id hpd;
118 /* can be used with hw i2c engine */
119 bool hw_capable;
120 /* uses multi-media i2c engine */
121 bool mm_i2c;
122 /* regs and bits */
123 uint32_t mask_clk_reg;
124 uint32_t mask_data_reg;
125 uint32_t a_clk_reg;
126 uint32_t a_data_reg;
127 uint32_t en_clk_reg;
128 uint32_t en_data_reg;
129 uint32_t y_clk_reg;
130 uint32_t y_data_reg;
131 uint32_t mask_clk_mask;
132 uint32_t mask_data_mask;
133 uint32_t a_clk_mask;
134 uint32_t a_data_mask;
135 uint32_t en_clk_mask;
136 uint32_t en_data_mask;
137 uint32_t y_clk_mask;
138 uint32_t y_data_mask;
139 };
140
141 struct radeon_tmds_pll {
142 uint32_t freq;
143 uint32_t value;
144 };
145
146 #define RADEON_MAX_BIOS_CONNECTOR 16
147
148 /* pll flags */
149 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
150 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
151 #define RADEON_PLL_USE_REF_DIV (1 << 2)
152 #define RADEON_PLL_LEGACY (1 << 3)
153 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
154 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
155 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
156 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
157 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
159 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
161 #define RADEON_PLL_USE_POST_DIV (1 << 12)
162 #define RADEON_PLL_IS_LCD (1 << 13)
163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
164
165 struct radeon_pll {
166 /* reference frequency */
167 uint32_t reference_freq;
168
169 /* fixed dividers */
170 uint32_t reference_div;
171 uint32_t post_div;
172
173 /* pll in/out limits */
174 uint32_t pll_in_min;
175 uint32_t pll_in_max;
176 uint32_t pll_out_min;
177 uint32_t pll_out_max;
178 uint32_t lcd_pll_out_min;
179 uint32_t lcd_pll_out_max;
180 uint32_t best_vco;
181
182 /* divider limits */
183 uint32_t min_ref_div;
184 uint32_t max_ref_div;
185 uint32_t min_post_div;
186 uint32_t max_post_div;
187 uint32_t min_feedback_div;
188 uint32_t max_feedback_div;
189 uint32_t min_frac_feedback_div;
190 uint32_t max_frac_feedback_div;
191
192 /* flags for the current clock */
193 uint32_t flags;
194
195 /* pll id */
196 uint32_t id;
197 };
198
199 struct radeon_i2c_chan {
200 struct i2c_adapter adapter;
201 struct drm_device *dev;
202 struct i2c_algo_bit_data bit;
203 struct radeon_i2c_bus_rec rec;
204 struct drm_dp_aux aux;
205 bool has_aux;
206 struct mutex mutex;
207 };
208
209 /* mostly for macs, but really any system without connector tables */
210 enum radeon_connector_table {
211 CT_NONE = 0,
212 CT_GENERIC,
213 CT_IBOOK,
214 CT_POWERBOOK_EXTERNAL,
215 CT_POWERBOOK_INTERNAL,
216 CT_POWERBOOK_VGA,
217 CT_MINI_EXTERNAL,
218 CT_MINI_INTERNAL,
219 CT_IMAC_G5_ISIGHT,
220 CT_EMAC,
221 CT_RN50_POWER,
222 CT_MAC_X800,
223 CT_MAC_G5_9600,
224 CT_SAM440EP,
225 CT_MAC_G4_SILVER
226 };
227
228 enum radeon_dvo_chip {
229 DVO_SIL164,
230 DVO_SIL1178,
231 };
232
233 struct radeon_afmt {
234 bool enabled;
235 int offset;
236 bool last_buffer_filled_status;
237 int id;
238 };
239
240 struct radeon_mode_info {
241 struct atom_context *atom_context;
242 struct card_info *atom_card_info;
243 enum radeon_connector_table connector_table;
244 bool mode_config_initialized;
245 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
246 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
247 /* DVI-I properties */
248 struct drm_property *coherent_mode_property;
249 /* DAC enable load detect */
250 struct drm_property *load_detect_property;
251 /* TV standard */
252 struct drm_property *tv_std_property;
253 /* legacy TMDS PLL detect */
254 struct drm_property *tmds_pll_property;
255 /* underscan */
256 struct drm_property *underscan_property;
257 struct drm_property *underscan_hborder_property;
258 struct drm_property *underscan_vborder_property;
259 /* audio */
260 struct drm_property *audio_property;
261 /* FMT dithering */
262 struct drm_property *dither_property;
263 /* Output CSC */
264 struct drm_property *output_csc_property;
265 /* hardcoded DFP edid from BIOS */
266 const struct drm_edid *bios_hardcoded_edid;
267
268 /* firmware flags */
269 u16 firmware_flags;
270 /* pointer to backlight encoder */
271 struct radeon_encoder *bl_encoder;
272
273 /* bitmask for active encoder frontends */
274 uint32_t active_encoders;
275 };
276
277 #define RADEON_MAX_BL_LEVEL 0xFF
278
279 struct radeon_backlight_privdata {
280 struct radeon_encoder *encoder;
281 uint8_t negative;
282 };
283
284 #define MAX_H_CODE_TIMING_LEN 32
285 #define MAX_V_CODE_TIMING_LEN 32
286
287 /* need to store these as reading
288 back code tables is excessive */
289 struct radeon_tv_regs {
290 uint32_t tv_uv_adr;
291 uint32_t timing_cntl;
292 uint32_t hrestart;
293 uint32_t vrestart;
294 uint32_t frestart;
295 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
296 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
297 };
298
299 struct radeon_atom_ss {
300 uint16_t percentage;
301 uint16_t percentage_divider;
302 uint8_t type;
303 uint16_t step;
304 uint8_t delay;
305 uint8_t range;
306 uint8_t refdiv;
307 /* asic_ss */
308 uint16_t rate;
309 uint16_t amount;
310 };
311
312 enum radeon_flip_status {
313 RADEON_FLIP_NONE,
314 RADEON_FLIP_PENDING,
315 RADEON_FLIP_SUBMITTED
316 };
317
318 struct radeon_crtc {
319 struct drm_crtc base;
320 int crtc_id;
321 bool enabled;
322 bool can_tile;
323 bool cursor_out_of_bounds;
324 uint32_t crtc_offset;
325 struct drm_gem_object *cursor_bo;
326 uint64_t cursor_addr;
327 int cursor_x;
328 int cursor_y;
329 int cursor_hot_x;
330 int cursor_hot_y;
331 int cursor_width;
332 int cursor_height;
333 int max_cursor_width;
334 int max_cursor_height;
335 uint32_t legacy_display_base_addr;
336 enum radeon_rmx_type rmx_type;
337 u8 h_border;
338 u8 v_border;
339 fixed20_12 vsc;
340 fixed20_12 hsc;
341 struct drm_display_mode native_mode;
342 int pll_id;
343 /* page flipping */
344 struct workqueue_struct *flip_queue;
345 struct radeon_flip_work *flip_work;
346 enum radeon_flip_status flip_status;
347 /* pll sharing */
348 struct radeon_atom_ss ss;
349 bool ss_enabled;
350 u32 adjusted_clock;
351 int bpc;
352 u32 pll_reference_div;
353 u32 pll_post_div;
354 u32 pll_flags;
355 struct drm_encoder *encoder;
356 struct drm_connector *connector;
357 /* for dpm */
358 u32 line_time;
359 u32 wm_low;
360 u32 wm_high;
361 u32 lb_vblank_lead_lines;
362 struct drm_display_mode hw_mode;
363 enum radeon_output_csc output_csc;
364 };
365
366 struct radeon_encoder_primary_dac {
367 /* legacy primary dac */
368 uint32_t ps2_pdac_adj;
369 };
370
371 struct radeon_encoder_lvds {
372 /* legacy lvds */
373 uint16_t panel_vcc_delay;
374 uint8_t panel_pwr_delay;
375 uint8_t panel_digon_delay;
376 uint8_t panel_blon_delay;
377 uint16_t panel_ref_divider;
378 uint8_t panel_post_divider;
379 uint16_t panel_fb_divider;
380 bool use_bios_dividers;
381 uint32_t lvds_gen_cntl;
382 /* panel mode */
383 struct drm_display_mode native_mode;
384 struct backlight_device *bl_dev;
385 int dpms_mode;
386 uint8_t backlight_level;
387 };
388
389 struct radeon_encoder_tv_dac {
390 /* legacy tv dac */
391 uint32_t ps2_tvdac_adj;
392 uint32_t ntsc_tvdac_adj;
393 uint32_t pal_tvdac_adj;
394
395 int h_pos;
396 int v_pos;
397 int h_size;
398 int supported_tv_stds;
399 bool tv_on;
400 enum radeon_tv_std tv_std;
401 struct radeon_tv_regs tv;
402 };
403
404 struct radeon_encoder_int_tmds {
405 /* legacy int tmds */
406 struct radeon_tmds_pll tmds_pll[4];
407 };
408
409 struct radeon_encoder_ext_tmds {
410 /* tmds over dvo */
411 struct radeon_i2c_chan *i2c_bus;
412 uint8_t slave_addr;
413 enum radeon_dvo_chip dvo_chip;
414 };
415
416 /* spread spectrum */
417 struct radeon_encoder_atom_dig {
418 bool linkb;
419 /* atom dig */
420 bool coherent_mode;
421 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
422 /* atom lvds/edp */
423 uint32_t lcd_misc;
424 uint16_t panel_pwr_delay;
425 uint32_t lcd_ss_id;
426 /* panel mode */
427 struct drm_display_mode native_mode;
428 struct backlight_device *bl_dev;
429 int dpms_mode;
430 uint8_t backlight_level;
431 int panel_mode;
432 struct radeon_afmt *afmt;
433 struct r600_audio_pin *pin;
434 };
435
436 struct radeon_encoder_atom_dac {
437 enum radeon_tv_std tv_std;
438 };
439
440 struct radeon_encoder {
441 struct drm_encoder base;
442 uint32_t encoder_enum;
443 uint32_t encoder_id;
444 uint32_t devices;
445 uint32_t active_device;
446 uint32_t flags;
447 uint32_t pixel_clock;
448 enum radeon_rmx_type rmx_type;
449 enum radeon_underscan_type underscan_type;
450 uint32_t underscan_hborder;
451 uint32_t underscan_vborder;
452 struct drm_display_mode native_mode;
453 void *enc_priv;
454 int audio_polling_active;
455 bool is_ext_encoder;
456 u16 caps;
457 struct radeon_audio_funcs *audio;
458 enum radeon_output_csc output_csc;
459 bool can_mst;
460 uint32_t offset;
461 };
462
463 struct radeon_connector_atom_dig {
464 uint32_t igp_lane_info;
465 /* displayport */
466 u8 dpcd[DP_RECEIVER_CAP_SIZE];
467 u8 dp_sink_type;
468 int dp_clock;
469 int dp_lane_count;
470 bool edp_on;
471 };
472
473 struct radeon_gpio_rec {
474 bool valid;
475 u8 id;
476 u32 reg;
477 u32 mask;
478 u32 shift;
479 };
480
481 struct radeon_hpd {
482 enum radeon_hpd_id hpd;
483 u8 plugged_state;
484 struct radeon_gpio_rec gpio;
485 };
486
487 struct radeon_router {
488 u32 router_id;
489 struct radeon_i2c_bus_rec i2c_info;
490 u8 i2c_addr;
491 /* i2c mux */
492 bool ddc_valid;
493 u8 ddc_mux_type;
494 u8 ddc_mux_control_pin;
495 u8 ddc_mux_state;
496 /* clock/data mux */
497 bool cd_valid;
498 u8 cd_mux_type;
499 u8 cd_mux_control_pin;
500 u8 cd_mux_state;
501 };
502
503 enum radeon_connector_audio {
504 RADEON_AUDIO_DISABLE = 0,
505 RADEON_AUDIO_ENABLE = 1,
506 RADEON_AUDIO_AUTO = 2
507 };
508
509 enum radeon_connector_dither {
510 RADEON_FMT_DITHER_DISABLE = 0,
511 RADEON_FMT_DITHER_ENABLE = 1,
512 };
513
514 struct radeon_connector {
515 struct drm_connector base;
516 uint32_t connector_id;
517 uint32_t devices;
518 struct radeon_i2c_chan *ddc_bus;
519 /* some systems have an hdmi and vga port with a shared ddc line */
520 bool shared_ddc;
521 bool use_digital;
522 /* we need to mind the EDID between detect
523 and get modes due to analog/digital/tvencoder */
524 struct edid *edid;
525 void *con_priv;
526 bool dac_load_detect;
527 bool detected_by_load; /* if the connection status was determined by load */
528 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
529 uint16_t connector_object_id;
530 struct radeon_hpd hpd;
531 struct radeon_router router;
532 struct radeon_i2c_chan *router_bus;
533 enum radeon_connector_audio audio;
534 enum radeon_connector_dither dither;
535 int pixelclock_for_modeset;
536 };
537
538 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
539 ((em) == ATOM_ENCODER_MODE_DP_MST))
540
541 struct atom_clock_dividers {
542 u32 post_div;
543 union {
544 struct {
545 #ifdef __BIG_ENDIAN
546 u32 reserved : 6;
547 u32 whole_fb_div : 12;
548 u32 frac_fb_div : 14;
549 #else
550 u32 frac_fb_div : 14;
551 u32 whole_fb_div : 12;
552 u32 reserved : 6;
553 #endif
554 };
555 u32 fb_div;
556 };
557 u32 ref_div;
558 bool enable_post_div;
559 bool enable_dithen;
560 u32 vco_mode;
561 u32 real_clock;
562 /* added for CI */
563 u32 post_divider;
564 u32 flags;
565 };
566
567 struct atom_mpll_param {
568 union {
569 struct {
570 #ifdef __BIG_ENDIAN
571 u32 reserved : 8;
572 u32 clkfrac : 12;
573 u32 clkf : 12;
574 #else
575 u32 clkf : 12;
576 u32 clkfrac : 12;
577 u32 reserved : 8;
578 #endif
579 };
580 u32 fb_div;
581 };
582 u32 post_div;
583 u32 bwcntl;
584 u32 dll_speed;
585 u32 vco_mode;
586 u32 yclk_sel;
587 u32 qdr;
588 u32 half_rate;
589 };
590
591 #define MEM_TYPE_GDDR5 0x50
592 #define MEM_TYPE_GDDR4 0x40
593 #define MEM_TYPE_GDDR3 0x30
594 #define MEM_TYPE_DDR2 0x20
595 #define MEM_TYPE_GDDR1 0x10
596 #define MEM_TYPE_DDR3 0xb0
597 #define MEM_TYPE_MASK 0xf0
598
599 struct atom_memory_info {
600 u8 mem_vendor;
601 u8 mem_type;
602 };
603
604 #define MAX_AC_TIMING_ENTRIES 16
605
606 struct atom_memory_clock_range_table {
607 u8 num_entries;
608 u8 rsv[3];
609 u32 mclk[MAX_AC_TIMING_ENTRIES];
610 };
611
612 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
613 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
614
615 struct atom_mc_reg_entry {
616 u32 mclk_max;
617 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
618 };
619
620 struct atom_mc_register_address {
621 u16 s1;
622 u8 pre_reg_data;
623 };
624
625 struct atom_mc_reg_table {
626 u8 last;
627 u8 num_entries;
628 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
629 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
630 };
631
632 #define MAX_VOLTAGE_ENTRIES 32
633
634 struct atom_voltage_table_entry {
635 u16 value;
636 u32 smio_low;
637 };
638
639 struct atom_voltage_table {
640 u32 count;
641 u32 mask_low;
642 u32 phase_delay;
643 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
644 };
645
646 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
647 #define DRM_SCANOUTPOS_VALID (1 << 0)
648 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
649 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
650 #define USE_REAL_VBLANKSTART (1 << 30)
651 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
652
653 extern void
654 radeon_add_atom_connector(struct drm_device *dev,
655 uint32_t connector_id,
656 uint32_t supported_device,
657 int connector_type,
658 struct radeon_i2c_bus_rec *i2c_bus,
659 uint32_t igp_lane_info,
660 uint16_t connector_object_id,
661 struct radeon_hpd *hpd,
662 struct radeon_router *router);
663 extern void
664 radeon_add_legacy_connector(struct drm_device *dev,
665 uint32_t connector_id,
666 uint32_t supported_device,
667 int connector_type,
668 struct radeon_i2c_bus_rec *i2c_bus,
669 uint16_t connector_object_id,
670 struct radeon_hpd *hpd);
671 extern uint32_t
672 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
673 uint8_t dac);
674 extern void radeon_link_encoder_connector(struct drm_device *dev);
675
676 extern enum radeon_tv_std
677 radeon_combios_get_tv_info(struct radeon_device *rdev);
678 extern enum radeon_tv_std
679 radeon_atombios_get_tv_info(struct radeon_device *rdev);
680 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
681 u16 *vddc, u16 *vddci, u16 *mvdd);
682
683 extern void
684 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
685 struct drm_encoder *encoder,
686 bool connected);
687 extern void
688 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
689 struct drm_encoder *encoder,
690 bool connected);
691
692 extern struct drm_connector *
693 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
694 extern struct drm_connector *
695 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
696 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
697 u32 pixel_clock);
698
699 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
700 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
701 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
702 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
703
704 extern void radeon_connector_hotplug(struct drm_connector *connector);
705 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
706 struct drm_display_mode *mode);
707 extern void radeon_dp_set_link_config(struct drm_connector *connector,
708 const struct drm_display_mode *mode);
709 extern void radeon_dp_link_train(struct drm_encoder *encoder,
710 struct drm_connector *connector);
711 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
712 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
713 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
714 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
715 struct drm_connector *connector);
716 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
717 u8 power_state);
718 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
719 extern ssize_t
720 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
721
722 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
723 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
724 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
725 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
726 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
727 int action, uint8_t lane_num,
728 uint8_t lane_set);
729 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
730 int action, uint8_t lane_num,
731 uint8_t lane_set, int fe);
732 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
733 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
734 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
735
736 extern void radeon_i2c_init(struct radeon_device *rdev);
737 extern void radeon_i2c_fini(struct radeon_device *rdev);
738 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
739 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
740 extern void radeon_i2c_add(struct radeon_device *rdev,
741 struct radeon_i2c_bus_rec *rec,
742 const char *name);
743 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
744 struct radeon_i2c_bus_rec *i2c_bus);
745 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
746 struct radeon_i2c_bus_rec *rec,
747 const char *name);
748 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
749 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
750 u8 slave_addr,
751 u8 addr,
752 u8 *val);
753 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
754 u8 slave_addr,
755 u8 addr,
756 u8 val);
757 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
758 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
759 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
760
761 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
762 struct radeon_atom_ss *ss,
763 int id);
764 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
765 struct radeon_atom_ss *ss,
766 int id, u32 clock);
767 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
768 u8 id);
769
770 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
771 uint64_t freq,
772 uint32_t *dot_clock_p,
773 uint32_t *fb_div_p,
774 uint32_t *frac_fb_div_p,
775 uint32_t *ref_div_p,
776 uint32_t *post_div_p);
777
778 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
779 u32 freq,
780 u32 *dot_clock_p,
781 u32 *fb_div_p,
782 u32 *frac_fb_div_p,
783 u32 *ref_div_p,
784 u32 *post_div_p);
785
786 extern void radeon_setup_encoder_clones(struct drm_device *dev);
787
788 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
789 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
790 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
791 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
792 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
793 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
794 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
795 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
796 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
797 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
798 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
799
800 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
801 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
802 struct drm_framebuffer *old_fb);
803 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
804 struct drm_framebuffer *fb,
805 int x, int y,
806 enum mode_set_atomic state);
807 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
808 struct drm_display_mode *mode,
809 struct drm_display_mode *adjusted_mode,
810 int x, int y,
811 struct drm_framebuffer *old_fb);
812 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
813
814 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
815 struct drm_framebuffer *old_fb);
816 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
817 struct drm_framebuffer *fb,
818 int x, int y,
819 enum mode_set_atomic state);
820 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
821 struct drm_framebuffer *fb,
822 int x, int y, int atomic);
823 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
824 struct drm_file *file_priv,
825 uint32_t handle,
826 uint32_t width,
827 uint32_t height,
828 int32_t hot_x,
829 int32_t hot_y);
830 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
831 int x, int y);
832 extern void radeon_cursor_reset(struct drm_crtc *crtc);
833
834 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
835 unsigned int flags, int *vpos, int *hpos,
836 ktime_t *stime, ktime_t *etime,
837 const struct drm_display_mode *mode);
838
839 extern bool
840 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
841 int *vpos, int *hpos,
842 ktime_t *stime, ktime_t *etime,
843 const struct drm_display_mode *mode);
844
845 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
846 extern struct edid *
847 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
848 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
849 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
850 extern struct radeon_encoder_atom_dig *
851 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
852 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
853 struct radeon_encoder_int_tmds *tmds);
854 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
855 struct radeon_encoder_int_tmds *tmds);
856 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
857 struct radeon_encoder_int_tmds *tmds);
858 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
859 struct radeon_encoder_ext_tmds *tmds);
860 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
861 struct radeon_encoder_ext_tmds *tmds);
862 extern struct radeon_encoder_primary_dac *
863 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
864 extern struct radeon_encoder_tv_dac *
865 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
866 extern struct radeon_encoder_lvds *
867 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
868 extern struct radeon_encoder_tv_dac *
869 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
870 extern struct radeon_encoder_primary_dac *
871 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
872 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
873 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
874 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
875 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
876 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
877 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
878 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
879 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
880 extern void
881 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
882 extern void
883 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
884 extern void
885 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
886 extern void
887 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
888 int radeon_framebuffer_init(struct drm_device *dev,
889 struct drm_framebuffer *rfb,
890 const struct drm_mode_fb_cmd2 *mode_cmd,
891 struct drm_gem_object *obj);
892
893 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
894 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
895 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
896 void radeon_atombios_init_crtc(struct drm_device *dev,
897 struct radeon_crtc *radeon_crtc);
898 void radeon_legacy_init_crtc(struct drm_device *dev,
899 struct radeon_crtc *radeon_crtc);
900
901 void radeon_get_clock_info(struct drm_device *dev);
902
903 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
904 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
905
906 void radeon_enc_destroy(struct drm_encoder *encoder);
907 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
908 void radeon_combios_asic_init(struct drm_device *dev);
909 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
910 const struct drm_display_mode *mode,
911 struct drm_display_mode *adjusted_mode);
912 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
913 struct drm_display_mode *adjusted_mode);
914 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
915
916 /* legacy tv */
917 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
918 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
919 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
920 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
921 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
922 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
923 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
924 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
925 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
926 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
927 struct drm_display_mode *mode,
928 struct drm_display_mode *adjusted_mode);
929
930 /* fmt blocks */
931 void avivo_program_fmt(struct drm_encoder *encoder);
932 void dce3_program_fmt(struct drm_encoder *encoder);
933 void dce4_program_fmt(struct drm_encoder *encoder);
934 void dce8_program_fmt(struct drm_encoder *encoder);
935
936 /* fbdev layer */
937 #if defined(CONFIG_DRM_FBDEV_EMULATION)
938 void radeon_fbdev_setup(struct radeon_device *rdev);
939 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
940 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
941 #else
radeon_fbdev_setup(struct radeon_device * rdev)942 static inline void radeon_fbdev_setup(struct radeon_device *rdev)
943 { }
radeon_fbdev_set_suspend(struct radeon_device * rdev,int state)944 static inline void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
945 { }
radeon_fbdev_robj_is_fb(struct radeon_device * rdev,struct radeon_bo * robj)946 static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
947 {
948 return false;
949 }
950 #endif
951
952 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
953
954 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
955
956 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
957 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
958 #endif
959