1 /*------------------------------------------------------------------------- 2 at89c51id2.h: Register Declarations for the Atmel AT89C51ID2 Processor 3 4 Copyright (C) 2014, Victor Munoz / victor at munoz.name 5 6 This library is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2, or (at your option) any 9 later version. 10 11 This library is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this library; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 MA 02110-1301, USA. 20 21 As a special exception, if you link this library with other files, 22 some of which are compiled with SDCC, to produce an executable, 23 this library does not by itself cause the resulting executable to 24 be covered by the GNU General Public License. This exception does 25 not however invalidate any other reasons why the executable file 26 might be covered by the GNU General Public License. 27 -------------------------------------------------------------------------*/ 28 29 #ifndef REG_AT89C51ID2_H 30 #define REG_AT89C51ID2_H 31 32 #include <at89c51ed2.h> // Load definitions for the at89c51ed2.h 33 34 //Clock control Register 0 CKCON0(0x8F) additional definitions 35 #define TWIX2 0x80 // 2-wire clock (CPU clock X2 only) '1'=12 ck/cy, '0'=6 ck/cy 36 37 // Two wire interface control registers 38 __sfr __at (0x93) SSCON; // Synchronous Serial Control register (93h) 39 #define CR2 0x80 // Control Rate bit 2 40 #define SSIE 0x40 // Synchronous Serial Interface Enable bit 41 #define STA 0x20 // Start flag 42 #define STO 0x10 // Stop flag 43 #define SI 0x08 // Synchronous Serial Interrupt flag 44 #define AA 0x04 // Assert Acknowledge flag 45 #define CR1 0x02 // Control Rate bit 1 46 #define CR0 0x01 // Control Rate bit 0 47 __sfr __at (0x94) SSCS; // Synchronous Serial Control and Status Register (read) (094h) 48 #define SC4 0x80 // Status Code bit 4 49 #define SC3 0x40 // Status Code bit 3 50 #define SC2 0x20 // Status Code bit 2 51 #define SC1 0x10 // Status Code bit 1 52 #define SC0 0x08 // Status Code bit 0 53 __sfr __at (0x95) SSDAT; // Synchronous Serial Data register (read/write) (095h) 54 __sfr __at (0x96) SSADR; // Synchronous Serial Address Register (read/write) (096h) 55 #define GC 0x01 // General Call bit 56 57 //Interrupt Enable 1 IEN1(0xB1) additional definitions 58 #define ETWI 0x02 // Two Wire Interrupt Enable bit. 59 60 //Interrupt Priority 1 LOW IPL1(0xB2) additional definitions 61 #define TWIL 0x02 62 63 //Interrupt Priority 1 HIGH IPH1(0xB3) additional definitions 64 #define TWIH 0x02 65 66 /* Interrupt numbers: address = (number * 8) + 3 */ 67 #define TWI_VECTOR 8 /* 0x43 Two wire interface */ 68 69 #endif /*REG_AT89C51ID2_H*/ 70