1 /* $NetBSD: tx39irreg.h,v 1.3 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Toshiba TX3912 IR module 33 */ 34 35 #define TX39_IRCTRL1_REG 0x0a0 /* R/W */ 36 #define TX39_IRCTRL2_REG 0x0a4 /* W */ 37 #define TX39_IRTXHOLD_REG 0x0a8 /* W */ 38 39 /* 40 * IR control 1 register 41 */ 42 #define TX39_IRCTRL1_CARDET 0x01000000 43 44 #define TX39_IRCTRL1_BAUDVAL_SHIFT 16 45 #define TX39_IRCTRL1_BAUDVAL_MASK 0xff 46 #define TX39_IRCTRL1_BAUDVAL(cr) \ 47 (((cr) >> TX39_IRCTRL1_BAUDVAL_SHIFT) & \ 48 TX39_IRCTRL1_BAUDVAL_MASK) 49 #define TX39_IRCTRL1_BAUDVAL_SET(cr, val) \ 50 ((cr) | (((val) << TX39_IRCTRL1_BAUDVAL_SHIFT) & \ 51 (TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT))) 52 #define TX39_IRCTRL1_BAUDVAL_CLR(cr) \ 53 ((cr) &= ~(TX39_IRCTRL1_BAUDVAL_MASK << TX39_IRCTRL1_BAUDVAL_SHIFT)) 54 55 #define TX39_IRCTRL1_TESTIR 0x00000010 /* don't set */ 56 #define TX39_IRCTRL1_DTINVERT 0x00000008 57 #define TX39_IRCTRL1_RXPWR 0x00000004 58 #define TX39_IRCTRL1_ENSTATE 0x00000002 59 #define TX39_IRCTRL1_ENCOMSM 0x00000001 60 61 /* 62 * IR control 2 register 63 */ 64 /* 65 * period = (PER + 1) * (BAUDVAL + 1) * (1/3.6864MHz) 66 */ 67 #define TX39_IRCTRL2_PER_SHIFT 24 68 #define TX39_IRCTRL2_PER_MASK 0xff 69 #define TX39_IRCTRL2_PER_SET(cr, val) \ 70 ((cr) | (((val) << TX39_IRCTRL2_PER_SHIFT) & \ 71 (TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT))) 72 #define TX39_IRCTRL2_PER_CLR(cr) \ 73 ((cr) &= ~(TX39_IRCTRL2_PER_MASK << TX39_IRCTRL2_PER_SHIFT)) 74 75 /* 76 * on time = ONTIME * (BAUDVAL + 1) * (1/3.6864MHz) 77 */ 78 #define TX39_IRCTRL2_ONTIME_SHIFT 16 79 #define TX39_IRCTRL2_ONTIME_MASK 0xff 80 #define TX39_IRCTRL2_ONTIME_SET(cr, val) \ 81 ((cr) | (((val) << TX39_IRCTRL2_ONTIME_SHIFT) & \ 82 (TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT))) 83 #define TX39_IRCTRL2_ONTIME_CLR(cr) \ 84 ((cr) &= ~(TX39_IRCTRL2_ONTIME_MASK << TX39_IRCTRL2_ONTIME_SHIFT)) 85 86 /* 87 * delay time = (DELAYVAL + 1) * 7.8ms 88 */ 89 #define TX39_IRCTRL2_DELAYVAL_SHIFT 8 90 #define TX39_IRCTRL2_DELAYVAL_MASK 0xff 91 #define TX39_IRCTRL2_DELAYVAL_SET(cr, val) \ 92 ((cr) | (((val) << TX39_IRCTRL2_DELAYVAL_SHIFT) & \ 93 (TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT))) 94 #define TX39_IRCTRL2_DELAYVAL_CLR(cr) \ 95 ((cr) &= ~(TX39_IRCTRL2_DELAYVAL_MASK << TX39_IRCTRL2_DELAYVAL_SHIFT)) 96 97 /* 98 * wait time = (DELAYVAL + 1) * (WAITVAL + 1) * 7.8ms 99 */ 100 #define TX39_IRCTRL2_WAITVAL_SHIFT 0 101 #define TX39_IRCTRL2_WAITVAL_MASK 0xff 102 #define TX39_IRCTRL2_WAITVAL_SET(cr, val) \ 103 ((cr) | (((val) << TX39_IRCTRL2_WAITVAL_SHIFT) & \ 104 (TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT))) 105 #define TX39_IRCTRL2_WAITVAL_CLR(cr) \ 106 ((cr) &= ~(TX39_IRCTRL2_WAITVAL_MASK << TX39_IRCTRL2_WAITVAL_SHIFT)) 107