1 /* $OpenBSD: if_udavreg.h,v 1.16 2022/01/09 05:43:00 jsg Exp $ */ 2 /* $NetBSD: if_udavreg.h,v 1.2 2003/09/04 15:17:39 tsutsui Exp $ */ 3 /* $nabe: if_udavreg.h,v 1.2 2003/08/21 16:26:40 nabe Exp $ */ 4 /* 5 * Copyright (c) 2003 6 * Shingo WATANABE <nabe@nabechan.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #define UDAV_TX_LIST_CNT 1 35 #define UDAV_RX_LIST_CNT 1 36 37 #define UDAV_TX_TIMEOUT 1000 38 #define UDAV_TIMEOUT 10000 39 40 41 /* Request */ 42 #define UDAV_REQ_REG_READ 0x00 /* Read from register(s) */ 43 #define UDAV_REQ_REG_WRITE 0x01 /* Write to register(s) */ 44 #define UDAV_REQ_REG_WRITE1 0x03 /* Write to a register */ 45 46 #define UDAV_REQ_MEM_READ 0x02 /* Read from memory */ 47 #define UDAV_REQ_MEM_WRITE 0x05 /* Write to memory */ 48 #define UDAV_REQ_MEM_WRITE1 0x07 /* Write a byte to memory */ 49 50 /* Registers */ 51 #define UDAV_NCR 0x00 /* Network Control Register */ 52 #define UDAV_NCR_EXT_PHY (1<<7) /* Select External PHY */ 53 #define UDAV_NCR_WAKEEN (1<<6) /* Wakeup Event Enable */ 54 #define UDAV_NCR_FCOL (1<<4) /* Force Collision Mode */ 55 #define UDAV_NCR_FDX (1<<3) /* Full-Duplex Mode (RO on Int. PHY) */ 56 #define UDAV_NCR_LBK1 (1<<2) /* Loopback Mode */ 57 #define UDAV_NCR_LBK0 (1<<1) /* Loopback Mode */ 58 #define UDAV_NCR_RST (1<<0) /* Software reset */ 59 60 #define UDAV_NSR 0x01 /* Network Status Register */ 61 #define UDAV_NSR_SPEED (1<<7) /* Media Speed (Int. PHY) */ 62 #define UDAV_NSR_LINKST (1<<6) /* Link Status (Int. PHY) */ 63 #define UDAV_NSR_WAKEST (1<<5) /* Wakeup Status */ 64 #define UDAV_NSR_TXFULL (1<<4) /* TX FIFO Full */ 65 #define UDAV_NSR_TX2END (1<<3) /* TX Packet 2 Complete Status */ 66 #define UDAV_NSR_TX1END (1<<2) /* TX Packet 1 Complete Status */ 67 #define UDAV_NSR_RXOV (1<<1) /* RX FIFO Overflow */ 68 #define UDAV_NSR_RXRDY (1<<0) /* RX Packet Ready */ 69 70 #define UDAV_RCR 0x05 /* RX Control Register */ 71 #define UDAV_RCR_WTDIS (1<<6) /* Watchdog Timer Disable */ 72 #define UDAV_RCR_DIS_LONG (1<<5) /* Discard Long Packet(over 1522Byte) */ 73 #define UDAV_RCR_DIS_CRC (1<<4) /* Discard CRC Error Packet */ 74 #define UDAV_RCR_ALL (1<<3) /* Pass All Multicast */ 75 #define UDAV_RCR_RUNT (1<<2) /* Pass Runt Packet */ 76 #define UDAV_RCR_PRMSC (1<<1) /* Promiscuous Mode */ 77 #define UDAV_RCR_RXEN (1<<0) /* RX Enable */ 78 79 #define UDAV_RSR 0x06 /* RX Status Register */ 80 #define UDAV_RSR_RF (1<<7) /* Runt Frame */ 81 #define UDAV_RSR_MF (1<<6) /* Multicast Frame */ 82 #define UDAV_RSR_LCS (1<<5) /* Late Collision Seen */ 83 #define UDAV_RSR_RWTO (1<<4) /* Receive Watchdog Time-Out */ 84 #define UDAV_RSR_PLE (1<<3) /* Physical Layer Error */ 85 #define UDAV_RSR_AE (1<<2) /* Alignment Error */ 86 #define UDAV_RSR_CE (1<<1) /* CRC Error */ 87 #define UDAV_RSR_FOE (1<<0) /* FIFO Overflow Error */ 88 #define UDAV_RSR_ERR (UDAV_RSR_RF | UDAV_RSR_LCS | UDAV_RSR_RWTO |\ 89 UDAV_RSR_PLE | UDAV_RSR_AE | UDAV_RSR_CE |\ 90 UDAV_RSR_FOE) 91 92 #define UDAV_EPCR 0x0b /* EEPROM & PHY Control Register */ 93 #define UDAV_EPCR_REEP (1<<5) /* Reload EEPROM */ 94 #define UDAV_EPCR_WEP (1<<4) /* Write EEPROM enable */ 95 #define UDAV_EPCR_EPOS (1<<3) /* EEPROM or PHY Operation Select */ 96 #define UDAV_EPCR_ERPRR (1<<2) /* EEPROM/PHY Register Read Command */ 97 #define UDAV_EPCR_ERPRW (1<<1) /* EEPROM/PHY Register Write Command */ 98 #define UDAV_EPCR_ERRE (1<<0) /* EEPROM/PHY Access Status */ 99 100 #define UDAV_EPAR 0x0c /* EEPROM & PHY Control Register */ 101 #define UDAV_EPAR_PHY_ADR1 (1<<7) /* PHY Address bit 1 */ 102 #define UDAV_EPAR_PHY_ADR0 (1<<6) /* PHY Address bit 0 */ 103 #define UDAV_EPAR_EROA (1<<0) /* EEPROM Word/PHY Register Address */ 104 #define UDAV_EPAR_EROA_MASK (0x1f) /* [5:0] */ 105 106 #define UDAV_EPDRL 0x0d /* EEPROM & PHY Data Register */ 107 #define UDAV_EPDRH 0x0e /* EEPROM & PHY Data Register */ 108 109 #define UDAV_PAR0 0x10 /* Ethernet Address, load from EEPROM */ 110 #define UDAV_PAR1 0x11 /* Ethernet Address, load from EEPROM */ 111 #define UDAV_PAR2 0x12 /* Ethernet Address, load from EEPROM */ 112 #define UDAV_PAR3 0x13 /* Ethernet Address, load from EEPROM */ 113 #define UDAV_PAR4 0x14 /* Ethernet Address, load from EEPROM */ 114 #define UDAV_PAR5 0x15 /* Ethernet Address, load from EEPROM */ 115 #define UDAV_PAR UDAV_PAR0 116 117 #define UDAV_MAR0 0x16 /* Multicast Register */ 118 #define UDAV_MAR1 0x17 /* Multicast Register */ 119 #define UDAV_MAR2 0x18 /* Multicast Register */ 120 #define UDAV_MAR3 0x19 /* Multicast Register */ 121 #define UDAV_MAR4 0x1a /* Multicast Register */ 122 #define UDAV_MAR5 0x1b /* Multicast Register */ 123 #define UDAV_MAR6 0x1c /* Multicast Register */ 124 #define UDAV_MAR7 0x1d /* Multicast Register */ 125 #define UDAV_MAR UDAV_MAR0 126 127 #define UDAV_GPCR 0x1e /* General purpose control register */ 128 #define UDAV_GPCR_GEP_CNTL6 (1<<6) /* General purpose control 6 */ 129 #define UDAV_GPCR_GEP_CNTL5 (1<<5) /* General purpose control 5 */ 130 #define UDAV_GPCR_GEP_CNTL4 (1<<4) /* General purpose control 4 */ 131 #define UDAV_GPCR_GEP_CNTL3 (1<<3) /* General purpose control 3 */ 132 #define UDAV_GPCR_GEP_CNTL2 (1<<2) /* General purpose control 2 */ 133 #define UDAV_GPCR_GEP_CNTL1 (1<<1) /* General purpose control 1 */ 134 #define UDAV_GPCR_GEP_CNTL0 (1<<0) /* General purpose control 0 */ 135 136 #define UDAV_GPR 0x1f /* General purpose register */ 137 #define UDAV_GPR_GEPIO6 (1<<6) /* General purpose 6 */ 138 #define UDAV_GPR_GEPIO5 (1<<5) /* General purpose 5 */ 139 #define UDAV_GPR_GEPIO4 (1<<4) /* General purpose 4 */ 140 #define UDAV_GPR_GEPIO3 (1<<3) /* General purpose 3 */ 141 #define UDAV_GPR_GEPIO2 (1<<2) /* General purpose 2 */ 142 #define UDAV_GPR_GEPIO1 (1<<1) /* General purpose 1 */ 143 #define UDAV_GPR_GEPIO0 (1<<0) /* General purpose 0 */ 144 145 #define GET_IFP(sc) (&(sc)->sc_ac.ac_if) 146 #define GET_MII(sc) (&(sc)->sc_mii) 147 148 struct udav_chain { 149 struct udav_softc *udav_sc; 150 struct usbd_xfer *udav_xfer; 151 char *udav_buf; 152 struct mbuf *udav_mbuf; 153 int udav_idx; 154 }; 155 156 struct udav_cdata { 157 struct udav_chain udav_tx_chain[UDAV_TX_LIST_CNT]; 158 struct udav_chain udav_rx_chain[UDAV_TX_LIST_CNT]; 159 #if 0 160 /* XXX: Interrupt Endpoint is not yet supported! */ 161 struct udav_intrpkg udav_ibuf; 162 #endif 163 int udav_tx_prod; 164 int udav_tx_cons; 165 int udav_tx_cnt; 166 int udav_rx_prod; 167 }; 168 169 struct udav_softc { 170 struct device sc_dev; /* base device */ 171 struct usbd_device *sc_udev; 172 173 /* USB */ 174 struct usbd_interface *sc_ctl_iface; 175 /* int sc_ctl_iface_no; */ 176 int sc_bulkin_no; /* bulk in endpoint */ 177 int sc_bulkout_no; /* bulk out endpoint */ 178 int sc_intrin_no; /* intr in endpoint */ 179 struct usbd_pipe *sc_pipe_rx; 180 struct usbd_pipe *sc_pipe_tx; 181 struct usbd_pipe *sc_pipe_intr; 182 struct timeout sc_stat_ch; 183 u_int sc_rx_errs; 184 /* u_int sc_intr_errs; */ 185 struct timeval sc_rx_notice; 186 187 /* Ethernet */ 188 struct arpcom sc_ac; /* ethernet common */ 189 struct mii_data sc_mii; 190 struct rwlock sc_mii_lock; 191 int sc_link; 192 #define sc_media udav_mii.mii_media 193 struct udav_cdata sc_cdata; 194 195 int sc_refcnt; 196 197 struct usb_task sc_tick_task; 198 struct usb_task sc_stop_task; 199 200 u_int16_t sc_flags; 201 }; 202 203 struct udav_rx_hdr { 204 uByte pktstat; 205 uWord length; 206 } __packed; 207 #define UDAV_RX_HDRLEN sizeof(struct udav_rx_hdr) 208 209 /* Packet length */ 210 #define UDAV_MAX_MTU 1522 /* According to datasheet */ 211 #define UDAV_MIN_FRAME_LEN 60 212 #define UDAV_BUFSZ UDAV_MAX_MTU + UDAV_RX_HDRLEN 213