1 /* $OpenBSD: umcs.h,v 1.6 2023/04/11 00:45:09 jsg Exp $ */ 2 /* $NetBSD: umcs.h,v 1.1 2014/03/16 09:34:45 martin Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _UMCS_H_ 31 #define _UMCS_H_ 32 33 #define UMCS_MAX_PORTS 4 34 35 #define UMCS_READ_LENGTH 1 /* bytes */ 36 37 /* Read/Write registers vendor commands */ 38 #define UMCS_READ 0x0d 39 #define UMCS_WRITE 0x0e 40 41 #define UMCS_CONFIG_NO 0 42 #define UMCS_IFACE_NO 0 43 44 /* Read/Write EEPROM values */ 45 #define UMCS_EEPROM_RW_WVALUE 0x0900 46 47 /* 48 * All these registers are documented only in full datasheet, which 49 * can be requested from MosChip tech support. 50 */ 51 #define UMCS_SP1 0x00 /* Option bits for UART 1, R/W */ 52 #define UMCS_CTRL1 0x01 /* Control bits for UART 1, R/W */ 53 #define UMCS_PINPONGHIGH 0x02 /* High bits of ping-pong reg, R/W */ 54 #define UMCS_PINPONGLOW 0x03 /* Low bits of ping-pong reg, R/W */ 55 56 57 /* DCRx_1 Registers goes here (see below, they are documented) */ 58 #define UMCS_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, R/W */ 59 #define UMCS_SP2 0x08 /* Option bits for UART 2, R/W */ 60 #define UMCS_CTRL2 0x09 /* Control bits for UART 2, R/W */ 61 #define UMCS_SP3 0x0a /* Option bits for UART 3, R/W */ 62 #define UMCS_CTRL3 0x0b /* Control bits for UART 3, R/W */ 63 #define UMCS_SP4 0x0c /* Option bits for UART 4, R/W */ 64 #define UMCS_CTRL4 0x0d /* Control bits for UART 4, R/W */ 65 #define UMCS_PLL_DIV_M 0x0e /* Pre-divider for PLL, R/W */ 66 #define UMCS_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ 67 #define UMCS_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ 68 #define UMCS_CLK_MUX 0x12 /* PLL clock & Int. ep ctrl, R/W */ 69 #define UMCS_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ 70 #define UMCS_CLK_SELECT12 0x13 /* Clock source for ports 1 & 2, R/W */ 71 #define UMCS_CLK_SELECT34 0x14 /* Clock source for ports 3 & 4, R/W */ 72 #define UMCS_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ 73 74 75 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 76 #define UMCS_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ 77 #define UMCS_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ 78 #define UMCS_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ 79 #define UMCS_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ 80 #define UMCS_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ 81 #define UMCS_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ 82 #define UMCS_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ 83 #define UMCS_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ 84 #define UMCS_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ 85 #define UMCS_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ 86 #define UMCS_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ 87 #define UMCS_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ 88 #define UMCS_MODE 0x2b /* Hardware configuration, R */ 89 #define UMCS_SP1_ICG 0x2c /* Inter char gap config, port 1, R/W */ 90 #define UMCS_SP2_ICG 0x2d /* Inter char gap config, port 2, R/W */ 91 #define UMCS_SP3_ICG 0x2e /* Inter char gap config, port 3, R/W */ 92 #define UMCS_SP4_ICG 0x2f /* Inter char gap config, port 4, R/W */ 93 #define UMCS_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & 2, R/W */ 94 #define UMCS_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & 4, R/W */ 95 #define UMCS_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 1, R */ 96 #define UMCS_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port 1, R */ 97 #define UMCS_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port 2, R */ 98 #define UMCS_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port 2, R */ 99 #define UMCS_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port 3, R */ 100 #define UMCS_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port 3, R */ 101 #define UMCS_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port 4, R */ 102 #define UMCS_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port 4, R */ 103 #define UMCS_ZERO_PERIOD1 0x3a /* Period btw frames for Port 1, R/W */ 104 #define UMCS_ZERO_PERIOD2 0x3b /* Period btw frames for Port 2 R/W */ 105 #define UMCS_ZERO_PERIOD3 0x3c /* Period btw frames for Port 3, R/W */ 106 #define UMCS_ZERO_PERIOD4 0x3d /* Period btw frames for Port 4, R/W */ 107 #define UMCS_ZERO_ENABLE 0x3e /* Enable zero-out frames, R/W */ 108 109 /* Low 8 bits and high 1 bit of threshold values for Bulk-Out ports 1-4 */ 110 #define UMCS_THR_VAL_LOW1 0x3f 111 #define UMCS_THR_VAL_HIGH1 0x40 112 #define UMCS_THR_VAL_LOW2 0x41 113 #define UMCS_THR_VAL_HIGH2 0x42 114 #define UMCS_THR_VAL_LOW3 0x43 115 #define UMCS_THR_VAL_HIGH3 0x44 116 #define UMCS_THR_VAL_LOW4 0x45 117 #define UMCS_THR_VAL_HIGH4 0x46 118 119 120 /* Bits for SPx registers */ 121 #define UMCS_SPx_LOOP_PIPES 0x01 /* Loop Out FIFO to In FIFO */ 122 #define UMCS_SPx_SKIP_ERR_DATA 0x02 /* Drop data received with errors */ 123 #define UMCS_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ 124 #define UMCS_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ 125 #define UMCS_SPx_CLK_MASK 0x70 /* Mask to extract Baud CLK source */ 126 #define UMCS_SPx_CLK_X1 0x00 /* Max speed = 115200 bps, default */ 127 #define UMCS_SPx_CLK_X2 0x10 /* Max speed = 230400 bps */ 128 #define UMCS_SPx_CLK_X35 0x20 /* Max speed = 403200 bps */ 129 #define UMCS_SPx_CLK_X4 0x30 /* Max speed = 460800 bps */ 130 #define UMCS_SPx_CLK_X7 0x40 /* Max speed = 806400 bps */ 131 #define UMCS_SPx_CLK_X8 0x50 /* Max speed = 921600 bps */ 132 #define UMCS_SPx_CLK_24MHZ 0x60 /* Max speed = 1.5Mbps */ 133 #define UMCS_SPx_CLK_48MHZ 0x70 /* Max speed = 3.0 Mbps */ 134 #define UMCS_SPx_CLK_SHIFT 4 /* Shift to get clock value */ 135 #define UMCS_SPx_UART_RESET 0x80 /* Reset UART */ 136 137 138 /* Bits for CTRL registers */ 139 #define UMCS_CTRL_HWFC 0x01 /* Enable hardware flow control */ 140 #define UMCS_CTRL_UNUSED1 0x02 /* Reserved */ 141 #define UMCS_CTRL_CTS_ENABLE 0x04 /* CTS changes are translated to MSR */ 142 #define UMCS_CTRL_UNUSED2 0x08 /* Reserved for ports 2,3,4 */ 143 #define UMCS_CTRL1_DRIVER_DONE 0x08 /* Memory can be use as FIFO */ 144 #define UMCS_CTRL_RX_NEGATE 0x10 /* Negate RX input */ 145 #define UMCS_CTRL_RX_DISABLE 0x20 /* Disable RX logic */ 146 #define UMCS_CTRL_FSM_CONTROL 0x40 /* Disable RX FSM when TX is active */ 147 #define UMCS_CTRL_UNUSED3 0x80 /* Reserved */ 148 149 150 /* 151 * Bits for PINPONGx registers. These registers control how often two 152 * input buffers for Bulk-In FIFOs are swapped. One of buffers is used 153 * for USB transfer, other for receiving data from UART. Exact meaning 154 * of 15 bit value in these registers is unknown 155 */ 156 #define UMCS_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW register */ 157 #define UMCS_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW register */ 158 159 160 /* 161 * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but email from tech support 162 * confirms, that it is register for GPIO_0 and GPIO_1 data input/output. 163 * Chips has 2 GPIO, but first one (lower bit) MUST be used by device 164 * authors as "number of port" indicator, grounded (0) for two-port 165 * devices and pulled-up to 1 for 4-port devices. 166 */ 167 #define UMCS_GPIO_4PORTS 0x01 /* Device has 4 ports configured */ 168 #define UMCS_GPIO_GPIO_0 0x01 /* The same as above */ 169 #define UMCS_GPIO_GPIO_1 0x02 /* GPIO_1 data */ 170 171 /* 172 * Constants for PLL dividers. Output frequency of PLL is: 173 * Fout = (N/M) * Fin. 174 * Default PLL input frequency Fin is 12Mhz (on-chip). 175 */ 176 #define UMCS_PLL_DIV_M_BITS 6 /* Number of bits for M divider */ 177 #define UMCS_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ 178 #define UMCS_PLL_DIV_M_MIN 1 /* Minimum value for M, (0 forbidden) */ 179 #define UMCS_PLL_DIV_M_DEF 1 /* Default value for M */ 180 #define UMCS_PLL_DIV_M_MAX 63 /* Maximum value for M */ 181 #define UMCS_PLL_DIV_N_BITS 6 /* Number of bits for N divider */ 182 #define UMCS_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ 183 #define UMCS_PLL_DIV_N_MIN 1 /* Minimum value for N, (0 forbidden) */ 184 #define UMCS_PLL_DIV_N_DEF 8 /* Default value for N */ 185 #define UMCS_PLL_DIV_N_MAX 63 /* Maximum value for N */ 186 187 188 /* Bits for CLK_MUX register */ 189 #define UMCS_CLK_MUX_INMASK 0x03 /* Mask to extract PLL clock input */ 190 #define UMCS_CLK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ 191 #define UMCS_CLK_MUX_INEXTRN 0x01 /* External PLL input */ 192 #define UMCS_CLK_MUX_INRSV1 0x02 /* Reserved */ 193 #define UMCS_CLK_MUX_INRSV2 0x03 /* Reserved */ 194 #define UMCS_CLK_MUX_PLLHIGH 0x04 /* 20MHz-100MHz or 100MHz-300MHz range*/ 195 #define UMCS_CLK_MUX_INTRFIFOS 0x08 /* Enable FIFOs status (+8 bytes) */ 196 #define UMCS_CLK_MUX_RESERVED1 0x10 /* Unused */ 197 #define UMCS_CLK_MUX_RESERVED2 0x20 /* Unused */ 198 #define UMCS_CLK_MUX_RESERVED3 0x40 /* Unused */ 199 #define UMCS_CLK_MUX_RESERVED4 0x80 /* Unused */ 200 201 202 /* Bits for CLK_SELECTxx registers */ 203 #define UMCS_CLK_SELECT1_MASK 0x07 /* Bits for port 1 in CLK_SELECT12 */ 204 #define UMCS_CLK_SELECT1_SHIFT 0 /* Shift for port 1in CLK_SELECT12 */ 205 #define UMCS_CLK_SELECT2_MASK 0x38 /* Bits for port 2 in CLK_SELECT12 */ 206 #define UMCS_CLK_SELECT2_SHIFT 3 /* Shift for port 2 in CLK_SELECT12 */ 207 #define UMCS_CLK_SELECT3_MASK 0x07 /* Bits for port 3 in CLK_SELECT23 */ 208 #define UMCS_CLK_SELECT3_SHIFT 0 /* Shift for port 3 in CLK_SELECT23 */ 209 #define UMCS_CLK_SELECT4_MASK 0x38 /* Bits for port 4 in CLK_SELECT23 */ 210 #define UMCS_CLK_SELECT4_SHIFT 3 /* Shift for port 4 in CLK_SELECT23 */ 211 #define UMCS_CLK_SELECT_STD 0x00 /* STANDARD rate derived from 96Mhz */ 212 #define UMCS_CLK_SELECT_30MHZ 0x01 /* 30Mhz */ 213 #define UMCS_CLK_SELECT_96MHZ 0x02 /* 96Mhz direct */ 214 #define UMCS_CLK_SELECT_120MHZ 0x03 /* 120Mhz */ 215 #define UMCS_CLK_SELECT_PLL 0x04 /* PLL output */ 216 #define UMCS_CLK_SELECT_EXT 0x05 /* External clock input */ 217 #define UMCS_CLK_SELECT_RES1 0x06 /* Unused */ 218 #define UMCS_CLK_SELECT_RES2 0x07 /* Unused */ 219 220 221 /* Bits for MODE register */ 222 #define UMCS_MODE_RESERVED1 0x01 /* Unused */ 223 #define UMCS_MODE_RESET 0x02 /* RESET = Active High (default) */ 224 #define UMCS_MODE_SER_PRSNT 0x04 /* Reserved (default) */ 225 #define UMCS_MODE_PLLBYPASS 0x08 /* PLL output is bypassed */ 226 #define UMCS_MODE_PORBYPASS 0x10 /* Power-On Reset is bypassed */ 227 #define UMCS_MODE_SELECT24S 0x20 /* 4 or 2 Serial Ports / IrDA active */ 228 #define UMCS_MODE_EEPROMWR 0x40 /* EEPROM write is enabled (default) */ 229 #define UMCS_MODE_IRDA 0x80 /* IrDA mode is activated (default) */ 230 231 /* All 8 bits is used as number of BAUD clocks of pause */ 232 #define UMCS_SPx_ICG_DEF 0x24 233 234 235 /* 236 * Bits for RX_SAMPLINGxx registers. These registers control when 237 * bit value will be sampled within the baud period. 238 * 0 is very beginning of period, 15 is very end, 7 is the middle. 239 */ 240 #define UMCS_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in RX_SAMPLING12 */ 241 #define UMCS_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in RX_SAMPLING12 */ 242 #define UMCS_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in RX_SAMPLING12 */ 243 #define UMCS_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in RX_SAMPLING12 */ 244 #define UMCS_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in RX_SAMPLING23 */ 245 #define UMCS_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in RX_SAMPLING23 */ 246 #define UMCS_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in RX_SAMPLING23 */ 247 #define UMCS_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in RX_SAMPLING23 */ 248 #define UMCS_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ 249 #define UMCS_RX_SAMPLINGx_DEF 7 /* Default for any RX Sampling */ 250 #define UMCS_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ 251 252 /* Number of Bulk-in requests before sending zero-sized reply */ 253 #define UMCS_ZERO_PERIODx_DEF 20 254 255 256 /* Bits to enable sending zero-sized replies, per port, (default is on) */ 257 #define UMCS_ZERO_ENABLE_PORT1 0x01 258 #define UMCS_ZERO_ENABLE_PORT2 0x02 259 #define UMCS_ZERO_ENABLE_PORT3 0x04 260 #define UMCS_ZERO_ENABLE_PORT4 0x08 261 262 263 /* Bits for THR_VAL_HIx */ 264 #define UMCS_THR_VAL_HIMASK 0x01 /* Only one bit is used */ 265 #define UMCS_THR_VAL_HIMUL 256 /* This one bit is means "256" */ 266 #define UMCS_THR_VAL_HISHIFT 8 /* This one bit is means "256" */ 267 #define UMCS_THR_VAL_HIENABLE 0x80 /* Enable threshold */ 268 269 /* These are documented in "public" datasheet */ 270 #define UMCS_DCR0_1 0x04 /* Device ctrl reg 0 for Port 1, R/W */ 271 #define UMCS_DCR1_1 0x05 /* Device ctrl reg 1 for Port 1, R/W */ 272 #define UMCS_DCR2_1 0x06 /* Device ctrl reg 2 for Port 1, R/W */ 273 #define UMCS_DCR0_2 0x16 /* Device ctrl reg 0 for Port 2, R/W */ 274 #define UMCS_DCR1_2 0x17 /* Device ctrl reg 1 for Port 2, R/W */ 275 #define UMCS_DCR2_2 0x18 /* Device ctrl reg 2 for Port 2, R/W */ 276 #define UMCS_DCR0_3 0x19 /* Device ctrl reg 0 for Port 3, R/W */ 277 #define UMCS_DCR1_3 0x1a /* Device ctrl reg 1 for Port 3, R/W */ 278 #define UMCS_DCR2_3 0x1b /* Device ctrl reg 2 for Port 3, R/W */ 279 #define UMCS_DCR0_4 0x1c /* Device ctrl reg 0 for Port 4, R/W */ 280 #define UMCS_DCR1_4 0x1d /* Device ctrl reg 1 for Port 4, R/W */ 281 #define UMCS_DCR2_4 0x1e /* Device ctrl reg 2 for Port 4, R/W */ 282 283 284 /* Bits of DCR0 registers, documented in datasheet */ 285 #define UMCS_DCR0_PWRSAVE 0x01 /* Transceiver off when USB Suspended */ 286 #define UMCS_DCR0_RESERVED1 0x02 /* Unused */ 287 #define UMCS_DCR0_GPIO_MASK 0x0c /* GPIO Mode bits */ 288 #define UMCS_DCR0_GPIO_IN 0x00 /* GPIO Mode - Input (0b00) */ 289 #define UMCS_DCR0_GPIO_OUT 0x08 /* GPIO Mode - Input (0b10) */ 290 #define UMCS_DCR0_RTS_ACTHI 0x10 /* RTS Active is High, (default low) */ 291 #define UMCS_DCR0_RTS_AUTO 0x20 /* Control by state TX buffer or MCR */ 292 #define UMCS_DCR0_IRDA 0x40 /* IrDA mode */ 293 #define UMCS_DCR0_RESERVED2 0x80 /* Unused */ 294 295 /* Bits of DCR1 registers, documented in datasheet, work only for port 1. */ 296 #define UMCS_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to get GPIO value */ 297 #define UMCS_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current 6mA */ 298 #define UMCS_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current 8mA */ 299 #define UMCS_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current 10mA */ 300 #define UMCS_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current 12mA */ 301 #define UMCS_DCR1_UART_CURRENT_MASK 0x0c /* Mask to get UART value */ 302 #define UMCS_DCR1_UART_CURRENT_6MA 0x00 /* Output current 6mA */ 303 #define UMCS_DCR1_UART_CURRENT_8MA 0x04 /* Output current 8mA default */ 304 #define UMCS_DCR1_UART_CURRENT_10MA 0x08 /* UART output current 10mA */ 305 #define UMCS_DCR1_UART_CURRENT_12MA 0x0c /* UART output current 12mA */ 306 #define UMCS_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB Wakeup */ 307 #define UMCS_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power down */ 308 #define UMCS_DCR1_LONG_INTERRUPT 0x40 /* Enable FIFO statistics */ 309 #define UMCS_DCR1_RESERVED1 0x80 /* Unused */ 310 311 /* 312 * Bits of DCR2 registers, documented in datasheet 313 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and 314 * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled). 315 */ 316 #define UMCS_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change, default = 0 */ 317 #define UMCS_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change, default = 0 */ 318 #define UMCS_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change, default = 1 */ 319 #define UMCS_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change, default = 0 */ 320 #define UMCS_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change, dflt = 0 */ 321 #define UMCS_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME signal, 322 * DISCONNECT otherwise, default = 1 */ 323 #define UMCS_DCR2_RESERVED1 0x40 /* Unused */ 324 #define UMCS_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1: Pin 12 325 * Active High, default = 0 */ 326 327 /* Documented UART registers (fully compatible with 16550 UART) */ 328 #define UMCS_REG_THR 0x00 /* Transmitter Holding Register W */ 329 #define UMCS_REG_RHR 0x00 /* Receiver Holding Register R */ 330 #define UMCS_REG_IER 0x01 /* Interrupt enable register - R/W */ 331 #define UMCS_REG_FCR 0x02 /* FIFO Control register - W */ 332 #define UMCS_REG_ISR 0x02 /* Interrupt Status Register R */ 333 #define UMCS_REG_LCR 0x03 /* Line control register R/W */ 334 #define UMCS_REG_MCR 0x04 /* Modem control register R/W */ 335 #define UMCS_REG_LSR 0x05 /* Line status register R */ 336 #define UMCS_REG_MSR 0x06 /* Modem status register R */ 337 #define UMCS_REG_SCRATCHPAD 0x07 /* Scratch pad register */ 338 339 #define UMCS_REG_DLL 0x00 /* Low bits of BAUD divider */ 340 #define UMCS_REG_DLM 0x01 /* High bits of BAUD divider */ 341 342 /* IER bits */ 343 #define UMCS_IER_RXREADY 0x01 /* RX Ready interrupt mask */ 344 #define UMCS_IER_TXREADY 0x02 /* TX Ready interrupt mask */ 345 #define UMCS_IER_RXSTAT 0x04 /* RX Status interrupt mask */ 346 #define UMCS_IER_MODEM 0x08 /* Modem status change interrupt mask */ 347 #define UMCS_IER_SLEEP 0x10 /* SLEEP enable */ 348 349 /* FCR bits */ 350 #define UMCS_FCR_ENABLE 0x01 /* Enable FIFO */ 351 #define UMCS_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ 352 #define UMCS_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ 353 #define UMCS_FCR_RTLMASK 0xa0 /* Select RHR Interrupt Trigger level */ 354 #define UMCS_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ 355 #define UMCS_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ 356 #define UMCS_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ 357 #define UMCS_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ 358 359 /* ISR bits */ 360 #define UMCS_ISR_NOPENDING 0x01 /* No interrupt pending */ 361 #define UMCS_ISR_INTMASK 0x3f /* Mask to select interrupt source */ 362 #define UMCS_ISR_RXERR 0x06 /* Receiver error */ 363 #define UMCS_ISR_RXHASDATA 0x04 /* Receiver has data */ 364 #define UMCS_ISR_RXTIMEOUT 0x0c /* Receiver timeout */ 365 #define UMCS_ISR_TXEMPTY 0x02 /* Transmitter empty */ 366 #define UMCS_ISR_MSCHANGE 0x00 /* Modem status change */ 367 368 /* LCR bits */ 369 #define UMCS_LCR_DATALENMASK 0x03 /* Mask for data length */ 370 #define UMCS_LCR_DATALEN5 0x00 /* 5 data bits */ 371 #define UMCS_LCR_DATALEN6 0x01 /* 6 data bits */ 372 #define UMCS_LCR_DATALEN7 0x02 /* 7 data bits */ 373 #define UMCS_LCR_DATALEN8 0x03 /* 8 data bits */ 374 375 #define UMCS_LCR_STOPBMASK 0x04 /* Mask for stop bits */ 376 #define UMCS_LCR_STOPB1 0x00 /* 1 stop bit in any case */ 377 #define UMCS_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on data len*/ 378 379 #define UMCS_LCR_PARITYMASK 0x38 /* Mask for all parity data */ 380 #define UMCS_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ 381 #define UMCS_LCR_PARITYODD 0x00 /* Parity Odd */ 382 #define UMCS_LCR_PARITYEVEN 0x10 /* Parity Even */ 383 #define UMCS_LCR_PARITYODD 0x00 /* Parity Odd */ 384 #define UMCS_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ 385 386 #define UMCS_LCR_BREAK 0x40 /* Send BREAK */ 387 #define UMCS_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of xHR/IER */ 388 389 /* LSR bits */ 390 #define UMCS_LSR_RHRAVAIL 0x01 /* Data available for read */ 391 #define UMCS_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ 392 #define UMCS_LSR_PARITYERR 0x04 /* Parity error */ 393 #define UMCS_LSR_FRAMEERR 0x10 /* Framing error */ 394 #define UMCS_LSR_BREAKERR 0x20 /* BREAK signal received */ 395 #define UMCS_LSR_THREMPTY 0x40 /* THR register is empty, ready for 396 * transmit */ 397 #define UMCS_LSR_HASERR 0x80 /* Has error in receiver FIFO */ 398 399 /* MCR bits */ 400 #define UMCS_MCR_DTR 0x01 /* Force DTR to be active (low) */ 401 #define UMCS_MCR_RTS 0x02 /* Force RTS to be active (low) */ 402 #define UMCS_MCR_IE 0x04 /* Enable interrupts (not documented) */ 403 #define UMCS_MCR_LOOPBACK 0x10 /* Enable local loopback test mode */ 404 #define UMCS_MCR_CTSRTS 0x20 /* Enable CTS/RTS in 550 (FIFO) mode */ 405 #define UMCS_MCR_DTRDSR 0x40 /* Enable DTR/DSR in 550 (FIFO) mode */ 406 #define UMCS_MCR_DCD 0x80 /* Enable DCD in 550 (FIFO) mode */ 407 408 /* MSR bits */ 409 #define UMCS_MSR_DELTACTS 0x01 /* CTS was changed since last read */ 410 #define UMCS_MSR_DELTADSR 0x02 /* DSR was changed since last read */ 411 #define UMCS_MSR_DELTARI 0x04 /* RI was changed since last read */ 412 #define UMCS_MSR_DELTADCD 0x08 /* DCD was changed since last read */ 413 #define UMCS_MSR_NEGCTS 0x10 /* Negated CTS signal */ 414 #define UMCS_MSR_NEGDSR 0x20 /* Negated DSR signal */ 415 #define UMCS_MSR_NEGRI 0x40 /* Negated RI signal */ 416 #define UMCS_MSR_NEGDCD 0x80 /* Negated DCD signal */ 417 418 /* SCRATCHPAD bits */ 419 #define UMCS_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ 420 #define UMCS_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High = RX */ 421 #define UMCS_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High = TX */ 422 423 #endif /* _UMCS_H_ */ 424