1 /*++ 2 3 Copyright (c) 2004-2005 Alexandr A. Telyatnikov (Alter) 4 5 Module Name: 6 uata_ctl.h 7 8 Abstract: 9 This header contains definitions for private UniATA SRB_IOCTL. 10 11 Author: 12 Alexander A. Telyatnikov (Alter) 13 14 Environment: 15 kernel mode only 16 17 Notes: 18 19 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 30 Revision History: 31 32 Licence: 33 GPLv2 34 35 --*/ 36 37 #ifndef __UNIATA_IO_CONTROL_CODES__H__ 38 #define __UNIATA_IO_CONTROL_CODES__H__ 39 40 //#include "scsi.h" 41 42 #pragma pack(push, 8) 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif //__cplusplus 47 48 #define AHCI_MAX_PORT 32 49 #define IDE_MAX_CHAN 16 50 // Thanks to SATA Port Multipliers: 51 #define IDE_MAX_LUN_PER_CHAN 2 52 #define IDE_MAX_LUN (AHCI_MAX_PORT*IDE_MAX_LUN_PER_CHAN) 53 54 #define MAX_QUEUE_STAT 8 55 56 #define UNIATA_COMM_PORT_VENDOR_STR "UNIATA " "Management Port " UNIATA_VER_STR 57 58 #ifndef UNIATA_CORE 59 60 #define IOCTL_SCSI_MINIPORT_UNIATA_FIND_DEVICES ((FILE_DEVICE_SCSI << 16) + 0x09a0) 61 #define IOCTL_SCSI_MINIPORT_UNIATA_DELETE_DEVICE ((FILE_DEVICE_SCSI << 16) + 0x09a1) 62 #define IOCTL_SCSI_MINIPORT_UNIATA_SET_MAX_MODE ((FILE_DEVICE_SCSI << 16) + 0x09a2) 63 #define IOCTL_SCSI_MINIPORT_UNIATA_GET_MODE ((FILE_DEVICE_SCSI << 16) + 0x09a3) 64 #define IOCTL_SCSI_MINIPORT_UNIATA_ADAPTER_INFO ((FILE_DEVICE_SCSI << 16) + 0x09a4) 65 //#define IOCTL_SCSI_MINIPORT_UNIATA_LUN_IDENT ((FILE_DEVICE_SCSI << 16) + 0x09a5) -> IOCTL_SCSI_MINIPORT_IDENTIFY 66 #define IOCTL_SCSI_MINIPORT_UNIATA_RESETBB ((FILE_DEVICE_SCSI << 16) + 0x09a5) 67 #define IOCTL_SCSI_MINIPORT_UNIATA_RESET_DEVICE ((FILE_DEVICE_SCSI << 16) + 0x09a6) 68 #define IOCTL_SCSI_MINIPORT_UNIATA_REG_IO ((FILE_DEVICE_SCSI << 16) + 0x09a7) 69 #define IOCTL_SCSI_MINIPORT_UNIATA_GET_VERSION ((FILE_DEVICE_SCSI << 16) + 0x09a8) 70 71 typedef struct _ADDREMOVEDEV { 72 ULONG WaitForPhysicalLink; // us 73 ULONG Flags; 74 75 #define UNIATA_REMOVE_FLAGS_HIDE 0x01 76 #define UNIATA_ADD_FLAGS_UNHIDE 0x01 77 78 } ADDREMOVEDEV, *PADDREMOVEDEV; 79 80 typedef struct _SETTRANSFERMODE { 81 ULONG MaxMode; 82 ULONG OrigMode; 83 BOOLEAN ApplyImmediately; 84 UCHAR Reserved[3]; 85 } SETTRANSFERMODE, *PSETTRANSFERMODE; 86 87 typedef struct _GETTRANSFERMODE { 88 ULONG MaxMode; 89 ULONG OrigMode; 90 ULONG CurrentMode; 91 ULONG PhyMode; // since v0.42i6 92 } GETTRANSFERMODE, *PGETTRANSFERMODE; 93 94 typedef struct _GETDRVVERSION { 95 ULONG Length; 96 USHORT VersionMj; 97 USHORT VersionMn; 98 USHORT SubVerMj; 99 USHORT SubVerMn; 100 ULONG Reserved; 101 } GETDRVVERSION, *PGETDRVVERSION; 102 103 typedef struct _CHANINFO { 104 ULONG MaxTransferMode; // may differ from Controller's value due to 40-pin cable 105 ULONG ChannelCtrlFlags; 106 LONGLONG QueueStat[MAX_QUEUE_STAT]; 107 LONGLONG ReorderCount; 108 LONGLONG IntersectCount; 109 LONGLONG TryReorderCount; 110 LONGLONG TryReorderHeadCount; 111 LONGLONG TryReorderTailCount; /* in-order requests */ 112 // ULONG opt_MaxTransferMode; // user-specified 113 } CHANINFO, *PCHANINFO; 114 115 typedef struct _ADAPTERINFO { 116 // Device identification 117 ULONG HeaderLength; 118 ULONG DevID; 119 ULONG RevID; 120 ULONG slotNumber; 121 ULONG SystemIoBusNumber; 122 ULONG DevIndex; 123 124 ULONG Channel; 125 126 ULONG HbaCtrlFlags; 127 BOOLEAN simplexOnly; 128 BOOLEAN MemIo; 129 BOOLEAN UnknownDev; 130 BOOLEAN MasterDev; 131 132 ULONG MaxTransferMode; 133 ULONG HwFlags; 134 ULONG OrigAdapterInterfaceType; 135 136 CHAR DeviceName[64]; 137 138 ULONG BusInterruptLevel; // Interrupt level 139 ULONG InterruptMode; // Interrupt Mode (Level or Edge) 140 ULONG BusInterruptVector; 141 // Number of channels being supported by one instantiation 142 // of the device extension. Normally (and correctly) one, but 143 // with so many broken PCI IDE controllers being sold, we have 144 // to support them. 145 ULONG NumberChannels; 146 BOOLEAN ChanInfoValid; 147 148 UCHAR NumberLuns; // per channel 149 BOOLEAN LunInfoValid; 150 BOOLEAN ChanHeaderLengthValid; // since v0.42i8 151 152 ULONG AdapterInterfaceType; 153 ULONG ChanHeaderLength; 154 ULONG LunHeaderLength; 155 156 //CHANINFO Chan[0]; 157 158 } ADAPTERINFO, *PADAPTERINFO; 159 160 #ifdef USER_MODE 161 162 typedef enum _INTERFACE_TYPE { 163 InterfaceTypeUndefined = -1, 164 Internal, 165 Isa, 166 Eisa, 167 MicroChannel, 168 TurboChannel, 169 PCIBus, 170 VMEBus, 171 NuBus, 172 PCMCIABus, 173 CBus, 174 MPIBus, 175 MPSABus, 176 ProcessorInternal, 177 InternalPowerBus, 178 PNPISABus, 179 MaximumInterfaceType 180 } INTERFACE_TYPE, *PINTERFACE_TYPE; 181 182 typedef struct _PCI_SLOT_NUMBER { 183 union { 184 struct { 185 ULONG DeviceNumber:5; 186 ULONG FunctionNumber:3; 187 ULONG Reserved:24; 188 } bits; 189 ULONG AsULONG; 190 } u; 191 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER; 192 193 #endif 194 195 #ifndef ATA_FLAGS_DRDY_REQUIRED 196 197 //The ATA_PASS_THROUGH_DIRECT structure is used in conjunction with an IOCTL_ATA_PASS_THROUGH_DIRECT request to instruct the port driver to send an embedded ATA command to the target device. 198 199 typedef struct _ATA_PASS_THROUGH_DIRECT { 200 USHORT Length; 201 USHORT AtaFlags; 202 UCHAR PathId; 203 UCHAR TargetId; 204 UCHAR Lun; 205 UCHAR ReservedAsUchar; 206 ULONG DataTransferLength; 207 ULONG TimeOutValue; 208 ULONG ReservedAsUlong; 209 PVOID DataBuffer; 210 union { 211 UCHAR PreviousTaskFile[8]; 212 IDEREGS Regs; 213 }; 214 union { 215 UCHAR CurrentTaskFile[8]; 216 IDEREGS RegsH; 217 }; 218 } ATA_PASS_THROUGH_DIRECT, *PATA_PASS_THROUGH_DIRECT; 219 220 #define ATA_FLAGS_DRDY_REQUIRED 0x01 // Wait for DRDY status from the device before sending the command to the device. 221 #define ATA_FLAGS_DATA_OUT 0x02 // Write data to the device. 222 #define ATA_FLAGS_DATA_IN 0x04 // Read data from the device. 223 #define ATA_FLAGS_48BIT_COMMAND 0x08 // The ATA command to be send uses the 48 bit LBA feature set. 224 // When this flag is set, the contents of the PreviousTaskFile member in the 225 // ATA_PASS_THROUGH_DIRECT structure should be valid. 226 #define ATA_FLAGS_USE_DMA 0x10 // Set the transfer mode to DMA. 227 #define ATA_FLAGS_NO_MULTIPLE 0x20 // Read single sector only. 228 229 #endif //ATA_FLAGS_DRDY_REQUIRED 230 231 #pragma pack(pop) 232 233 #pragma pack(push, 1) 234 typedef struct _IDEREGS_EX { 235 union { 236 UCHAR bFeaturesReg; // Used for specifying SMART "commands" on input. 237 UCHAR bErrorReg; // Error on output. 238 }; 239 UCHAR bSectorCountReg; // IDE sector count register 240 UCHAR bSectorNumberReg; // IDE sector number register 241 UCHAR bCylLowReg; // IDE low order cylinder value 242 UCHAR bCylHighReg; // IDE high order cylinder value 243 UCHAR bDriveHeadReg; // IDE drive/head register 244 union { 245 UCHAR bCommandReg; // Actual IDE command. 246 UCHAR bStatusReg; // Status register. 247 }; 248 UCHAR bOpFlags; // 00 - send 249 // 01 - read regs 250 // 08 - lba48 251 // 10 - treat timeout as msec 252 253 #define UNIATA_SPTI_EX_SND 0x00 254 #define UNIATA_SPTI_EX_RCV 0x01 255 #define UNIATA_SPTI_EX_LBA48 0x08 256 //#define UNIATA_SPTI_EX_SPEC_TO 0x10 257 //#define UNIATA_SPTI_EX_FREEZE_TO 0x20 // do not reset device on timeout and keep interrupts disabled 258 #define UNIATA_SPTI_EX_USE_DMA 0x10 // Force DMA transfer mode 259 260 // use 'invalid' combination to specify special TO options 261 #define UNIATA_SPTI_EX_SPEC_TO (ATA_FLAGS_DATA_OUT | ATA_FLAGS_DATA_IN) 262 263 UCHAR bFeaturesRegH; // feature (high part for LBA48 mode) 264 UCHAR bSectorCountRegH; // IDE sector count register (high part for LBA48 mode) 265 UCHAR bSectorNumberRegH; // IDE sector number register (high part for LBA48 mode) 266 UCHAR bCylLowRegH; // IDE low order cylinder value (high part for LBA48 mode) 267 UCHAR bCylHighRegH; // IDE high order cylinder value (high part for LBA48 mode) 268 UCHAR bReserved2; // 0 269 } IDEREGS_EX, *PIDEREGS_EX, *LPIDEREGS_EX; 270 271 typedef struct _UNIATA_REG_IO { 272 USHORT RegIDX; 273 UCHAR RegSz:3; // 0=1, 1=2, 2=4, 3=1+1 (for lba48) 4=2+2 (for lba48) 274 UCHAR InOut:1; // 0=in, 1=out 275 UCHAR Reserved:4; 276 UCHAR Reserved1; 277 union { 278 ULONG Data; 279 ULONG d32; 280 USHORT d16[2]; 281 USHORT d8[2]; 282 }; 283 } UNIATA_REG_IO, *PUNIATA_REG_IO; 284 285 typedef struct _UNIATA_REG_IO_HDR { 286 ULONG ItemCount; 287 UNIATA_REG_IO r[1]; 288 } UNIATA_REG_IO_HDR, *PUNIATA_REG_IO_HDR; 289 290 #pragma pack(pop) 291 292 #pragma pack(push, 1) 293 294 typedef struct _UNIATA_CTL { 295 SRB_IO_CONTROL hdr; 296 SCSI_ADDRESS addr; 297 ULONG Reserved; 298 union { 299 UCHAR RawData[1]; 300 ADDREMOVEDEV FindDelDev; 301 SETTRANSFERMODE SetMode; 302 GETTRANSFERMODE GetMode; 303 ADAPTERINFO AdapterInfo; 304 // IDENTIFY_DATA2 LunIdent; 305 // ATA_PASS_THROUGH_DIRECT AtaDirect; 306 GETDRVVERSION Version; 307 UNIATA_REG_IO_HDR RegIo; 308 }; 309 } UNIATA_CTL, *PUNIATA_CTL; 310 311 typedef struct _SCSI_PASS_THROUGH_WITH_BUFFERS { 312 SCSI_PASS_THROUGH spt; 313 ULONG Filler; // realign buffers to double word boundary 314 UCHAR ucSenseBuf[32]; 315 UCHAR ucDataBuf[512]; // recommended minimum 316 } SCSI_PASS_THROUGH_WITH_BUFFERS, *PSCSI_PASS_THROUGH_WITH_BUFFERS; 317 318 typedef struct _SCSI_PASS_THROUGH_DIRECT_WITH_BUFFER { 319 SCSI_PASS_THROUGH_DIRECT sptd; 320 ULONG Filler; // realign buffer to double word boundary 321 UCHAR ucSenseBuf[32]; 322 } SCSI_PASS_THROUGH_DIRECT_WITH_BUFFER, *PSCSI_PASS_THROUGH_DIRECT_WITH_BUFFER; 323 324 #endif //UNIATA_CORE 325 326 #ifdef __cplusplus 327 }; 328 #endif //__cplusplus 329 330 #pragma pack(pop) 331 332 #endif //__UNIATA_IO_CONTROL_CODES__H__ 333