1 /* OPCODE.H (c) Copyright Jan Jaeger, 2000-2009 */ 2 /* Instruction decoding macros and prototypes */ 3 4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */ 5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */ 6 7 #ifndef _OPCODE_H 8 #define _OPCODE_H 9 10 #include "hercules.h" 11 12 #ifndef _CPU_C_ 13 #ifndef _HENGINE_DLL_ 14 #define CPU_DLL_IMPORT DLL_IMPORT 15 #else /* _HENGINE_DLL_ */ 16 #define CPU_DLL_IMPORT extern 17 #endif /* _HENGINE_DLL_ */ 18 #else /* _CPU_C_ */ 19 #define CPU_DLL_IMPORT DLL_EXPORT 20 #endif /* _CPU_C_ */ 21 22 #ifndef _OPCODE_C_ 23 #ifndef _HENGINE_DLL_ 24 #define OPC_DLL_IMPORT DLL_IMPORT 25 #else /* _HENGINE_DLL_ */ 26 #define OPC_DLL_IMPORT extern 27 #endif /* _HENGINE_DLL_ */ 28 #else /* _OPCODE_C_ */ 29 #define OPC_DLL_IMPORT DLL_EXPORT 30 #endif /* _OPCODE_C_ */ 31 32 #if defined(_370) 33 #define _GEN370(_name) &s370_ ## _name, 34 #else 35 #define _GEN370(_name) 36 #endif 37 38 #if defined(_390) 39 #define _GEN390(_name) &s390_ ## _name, 40 #else 41 #define _GEN390(_name) 42 #endif 43 44 #if defined(_900) 45 #define _GEN900(_name) &z900_ ## _name, 46 #else 47 #define _GEN900(_name) 48 #endif 49 50 51 #define GENx___x___x___ \ 52 { \ 53 _GEN370(operation_exception) \ 54 _GEN390(operation_exception) \ 55 _GEN900(operation_exception) \ 56 (void*)&disasm_none, \ 57 (void*)&"?????" "\0" "?" \ 58 } 59 60 #define GENx370x___x___(_name,_format,_mnemonic) \ 61 { \ 62 _GEN370(_name) \ 63 _GEN390(operation_exception) \ 64 _GEN900(operation_exception) \ 65 (void*)&disasm_ ## _format, \ 66 (void*)& _mnemonic "\0" #_name \ 67 } 68 69 #define GENx___x390x___(_name,_format,_mnemonic) \ 70 { \ 71 _GEN370(operation_exception) \ 72 _GEN390(_name) \ 73 _GEN900(operation_exception) \ 74 (void*)&disasm_ ## _format, \ 75 (void*)& _mnemonic "\0" #_name \ 76 } 77 78 #define GENx370x390x___(_name,_format,_mnemonic) \ 79 { \ 80 _GEN370(_name) \ 81 _GEN390(_name) \ 82 _GEN900(operation_exception) \ 83 (void*)&disasm_ ## _format, \ 84 (void*)& _mnemonic "\0" #_name \ 85 } 86 87 #define GENx___x___x900(_name,_format,_mnemonic) \ 88 { \ 89 _GEN370(operation_exception) \ 90 _GEN390(operation_exception) \ 91 _GEN900(_name) \ 92 (void*)&disasm_ ## _format, \ 93 (void*)& _mnemonic "\0" #_name \ 94 } 95 96 #define GENx370x___x900(_name,_format,_mnemonic) \ 97 { \ 98 _GEN370(_name) \ 99 _GEN390(operation_exception) \ 100 _GEN900(_name) \ 101 (void*)&disasm_ ## _format, \ 102 (void*)& _mnemonic "\0" #_name \ 103 } 104 105 #define GENx___x390x900(_name,_format,_mnemonic) \ 106 { \ 107 _GEN370(operation_exception) \ 108 _GEN390(_name) \ 109 _GEN900(_name) \ 110 (void*)&disasm_ ## _format, \ 111 (void*)& _mnemonic "\0" #_name \ 112 } 113 114 #define GENx370x390x900(_name,_format,_mnemonic) \ 115 { \ 116 _GEN370(_name) \ 117 _GEN390(_name) \ 118 _GEN900(_name) \ 119 (void*)&disasm_ ## _format, \ 120 (void*)& _mnemonic "\0" #_name \ 121 } 122 123 /* The following variants of the opcode table definition macros 124 specify 37X (370 EXTENSIONS) instead of 370 to indicate that 125 they are ESA/390 and ESAME instructions back-ported to S/370 */ 126 #define GENx37Xx390x___ GENx370x390x___ 127 #define GENx37Xx___x900 GENx370x___x900 128 #define GENx37Xx390x900 GENx370x390x900 129 130 131 typedef void (ATTR_REGPARM(2) *zz_func) (BYTE inst[], REGS *regs); 132 133 #define ILC(_b) ((_b) < 0x40 ? 2 : (_b) < 0xc0 ? 4 : 6) 134 135 #define REAL_ILC(_regs) \ 136 (likely(!(_regs)->execflag) ? (_regs)->psw.ilc : (_regs)->exrl ? 6 : 4) 137 138 /* Gabor Hoffer (performance option) */ 139 OPC_DLL_IMPORT zz_func s370_opcode_table[]; 140 OPC_DLL_IMPORT zz_func s390_opcode_table[]; 141 OPC_DLL_IMPORT zz_func z900_opcode_table[]; 142 143 OPC_DLL_IMPORT zz_func opcode_table[][GEN_MAXARCH]; 144 OPC_DLL_IMPORT zz_func opcode_01xx[][GEN_MAXARCH]; 145 extern zz_func v_opcode_a4xx[][GEN_MAXARCH]; 146 OPC_DLL_IMPORT zz_func opcode_a5xx[][GEN_MAXARCH]; 147 extern zz_func v_opcode_a5xx[][GEN_MAXARCH]; 148 extern zz_func v_opcode_a6xx[][GEN_MAXARCH]; 149 OPC_DLL_IMPORT zz_func opcode_a7xx[][GEN_MAXARCH]; 150 OPC_DLL_IMPORT zz_func opcode_b2xx[][GEN_MAXARCH]; 151 OPC_DLL_IMPORT zz_func opcode_b3xx[][GEN_MAXARCH]; 152 OPC_DLL_IMPORT zz_func opcode_b9xx[][GEN_MAXARCH]; 153 OPC_DLL_IMPORT zz_func opcode_c0xx[][GEN_MAXARCH]; 154 OPC_DLL_IMPORT zz_func opcode_c2xx[][GEN_MAXARCH]; /*@Z9*/ 155 OPC_DLL_IMPORT zz_func opcode_c4xx[][GEN_MAXARCH]; /*208*/ 156 OPC_DLL_IMPORT zz_func opcode_c6xx[][GEN_MAXARCH]; /*208*/ 157 OPC_DLL_IMPORT zz_func opcode_c8xx[][GEN_MAXARCH]; 158 OPC_DLL_IMPORT zz_func opcode_ccxx[][GEN_MAXARCH]; /*810*/ 159 OPC_DLL_IMPORT zz_func opcode_e3xx[][GEN_MAXARCH]; 160 OPC_DLL_IMPORT zz_func opcode_e4xx[256][GEN_MAXARCH]; 161 extern zz_func v_opcode_e4xx[][GEN_MAXARCH]; 162 OPC_DLL_IMPORT zz_func opcode_e5xx[][GEN_MAXARCH]; 163 OPC_DLL_IMPORT zz_func opcode_e6xx[][GEN_MAXARCH]; 164 OPC_DLL_IMPORT zz_func opcode_ebxx[][GEN_MAXARCH]; 165 OPC_DLL_IMPORT zz_func opcode_ecxx[][GEN_MAXARCH]; 166 OPC_DLL_IMPORT zz_func opcode_edxx[][GEN_MAXARCH]; 167 168 169 #define DISASM_INSTRUCTION(_inst, p) \ 170 disasm_table((_inst), 0, p) 171 172 typedef int (*func) (); 173 174 extern int disasm_table (BYTE inst[], char mnemonic[], char *p); 175 176 177 #if defined(OPTION_INSTRUCTION_COUNTING) 178 179 #define COUNT_INST(_inst, _regs) \ 180 do { \ 181 int used; \ 182 switch((_inst)[0]) { \ 183 case 0x01: \ 184 used = sysblk.imap01[(_inst)[1]]++; \ 185 break; \ 186 case 0xA4: \ 187 used = sysblk.imapa4[(_inst)[1]]++; \ 188 break; \ 189 case 0xA5: \ 190 used = sysblk.imapa5[(_inst)[1] & 0x0F]++; \ 191 break; \ 192 case 0xA6: \ 193 used = sysblk.imapa6[(_inst)[1]]++; \ 194 break; \ 195 case 0xA7: \ 196 used = sysblk.imapa7[(_inst)[1] & 0x0F]++; \ 197 break; \ 198 case 0xB2: \ 199 used = sysblk.imapb2[(_inst)[1]]++; \ 200 break; \ 201 case 0xB3: \ 202 used = sysblk.imapb3[(_inst)[1]]++; \ 203 break; \ 204 case 0xB9: \ 205 used = sysblk.imapb9[(_inst)[1]]++; \ 206 break; \ 207 case 0xC0: \ 208 used = sysblk.imapc0[(_inst)[1] & 0x0F]++; \ 209 break; \ 210 case 0xC2: /*@Z9*/ \ 211 used = sysblk.imapc2[(_inst)[1] & 0x0F]++; /*@Z9*/ \ 212 break; /*@Z9*/ \ 213 case 0xC4: /*208*/ \ 214 used = sysblk.imapc4[(_inst)[1] & 0x0F]++; /*208*/ \ 215 break; /*208*/ \ 216 case 0xC6: /*208*/ \ 217 used = sysblk.imapc6[(_inst)[1] & 0x0F]++; /*208*/ \ 218 break; /*208*/ \ 219 case 0xC8: \ 220 used = sysblk.imapc8[(_inst)[1] & 0x0F]++; \ 221 break; \ 222 case 0xE3: \ 223 used = sysblk.imape3[(_inst)[5]]++; \ 224 break; \ 225 case 0xE4: \ 226 used = sysblk.imape4[(_inst)[1]]++; \ 227 break; \ 228 case 0xE5: \ 229 used = sysblk.imape5[(_inst)[1]]++; \ 230 break; \ 231 case 0xEB: \ 232 used = sysblk.imapeb[(_inst)[5]]++; \ 233 break; \ 234 case 0xEC: \ 235 used = sysblk.imapec[(_inst)[5]]++; \ 236 break; \ 237 case 0xED: \ 238 used = sysblk.imaped[(_inst)[5]]++; \ 239 break; \ 240 default: \ 241 used = sysblk.imapxx[(_inst)[0]]++; \ 242 } \ 243 if(!used) \ 244 { \ 245 obtain_lock( &sysblk.icount_lock ); \ 246 logmsg("First use: "); \ 247 ARCH_DEP(display_inst) ((_regs), (_inst)); \ 248 release_lock( &sysblk.icount_lock ); \ 249 } \ 250 } while(0) 251 252 #else 253 254 #define COUNT_INST(_inst, _regs) 255 256 #endif 257 258 #if defined(_FEATURE_SIE) 259 #define SIE_MODE(_register_context) \ 260 unlikely((_register_context)->sie_mode) 261 #define SIE_STATE(_register_context) \ 262 ((_register_context)->sie_state) 263 #define SIE_FEATB(_regs, _feat_byte, _feat_name) \ 264 (((_regs)->siebk->SIE_ ## _feat_byte) & (SIE_ ## _feat_byte ## _ ## _feat_name)) 265 #define SIE_STATB(_regs, _feat_byte, _feat_name) \ 266 (SIE_MODE((_regs)) && SIE_FEATB((_regs), _feat_byte, _feat_name) ) 267 #define SIE_STATNB(_regs, _feat_byte, _feat_name) \ 268 (SIE_MODE((_regs)) && !SIE_FEATB((_regs), _feat_byte, _feat_name) ) 269 #else 270 #define SIE_MODE(_register_context) (0) 271 #define SIE_STATE(_register_context) (0) 272 #define SIE_FEATB(_register_context, _feat_byte, _feat_name) (0) 273 #define SIE_STATB(_register_context, _feat_byte, _feat_name) (0) 274 #endif 275 276 277 /* The footprint_buffer option saves a copy of the register context 278 every time an instruction is executed. This is for problem 279 determination only, as it severely impacts performance. *JJ */ 280 281 #if defined(OPTION_FOOTPRINT_BUFFER) 282 #define FOOTPRINT(_ip, _regs) \ 283 do { \ 284 sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]] = *(_regs); \ 285 memcpy(&sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]++].inst,(_ip),6); \ 286 sysblk.footprptr[(_regs)->cpuad] &= OPTION_FOOTPRINT_BUFFER - 1; \ 287 } while(0) 288 #endif 289 290 #if !defined(FOOTPRINT) 291 #define FOOTPRINT(_ip, _regs) 292 #endif 293 294 /* PSW Instruction Address manipulation */ 295 296 #define _PSW_IA(_regs, _n) \ 297 (VADR)((_regs)->AIV + ((intptr_t)(_regs)->ip - (intptr_t)(_regs)->aip) + (_n)) 298 299 #define PSW_IA(_regs, _n) \ 300 (_PSW_IA((_regs), (_n)) & ADDRESS_MAXWRAP((_regs))) 301 302 #define SET_PSW_IA(_regs) \ 303 do { \ 304 if ((_regs)->aie) (_regs)->psw.IA = PSW_IA((_regs), 0); \ 305 } while (0) 306 307 #define UPD_PSW_IA(_regs, _addr) \ 308 do { \ 309 (_regs)->psw.IA = (_addr) & ADDRESS_MAXWRAP(_regs); \ 310 if (likely((_regs)->aie != NULL)) { \ 311 if (likely((_regs)->AIV == ((_regs)->psw.IA & (PAGEFRAME_PAGEMASK|1)))) \ 312 (_regs)->ip = _PSW_IA_MAIN((_regs), (_regs)->psw.IA); \ 313 else \ 314 (_regs)->aie = NULL; \ 315 } \ 316 } while (0) 317 318 /* 319 * The next three macros are used by branch-and-link type instructions 320 * where the addressing mode is known. 321 * Note that wrap is not performed for PSW_IA64 and for PSW_IA31. 322 * For the latter, we expect branch-and-link code to `or' the hi bit 323 * on so there is no need to `and' it off. 324 */ 325 #define PSW_IA64(_regs, _n) \ 326 ((_regs)->AIV \ 327 + (((uintptr_t)(_regs)->ip + (unsigned int)(_n)) - (uintptr_t)(_regs)->aip)) 328 #define PSW_IA31(_regs, _n) \ 329 ((_regs)->AIV_L + ((uintptr_t)(_regs)->ip + (unsigned int)(_n)) \ 330 - (uintptr_t)(_regs)->aip) 331 #define PSW_IA24(_regs, _n) \ 332 (((_regs)->AIV_L + ((uintptr_t)(_regs)->ip + (unsigned int)(_n)) \ 333 - (uintptr_t)(_regs)->aip) & AMASK24) 334 335 /* Accelerator for instruction addresses */ 336 337 #define INVALIDATE_AIA(_regs) \ 338 do { \ 339 if ((_regs)->aie) { \ 340 (_regs)->psw.IA = PSW_IA((_regs), 0); \ 341 (_regs)->aie = NULL; \ 342 } \ 343 } while (0) 344 345 #define INVALIDATE_AIA_MAIN(_regs, _main) \ 346 do { \ 347 if ((_main) == (_regs)->aip && (_regs)->aie) { \ 348 (_regs)->psw.IA = PSW_IA((_regs), 0); \ 349 (_regs)->aie = NULL; \ 350 } \ 351 } while (0) 352 353 #if 1 354 #define _PSW_IA_MAIN(_regs, _addr) \ 355 ((BYTE *)((uintptr_t)(_regs)->aip | (uintptr_t)((_addr) & PAGEFRAME_BYTEMASK))) 356 #else 357 #define _PSW_IA_MAIN(_regs, _addr) \ 358 ((BYTE *)((_regs)->aim ^ (uintptr_t)(_addr))) 359 #endif 360 361 #define _VALID_IP(_regs, _exec) \ 362 ( \ 363 ( !(_exec) && (_regs)->ip < (_regs)->aie ) \ 364 || \ 365 ( (_exec) && ((_regs)->ET & (PAGEFRAME_PAGEMASK|0x01)) == (_regs)->AIV \ 366 && _PSW_IA_MAIN((_regs), (_regs)->ET) < (_regs)->aie \ 367 ) \ 368 ) 369 370 /* Instruction fetching */ 371 372 #define INSTRUCTION_FETCH(_regs, _exec) \ 373 likely(_VALID_IP((_regs),(_exec))) \ 374 ? ((_exec) ? _PSW_IA_MAIN((_regs), (_regs)->ET) : (_regs)->ip) \ 375 : ARCH_DEP(instfetch) ((_regs), (_exec)) 376 377 /* Instruction execution */ 378 379 #define EXECUTE_INSTRUCTION(_ip, _regs) \ 380 do { \ 381 FOOTPRINT ((_ip), (_regs)); \ 382 COUNT_INST ((_ip), (_regs)); \ 383 (_regs)->ARCH_DEP(opcode_table)[_ip[0]]((_ip), (_regs)); \ 384 } while(0) 385 386 #define UNROLLED_EXECUTE(_regs) \ 387 if ((_regs)->ip >= (_regs)->aie) break; \ 388 EXECUTE_INSTRUCTION((_regs)->ip, (_regs)) 389 390 /* Branching */ 391 392 #define SUCCESSFUL_BRANCH(_regs, _addr, _len) \ 393 do { \ 394 VADR _newia; \ 395 UPDATE_BEAR((_regs), 0); \ 396 _newia = (_addr) & ADDRESS_MAXWRAP((_regs)); \ 397 if (likely(!(_regs)->permode && !(_regs)->execflag) \ 398 && likely((_newia & (PAGEFRAME_PAGEMASK|0x01)) == (_regs)->AIV)) { \ 399 (_regs)->ip = (BYTE *)((uintptr_t)(_regs)->aim ^ (uintptr_t)_newia); \ 400 return; \ 401 } else { \ 402 if (unlikely((_regs)->execflag)) \ 403 UPDATE_BEAR((_regs), (_len) - ((_regs)->exrl ? 6 : 4)); \ 404 (_regs)->psw.IA = _newia; \ 405 (_regs)->aie = NULL; \ 406 PER_SB((_regs), (_regs)->psw.IA); \ 407 } \ 408 } while (0) 409 410 #define SUCCESSFUL_RELATIVE_BRANCH(_regs, _offset, _len) \ 411 do { \ 412 UPDATE_BEAR((_regs), 0); \ 413 if (likely(!(_regs)->permode && !(_regs)->execflag) \ 414 && likely((_regs)->ip + (_offset) >= (_regs)->aip) \ 415 && likely((_regs)->ip + (_offset) < (_regs)->aie)) { \ 416 (_regs)->ip += (_offset); \ 417 return; \ 418 } else { \ 419 if (likely(!(_regs)->execflag)) \ 420 (_regs)->psw.IA = PSW_IA((_regs), (_offset)); \ 421 else { \ 422 UPDATE_BEAR((_regs), (_len) - ((_regs)->exrl ? 6 : 4)); \ 423 (_regs)->psw.IA = (_regs)->ET + (_offset); \ 424 (_regs)->psw.IA &= ADDRESS_MAXWRAP((_regs)); \ 425 } \ 426 (_regs)->aie = NULL; \ 427 PER_SB((_regs), (_regs)->psw.IA); \ 428 } \ 429 } while (0) 430 431 /* BRCL, BRASL can branch +/- 4G. This is problematic on a 32 bit host */ 432 #define SUCCESSFUL_RELATIVE_BRANCH_LONG(_regs, _offset) \ 433 do { \ 434 UPDATE_BEAR((_regs), 0); \ 435 if (likely(!(_regs)->permode && !(_regs)->execflag) \ 436 && likely((_offset) > -4096) \ 437 && likely((_offset) < 4096) \ 438 && likely((_regs)->ip + (_offset) >= (_regs)->aip) \ 439 && likely((_regs)->ip + (_offset) < (_regs)->aie)) { \ 440 (_regs)->ip += (_offset); \ 441 return; \ 442 } else { \ 443 if (likely(!(_regs)->execflag)) \ 444 (_regs)->psw.IA = PSW_IA((_regs), (_offset)); \ 445 else { \ 446 UPDATE_BEAR((_regs), 6 - ((_regs)->exrl ? 6 : 4)); \ 447 (_regs)->psw.IA = (_regs)->ET + (_offset); \ 448 (_regs)->psw.IA &= ADDRESS_MAXWRAP((_regs)); \ 449 } \ 450 (_regs)->aie = NULL; \ 451 PER_SB((_regs), (_regs)->psw.IA); \ 452 } \ 453 } while (0) 454 455 /* CPU Stepping or Tracing */ 456 457 #define CPU_STEPPING(_regs, _ilc) \ 458 ( \ 459 sysblk.inststep \ 460 && ( \ 461 (sysblk.stepaddr[0] == 0 && sysblk.stepaddr[1] == 0) \ 462 || (sysblk.stepaddr[0] <= sysblk.stepaddr[1] \ 463 && PSW_IA((_regs), -(_ilc)) >= sysblk.stepaddr[0] \ 464 && PSW_IA((_regs), -(_ilc)) <= sysblk.stepaddr[1] \ 465 ) \ 466 || (sysblk.stepaddr[0] > sysblk.stepaddr[1] \ 467 && PSW_IA((_regs), -(_ilc)) >= sysblk.stepaddr[1] \ 468 && PSW_IA((_regs), -(_ilc)) <= sysblk.stepaddr[0] \ 469 ) \ 470 ) \ 471 ) 472 473 #define CPU_TRACING(_regs, _ilc) \ 474 ( \ 475 sysblk.insttrace \ 476 && ( \ 477 (sysblk.traceaddr[0] == 0 && sysblk.traceaddr[1] == 0) \ 478 || (sysblk.traceaddr[0] <= sysblk.traceaddr[1] \ 479 && PSW_IA((_regs), -(_ilc)) >= sysblk.traceaddr[0] \ 480 && PSW_IA((_regs), -(_ilc)) <= sysblk.traceaddr[1] \ 481 ) \ 482 || (sysblk.traceaddr[0] > sysblk.traceaddr[1] \ 483 && PSW_IA((_regs), -(_ilc)) >= sysblk.traceaddr[1] \ 484 && PSW_IA((_regs), -(_ilc)) <= sysblk.traceaddr[0] \ 485 ) \ 486 ) \ 487 ) 488 489 #define CPU_STEPPING_OR_TRACING(_regs, _ilc) \ 490 ( unlikely((_regs)->tracing) && \ 491 (CPU_STEPPING((_regs), (_ilc)) || CPU_TRACING((_regs), (_ilc))) \ 492 ) 493 494 #define CPU_TRACING_ALL \ 495 (sysblk.insttrace && sysblk.traceaddr[0] == 0 && sysblk.traceaddr[1] == 0) 496 497 #define CPU_STEPPING_ALL \ 498 (sysblk.inststep && sysblk.stepaddr[0] == 0 && sysblk.stepaddr[1] == 0) 499 500 #define CPU_STEPPING_OR_TRACING_ALL \ 501 ( CPU_TRACING_ALL || CPU_STEPPING_ALL ) 502 503 504 #define RETURN_INTCHECK(_regs) \ 505 longjmp((_regs)->progjmp, SIE_NO_INTERCEPT) 506 507 #define ODD_CHECK(_r, _regs) \ 508 if( (_r) & 1 ) \ 509 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 510 511 #define ODD2_CHECK(_r1, _r2, _regs) \ 512 if( ((_r1) & 1) || ((_r2) & 1) ) \ 513 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 514 515 #define HW_CHECK(_value, _regs) \ 516 if( (_value) & 1 ) \ 517 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 518 519 #define FW_CHECK(_value, _regs) \ 520 if( (_value) & 3 ) \ 521 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 522 523 #define DW_CHECK(_value, _regs) \ 524 if( (_value) & 7 ) \ 525 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 526 527 #define QW_CHECK(_value, _regs) \ 528 if( (_value) & 15 ) \ 529 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 530 531 /* Program check if m is not 0, 1, or 4 to 7 */ 532 #define HFPM_CHECK(_m, _regs) \ 533 if (((_m) == 2) || ((_m) == 3) || ((_m) & 8)) \ 534 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 535 536 #define PRIV_CHECK(_regs) \ 537 if( PROBSTATE(&(_regs)->psw) ) \ 538 (_regs)->program_interrupt( (_regs), PGM_PRIVILEGED_OPERATION_EXCEPTION) 539 540 /* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating 541 the lower-numbered register of a floating-point register pair) */ 542 #define BFPREGPAIR_CHECK(_r, _regs) \ 543 if( ((_r) & 2) ) \ 544 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 545 546 /* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13 547 (lower-numbered register of a floating-point register pair) */ 548 #define BFPREGPAIR2_CHECK(_r1, _r2, _regs) \ 549 if( ((_r1) & 2) || ((_r2) & 2) ) \ 550 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 551 552 /* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating 553 the lower-numbered register of a floating-point register pair) */ 554 #define DFPREGPAIR_CHECK(_r, _regs) \ 555 if( ((_r) & 2) ) \ 556 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 557 558 /* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13 559 (lower-numbered register of a floating-point register pair) */ 560 #define DFPREGPAIR2_CHECK(_r1, _r2, _regs) \ 561 if( ((_r1) & 2) || ((_r2) & 2) ) \ 562 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 563 564 /* Program check if r1, r2, r3 are not all 0,1,4,5,8,9,12, or 13 565 (lower-numbered register of a floating-point register pair) */ 566 #define DFPREGPAIR3_CHECK(_r1, _r2, _r3, _regs) \ 567 if( ((_r1) & 2) || ((_r2) & 2) || ((_r3) & 2) ) \ 568 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 569 570 /* Program check if fpc is not valid contents for FPC register */ 571 #if defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY) /*810*/ 572 #define FPC_BRM FPC_BRM_3BIT 573 #define FPC_CHECK(_fpc, _regs) \ 574 if(((_fpc) & FPC_RESV_FPX) \ 575 || ((_fpc) & FPC_BRM_3BIT) == BRM_RESV4 \ 576 || ((_fpc) & FPC_BRM_3BIT) == BRM_RESV5 \ 577 || ((_fpc) & FPC_BRM_3BIT) == BRM_RESV6) \ 578 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 579 #else /*!defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/ 580 #define FPC_BRM FPC_BRM_2BIT 581 #define FPC_CHECK(_fpc, _regs) \ 582 if((_fpc) & FPC_RESERVED) \ 583 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 584 #endif /*!defined(FEATURE_FLOATING_POINT_EXTENSION_FACILITY)*/ /*810*/ 585 586 #define SSID_CHECK(_regs) \ 587 if((!((_regs)->GR_LHH(1) & 0x0001)) \ 588 || (_regs)->GR_LHH(1) > (0x0001|((FEATURE_LCSS_MAX-1) << 1))) \ 589 (_regs)->program_interrupt( (_regs), PGM_OPERAND_EXCEPTION) 590 591 #define IOID_TO_SSID(_ioid) \ 592 ((_ioid) >> 16) 593 594 #define IOID_TO_LCSS(_ioid) \ 595 ((_ioid) >> 17) 596 597 #define SSID_TO_LCSS(_ssid) \ 598 ((_ssid) >> 1) 599 600 #define LCSS_TO_SSID(_lcss) \ 601 (((_lcss) << 1) | 1) 602 603 #define PER_RANGE_CHECK(_addr, _low, _high) \ 604 ( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \ 605 (((_addr) >= ((_low) & MAXADDRESS)) && (_addr) <= ((_high) & MAXADDRESS)) : \ 606 (((_addr) >= ((_low) & MAXADDRESS)) || (_addr) <= ((_high) & MAXADDRESS)) ) 607 608 #define PER_RANGE_CHECK2(_addr1, _addr2, _low, _high) \ 609 ( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \ 610 (((_addr1) >= ((_low) & MAXADDRESS)) && (_addr1) <= ((_high) & MAXADDRESS)) || \ 611 (((_addr2) >= ((_low) & MAXADDRESS)) && (_addr2) <= ((_high) & MAXADDRESS)) || \ 612 (((_addr1) <= ((_low) & MAXADDRESS)) && (_addr2) >= ((_high) & MAXADDRESS)) : \ 613 (((_addr2) >= ((_low) & MAXADDRESS)) || (_addr1) <= ((_high) & MAXADDRESS)) ) 614 615 #ifdef WORDS_BIGENDIAN 616 #define CSWAP16(_x) (_x) 617 #define CSWAP32(_x) (_x) 618 #define CSWAP64(_x) (_x) 619 #else 620 #define CSWAP16(_x) bswap_16(_x) 621 #define CSWAP32(_x) bswap_32(_x) 622 #define CSWAP64(_x) bswap_64(_x) 623 #endif 624 625 #define FETCH_HW(_value, _storage) (_value) = fetch_hw(_storage) 626 #define FETCH_FW(_value, _storage) (_value) = fetch_fw(_storage) 627 #define FETCH_DW(_value, _storage) (_value) = fetch_dw(_storage) 628 629 #define STORE_HW(_storage, _value) store_hw(_storage, _value) 630 #define STORE_FW(_storage, _value) store_fw(_storage, _value) 631 #define STORE_DW(_storage, _value) store_dw(_storage, _value) 632 633 #include "machdep.h" 634 635 #endif /*!defined(_OPCODE_H)*/ 636 637 #undef SIE_ACTIVE 638 #if defined(FEATURE_INTERPRETIVE_EXECUTION) 639 #define SIE_ACTIVE(_regs) ((_regs)->sie_active) 640 #else 641 #define SIE_ACTIVE(_regs) (0) 642 #endif 643 644 #undef MULTIPLE_CONTROLLED_DATA_SPACE 645 #if defined(_FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE) 646 #define MULTIPLE_CONTROLLED_DATA_SPACE(_regs) \ 647 ( SIE_FEATB((_regs), MX, XC) && AR_BIT(&(_regs)->psw) ) 648 #else 649 #define MULTIPLE_CONTROLLED_DATA_SPACE(_regs) (0) 650 #endif 651 652 /* PER3 Breaking Event Address Recording (BEAR) */ 653 654 #undef UPDATE_BEAR 655 #undef SET_BEAR_REG 656 657 #if defined(FEATURE_PER3) 658 #define UPDATE_BEAR(_regs, _n) (_regs)->bear_ip = (_regs)->ip + (_n) 659 #define SET_BEAR_REG(_regs, _ip) \ 660 do { \ 661 if ((_ip)) { \ 662 (_regs)->bear = (_regs)->AIV \ 663 + (intptr_t)((_ip) - (_regs)->aip); \ 664 (_regs)->bear &= ADDRESS_MAXWRAP((_regs)); \ 665 regs->bear_ip = NULL; \ 666 } \ 667 } while (0) 668 #else 669 #define UPDATE_BEAR(_regs, _n) while (0) 670 #define SET_BEAR_REG(_regs, _ip) while (0) 671 #endif 672 673 /* Set addressing mode (BASSM, BSM) */ 674 675 #undef SET_ADDRESSING_MODE 676 #if defined(FEATURE_ESAME) 677 #define SET_ADDRESSING_MODE(_regs, _addr) \ 678 do { \ 679 if ((_addr) & 1) { \ 680 (_regs)->psw.amode64 = regs->psw.amode = 1; \ 681 (_regs)->psw.AMASK = AMASK64; \ 682 (_addr) ^= 1; \ 683 } else if ((_addr) & 0x80000000) { \ 684 (_regs)->psw.amode64 = 0; \ 685 (_regs)->psw.amode = 1; \ 686 (_regs)->psw.AMASK = AMASK31; \ 687 } else { \ 688 (_regs)->psw.amode64 = (_regs)->psw.amode = 0; \ 689 (_regs)->psw.AMASK = AMASK24; \ 690 } \ 691 } while (0) 692 #else /* !defined(FEATURE_ESAME) */ 693 #define SET_ADDRESSING_MODE(_regs, _addr) \ 694 do { \ 695 if ((_addr) & 0x80000000) { \ 696 (_regs)->psw.amode = 1; \ 697 (_regs)->psw.AMASK = AMASK31; \ 698 } else { \ 699 (_regs)->psw.amode = 0; \ 700 (_regs)->psw.AMASK = AMASK24; \ 701 } \ 702 } while (0) 703 #endif 704 705 #undef HFPREG_CHECK 706 #undef HFPREG2_CHECK 707 #undef HFPODD_CHECK 708 #undef HFPODD2_CHECK 709 #undef FPR2I 710 #undef FPREX 711 712 #if defined(FEATURE_BASIC_FP_EXTENSIONS) 713 #if defined(_FEATURE_SIE) 714 715 /* Program check if BFP instruction is executed when AFP control is zero */ 716 #define BFPINST_CHECK(_regs) \ 717 if( !((_regs)->CR(0) & CR0_AFP) \ 718 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 719 (_regs)->dxc = DXC_BFP_INSTRUCTION; \ 720 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 721 } 722 723 /* Program check if DFP instruction is executed when AFP control is zero */ 724 #define DFPINST_CHECK(_regs) \ 725 if( !((_regs)->CR(0) & CR0_AFP) \ 726 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 727 (_regs)->dxc = DXC_DFP_INSTRUCTION; \ 728 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 729 } 730 731 /* Program check if r1 is not 0, 2, 4, or 6 */ 732 #define HFPREG_CHECK(_r, _regs) \ 733 if( !((_regs)->CR(0) & CR0_AFP) \ 734 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 735 if( (_r) & 9 ) { \ 736 (_regs)->dxc = DXC_AFP_REGISTER; \ 737 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 738 } \ 739 } 740 741 /* Program check if r1 and r2 are not 0, 2, 4, or 6 */ 742 #define HFPREG2_CHECK(_r1, _r2, _regs) \ 743 if( !((_regs)->CR(0) & CR0_AFP) \ 744 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 745 if( ((_r1) & 9) || ((_r2) & 9) ) { \ 746 (_regs)->dxc = DXC_AFP_REGISTER; \ 747 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 748 } \ 749 } 750 751 /* Program check if r1 is not 0 or 4 */ 752 #define HFPODD_CHECK(_r, _regs) \ 753 if( (_r) & 2 ) \ 754 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \ 755 else if( !((_regs)->CR(0) & CR0_AFP) \ 756 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 757 if( (_r) & 9 ) { \ 758 (_regs)->dxc = DXC_AFP_REGISTER; \ 759 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 760 } \ 761 } 762 763 /* Program check if r1 and r2 are not 0 or 4 */ 764 #define HFPODD2_CHECK(_r1, _r2, _regs) \ 765 if( ((_r1) & 2) || ((_r2) & 2) ) \ 766 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \ 767 else if( !((_regs)->CR(0) & CR0_AFP) \ 768 || (SIE_MODE((_regs)) && !((_regs)->hostregs->CR(0) & CR0_AFP)) ) { \ 769 if( ((_r1) & 9) || ((_r2) & 9) ) { \ 770 (_regs)->dxc = DXC_AFP_REGISTER; \ 771 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 772 } \ 773 } 774 #else /*!defined(_FEATURE_SIE)*/ 775 776 /* Program check if BFP instruction is executed when AFP control is zero */ 777 #define BFPINST_CHECK(_regs) \ 778 if( !((_regs)->CR(0) & CR0_AFP) ) { \ 779 (_regs)->dxc = DXC_BFP_INSTRUCTION; \ 780 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 781 } 782 783 /* Program check if DFP instruction is executed when AFP control is zero */ 784 #define DFPINST_CHECK(_regs) \ 785 if( !((_regs)->CR(0) & CR0_AFP) ) { \ 786 (_regs)->dxc = DXC_DFP_INSTRUCTION; \ 787 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 788 } 789 790 791 /* Program check if r1 is not 0, 2, 4, or 6 */ 792 #define HFPREG_CHECK(_r, _regs) \ 793 if( !((_regs)->CR(0) & CR0_AFP) ) { \ 794 if( (_r) & 9 ) { \ 795 (_regs)->dxc = DXC_AFP_REGISTER; \ 796 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 797 } \ 798 } 799 800 /* Program check if r1 and r2 are not 0, 2, 4, or 6 */ 801 #define HFPREG2_CHECK(_r1, _r2, _regs) \ 802 if( !((_regs)->CR(0) & CR0_AFP) ) { \ 803 if( ((_r1) & 9) || ((_r2) & 9) ) { \ 804 (_regs)->dxc = DXC_AFP_REGISTER; \ 805 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 806 } \ 807 } 808 809 /* Program check if r1 is not 0 or 4 */ 810 #define HFPODD_CHECK(_r, _regs) \ 811 if( (_r) & 2 ) \ 812 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \ 813 else if( !((_regs)->CR(0) & CR0_AFP) ) { \ 814 if( (_r) & 9 ) { \ 815 (_regs)->dxc = DXC_AFP_REGISTER; \ 816 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 817 } \ 818 } 819 820 /* Program check if r1 and r2 are not 0 or 4 */ 821 #define HFPODD2_CHECK(_r1, _r2, _regs) \ 822 if( ((_r1) & 2) || ((_r2) & 2) ) \ 823 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION); \ 824 else if( !((_regs)->CR(0) & CR0_AFP) ) { \ 825 if( ((_r1) & 9) || ((_r2) & 9) ) { \ 826 (_regs)->dxc = DXC_AFP_REGISTER; \ 827 (_regs)->program_interrupt( (_regs), PGM_DATA_EXCEPTION); \ 828 } \ 829 } 830 831 #endif /*!defined(_FEATURE_SIE)*/ 832 833 834 /* Convert fpr to index */ 835 #define FPR2I(_r) \ 836 ((_r) << 1) 837 838 /* Offset of extended register */ 839 #define FPREX 4 840 841 #else /*!defined(FEATURE_BASIC_FP_EXTENSIONS)*/ 842 843 /* Program check if r1 is not 0, 2, 4, or 6 */ 844 #define HFPREG_CHECK(_r, _regs) \ 845 if( (_r) & 9 ) \ 846 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 847 848 /* Program check if r1 and r2 are not 0, 2, 4, or 6 */ 849 #define HFPREG2_CHECK(_r1, _r2, _regs) \ 850 if( ((_r1) & 9) || ((_r2) & 9) ) \ 851 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 852 853 /* Program check if r1 is not 0 or 4 */ 854 #define HFPODD_CHECK(_r, _regs) \ 855 if( (_r) & 11 ) \ 856 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 857 858 /* Program check if r1 and r2 are not 0 or 4 */ 859 #define HFPODD2_CHECK(_r1, _r2, _regs) \ 860 if( ((_r1) & 11) || ((_r2) & 11) ) \ 861 (_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION) 862 863 /* Convert fpr to index */ 864 #define FPR2I(_r) \ 865 (_r) 866 867 /* Offset of extended register */ 868 #define FPREX 2 869 870 #endif /*!defined(FEATURE_BASIC_FP_EXTENSIONS)*/ 871 872 #define TLBIX(_addr) (((VADR_L)(_addr) >> TLB_PAGESHIFT) & TLB_MASK) 873 874 #define MAINADDR(_main, _addr) \ 875 (BYTE*)((uintptr_t)(_main) ^ (uintptr_t)(_addr)) 876 877 #define NEW_MAINADDR(_regs, _addr, _aaddr) \ 878 (BYTE*)((uintptr_t)((_regs)->mainstor \ 879 + (uintptr_t)(_aaddr)) \ 880 ^ (uintptr_t)((_addr) & TLB_PAGEMASK)) 881 882 /* Perform invalidation after storage key update. 883 * If the REF or CHANGE bit is turned off for an absolute 884 * address then we need to invalidate any cached entries 885 * for that address on *all* CPUs. 886 * FIXME: Synchronization, esp for the CHANGE bit, should 887 * be tighter than what is provided here. 888 */ 889 890 #define STORKEY_INVALIDATE(_regs, _n) \ 891 do { \ 892 BYTE *mn; \ 893 mn = (_regs)->mainstor + ((_n) & PAGEFRAME_PAGEMASK); \ 894 ARCH_DEP(invalidate_tlbe)((_regs), mn); \ 895 if (sysblk.cpus > 1) { \ 896 int i; \ 897 OBTAIN_INTLOCK ((_regs)); \ 898 for (i = 0; i < HI_CPU; i++) { \ 899 if (IS_CPU_ONLINE(i) && i != (_regs)->cpuad) { \ 900 if ( sysblk.waiting_mask & CPU_BIT(i) ) \ 901 ARCH_DEP(invalidate_tlbe)(sysblk.regs[i], mn); \ 902 else { \ 903 ON_IC_INTERRUPT(sysblk.regs[i]); \ 904 if (!sysblk.regs[i]->invalidate) { \ 905 sysblk.regs[i]->invalidate = 1; \ 906 sysblk.regs[i]->invalidate_main = mn; \ 907 } else \ 908 sysblk.regs[i]->invalidate_main = NULL; \ 909 } \ 910 } \ 911 } \ 912 RELEASE_INTLOCK((_regs)); \ 913 } \ 914 } while (0) 915 916 #if defined(INLINE_STORE_FETCH_ADDR_CHECK) 917 #define FETCH_MAIN_ABSOLUTE(_addr, _regs, _len) \ 918 ARCH_DEP(fetch_main_absolute)((_addr), (_regs), (_len)) 919 #else 920 #define FETCH_MAIN_ABSOLUTE(_addr, _regs, _len) \ 921 ARCH_DEP(fetch_main_absolute)((_addr), (_regs)) 922 #endif 923 924 #define INST_UPDATE_PSW(_regs, _len, _ilc) \ 925 do { \ 926 if (_len) (_regs)->ip += (_len); \ 927 if (_ilc) (_regs)->psw.ilc = (_ilc); \ 928 } while(0) 929 930 /* Instruction decoders */ 931 932 /* 933 * A decoder is placed at the start of each instruction. The purpose 934 * of a decoder is to extract the operand fields according to the 935 * instruction format; to increment the instruction address (IA) field 936 * of the PSW by 2, 4, or 6 bytes; and to set the instruction length 937 * code (ILC) field of the PSW in case a program check occurs. 938 * 939 * Certain decoders have additional forms with 0 and _B suffixes. 940 * - the 0 suffix version does not update the PSW ILC. 941 * - the _B suffix version updates neither the PSW ILC nor the PSW IA. 942 * 943 * The "0" versions of the decoders are chosen whenever we know 944 * that past this point, no program interrupt will be generated 945 * (like most general instructions when no storage access is needed) 946 * therefore needing simpler prologue code. 947 * The "_B" versions for some of the decoders are intended for 948 * "branch" type operations where updating the PSW IA to IA+ILC 949 * should only be done after the branch is deemed impossible. 950 */ 951 952 #undef DECODER_TEST_RRE 953 #define DECODER_TEST_RRF_R 954 #define DECODER_TEST_RRF_M 955 #define DECODER_TEST_RRF_M4 956 #define DECODER_TEST_RRF_RM 957 #define DECODER_TEST_RRF_MM 958 #define DECODER_TEST_RRR 959 #undef DECODER_TEST_RX 960 #define DECODER_TEST_RXE 961 #define DECODER_TEST_RXF 962 #define DECODER_TEST_RXY 963 #undef DECODER_TEST_RS 964 #define DECODER_TEST_RSY 965 #undef DECODER_TEST_RSL 966 #undef DECODER_TEST_RSI 967 #undef DECODER_TEST_RI 968 #define DECODER_TEST_RIL 969 #define DECODER_TEST_RIL_A 970 #undef DECODER_TEST_RIS 971 #undef DECODER_TEST_RRS 972 #undef DECODER_TEST_SI 973 #define DECODER_TEST_SIY 974 #undef DECODER_TEST_SIL 975 #undef DECODER_TEST_S 976 #define DECODER_TEST_SS 977 #define DECODER_TEST_SS_L 978 #define DECODER_TEST_SSE 979 #define DECODER_TEST_SSF 980 981 /* E implied operands and extended op code */ 982 #undef E 983 #define E(_inst,_regs) E_DECODER((_inst), (_regs), 2, 2) 984 985 #define E_DECODER(_inst, _regs, _len, _ilc) \ 986 { \ 987 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 988 UNREFERENCED(_inst); \ 989 } 990 991 /* IE extended op code with two 4-bit immediate fields */ /*912*/ 992 #undef IE 993 #undef IE0 994 995 #define IE(_inst, _regs, _i1, _i2) \ 996 IE_DECODER(_inst, _regs, _i1, _i2, 4, 4) 997 #define IE0(_inst, _regs, _i1, _i2) \ 998 IE_DECODER(_inst, _regs, _i1, _i2, 4, 0) 999 1000 #define IE_DECODER(_inst, _regs, _i1, _i2, _len, _ilc) \ 1001 { \ 1002 int i = (_inst)[3]; \ 1003 (_i1) = i >> 4; \ 1004 (_i2) = i & 0x0F; \ 1005 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1006 } 1007 1008 /* MII mask with 12-bit and 24-bit relative address fields */ /*912*/ 1009 #undef MII_A 1010 #undef MII_A0 1011 1012 #define MII_A(_inst, _regs, _m1, _addr2, _addr3) \ 1013 MII_A_DECODER(_inst, _regs, _m1, _addr2, _addr3, 6, 6) 1014 #define MII_A0(_inst, _regs, _m1, _addr2, _addr3) \ 1015 MII_A_DECODER(_inst, _regs, _m1, _addr2, _addr3, 6, 0) 1016 1017 #define MII_A_DECODER(_inst, _regs, _m1, _addr2, _addr3, _len, _ilc) \ 1018 { \ 1019 U32 ri2, ri3; S64 offset; \ 1020 U32 temp = fetch_fw(&(_inst)[2]); \ 1021 int i = (_inst)[1]; \ 1022 (_m1) = (i >> 4) & 0x0F; \ 1023 ri2 = (i << 4) | (temp >> 24); \ 1024 ri3 = temp & 0xFFFFFF; \ 1025 offset = 2LL*(S32)ri2; \ 1026 (_addr2) = (likely(!(_regs)->execflag)) ? \ 1027 PSW_IA((_regs), offset) : \ 1028 ((_regs)->ET + offset) & ADDRESS_MAXWRAP((_regs)); \ 1029 offset = 2LL*(S32)ri3; \ 1030 (_addr3) = (likely(!(_regs)->execflag)) ? \ 1031 PSW_IA((_regs), offset) : \ 1032 ((_regs)->ET + offset) & ADDRESS_MAXWRAP((_regs)); \ 1033 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1034 } 1035 1036 /* RR register to register */ 1037 #undef RR 1038 #undef RR0 1039 #undef RR_B 1040 1041 #define RR(_inst, _regs, _r1, _r2) \ 1042 RR_DECODER(_inst, _regs, _r1, _r2, 2, 2) 1043 #define RR0(_inst, _regs, _r1, _r2) \ 1044 RR_DECODER(_inst, _regs, _r1, _r2, 2, 0) 1045 #define RR_B(_inst, _regs, _r1, _r2) \ 1046 RR_DECODER(_inst, _regs, _r1, _r2, 0, 0) 1047 1048 #define RR_DECODER(_inst, _regs, _r1, _r2, _len, _ilc) \ 1049 { \ 1050 int i = (_inst)[1]; \ 1051 (_r1) = i >> 4; \ 1052 (_r2) = i & 0x0F; \ 1053 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1054 } 1055 1056 /* RR special format for SVC instruction */ 1057 #undef RR_SVC 1058 1059 #define RR_SVC(_inst, _regs, _svc) \ 1060 RR_SVC_DECODER(_inst, _regs, _svc, 2, 2) 1061 1062 #define RR_SVC_DECODER(_inst, _regs, _svc, _ilc, _len) \ 1063 { \ 1064 (_svc) = (_inst)[1]; \ 1065 INST_UPDATE_PSW((_regs), (_ilc), (_len)); \ 1066 } 1067 1068 /* RRE register to register with extended op code */ 1069 #undef RRE 1070 #undef RRE0 1071 #undef RRE_B 1072 1073 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRE) 1074 #define RRE(_inst, _regs, _r1, _r2) \ 1075 RRE_DECODER(_inst, _regs, _r1, _r2, 4, 4) 1076 #define RRE0(_inst, _regs, _r1, _r2) \ 1077 RRE_DECODER(_inst, _regs, _r1, _r2, 4, 0) 1078 #define RRE_B(_inst, _regs, _r1, _r2) \ 1079 RRE_DECODER(_inst, _regs, _r1, _r2, 0, 0) 1080 #else 1081 #define RRE(_inst, _regs, _r1, _r2) \ 1082 RRE_DECODER_TEST(_inst, _regs, _r1, _r2, 4, 4) 1083 #define RRE0(_inst, _regs, _r1, _r2) \ 1084 RRE_DECODER_TEST(_inst, _regs, _r1, _r2, 4, 0) 1085 #define RRE_B(_inst, _regs, _r1, _r2) \ 1086 RRE_DECODER_TEST(_inst, _regs, _r1, _r2, 0, 0) 1087 #endif 1088 1089 #define RRE_DECODER(_inst, _regs, _r1, _r2, _len, _ilc) \ 1090 { \ 1091 int i = (_inst)[3]; \ 1092 (_r1) = i >> 4; \ 1093 (_r2) = i & 0xf; \ 1094 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1095 } 1096 1097 #define RRE_DECODER_TEST(_inst, _regs, _r1, _r2, _len, _ilc) \ 1098 { \ 1099 int i = (_inst)[3]; \ 1100 (_r2) = i & 0xf; \ 1101 (_r1) = i >> 4; \ 1102 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1103 } 1104 1105 /* RRF register to register with additional R3 field */ 1106 #undef RRF_R 1107 1108 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRF_R) 1109 #define RRF_R(_inst, _regs, _r1, _r2, _r3) \ 1110 RRF_R_DECODER(_inst, _regs, _r1, _r2, _r3, 4, 4) 1111 #else 1112 #define RRF_R(_inst, _regs, _r1, _r2, _r3) \ 1113 RRF_R_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, 4, 4) 1114 #endif 1115 1116 #define RRF_R_DECODER(_inst, _regs, _r1, _r2, _r3, _len, _ilc) \ 1117 { \ 1118 int i = (_inst)[2]; \ 1119 (_r1) = i >> 4; \ 1120 i = (_inst)[3]; \ 1121 (_r3) = i >> 4; \ 1122 (_r2) = i & 0xf; \ 1123 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1124 } 1125 1126 #define RRF_R_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _len, _ilc) \ 1127 { U32 temp = fetch_fw(_inst); \ 1128 (_r2) = (temp ) & 0xf; \ 1129 (_r3) = (temp >> 4) & 0xf; \ 1130 (_r1) = (temp >> 12) & 0xf; \ 1131 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1132 } 1133 1134 /* RRF register to register with additional M3 field */ 1135 #undef RRF_M 1136 1137 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRF_M) 1138 #define RRF_M(_inst, _regs, _r1, _r2, _m3) \ 1139 RRF_M_DECODER(_inst, _regs, _r1, _r2, _m3, 4, 4) 1140 #else 1141 #define RRF_M(_inst, _regs, _r1, _r2, _m3) \ 1142 RRF_M_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, 4, 4) 1143 #endif 1144 1145 #define RRF_M_DECODER(_inst, _regs, _r1, _r2, _m3, _len, _ilc) \ 1146 { \ 1147 int i = (_inst)[2]; \ 1148 (_m3) = i >> 4; \ 1149 i = (_inst)[3]; \ 1150 (_r1) = i >> 4; \ 1151 (_r2) = i & 0xf; \ 1152 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1153 } 1154 1155 #define RRF_M_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _len, _ilc) \ 1156 { U32 temp = fetch_fw(_inst); \ 1157 (_m3) = (temp >> 12) & 0xf; \ 1158 (_r2) = (temp ) & 0xf; \ 1159 (_r1) = (temp >> 4) & 0xf; \ 1160 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1161 } 1162 1163 1164 /* RRF register to register with additional M4 field */ 1165 #undef RRF_M4 1166 1167 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRF_M4) 1168 #define RRF_M4(_inst, _regs, _r1, _r2, _m4) \ 1169 RRF_M4_DECODER(_inst, _regs, _r1, _r2, _m4, 4, 4) 1170 #else 1171 #define RRF_M4(_inst, _regs, _r1, _r2, _m4) \ 1172 RRF_M4_DECODER_TEST(_inst, _regs, _r1, _r2, _m4, 4, 4) 1173 #endif 1174 1175 #define RRF_M4_DECODER(_inst, _regs, _r1, _r2, _m4, _len, _ilc) \ 1176 { \ 1177 int i = (_inst)[2]; \ 1178 (_m4) = i & 0xf; \ 1179 i = (_inst)[3]; \ 1180 (_r1) = i >> 4; \ 1181 (_r2) = i & 0xf; \ 1182 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1183 } 1184 1185 #define RRF_M4_DECODER_TEST(_inst, _regs, _r1, _r2, _m4, _len, _ilc) \ 1186 { U32 temp = fetch_fw(_inst); \ 1187 (_m4) = (temp >> 8) & 0xf; \ 1188 (_r2) = (temp ) & 0xf; \ 1189 (_r1) = (temp >> 4) & 0xf; \ 1190 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1191 } 1192 1193 /* RRF register to register with additional R3 and M4 fields */ 1194 #undef RRF_RM 1195 1196 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRF_RM) 1197 #define RRF_RM(_inst, _regs, _r1, _r2, _r3, _m4) \ 1198 RRF_RM_DECODER(_inst, _regs, _r1, _r2, _r3, _m4, 4, 4) 1199 #else 1200 #define RRF_RM(_inst, _regs, _r1, _r2, _r3, _m4) \ 1201 RRF_RM_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _m4, 4, 4) 1202 #endif 1203 1204 #define RRF_RM_DECODER(_inst, _regs, _r1, _r2, _r3, _m4, _len, _ilc) \ 1205 { \ 1206 int i = (_inst)[2]; \ 1207 (_r3) = i >> 4; \ 1208 (_m4) = i & 0xf; \ 1209 i = (_inst)[3]; \ 1210 (_r1) = i >> 4; \ 1211 (_r2) = i & 0xf; \ 1212 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1213 } 1214 1215 #define RRF_RM_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _m4, _len, _ilc) \ 1216 { U32 temp = fetch_fw(_inst); \ 1217 (_r3) = (temp >> 12) & 0xf; \ 1218 (_m4) = (temp >> 8) & 0xf; \ 1219 (_r2) = (temp ) & 0xf; \ 1220 (_r1) = (temp >> 4) & 0xf; \ 1221 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1222 } 1223 1224 /* RRF register to register with additional M3 and M4 fields */ 1225 #undef RRF_MM 1226 1227 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRF_MM) 1228 #define RRF_MM(_inst, _regs, _r1, _r2, _m3, _m4) \ 1229 RRF_MM_DECODER(_inst, _regs, _r1, _r2, _m3, _m4, 4, 4) 1230 #else 1231 #define RRF_MM(_inst, _regs, _r1, _r2, _m3, _m4) \ 1232 RRF_MM_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _m4, 4, 4) 1233 #endif 1234 1235 #define RRF_MM_DECODER(_inst, _regs, _r1, _r2, _m3, _m4, _len, _ilc) \ 1236 { \ 1237 int i = (_inst)[2]; \ 1238 (_m3) = i >> 4; \ 1239 (_m4) = i & 0xf; \ 1240 i = (_inst)[3]; \ 1241 (_r1) = i >> 4; \ 1242 (_r2) = i & 0xf; \ 1243 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1244 } 1245 1246 #define RRF_MM_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _m4, _len, _ilc) \ 1247 { U32 temp = fetch_fw(_inst); \ 1248 (_m3) = (temp >> 12) & 0xf; \ 1249 (_m4) = (temp >> 8) & 0xf; \ 1250 (_r2) = (temp ) & 0xf; \ 1251 (_r1) = (temp >> 4) & 0xf; \ 1252 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1253 } 1254 1255 /* RRE_MMA instructions are RRE format instructions which are treated 1256 as RRF_MM when the floating-point extension facility is installed */ 1257 #undef RRE_MMA 1258 1259 #if defined(FLOATING_POINT_EXTENSION_FACILITY) 1260 #define RRE_MMA(_inst, _regs, _r1, _r2, _m3, _m4) \ 1261 RRF_MM(_inst, _regs, _r1, _r2, _m3, _m4) 1262 #else 1263 #define RRE_MMA(_inst, _regs, _r1, _r2, _m3, _m4) \ 1264 { RRE(_inst, _regs, _r1, _r2); m3 = m4 = 0; } 1265 #endif 1266 1267 /* RRF_MMA instructions are RRF_M format instructions which are treated 1268 as RRF_MM when the floating-point extension facility is installed */ 1269 #undef RRF_MMA 1270 1271 #if defined(FLOATING_POINT_EXTENSION_FACILITY) 1272 #define RRF_MMA(_inst, _regs, _r1, _r2, _m3, _m4) \ 1273 RRF_MM(_inst, _regs, _r1, _r2, _m3, _m4) 1274 #else 1275 #define RRF_MMA(_inst, _regs, _r1, _r2, _m3, _m4) \ 1276 { RRF_M(_inst, _regs, _r1, _r2, _m3); m4 = 0; } 1277 #endif 1278 1279 /* RRR register to register with register */ 1280 #undef RRR 1281 #undef RRR0 1282 1283 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRR) 1284 #define RRR(_inst, _regs, _r1, _r2, _r3) \ 1285 RRR_DECODER(_inst, _regs, _r1, _r2, _r3, 4, 4) 1286 #define RRR0(_inst, _regs, _r1, _r2, _r3) \ 1287 RRR_DECODER(_inst, _regs, _r1, _r2, _r3, 4, 0) 1288 #else 1289 #define RRR(_inst, _regs, _r1, _r2, _r3) \ 1290 RRR_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, 4, 4) 1291 #define RRR0(_inst, _regs, _r1, _r2, _r3) \ 1292 RRR_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, 4, 0) 1293 #endif 1294 1295 #define RRR_DECODER(_inst, _regs, _r1, _r2, _r3, _len, _ilc) \ 1296 { \ 1297 int i = (_inst)[2]; \ 1298 (_r3) = i >> 4; \ 1299 i = (_inst)[3]; \ 1300 (_r1) = i >> 4; \ 1301 (_r2) = i & 0xf; \ 1302 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1303 } 1304 1305 #define RRR_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _len, _ilc) \ 1306 { U32 temp = fetch_fw(_inst); \ 1307 (_r3) = (temp >> 12) & 0xf; \ 1308 (_r2) = (temp ) & 0xf; \ 1309 (_r1) = (temp >> 4) & 0xf; \ 1310 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1311 } 1312 1313 /* RRR_M register to register with register with additional M4 field */ 1314 #undef RRR_M 1315 #undef RRR_M0 1316 1317 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRR_M) 1318 #define RRR_M(_inst, _regs, _r1, _r2, _r3, _m4) \ 1319 RRR_M_DECODER(_inst, _regs, _r1, _r2, _r3, _m4, 4, 4) 1320 #define RRR_M0(_inst, _regs, _r1, _r2, _r3, _m4) \ 1321 RRR_M_DECODER(_inst, _regs, _r1, _r2, _r3, _m4, 4, 0) 1322 #else 1323 #define RRR_M(_inst, _regs, _r1, _r2, _r3, _m4) \ 1324 RRR_M_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _m4, 4, 4) 1325 #define RRR_M0(_inst, _regs, _r1, _r2, _r3, _m4) \ 1326 RRR_M_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _m4, 4, 0) 1327 #endif 1328 1329 #define RRR_M_DECODER(_inst, _regs, _r1, _r2, _r3, _m4, _len, _ilc) \ 1330 { \ 1331 int i = (_inst)[2]; \ 1332 (_r3) = i >> 4; \ 1333 (_m4) = i & 0xf; \ 1334 i = (_inst)[3]; \ 1335 (_r1) = i >> 4; \ 1336 (_r2) = i & 0xf; \ 1337 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1338 } 1339 1340 #define RRR_M_DECODER_TEST(_inst, _regs, _r1, _r2, _r3, _m4, _len, _ilc) \ 1341 { U32 temp = fetch_fw(_inst); \ 1342 (_m4) = (temp >> 8) & 0xf; \ 1343 (_r3) = (temp >> 12) & 0xf; \ 1344 (_r2) = (temp ) & 0xf; \ 1345 (_r1) = (temp >> 4) & 0xf; \ 1346 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1347 } 1348 1349 /* RRR_MA instructions are RRR format instructions which are treated 1350 as RRR_M when the floating-point extension facility is installed */ 1351 #undef RRR_MA 1352 1353 #if defined(FLOATING_POINT_EXTENSION_FACILITY) 1354 #define RRR_MA(_inst, _regs, _r1, _r2, _r3, _m4) \ 1355 RRR_M(_inst, _regs, _r1, _r2, _r3, _m4) 1356 #else 1357 #define RRR_MA(_inst, _regs, _r1, _r2, _r3, _m4) \ 1358 { RRR(_inst, _regs, _r1, _r2, _r3); m4 = 0; } 1359 #endif 1360 1361 /* RX register and indexed storage */ 1362 #undef RX 1363 #undef RX0 1364 #undef RX_B 1365 1366 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RX) 1367 #define RX(_inst, _regs, _r1, _b2, _effective_addr2) \ 1368 RX_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 4, 4) 1369 #define RX0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1370 RX_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 4, 0) 1371 #define RX_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1372 RX_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1373 #else 1374 #define RX(_inst, _regs, _r1, _b2, _effective_addr2) \ 1375 RX_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 4, 4) 1376 #define RX0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1377 RX_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 4, 0) 1378 #define RX_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1379 RX_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1380 #endif 1381 1382 #define RX_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1383 { U32 temp = fetch_fw(_inst); \ 1384 (_r1) = (temp >> 20) & 0xf; \ 1385 (_b2) = (temp >> 16) & 0xf; \ 1386 (_effective_addr2) = temp & 0xfff; \ 1387 if((_b2)) \ 1388 (_effective_addr2) += (_regs)->GR((_b2)); \ 1389 (_b2) = (temp >> 12) & 0xf; \ 1390 if((_b2)) \ 1391 (_effective_addr2) += (_regs)->GR((_b2)); \ 1392 if ((_len)) \ 1393 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1394 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1395 } 1396 1397 #define RX_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1398 { U32 temp = fetch_fw(_inst); \ 1399 (_effective_addr2) = temp & 0xfff; \ 1400 (_b2) = (temp >> 16) & 0xf; \ 1401 if((_b2)) \ 1402 (_effective_addr2) += (_regs)->GR((_b2)); \ 1403 (_b2) = (temp >> 12) & 0xf; \ 1404 if((_b2)) \ 1405 (_effective_addr2) += (_regs)->GR((_b2)); \ 1406 if ((_len)) \ 1407 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1408 (_r1) = (temp >> 20) & 0xf; \ 1409 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1410 } 1411 1412 /* RX_BC register and indexed storage - optimized for BC */ 1413 #undef RX_BC 1414 1415 #define RX_BC(_inst, _regs, _b2, _effective_addr2) \ 1416 RX_BC_DECODER(_inst, _regs, _b2, _effective_addr2, 0, 0) 1417 1418 #define RX_BC_DECODER(_inst, _regs, _b2, _effective_addr2, _len, _ilc) \ 1419 { U32 temp = fetch_fw(_inst); \ 1420 (_effective_addr2) = temp & 0xfff; \ 1421 (_b2) = (temp >> 16) & 0xf; \ 1422 if(unlikely((_b2))) \ 1423 (_effective_addr2) += (_regs)->GR((_b2)); \ 1424 (_b2) = (temp >> 12) & 0xf; \ 1425 if(likely((_b2))) \ 1426 (_effective_addr2) += (_regs)->GR((_b2)); \ 1427 } 1428 1429 /* RXE register and indexed storage with extended op code */ 1430 #undef RXE 1431 1432 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RXE) 1433 #define RXE(_inst, _regs, _r1, _b2, _effective_addr2) \ 1434 RXE_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1435 #else 1436 #define RXE(_inst, _regs, _r1, _b2, _effective_addr2) \ 1437 RXE_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1438 #endif 1439 1440 #define RXE_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1441 { U32 temp = fetch_fw(_inst); \ 1442 (_r1) = (temp >> 20) & 0xf; \ 1443 (_b2) = (temp >> 16) & 0xf; \ 1444 (_effective_addr2) = temp & 0xfff; \ 1445 if((_b2)) \ 1446 { \ 1447 (_effective_addr2) += (_regs)->GR((_b2)); \ 1448 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1449 } \ 1450 (_b2) = (temp >> 12) & 0xf; \ 1451 if((_b2)) \ 1452 { \ 1453 (_effective_addr2) += (_regs)->GR((_b2)); \ 1454 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1455 } \ 1456 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1457 } 1458 1459 #define RXE_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1460 { U32 temp = fetch_fw(_inst); \ 1461 (_effective_addr2) = temp & 0xfff; \ 1462 (_b2) = (temp >> 16) & 0xf; \ 1463 if((_b2)) \ 1464 (_effective_addr2) += (_regs)->GR((_b2)); \ 1465 (_b2) = (temp >> 12) & 0xf; \ 1466 if((_b2)) \ 1467 (_effective_addr2) += (_regs)->GR((_b2)); \ 1468 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1469 (_r1) = (temp >> 20) & 0xf; \ 1470 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1471 } 1472 1473 /* RXF register and indexed storage with ext.opcode and additional R3 */ 1474 #undef RXF 1475 1476 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RXF) 1477 #define RXF(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1478 RXF_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1479 #else 1480 #define RXF(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1481 RXF_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1482 #endif 1483 1484 #define RXF_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1485 { U32 temp; \ 1486 (_r1) = (_inst)[4] >> 4; \ 1487 memcpy (&temp, (_inst), 4); \ 1488 temp = CSWAP32(temp); \ 1489 (_r3) = (temp >> 20) & 0xf; \ 1490 (_b2) = (temp >> 16) & 0xf; \ 1491 (_effective_addr2) = temp & 0xfff; \ 1492 if((_b2)) \ 1493 { \ 1494 (_effective_addr2) += (_regs)->GR((_b2)); \ 1495 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1496 } \ 1497 (_b2) = (temp >> 12) & 0xf; \ 1498 if((_b2)) \ 1499 { \ 1500 (_effective_addr2) += (_regs)->GR((_b2)); \ 1501 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1502 } \ 1503 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1504 } 1505 1506 #define RXF_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1507 { U32 temp = fetch_fw(_inst); \ 1508 (_effective_addr2) = temp & 0xfff; \ 1509 (_b2) = (temp >> 16) & 0xf; \ 1510 if((_b2)) \ 1511 (_effective_addr2) += (_regs)->GR((_b2)); \ 1512 (_b2) = (temp >> 12) & 0xf; \ 1513 if((_b2)) \ 1514 (_effective_addr2) += (_regs)->GR((_b2)); \ 1515 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1516 (_r3) = (temp >> 20) & 0xf; \ 1517 (_r1) = (_inst)[4] >> 4; \ 1518 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1519 } 1520 1521 /* RXY register and indexed storage with extended op code 1522 and long displacement */ 1523 #undef RXY 1524 #undef RXY0 1525 #undef RXY_B 1526 1527 #if defined(FEATURE_LONG_DISPLACEMENT) 1528 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RXY) 1529 #define RXY(_inst, _regs, _r1, _b2, _effective_addr2) \ 1530 RXY_DECODER_LD(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1531 #define RXY0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1532 RXY_DECODER_LD(_inst, _regs, _r1, _b2, _effective_addr2, 6, 0) 1533 #define RXY_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1534 RXY_DECODER_LD(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1535 #else 1536 #define RXY(_inst, _regs, _r1, _b2, _effective_addr2) \ 1537 RXY_DECODER_LD_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1538 #define RXY0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1539 RXY_DECODER_LD_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 6, 0) 1540 #define RXY_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1541 RXY_DECODER_LD_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1542 #endif 1543 #else /* !defined(FEATURE_LONG_DISPLACEMENT) */ 1544 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RXY) 1545 #define RXY(_inst, _regs, _r1, _b2, _effective_addr2) \ 1546 RXY_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1547 #define RXY0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1548 RXY_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 6, 0) 1549 #define RXY_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1550 RXY_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1551 #else 1552 #define RXY(_inst, _regs, _r1, _b2, _effective_addr2) \ 1553 RXY_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 6, 6) 1554 #define RXY0(_inst, _regs, _r1, _b2, _effective_addr2) \ 1555 RXY_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 6, 0) 1556 #define RXY_B(_inst, _regs, _r1, _b2, _effective_addr2) \ 1557 RXY_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, 0, 0) 1558 #endif 1559 #endif 1560 1561 #define RXY_DECODER_LD(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1562 { U32 temp; S32 temp2; int tempx; \ 1563 temp = fetch_fw(_inst); \ 1564 (_r1) = (temp >> 20) & 0xf; \ 1565 tempx = (temp >> 16) & 0xf; \ 1566 (_b2) = (temp >> 12) & 0xf; \ 1567 temp2 = (_inst[4] << 12) | (temp & 0xfff); \ 1568 if (temp2 & 0x80000) temp2 |= 0xfff00000; \ 1569 (_effective_addr2) = \ 1570 (tempx ? (_regs)->GR(tempx) : (GREG)0) + \ 1571 ((_b2) ? (_regs)->GR((_b2)) : (GREG)0) + \ 1572 temp2; \ 1573 if ((_len)) \ 1574 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1575 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1576 } 1577 1578 #define RXY_DECODER_LD_TEST(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1579 { U32 temp; S32 disp2; \ 1580 temp = fetch_fw(_inst); \ 1581 (_effective_addr2) = 0; \ 1582 (_b2) = (temp >> 16) & 0xf; \ 1583 if ((_b2)) \ 1584 (_effective_addr2) += (_regs)->GR((_b2)); \ 1585 (_b2) = (temp >> 12) & 0xf; \ 1586 if ((_b2)) \ 1587 (_effective_addr2) += (_regs)->GR((_b2)); \ 1588 disp2 = temp & 0xfff; \ 1589 if (unlikely((_inst)[4])) { \ 1590 disp2 |= (_inst[4] << 12); \ 1591 if (disp2 & 0x80000) disp2 |= 0xfff00000; \ 1592 } \ 1593 (_effective_addr2) += disp2; \ 1594 if ((_len)) \ 1595 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1596 (_r1) = (temp >> 20) & 0xf; \ 1597 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1598 } 1599 1600 #define RXY_DECODER(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1601 { U32 temp = fetch_fw(_inst); \ 1602 (_r1) = (temp >> 20) & 0xf; \ 1603 (_b2) = (temp >> 16) & 0xf; \ 1604 (_effective_addr2) = temp & 0xfff; \ 1605 if((_b2)) \ 1606 { \ 1607 (_effective_addr2) += (_regs)->GR((_b2)); \ 1608 if ((_len)) \ 1609 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1610 } \ 1611 (_b2) = (temp >> 12) & 0xf; \ 1612 if((_b2)) \ 1613 { \ 1614 (_effective_addr2) += (_regs)->GR((_b2)); \ 1615 if ((_len)) \ 1616 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1617 } \ 1618 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1619 } 1620 1621 #define RXY_DECODER_TEST(_inst, _regs, _r1, _b2, _effective_addr2, _len, _ilc) \ 1622 { U32 temp = fetch_fw(_inst); \ 1623 (_effective_addr2) = temp & 0xfff; \ 1624 (_b2) = (temp >> 16) & 0xf; \ 1625 if((_b2)) \ 1626 (_effective_addr2) += (_regs)->GR((_b2)); \ 1627 (_b2) = (temp >> 12) & 0xf; \ 1628 if((_b2)) \ 1629 (_effective_addr2) += (_regs)->GR((_b2)); \ 1630 if ((_len)) \ 1631 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1632 (_r1) = (temp >> 20) & 0xf; \ 1633 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1634 } 1635 1636 /* RS register and storage with additional R3 or M3 field */ 1637 #undef RS 1638 #undef RS0 1639 #undef RS_B 1640 1641 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RS) 1642 #define RS(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1643 RS_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 4, 4) 1644 #define RS0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1645 RS_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 4, 0) 1646 #define RS_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1647 RS_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1648 #else 1649 #define RS(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1650 RS_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 4, 4) 1651 #define RS0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1652 RS_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 4, 0) 1653 #define RS_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1654 RS_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1655 #endif 1656 1657 #define RS_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1658 { U32 temp = fetch_fw(_inst); \ 1659 (_r1) = (temp >> 20) & 0xf; \ 1660 (_r3) = (temp >> 16) & 0xf; \ 1661 (_b2) = (temp >> 12) & 0xf; \ 1662 (_effective_addr2) = temp & 0xfff; \ 1663 if((_b2)) \ 1664 { \ 1665 (_effective_addr2) += (_regs)->GR((_b2)); \ 1666 if ((_len)) \ 1667 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1668 } \ 1669 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1670 } 1671 1672 #define RS_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1673 { U32 temp = fetch_fw(_inst); \ 1674 (_effective_addr2) = temp & 0xfff; \ 1675 (_b2) = (temp >> 12) & 0xf; \ 1676 if((_b2)) \ 1677 { \ 1678 (_effective_addr2) += (_regs)->GR((_b2)); \ 1679 if ((_len)) \ 1680 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1681 } \ 1682 (_r3) = (temp >> 16) & 0xf; \ 1683 (_r1) = (temp >> 20) & 0xf; \ 1684 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1685 } 1686 1687 #if 0 1688 /* RSE register and storage with extended op code and additional 1689 R3 or M3 field (note, this is NOT the ESA/390 vector RSE format) */ 1690 /* Note: Effective June 2003, RSE is retired and replaced by RSY */ 1691 #undef RSE 1692 #define RSE(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1693 { U32 temp; \ 1694 memcpy (&temp, (_inst), 4); \ 1695 temp = CSWAP32(temp); \ 1696 (_r1) = (temp >> 20) & 0xf; \ 1697 (_r3) = (temp >> 16) & 0xf; \ 1698 (_b2) = (temp >> 12) & 0xf; \ 1699 (_effective_addr2) = temp & 0xfff; \ 1700 if((_b2) != 0) \ 1701 { \ 1702 (_effective_addr2) += (_regs)->GR((_b2)); \ 1703 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1704 } \ 1705 INST_UPDATE_PSW((_regs), 6, 6); \ 1706 } 1707 #endif 1708 1709 /* RSY register and storage with extended op code, long displacement, 1710 and additional R3 or M3 field */ 1711 #undef RSY 1712 #undef RSY0 1713 #undef RSY_B 1714 1715 #if defined(FEATURE_LONG_DISPLACEMENT) 1716 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RSY) 1717 #define RSY(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1718 RSY_DECODER_LD(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1719 #define RSY0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1720 RSY_DECODER_LD(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 0) 1721 #define RSY_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1722 RSY_DECODER_LD(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1723 #else 1724 #define RSY(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1725 RSY_DECODER_LD_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1726 #define RSY0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1727 RSY_DECODER_LD_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 0) 1728 #define RSY_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1729 RSY_DECODER_LD_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1730 #endif 1731 #else 1732 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RSY) 1733 #define RSY(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1734 RSY_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1735 #define RSY0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1736 RSY_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 0) 1737 #define RSY_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1738 RSY_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1739 #else 1740 #define RSY(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1741 RSY_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 6) 1742 #define RSY0(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1743 RSY_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 6, 0) 1744 #define RSY_B(_inst, _regs, _r1, _r3, _b2, _effective_addr2) \ 1745 RSY_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, 0, 0) 1746 #endif 1747 #endif 1748 1749 #define RSY_DECODER_LD(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1750 { U32 temp; S32 temp2; \ 1751 temp = fetch_fw(_inst); \ 1752 (_r1) = (temp >> 20) & 0xf; \ 1753 (_r3) = (temp >> 16) & 0xf; \ 1754 (_b2) = (temp >> 12) & 0xf; \ 1755 temp2 = (_inst[4] << 12) | (temp & 0xfff); \ 1756 if (temp2 & 0x80000) temp2 |= 0xfff00000; \ 1757 (_effective_addr2) = \ 1758 ((_b2) ? (_regs)->GR((_b2)) : (GREG)0) + \ 1759 temp2; \ 1760 if ((_len)) \ 1761 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1762 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1763 } 1764 1765 #define RSY_DECODER_LD_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1766 { U32 temp; S32 disp2; \ 1767 temp = fetch_fw(_inst); \ 1768 (_effective_addr2) = 0; \ 1769 (_b2) = (temp >> 12) & 0xf; \ 1770 if ((_b2)) \ 1771 _effective_addr2 += (_regs)->GR((_b2)); \ 1772 disp2 = temp & 0xfff; \ 1773 if (unlikely((_inst)[4])) { \ 1774 disp2 |= (_inst[4] << 12); \ 1775 if (disp2 & 0x80000) disp2 |= 0xfff00000; \ 1776 } \ 1777 (_effective_addr2) += disp2; \ 1778 if ((_len)) \ 1779 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1780 (_r3) = (temp >> 16) & 0xf; \ 1781 (_r1) = (temp >> 20) & 0xf; \ 1782 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1783 } 1784 1785 #define RSY_DECODER(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1786 { U32 temp = fetch_fw(_inst); \ 1787 (_r1) = (temp >> 20) & 0xf; \ 1788 (_r3) = (temp >> 16) & 0xf; \ 1789 (_b2) = (temp >> 12) & 0xf; \ 1790 (_effective_addr2) = temp & 0xfff; \ 1791 if((_b2) != 0) \ 1792 { \ 1793 (_effective_addr2) += (_regs)->GR((_b2)); \ 1794 if ((_len)) \ 1795 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1796 } \ 1797 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1798 } 1799 1800 #define RSY_DECODER_TEST(_inst, _regs, _r1, _r3, _b2, _effective_addr2, _len, _ilc) \ 1801 { U32 temp = fetch_fw(_inst); \ 1802 (_effective_addr2) = temp & 0xfff; \ 1803 (_b2) = (temp >> 12) & 0xf; \ 1804 if((_b2)) \ 1805 (_effective_addr2) += (_regs)->GR((_b2)); \ 1806 if ((_len)) \ 1807 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1808 (_r3) = (temp >> 16) & 0xf; \ 1809 (_r1) = (temp >> 20) & 0xf; \ 1810 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1811 } 1812 1813 /* RSL storage operand with extended op code and 4-bit L field */ 1814 #undef RSL 1815 1816 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RSL) 1817 #define RSL(_inst, _regs, _l1, _b1, _effective_addr1) \ 1818 RSL_DECODER(_inst, _regs, _l1, _b1, _effective_addr1, 6, 6) 1819 #else 1820 #define RSL(_inst, _regs, _l1, _b1, _effective_addr1) \ 1821 RSL_DECODER_TEST(_inst, _regs, _l1, _b1, _effective_addr1, 6, 6) 1822 #endif 1823 1824 #define RSL_DECODER(_inst, _regs, _l1, _b1, _effective_addr1, _len, _ilc) \ 1825 { U32 temp = fetch_fw(_inst); \ 1826 (_l1) = (temp >> 20) & 0xf; \ 1827 (_b1) = (temp >> 12) & 0xf; \ 1828 (_effective_addr1) = temp & 0xfff; \ 1829 if((_b1) != 0) \ 1830 { \ 1831 (_effective_addr1) += (_regs)->GR((_b1)); \ 1832 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 1833 } \ 1834 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1835 } 1836 1837 #define RSL_DECODER_TEST(_inst, _regs, _l1, _b1, _effective_addr1, _len, _ilc) \ 1838 { U32 temp = fetch_fw(_inst); \ 1839 (_effective_addr1) = temp & 0xfff; \ 1840 (_b1) = (temp >> 12) & 0xf; \ 1841 if((_b1)) { \ 1842 (_effective_addr1) += (_regs)->GR((_b1)); \ 1843 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 1844 } \ 1845 (_l1) = (temp >> 20) & 0xf; \ 1846 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1847 } 1848 1849 /* RSL register and storage with extended op code, 8-bit L field, and mask */ 1850 #undef RSL_RM 1851 1852 #define RSL_RM(_inst, _regs, _r1, _l2, _b2, _effective_addr2, _m3) \ 1853 RSL_RM_DECODER(_inst, _regs, _r1, _l2, _b2, _effective_addr2, _m3, 6, 6) 1854 1855 #define RSL_RM_DECODER(_inst, _regs, _r1, _l2, _b2, _effective_addr2, _m3, _len, _ilc) \ 1856 { U32 temp = fetch_fw(&(_inst)[1]); \ 1857 (_m3) = temp & 0xf; \ 1858 (_r1) = (temp >> 4) & 0xf; \ 1859 (_effective_addr2) = (temp >> 8) & 0xfff; \ 1860 (_b2) = (temp >> 20) & 0xf; \ 1861 (_l2) = (temp >> 24) & 0xff; \ 1862 if((_b2)) { \ 1863 (_effective_addr2) += (_regs)->GR((_b2)); \ 1864 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 1865 } \ 1866 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1867 } 1868 1869 /* RSI register and immediate with additional R3 field */ 1870 #undef RSI 1871 #undef RSI0 1872 #undef RSI_B 1873 1874 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RSI) 1875 #define RSI(_inst, _regs, _r1, _r3, _i2) \ 1876 RSI_DECODER(_inst, _regs, _r1, _r3, _i2, 4, 4) 1877 #define RSI0(_inst, _regs, _r1, _r3, _i2) \ 1878 RSI_DECODER(_inst, _regs, _r1, _r3, _i2, 4, 0) 1879 #define RSI_B(_inst, _regs, _r1, _r3, _i2) \ 1880 RSI_DECODER(_inst, _regs, _r1, _r3, _i2, 0, 0) 1881 #else 1882 #define RSI(_inst, _regs, _r1, _r3, _i2) \ 1883 RSI_DECODER_TEST(_inst, _regs, _r1, _r3, _i2, 4, 4) 1884 #define RSI0(_inst, _regs, _r1, _r3, _i2) \ 1885 RSI_DECODER_TEST(_inst, _regs, _r1, _r3, _i2, 4, 0) 1886 #define RSI_B(_inst, _regs, _r1, _r3, _i2) \ 1887 RSI_DECODER_TEST(_inst, _regs, _r1, _r3, _i2, 0, 0) 1888 #endif 1889 1890 #define RSI_DECODER(_inst, _regs, _r1, _r3, _i2, _len, _ilc) \ 1891 { U32 temp = fetch_fw(_inst); \ 1892 (_r1) = (temp >> 20) & 0xf; \ 1893 (_r3) = (temp >> 16) & 0xf; \ 1894 (_i2) = temp & 0xffff; \ 1895 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1896 } 1897 1898 #define RSI_DECODER_TEST(_inst, _regs, _r1, _r3, _i2, _len, _ilc) \ 1899 { U32 temp = fetch_fw(_inst); \ 1900 (_i2) = temp & 0xffff; \ 1901 (_r3) = (temp >> 16) & 0xf; \ 1902 (_r1) = (temp >> 20) & 0xf; \ 1903 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1904 } 1905 1906 /* RI register and immediate with extended 4-bit op code */ 1907 #undef RI 1908 #undef RI0 1909 #undef RI_B 1910 1911 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RI) 1912 #define RI(_inst, _regs, _r1, _i2) \ 1913 RI_DECODER(_inst, _regs, _r1, _i2, 4, 4) 1914 #define RI0(_inst, _regs, _r1, _i2) \ 1915 RI_DECODER(_inst, _regs, _r1, _i2, 4, 0) 1916 #define RI_B(_inst, _regs, _r1, _i2) \ 1917 RI_DECODER(_inst, _regs, _r1, _i2, 0, 0) 1918 #else 1919 #define RI(_inst, _regs, _r1, _i2) \ 1920 RI_DECODER_TEST(_inst, _regs, _r1, _i2, 4, 4) 1921 #define RI0(_inst, _regs, _r1, _i2) \ 1922 RI_DECODER_TEST(_inst, _regs, _r1, _i2, 4, 0) 1923 #define RI_B(_inst, _regs, _r1, _i2) \ 1924 RI_DECODER_TEST(_inst, _regs, _r1, _i2, 0, 0) 1925 #endif 1926 1927 #define RI_DECODER(_inst, _regs, _r1, _i2, _len, _ilc) \ 1928 { U32 temp = fetch_fw(_inst); \ 1929 (_r1) = (temp >> 20) & 0xf; \ 1930 (_i2) = temp & 0xffff; \ 1931 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1932 } 1933 1934 #define RI_DECODER_TEST(_inst, _regs, _r1, _i2, _len, _ilc) \ 1935 { U32 temp = fetch_fw(_inst); \ 1936 (_i2) = temp & 0xffff; \ 1937 (_r1) = (temp >> 20) & 0xf; \ 1938 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1939 } 1940 1941 /* RIE register and immediate with ext.opcode and additional R3 */ 1942 #undef RIE 1943 #undef RIE0 1944 #undef RIE_B 1945 1946 #define RIE(_inst, _regs, _r1, _r3, _i2) \ 1947 RIE_DECODER(_inst, _regs, _r1, _r3, _i2, 6, 6) 1948 #define RIE0(_inst, _regs, _r1, _r3, _i2) \ 1949 RIE_DECODER(_inst, _regs, _r1, _r3, _i2, 6, 0) 1950 #define RIE_B(_inst, _regs, _r1, _r3, _i2) \ 1951 RIE_DECODER(_inst, _regs, _r1, _r3, _i2, 0, 0) 1952 1953 #define RIE_DECODER(_inst, _regs, _r1, _r3, _i2, _len, _ilc) \ 1954 { U32 temp = fetch_fw(_inst); \ 1955 (_r1) = (temp >> 20) & 0xf; \ 1956 (_r3) = (temp >> 16) & 0xf; \ 1957 (_i2) = temp & 0xffff; \ 1958 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1959 } 1960 1961 /* RIE register and immediate with mask */ /*208*/ 1962 #undef RIE_RIM 1963 1964 #define RIE_RIM(_inst, _regs, _r1, _i2, _m3) \ 1965 RIE_RIM_DECODER(_inst, _regs, _r1, _i2, _m3, 6, 6) 1966 1967 #define RIE_RIM_DECODER(_inst, _regs, _r1, _i2, _m3, _len, _ilc) \ 1968 { U32 temp = fetch_fw(&(_inst)[1]); \ 1969 (_m3) = (temp >> 4) & 0xf; \ 1970 (_i2) = (temp >> 8) & 0xffff; \ 1971 (_r1) = (temp >> 28) & 0xf; \ 1972 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1973 } 1974 1975 /* RIE register to register with immediate and mask */ /*208*/ 1976 #undef RIE_RRIM 1977 #undef RIE_RRIM0 1978 #undef RIE_RRIM_B 1979 1980 #define RIE_RRIM(_inst, _regs, _r1, _r2, _i4, _m3) \ 1981 RIE_RRIM_DECODER(_inst, _regs, _r1, _r2, _i4, _m3, 6, 6) 1982 #define RIE_RRIM0(_inst, _regs, _r1, _r2, _i4, _m3) \ 1983 RIE_RRIM_DECODER(_inst, _regs, _r1, _r2, _i4, _m3, 6, 0) 1984 #define RIE_RRIM_B(_inst, _regs, _r1, _r2, _i4, _m3) \ 1985 RIE_RRIM_DECODER(_inst, _regs, _r1, _r2, _i4, _m3, 0, 0) 1986 1987 #define RIE_RRIM_DECODER(_inst, _regs, _r1, _r2, _i4, _m3, _len, _ilc) \ 1988 { U32 temp = fetch_fw(&(_inst)[1]); \ 1989 (_m3) = (temp >> 4) & 0xf; \ 1990 (_i4) = (temp >> 8) & 0xffff; \ 1991 (_r2) = (temp >> 24) & 0xf; \ 1992 (_r1) = (temp >> 28) & 0xf; \ 1993 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 1994 } 1995 1996 /* RIE register and mask with longer immediate and immediate */ /*208*/ 1997 #undef RIE_RMII 1998 #undef RIE_RMII0 1999 #undef RIE_RMII_B 2000 2001 #define RIE_RMII(_inst, _regs, _r1, _i2, _m3, _i4) \ 2002 RIE_RMII_DECODER(_inst, _regs, _r1, _i2, _m3, _i4, 6, 6) 2003 #define RIE_RMII0(_inst, _regs, _r1, _i2, _m3, _i4) \ 2004 RIE_RMII_DECODER(_inst, _regs, _r1, _i2, _m3, _i4, 6, 0) 2005 #define RIE_RMII_B(_inst, _regs, _r1, _i2, _m3, _i4) \ 2006 RIE_RMII_DECODER(_inst, _regs, _r1, _i2, _m3, _i4, 0, 0) 2007 2008 #define RIE_RMII_DECODER(_inst, _regs, _r1, _i2, _m3, _i4, _len, _ilc) \ 2009 { U32 temp = fetch_fw(&(_inst)[1]); \ 2010 (_i2) = temp & 0xff; \ 2011 (_i4) = (temp >> 8) & 0xffff; \ 2012 (_m3) = (temp >> 24) & 0xf; \ 2013 (_r1) = (temp >> 28) & 0xf; \ 2014 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2015 } 2016 2017 /* RIE register to register with three immediate fields */ /*208*/ 2018 #undef RIE_RRIII 2019 2020 #define RIE_RRIII(_inst, _regs, _r1, _r2, _i3, _i4, _i5) \ 2021 RIE_RRIII_DECODER(_inst, _regs, _r1, _r2, _i3, _i4, _i5, 6, 6) 2022 2023 #define RIE_RRIII_DECODER(_inst, _regs, _r1, _r2, _i3, _i4, _i5, _len, _ilc) \ 2024 { U32 temp = fetch_fw(&(_inst)[1]); \ 2025 (_i5) = temp & 0xff; \ 2026 (_i4) = (temp >> 8) & 0xff; \ 2027 (_i3) = (temp >> 16) & 0xff; \ 2028 (_r2) = (temp >> 24) & 0xf; \ 2029 (_r1) = (temp >> 28) & 0xf; \ 2030 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2031 } 2032 2033 /* RIL register and longer immediate with extended 4 bit op code */ 2034 #undef RIL 2035 #undef RIL0 2036 #undef RIL_B 2037 2038 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RIL) 2039 #define RIL(_inst, _regs, _r1, _op, _i2) \ 2040 RIL_DECODER(_inst, _regs, _r1, _op, _i2, 6, 6) 2041 #define RIL0(_inst, _regs, _r1, _op, _i2) \ 2042 RIL_DECODER(_inst, _regs, _r1, _op, _i2, 6, 0) 2043 #define RIL_B(_inst, _regs, _r1, _op, _i2) \ 2044 RIL_DECODER(_inst, _regs, _r1, _op, _i2, 0, 0) 2045 #else 2046 #define RIL(_inst, _regs, _r1, _op, _i2) \ 2047 RIL_DECODER_TEST(_inst, _regs, _r1, _op, _i2, 6, 6) 2048 #define RIL0(_inst, _regs, _r1, _op, _i2) \ 2049 RIL_DECODER_TEST(_inst, _regs, _r1, _op, _i2, 6, 0) 2050 #define RIL_B(_inst, _regs, _r1, _op, _i2) \ 2051 RIL_DECODER_TEST(_inst, _regs, _r1, _op, _i2, 0, 0) 2052 #endif 2053 2054 #define RIL_DECODER(_inst, _regs, _r1, _op, _i2, _len, _ilc) \ 2055 { U32 temp = fetch_fw(_inst); \ 2056 (_r1) = (temp >> 20) & 0xf; \ 2057 (_op) = (temp >> 16) & 0xf; \ 2058 (_i2) = ((temp & 0xffff) << 16) \ 2059 | ((_inst)[4] << 8) \ 2060 | (_inst)[5]; \ 2061 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2062 } 2063 2064 #define RIL_DECODER_TEST(_inst, _regs, _r1, _op, _i2, _len, _ilc) \ 2065 { \ 2066 (_i2) = fetch_fw(&(_inst)[2]); \ 2067 (_op) = ((_inst)[1] ) & 0xf; \ 2068 (_r1) = ((_inst)[1] >> 4) & 0xf; \ 2069 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2070 } 2071 2072 /* RIL register and longer immediate relative address */ 2073 #undef RIL_A 2074 2075 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RIL_A) 2076 #define RIL_A(_inst, _regs, _r1, _addr2) \ 2077 RIL_A_DECODER(_inst, _regs, _r1, _addr2, 6, 6) 2078 #else 2079 #define RIL_A(_inst, _regs, _r1, _addr2) \ 2080 RIL_A_DECODER_TEST(_inst, _regs, _r1, _addr2, 6, 6) 2081 #endif 2082 2083 #define RIL_A_DECODER(_inst, _regs, _r1, _addr2, _len, _ilc) \ 2084 { U32 temp = fetch_fw(_inst); \ 2085 S64 offset; \ 2086 (_r1) = (temp >> 20) & 0xf; \ 2087 offset = 2LL*(S32)(((temp & 0xffff) << 16) \ 2088 | ((_inst)[4] << 8) \ 2089 | (_inst)[5]); \ 2090 (_addr2) = (likely(!(_regs)->execflag)) ? \ 2091 PSW_IA((_regs), offset) : \ 2092 ((_regs)->ET + offset) & ADDRESS_MAXWRAP((_regs)); \ 2093 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2094 } 2095 2096 #define RIL_A_DECODER_TEST(_inst, _regs, _r1, _addr2, _len, _ilc) \ 2097 { \ 2098 S64 offset = 2LL*(S32)(fetch_fw(&(_inst)[2])); \ 2099 (_r1) = ((_inst)[1] >> 4) & 0xf; \ 2100 (_addr2) = (likely(!(_regs)->execflag)) ? \ 2101 PSW_IA((_regs), offset) : \ 2102 ((_regs)->ET + offset) & ADDRESS_MAXWRAP((_regs)); \ 2103 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2104 } 2105 2106 /* RIS register, immediate, mask, and storage */ /*208*/ 2107 #undef RIS 2108 #undef RIS0 2109 #undef RIS_B 2110 2111 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RIS) 2112 #define RIS(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2113 RIS_DECODER(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 6, 6) 2114 #define RIS0(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2115 RIS_DECODER(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 6, 0) 2116 #define RIS_B(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2117 RIS_DECODER(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 0, 0) 2118 #else 2119 #define RIS(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2120 RIS_DECODER_TEST(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 6, 6) 2121 #define RISO(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2122 RIS_DECODER_TEST(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 6, 0) 2123 #define RIS_B(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4) \ 2124 RIS_DECODER_TEST(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, 0, 0) 2125 #endif 2126 2127 #define RIS_DECODER(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, _len, _ilc) \ 2128 { U32 temp = fetch_fw(_inst); \ 2129 (_effective_addr4) = temp & 0xfff; \ 2130 (_b4) = (temp >> 12) & 0xf; \ 2131 if((_b4) != 0) \ 2132 { \ 2133 (_effective_addr4) += (_regs)->GR((_b4)); \ 2134 (_effective_addr4) &= ADDRESS_MAXWRAP((_regs)); \ 2135 } \ 2136 (_m3) = (temp >> 16) & 0xf; \ 2137 (_r1) = (temp >> 20) & 0xf; \ 2138 (_i2) = (_inst)[4]; \ 2139 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2140 } 2141 2142 #define RIS_DECODER_TEST(_inst, _regs, _r1, _i2, _m3, _b4, _effective_addr4, _len, _ilc) \ 2143 { U32 temp = fetch_fw(_inst); \ 2144 (_effective_addr4) = temp & 0xfff; \ 2145 (_b4) = (temp >> 12) & 0xf; \ 2146 if((_b4)) { \ 2147 (_effective_addr4) += (_regs)->GR((_b4)); \ 2148 (_effective_addr4) &= ADDRESS_MAXWRAP((_regs)); \ 2149 } \ 2150 (_m3) = (temp >> 16) & 0xf; \ 2151 (_r1) = (temp >> 20) & 0xf; \ 2152 (_i2) = (_inst)[4]; \ 2153 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2154 } 2155 2156 /* RRS register, immediate, mask, and storage */ /*208*/ 2157 #undef RRS 2158 #undef RRS0 2159 #undef RRS_B 2160 2161 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_RRS) 2162 #define RRS(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2163 RRS_DECODER(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 6, 6) 2164 #define RRS0(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2165 RRS_DECODER(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 6, 0) 2166 #define RRS_B(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2167 RRS_DECODER(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 0, 0) 2168 #else 2169 #define RRS(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2170 RRS_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 6, 6) 2171 #define RRS0(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2172 RRS_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 6, 0) 2173 #define RRS_B(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4) \ 2174 RRS_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, 0, 0) 2175 #endif 2176 2177 #define RRS_DECODER(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, _len, _ilc) \ 2178 { U32 temp = fetch_fw(_inst); \ 2179 (_effective_addr4) = temp & 0xfff; \ 2180 (_b4) = (temp >> 12) & 0xf; \ 2181 if((_b4) != 0) \ 2182 { \ 2183 (_effective_addr4) += (_regs)->GR((_b4)); \ 2184 (_effective_addr4) &= ADDRESS_MAXWRAP((_regs)); \ 2185 } \ 2186 (_r2) = (temp >> 16) & 0xf; \ 2187 (_r1) = (temp >> 20) & 0xf; \ 2188 (_m3) = ((_inst)[4] >> 4) & 0xf; \ 2189 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2190 } 2191 2192 #define RRS_DECODER_TEST(_inst, _regs, _r1, _r2, _m3, _b4, _effective_addr4, _len, _ilc) \ 2193 { U32 temp = fetch_fw(_inst); \ 2194 (_effective_addr4) = temp & 0xfff; \ 2195 (_b4) = (temp >> 12) & 0xf; \ 2196 if((_b4)) { \ 2197 (_effective_addr4) += (_regs)->GR((_b4)); \ 2198 (_effective_addr4) &= ADDRESS_MAXWRAP((_regs)); \ 2199 } \ 2200 (_r2) = (temp >> 16) & 0xf; \ 2201 (_r1) = (temp >> 20) & 0xf; \ 2202 (_m3) = ((_inst)[4] >> 4) & 0xf; \ 2203 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2204 } 2205 2206 /* SI storage and immediate */ 2207 #undef SI 2208 2209 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SI) 2210 #define SI(_inst, _regs, _i2, _b1, _effective_addr1) \ 2211 SI_DECODER(_inst, _regs, _i2, _b1, _effective_addr1, 4, 4) 2212 #else 2213 #define SI(_inst, _regs, _i2, _b1, _effective_addr1) \ 2214 SI_DECODER_TEST(_inst, _regs, _i2, _b1, _effective_addr1, 4, 4) 2215 #endif 2216 2217 #define SI_DECODER(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2218 { U32 temp = fetch_fw(_inst); \ 2219 (_i2) = (temp >> 16) & 0xff; \ 2220 (_b1) = (temp >> 12) & 0xf; \ 2221 (_effective_addr1) = temp & 0xfff; \ 2222 if((_b1) != 0) \ 2223 { \ 2224 (_effective_addr1) += (_regs)->GR((_b1)); \ 2225 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2226 } \ 2227 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2228 } 2229 2230 #define SI_DECODER_TEST(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2231 { U32 temp = fetch_fw(_inst); \ 2232 (_effective_addr1) = temp & 0xfff; \ 2233 (_b1) = (temp >> 12) & 0xf; \ 2234 if((_b1)) { \ 2235 (_effective_addr1) += (_regs)->GR((_b1)); \ 2236 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2237 } \ 2238 (_i2) = (temp >> 16) & 0xff; \ 2239 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2240 } 2241 2242 /* SIY storage and immediate with long displacement */ 2243 #undef SIY 2244 2245 #if defined(FEATURE_LONG_DISPLACEMENT) 2246 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SIY) 2247 #define SIY(_inst, _regs, _i2, _b1, _effective_addr1) \ 2248 SIY_DECODER_LD(_inst, _regs, _i2, _b1, _effective_addr1, 6, 6) 2249 #else 2250 #define SIY(_inst, _regs, _i2, _b1, _effective_addr1) \ 2251 SIY_DECODER_LD_TEST(_inst, _regs, _i2, _b1, _effective_addr1, 6, 6) 2252 #endif 2253 #endif /* defined(FEATURE_LONG_DISPLACEMENT) */ 2254 2255 #define SIY_DECODER_LD(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2256 { U32 temp; S32 temp1; \ 2257 temp = fetch_fw(_inst); \ 2258 (_i2) = (temp >> 16) & 0xff; \ 2259 (_b1) = (temp >> 12) & 0xf; \ 2260 temp1 = (_inst[4] << 12) | (temp & 0xfff); \ 2261 if (temp1 & 0x80000) temp1 |= 0xfff00000; \ 2262 (_effective_addr1) = \ 2263 ((_b1) ? (_regs)->GR((_b1)) : (GREG)0) + \ 2264 temp1; \ 2265 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2266 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2267 } 2268 2269 #define SIY_DECODER_LD_TEST(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2270 { U32 temp; S32 disp; \ 2271 temp = fetch_fw(_inst); \ 2272 (_effective_addr1) = 0; \ 2273 (_b1) = (temp >> 12) & 0xf; \ 2274 if ((_b1)) \ 2275 (_effective_addr1) += (_regs)->GR((_b1)); \ 2276 disp = temp & 0xfff; \ 2277 if (unlikely((_inst)[4])) { \ 2278 disp |= (_inst[4] << 12); \ 2279 if (disp & 0x80000) disp |= 0xfff00000; \ 2280 } \ 2281 (_effective_addr1) += disp; \ 2282 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2283 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2284 (_i2) = (temp >> 16) & 0xff; \ 2285 } 2286 2287 /* SIL storage and longer immediate */ /*208*/ 2288 #undef SIL 2289 2290 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SIL) 2291 #define SIL(_inst, _regs, _i2, _b1, _effective_addr1) \ 2292 SIL_DECODER(_inst, _regs, _i2, _b1, _effective_addr1, 6, 6) 2293 #else 2294 #define SIL(_inst, _regs, _i2, _b1, _effective_addr1) \ 2295 SIL_DECODER_TEST(_inst, _regs, _i2, _b1, _effective_addr1, 6, 6) 2296 #endif 2297 2298 #define SIL_DECODER(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2299 { U32 temp = fetch_fw(&(_inst)[2]); \ 2300 (_i2) = temp & 0xffff; \ 2301 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2302 (_b1) = (temp >> 28) & 0xf; \ 2303 if((_b1) != 0) \ 2304 { \ 2305 (_effective_addr1) += (_regs)->GR((_b1)); \ 2306 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2307 } \ 2308 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2309 } 2310 2311 #define SIL_DECODER_TEST(_inst, _regs, _i2, _b1, _effective_addr1, _len, _ilc) \ 2312 { U32 temp = fetch_fw(&(_inst)[2]); \ 2313 (_i2) = temp & 0xffff; \ 2314 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2315 (_b1) = (temp >> 28) & 0xf; \ 2316 if((_b1) != 0) \ 2317 { \ 2318 (_effective_addr1) += (_regs)->GR((_b1)); \ 2319 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2320 } \ 2321 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2322 } 2323 2324 /* SMI storage with mask and 16-bit relative address */ /*912*/ 2325 #undef SMI_A 2326 #undef SMI_A0 2327 2328 #define SMI_A(_inst, _regs, _m1, _addr2, _b3, _addr3) \ 2329 SMI_A_DECODER(_inst, _regs, _m1, _addr2, _b3, _addr3, 6, 6) 2330 #define SMI_A0(_inst, _regs, _m1, _addr2, _b3, _addr3) \ 2331 SMI_A_DECODER(_inst, _regs, _m1, _addr2, _b3, _addr3, 6, 0) 2332 2333 #define SMI_A_DECODER(_inst, _regs, _m1, _addr2, _b3, _addr3, _len, _ilc) \ 2334 { \ 2335 U32 ri2; S64 offset; \ 2336 U32 temp = fetch_fw(&(_inst)[2]); \ 2337 int i = (_inst)[1]; \ 2338 (_m1) = (i >> 4) & 0x0F; \ 2339 ri2 = temp & 0xFFFF; \ 2340 (_addr3) = (temp >> 16) & 0xFFF; \ 2341 (_b3) = (temp >> 28) & 0x0F; \ 2342 if((_b3)) \ 2343 { \ 2344 (_addr3) += (_regs)->GR((_b3)); \ 2345 (_addr3) &= ADDRESS_MAXWRAP((_regs)); \ 2346 } \ 2347 offset = 2LL*(S32)ri2; \ 2348 (_addr2) = (likely(!(_regs)->execflag)) ? \ 2349 PSW_IA((_regs), offset) : \ 2350 ((_regs)->ET + offset) & ADDRESS_MAXWRAP((_regs)); \ 2351 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2352 } 2353 2354 /* S storage operand only */ 2355 #undef S 2356 2357 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_S) 2358 #define S(_inst, _regs, _b2, _effective_addr2) \ 2359 S_DECODER(_inst, _regs, _b2, _effective_addr2, 4, 4) 2360 #else 2361 #define S(_inst, _regs, _b2, _effective_addr2) \ 2362 S_DECODER_TEST(_inst, _regs, _b2, _effective_addr2, 4, 4) 2363 #endif 2364 2365 #define S_DECODER(_inst, _regs, _b2, _effective_addr2, _len, _ilc) \ 2366 { U32 temp = fetch_fw(_inst); \ 2367 (_b2) = (temp >> 12) & 0xf; \ 2368 (_effective_addr2) = temp & 0xfff; \ 2369 if((_b2) != 0) \ 2370 { \ 2371 (_effective_addr2) += (_regs)->GR((_b2)); \ 2372 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2373 } \ 2374 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2375 } 2376 2377 #define S_DECODER_TEST(_inst, _regs, _b2, _effective_addr2, _len, _ilc) \ 2378 { U32 temp = fetch_fw(_inst); \ 2379 (_effective_addr2) = temp & 0xfff; \ 2380 (_b2) = (temp >> 12) & 0xf; \ 2381 if((_b2) != 0) { \ 2382 (_effective_addr2) += (_regs)->GR((_b2)); \ 2383 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2384 } \ 2385 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2386 } 2387 2388 /* SS storage to storage with two 4-bit L or R fields */ 2389 #undef SS 2390 2391 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SS) 2392 #define SS(_inst, _regs, _r1, _r3, \ 2393 _b1, _effective_addr1, _b2, _effective_addr2) \ 2394 SS_DECODER(_inst, _regs, _r1, _r3, \ 2395 _b1, _effective_addr1, _b2, _effective_addr2, 6, 6) 2396 #else 2397 #define SS(_inst, _regs, _r1, _r3, \ 2398 _b1, _effective_addr1, _b2, _effective_addr2) \ 2399 SS_DECODER_TEST(_inst, _regs, _r1, _r3, \ 2400 _b1, _effective_addr1, _b2, _effective_addr2, 6, 6) 2401 #endif 2402 2403 #define SS_DECODER(_inst, _regs, _r1, _r3, \ 2404 _b1, _effective_addr1, _b2, _effective_addr2, _len, _ilc) \ 2405 { U32 temp = fetch_fw(_inst); \ 2406 (_r1) = (temp >> 20) & 0xf; \ 2407 (_r3) = (temp >> 16) & 0xf; \ 2408 (_b1) = (temp >> 12) & 0xf; \ 2409 (_effective_addr1) = temp & 0xfff; \ 2410 if((_b1) != 0) \ 2411 { \ 2412 (_effective_addr1) += (_regs)->GR((_b1)); \ 2413 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2414 } \ 2415 (_b2) = (_inst)[4] >> 4; \ 2416 (_effective_addr2) = (((_inst)[4] & 0x0F) << 8) | (_inst)[5]; \ 2417 if((_b2) != 0) \ 2418 { \ 2419 (_effective_addr2) += (_regs)->GR((_b2)); \ 2420 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2421 } \ 2422 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2423 } 2424 2425 #define SS_DECODER_TEST(_inst, _regs, _r1, _r3, \ 2426 _b1, _effective_addr1, _b2, _effective_addr2, _len, _ilc) \ 2427 { U32 temp; \ 2428 temp = fetch_fw((_inst)+2); \ 2429 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2430 (_b1) = (temp >> 28); \ 2431 if ((_b1)) { \ 2432 (_effective_addr1) += (_regs)->GR((_b1)); \ 2433 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2434 } \ 2435 (_effective_addr2) = temp & 0xfff; \ 2436 (_b2) = (temp >> 12) & 0xf; \ 2437 if ((_b2)) { \ 2438 (_effective_addr2) += (_regs)->GR((_b2)); \ 2439 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2440 } \ 2441 (_r3) = ((_inst)[1] ) & 0xf; \ 2442 (_r1) = ((_inst)[1] >> 4) & 0xf; \ 2443 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2444 } 2445 2446 /* SS storage to storage with one 8-bit L field */ 2447 #undef SS_L 2448 2449 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SS_L) 2450 #define SS_L(_inst, _regs, _l, \ 2451 _b1, _effective_addr1, _b2, _effective_addr2) \ 2452 SS_L_DECODER(_inst, _regs, _l, \ 2453 _b1, _effective_addr1, _b2, _effective_addr2, 6, 6) 2454 #else 2455 #define SS_L(_inst, _regs, _l, \ 2456 _b1, _effective_addr1, _b2, _effective_addr2) \ 2457 SS_L_DECODER_TEST(_inst, _regs, _l, \ 2458 _b1, _effective_addr1, _b2, _effective_addr2, 6, 6) 2459 #endif 2460 2461 #define SS_L_DECODER(_inst, _regs, _l, \ 2462 _b1, _effective_addr1, _b2, _effective_addr2, _len, _ilc) \ 2463 { U32 temp = fetch_fw(_inst); \ 2464 (_l) = (temp >> 16) & 0xff; \ 2465 (_b1) = (temp >> 12) & 0xf; \ 2466 (_effective_addr1) = temp & 0xfff; \ 2467 if((_b1) != 0) \ 2468 { \ 2469 (_effective_addr1) += (_regs)->GR((_b1)); \ 2470 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2471 } \ 2472 (_b2) = (_inst)[4] >> 4; \ 2473 (_effective_addr2) = (((_inst)[4] & 0x0F) << 8) | (_inst)[5]; \ 2474 if((_b2) != 0) \ 2475 { \ 2476 (_effective_addr2) += (_regs)->GR((_b2)); \ 2477 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2478 } \ 2479 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2480 } 2481 2482 #define SS_L_DECODER_TEST(_inst, _regs, _l, \ 2483 _b1, _effective_addr1, _b2, _effective_addr2, _len, _ilc) \ 2484 { U32 temp; \ 2485 temp = fetch_fw((_inst)+2); \ 2486 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2487 (_b1) = (temp >> 28); \ 2488 if((_b1)) { \ 2489 (_effective_addr1) += (_regs)->GR((_b1)); \ 2490 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2491 } \ 2492 (_effective_addr2) = temp & 0xfff; \ 2493 (_b2) = (temp >> 12) & 0xf; \ 2494 if ((_b2)) { \ 2495 (_effective_addr2) += (_regs)->GR((_b2)); \ 2496 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2497 } \ 2498 (_l) = (_inst)[1]; \ 2499 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2500 } 2501 2502 /* SSE storage to storage with extended op code */ 2503 #undef SSE 2504 2505 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SSE) 2506 #define SSE(_inst, _regs, _b1, _effective_addr1, \ 2507 _b2, _effective_addr2) \ 2508 SSE_DECODER(_inst, _regs, _b1, _effective_addr1, \ 2509 _b2, _effective_addr2, 6, 6) 2510 #else 2511 #define SSE(_inst, _regs, _b1, _effective_addr1, \ 2512 _b2, _effective_addr2) \ 2513 SSE_DECODER_TEST(_inst, _regs, _b1, _effective_addr1, \ 2514 _b2, _effective_addr2, 6, 6) 2515 #endif 2516 2517 #define SSE_DECODER(_inst, _regs, _b1, _effective_addr1, \ 2518 _b2, _effective_addr2, _len, _ilc) \ 2519 { U32 temp = fetch_fw(_inst); \ 2520 (_b1) = (temp >> 12) & 0xf; \ 2521 (_effective_addr1) = temp & 0xfff; \ 2522 if((_b1) != 0) \ 2523 { \ 2524 (_effective_addr1) += (_regs)->GR((_b1)); \ 2525 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2526 } \ 2527 (_b2) = (_inst)[4] >> 4; \ 2528 (_effective_addr2) = (((_inst)[4] & 0x0F) << 8) | (_inst)[5]; \ 2529 if((_b2) != 0) \ 2530 { \ 2531 (_effective_addr2) += (_regs)->GR((_b2)); \ 2532 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2533 } \ 2534 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2535 } 2536 2537 #define SSE_DECODER_TEST(_inst, _regs, _b1, _effective_addr1, \ 2538 _b2, _effective_addr2, _len, _ilc) \ 2539 { U32 temp = fetch_fw((_inst)+2); \ 2540 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2541 (_b1) = (temp >> 28); \ 2542 if((_b1)) { \ 2543 (_effective_addr1) += (_regs)->GR((_b1)); \ 2544 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2545 } \ 2546 (_effective_addr2) = temp & 0xfff; \ 2547 (_b2) = (temp >> 12) & 0xf; \ 2548 if ((_b2)) { \ 2549 (_effective_addr2) += (_regs)->GR((_b2)); \ 2550 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2551 } \ 2552 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2553 } 2554 2555 /* SSF storage to storage with additional register */ 2556 #undef SSF 2557 2558 #if !defined(DECODER_TEST)&&!defined(DECODER_TEST_SSF) 2559 #define SSF(_inst, _regs, _b1, _effective_addr1, \ 2560 _b2, _effective_addr2, _r3) \ 2561 SSF_DECODER(_inst, _regs, _b1, _effective_addr1, \ 2562 _b2, _effective_addr2, _r3, 6, 6) 2563 #else 2564 #define SSF(_inst, _regs, _b1, _effective_addr1, \ 2565 _b2, _effective_addr2, _r3) \ 2566 SSF_DECODER_TEST(_inst, _regs, _b1, _effective_addr1, \ 2567 _b2, _effective_addr2, _r3, 6, 6) 2568 #endif 2569 2570 #define SSF_DECODER(_inst, _regs, _b1, _effective_addr1, \ 2571 _b2, _effective_addr2, _r3, _len, _ilc) \ 2572 { U32 temp = fetch_fw(_inst); \ 2573 (_r3) = (temp >> 20) & 0xf; \ 2574 (_b1) = (temp >> 12) & 0xf; \ 2575 (_effective_addr1) = temp & 0xfff; \ 2576 if((_b1) != 0) \ 2577 { \ 2578 (_effective_addr1) += (_regs)->GR((_b1)); \ 2579 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2580 } \ 2581 (_b2) = (_inst)[4] >> 4; \ 2582 (_effective_addr2) = (((_inst)[4] & 0x0F) << 8) | (_inst)[5]; \ 2583 if((_b2) != 0) \ 2584 { \ 2585 (_effective_addr2) += (_regs)->GR((_b2)); \ 2586 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2587 } \ 2588 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2589 } 2590 2591 #define SSF_DECODER_TEST(_inst, _regs, _b1, _effective_addr1, \ 2592 _b2, _effective_addr2, _r3, _len, _ilc) \ 2593 { U32 temp; \ 2594 temp = fetch_fw((_inst)+2); \ 2595 (_effective_addr1) = (temp >> 16) & 0xfff; \ 2596 (_b1) = (temp >> 28); \ 2597 if((_b1)) { \ 2598 (_effective_addr1) += (_regs)->GR((_b1)); \ 2599 (_effective_addr1) &= ADDRESS_MAXWRAP((_regs)); \ 2600 } \ 2601 (_effective_addr2) = temp & 0xfff; \ 2602 (_b2) = (temp >> 12) & 0xf; \ 2603 if ((_b2)) { \ 2604 (_effective_addr2) += (_regs)->GR((_b2)); \ 2605 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2606 } \ 2607 (_b1) = ((_inst)[1] ) & 0xf;\ 2608 (_r3) = ((_inst)[1] >> 4) & 0xf; \ 2609 INST_UPDATE_PSW((_regs), (_len), (_ilc)); \ 2610 } 2611 2612 #undef SIE_TRANSLATE_ADDR 2613 #undef SIE_LOGICAL_TO_ABS 2614 #undef SIE_INTERCEPT 2615 #undef SIE_TRANSLATE 2616 2617 2618 #if defined(_FEATURE_SIE) 2619 2620 #define SIE_SET_VI(_who, _when, _why, _regs) \ 2621 { \ 2622 (_regs)->siebk->vi_who = (_who); \ 2623 (_regs)->siebk->vi_when = (_when); \ 2624 STORE_HW((_regs)->siebk->vi_why, (_why)); \ 2625 memset((_regs)->siebk->vi_zero, 0, 6); \ 2626 } 2627 2628 #if __GEN_ARCH == 900 || (__GEN_ARCH == 390 && !defined(_FEATURE_ZSIE)) 2629 2630 #define SIE_TRANSLATE_ADDR(_addr, _arn, _regs, _acctype) \ 2631 ARCH_DEP(translate_addr)((_addr), (_arn), (_regs), (_acctype)) 2632 2633 #define SIE_LOGICAL_TO_ABS(_addr, _arn, _regs, _acctype, _akey) \ 2634 ( \ 2635 ARCH_DEP(logical_to_main)((_addr), (_arn), (_regs), (_acctype), (_akey)), \ 2636 (_regs)->dat.aaddr \ 2637 ) 2638 2639 #elif __GEN_ARCH == 370 && defined(_FEATURE_SIE) 2640 2641 #define SIE_TRANSLATE_ADDR(_addr, _arn, _regs, _acctype) \ 2642 s390_translate_addr((_addr), (_arn), (_regs), (_acctype)) 2643 2644 #define SIE_LOGICAL_TO_ABS(_addr, _arn, _regs, _acctype, _akey) \ 2645 ( \ 2646 s390_logical_to_main((_addr), (_arn), (_regs), (_acctype), (_akey)), \ 2647 (_regs)->dat.aaddr \ 2648 ) 2649 2650 #else /*__GEN_ARCH == 390 && defined(_FEATURE_ZSIE)*/ 2651 2652 #define SIE_TRANSLATE_ADDR(_addr, _arn, _regs, _acctype) \ 2653 ( ((_regs)->arch_mode == ARCH_390) ? \ 2654 s390_translate_addr((_addr), (_arn), (_regs), (_acctype)) : \ 2655 z900_translate_addr((_addr), (_arn), (_regs), (_acctype)) ) 2656 2657 #define SIE_LOGICAL_TO_ABS(_addr, _arn, _regs, _acctype, _akey) \ 2658 ( \ 2659 (((_regs)->arch_mode == ARCH_390) \ 2660 ? s390_logical_to_main((_addr), (_arn), (_regs), (_acctype), (_akey)) \ 2661 : z900_logical_to_main((_addr), (_arn), (_regs), (_acctype), (_akey))), \ 2662 (_regs)->dat.aaddr \ 2663 ) 2664 2665 #endif 2666 2667 #define SIE_INTERCEPT(_regs) \ 2668 do { \ 2669 if(SIE_MODE((_regs))) \ 2670 longjmp((_regs)->progjmp, SIE_INTERCEPT_INST); \ 2671 } while(0) 2672 2673 #define SIE_TRANSLATE(_addr, _acctype, _regs) \ 2674 do { \ 2675 if(SIE_MODE((_regs)) && !(_regs)->sie_pref) \ 2676 *(_addr) = SIE_LOGICAL_TO_ABS ((_regs)->sie_mso + *(_addr), \ 2677 USE_PRIMARY_SPACE, (_regs)->hostregs, (_acctype), 0); \ 2678 } while(0) 2679 2680 #else /*!defined(_FEATURE_SIE)*/ 2681 2682 #define SIE_TRANSLATE_ADDR(_addr, _arn, _regs, _acctype) 2683 #define SIE_LOGICAL_TO_ABS(_addr, _arn, _regs, _acctype, _akey) 2684 #define SIE_INTERCEPT(_regs) 2685 #define SIE_TRANSLATE(_addr, _acctype, _regs) 2686 2687 #endif /*!defined(_FEATURE_SIE)*/ 2688 2689 2690 #undef SIE_XC_INTERCEPT 2691 2692 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE) 2693 2694 #define SIE_XC_INTERCEPT(_regs) \ 2695 if(SIE_STATB((_regs), MX, XC)) \ 2696 SIE_INTERCEPT((_regs)) 2697 2698 #else /*!defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/ 2699 2700 #define SIE_XC_INTERCEPT(_regs) 2701 2702 #endif /*!defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/ 2703 2704 2705 #if defined(FEATURE_VECTOR_FACILITY) 2706 2707 #if !defined(_VFDEFS) 2708 2709 #define _VFDEFS 2710 2711 #define VOP_CHECK(_regs) \ 2712 if(!((_regs)->CR(0) & CR0_VOP) || !(_regs)->vf->online) \ 2713 (_regs)->program_interrupt((_regs), PGM_VECTOR_OPERATION_EXCEPTION) 2714 2715 #define VR_INUSE(_vr, _regs) \ 2716 ((_regs)->vf->vsr & (VSR_VIU0 >> ((_vr) >> 1))) 2717 2718 #define VR_CHANGED(_vr, _regs) \ 2719 ((_regs)->vf->vsr & (VSR_VCH0 >> ((_vr) >> 1))) 2720 2721 #define SET_VR_INUSE(_vr, _regs) \ 2722 (_regs)->vf->vsr |= (VSR_VIU0 >> ((_vr) >> 1)) 2723 2724 #define SET_VR_CHANGED(_vr, _regs) \ 2725 (_regs)->vf->vsr |= (VSR_VCH0 >> ((_vr) >> 1)) 2726 2727 #define RESET_VR_INUSE(_vr, _regs) \ 2728 (_regs)->vf->vsr &= ~(VSR_VIU0 >> ((_vr) >> 1)) 2729 2730 #define RESET_VR_CHANGED(_vr, _regs) \ 2731 (_regs)->vf->vsr &= ~(VSR_VCH0 >> ((_vr) >> 1)) 2732 2733 #define VMR_SET(_section, _regs) \ 2734 ((_regs)->vf->vmr[(_section) >> 3] & (0x80 >> ((_section) & 7))) 2735 2736 #define MASK_MODE(_regs) \ 2737 ((_regs)->vf->vsr & VSR_M) 2738 2739 #define VECTOR_COUNT(_regs) \ 2740 (((_regs)->vf->vsr & VSR_VCT) >> 32) 2741 2742 #define VECTOR_IX(_regs) \ 2743 (((_regs)->vf->vsr & VSR_VIX) >> 16) 2744 2745 #endif /*!defined(_VFDEFS)*/ 2746 2747 /* VST and QST formats are the same */ 2748 #undef VST 2749 #define VST(_inst, _regs, _vr3, _rt2, _vr1, _rs2) \ 2750 { \ 2751 (_qr3) = (_inst)[2] >> 4; \ 2752 (_rt2) = (_inst)[2] & 0x0F; \ 2753 (_vr1) = (_inst)[3] >> 4; \ 2754 (_rs2) = (_inst)[3] & 0x0F; \ 2755 INST_UPDATE_PSW((_regs), 4, 4); \ 2756 } 2757 2758 /* VR, VV and QV formats are the same */ 2759 #undef VR 2760 #define VR(_inst, _regs, _qr3, _vr1, _vr2) \ 2761 { \ 2762 (_qr3) = (_inst)[2] >> 4; \ 2763 (_vr1) = (_inst)[3] >> 4; \ 2764 (_vr2) = (_inst)[3] & 0x0F; \ 2765 INST_UPDATE_PSW((_regs), 4, 4); \ 2766 } 2767 2768 #undef VS 2769 #define VS(_inst, _regs, _rs2) \ 2770 { \ 2771 (_rs2) = (_inst)[3] & 0x0F; \ 2772 INST_UPDATE_PSW((_regs), 4, 4); \ 2773 } 2774 2775 /* The RSE vector instruction format of ESA/390 is referred to as 2776 VRSE to avoid conflict with the ESAME RSE instruction format */ 2777 #undef VRSE 2778 #define VRSE(_inst, _regs, _r3, _vr1, \ 2779 _b2, _effective_addr2) \ 2780 { \ 2781 (_r3) = (_inst)[2] >> 4; \ 2782 (_vr1) = (_inst)[3] >> 4; \ 2783 (_b2) = (_inst)[4] >> 4; \ 2784 (_effective_addr2) = (((_inst)[4] & 0x0F) << 8) | (_inst)[5]; \ 2785 if((_b2) != 0) \ 2786 { \ 2787 (_effective_addr2) += (_regs)->GR((_b2)); \ 2788 (_effective_addr2) &= ADDRESS_MAXWRAP((_regs)); \ 2789 } \ 2790 INST_UPDATE_PSW((_regs), 6, 6); \ 2791 } 2792 2793 /* S format instructions where the effective address does not wrap */ 2794 #undef S_NW 2795 #define S_NW(_inst, _regs, _b2, _effective_addr2) \ 2796 { \ 2797 (_b2) = (_inst)[2] >> 4; \ 2798 (_effective_addr2) = (((_inst)[2] & 0x0F) << 8) | (_inst)[3]; \ 2799 if((_b2) != 0) \ 2800 { \ 2801 (_effective_addr2) += (_regs)->GR((_b2)); \ 2802 } \ 2803 INST_UPDATE_PSW((_regs), 4, 4); \ 2804 } 2805 2806 #endif /*defined(FEATURE_VECTOR_FACILITY)*/ 2807 2808 #define PERFORM_SERIALIZATION(_regs) do { } while (0) 2809 #define PERFORM_CHKPT_SYNC(_regs) do { } while (0) 2810 2811 /* Functions in module channel.c */ 2812 int ARCH_DEP(startio) (REGS *regs, DEVBLK *dev, ORB *orb); 2813 void *s370_execute_ccw_chain (DEVBLK *dev); 2814 void *s390_execute_ccw_chain (DEVBLK *dev); 2815 void *z900_execute_ccw_chain (DEVBLK *dev); 2816 int stchan_id (REGS *regs, U16 chan); 2817 int testch (REGS *regs, U16 chan); 2818 int testio (REGS *regs, DEVBLK *dev, BYTE ibyte); 2819 int test_subchan (REGS *regs, DEVBLK *dev, IRB *irb); 2820 int cancel_subchan (REGS *regs, DEVBLK *dev); 2821 void clear_subchan (REGS *regs, DEVBLK *dev); 2822 int halt_subchan (REGS *regs, DEVBLK *dev); 2823 int haltio (REGS *regs, DEVBLK *dev, BYTE ibyte); 2824 int resume_subchan (REGS *regs, DEVBLK *dev); 2825 int ARCH_DEP(present_io_interrupt) (REGS *regs, U32 *ioid, 2826 U32 *ioparm, U32 *iointid, BYTE *csw); 2827 int ARCH_DEP(present_zone_io_interrupt) (U32 *ioid, U32 *ioparm, 2828 U32 *iointid, BYTE zone); 2829 void io_reset (void); 2830 int chp_reset(REGS *, BYTE chpid); 2831 void channelset_reset(REGS *regs); 2832 DLL_EXPORT int device_attention (DEVBLK *dev, BYTE unitstat); 2833 DLL_EXPORT int ARCH_DEP(device_attention) (DEVBLK *dev, BYTE unitstat); 2834 2835 2836 /* Functions in module cpu.c */ 2837 /* define all arch_load|store_psw */ 2838 /* regardless of current architecture (if any) */ 2839 #if defined(_370) 2840 void s370_store_psw (REGS *regs, BYTE *addr); 2841 int s370_load_psw (REGS *regs, BYTE *addr); 2842 void s370_process_trace (REGS *regs); 2843 #endif 2844 #if defined(_390) 2845 int s390_load_psw (REGS *regs, BYTE *addr); 2846 void s390_store_psw (REGS *regs, BYTE *addr); 2847 void s390_process_trace (REGS *regs); 2848 #endif /*defined(_FEATURE_ZSIE)*/ 2849 #if defined(_900) 2850 int z900_load_psw (REGS *regs, BYTE *addr); 2851 void z900_store_psw (REGS *regs, BYTE *addr); 2852 void z900_process_trace (REGS *regs); 2853 #endif 2854 2855 int cpu_init (int cpu, REGS *regs, REGS *hostregs); 2856 void ARCH_DEP(perform_io_interrupt) (REGS *regs); 2857 void ARCH_DEP(checkstop_config)(void); 2858 #if defined(_FEATURE_SIE) 2859 CPU_DLL_IMPORT void (ATTR_REGPARM(2) s370_program_interrupt) (REGS *regs, int code); 2860 #endif /*!defined(_FEATURE_SIE)*/ 2861 #if defined(_FEATURE_ZSIE) 2862 CPU_DLL_IMPORT void (ATTR_REGPARM(2) s390_program_interrupt) (REGS *regs, int code); 2863 #endif /*!defined(_FEATURE_ZSIE)*/ 2864 CPU_DLL_IMPORT void (ATTR_REGPARM(2) ARCH_DEP(program_interrupt)) (REGS *regs, int code); 2865 void *cpu_thread (int *cpu); 2866 DLL_EXPORT void copy_psw (REGS *regs, BYTE *addr); 2867 void display_psw (REGS *regs); 2868 2869 2870 /* Functions in module vm.c */ 2871 int ARCH_DEP(diag_devtype) (int r1, int r2, REGS *regs); 2872 int ARCH_DEP(syncblk_io) (int r1, int r2, REGS *regs); 2873 int ARCH_DEP(syncgen_io) (int r1, int r2, REGS *regs); 2874 void ARCH_DEP(extid_call) (int r1, int r2, REGS *regs); 2875 int ARCH_DEP(cpcmd_call) (int r1, int r2, REGS *regs); 2876 void ARCH_DEP(pseudo_timer) (U32 code, int r1, int r2, REGS *regs); 2877 void ARCH_DEP(access_reipl_data) (int r1, int r2, REGS *regs); 2878 int ARCH_DEP(diag_ppagerel) (int r1, int r2, REGS *regs); 2879 void ARCH_DEP(vm_info) (int r1, int r2, REGS *regs); 2880 int ARCH_DEP(device_info) (int r1, int r2, REGS *regs); 2881 2882 2883 /* Functions in module vmd250.c */ 2884 int ARCH_DEP(vm_blockio) (int r1, int r2, REGS *regs); 2885 2886 2887 /* Functions in module control.c */ 2888 void ARCH_DEP(load_real_address_proc) (REGS *regs, 2889 int r1, int b2, VADR effective_addr2); 2890 2891 2892 /* Functions in module decimal.c */ 2893 void packed_to_binary (BYTE *dec, int len, U64 *result, 2894 int *ovf, int *dxf); 2895 void binary_to_packed (S64 bin, BYTE *result); 2896 2897 2898 /* Functions in module diagnose.c */ 2899 void ARCH_DEP(diagnose_call) (VADR effective_addr2, int b2, int r1, int r3, 2900 REGS *regs); 2901 2902 2903 /* Functions in module diagmssf.c */ 2904 void ARCH_DEP(scpend_call) (void); 2905 int ARCH_DEP(mssf_call) (int r1, int r2, REGS *regs); 2906 void ARCH_DEP(diag204_call) (int r1, int r2, REGS *regs); 2907 void ARCH_DEP(diag224_call) (int r1, int r2, REGS *regs); 2908 2909 2910 /* Functions in module external.c */ 2911 void ARCH_DEP(perform_external_interrupt) (REGS *regs); 2912 void ARCH_DEP(store_status) (REGS *ssreg, RADR aaddr); 2913 void store_status (REGS *ssreg, U64 aaddr); 2914 2915 2916 /* Functions in module ipl.c */ 2917 int load_ipl (U16 lcss, U16 devnum, int cpu, int clear); 2918 int ARCH_DEP(load_ipl) (U16 lcss, U16 devnum, int cpu, int clear); 2919 int system_reset (int cpu, int clear); 2920 int ARCH_DEP(system_reset) (int cpu, int clear); 2921 int cpu_reset (REGS *regs); 2922 int ARCH_DEP(cpu_reset) (REGS *regs); 2923 int initial_cpu_reset (REGS *regs); 2924 int ARCH_DEP(initial_cpu_reset) (REGS *regs); 2925 int ARCH_DEP(common_load_begin) (int cpu, int clear); 2926 int ARCH_DEP(common_load_finish) (REGS *regs); 2927 void storage_clear(void); 2928 void xstorage_clear(void); 2929 2930 2931 /* Functions in module scedasd.c */ 2932 void set_sce_dir (char *path); 2933 char *get_sce_dir (); 2934 int load_main (char *fname, RADR startloc); 2935 int ARCH_DEP(load_main) (char *fname, RADR startloc); 2936 int load_hmc (char *fname, int cpu, int clear); 2937 int ARCH_DEP(load_hmc) (char *fname, int cpu, int clear); 2938 void ARCH_DEP(sclp_scedio_request) (SCCB_HEADER *); 2939 void ARCH_DEP(sclp_scedio_event) (SCCB_HEADER *); 2940 2941 2942 /* Functions in module machchk.c */ 2943 int ARCH_DEP(present_mck_interrupt) (REGS *regs, U64 *mcic, U32 *xdmg, 2944 RADR *fsta); 2945 U32 channel_report (REGS *); 2946 void machine_check_crwpend (void); 2947 void ARCH_DEP(sync_mck_interrupt) (REGS *regs); 2948 void sigabend_handler (int signo); 2949 2950 2951 /* Functions in module opcode.c */ 2952 OPC_DLL_IMPORT void copy_opcode_tables (); 2953 void set_opcode_pointers (REGS *regs); 2954 2955 2956 /* Functions in module panel.c */ 2957 void ARCH_DEP(display_inst) (REGS *regs, BYTE *inst); 2958 void display_inst (REGS *regs, BYTE *inst); 2959 2960 2961 /* Functions in module sie.c */ 2962 void ARCH_DEP(sie_exit) (REGS *regs, int code); 2963 void ARCH_DEP(diagnose_002) (REGS *regs, int r1, int r3); 2964 2965 2966 /* Functions in module stack.c */ 2967 void ARCH_DEP(trap_x) (int trap_is_trap4, REGS *regs, U32 trap_operand); 2968 void ARCH_DEP(form_stack_entry) (BYTE etype, VADR retna, VADR calla, 2969 U32 csi, U32 pcnum, REGS *regs); 2970 VADR ARCH_DEP(locate_stack_entry) (int prinst, LSED *lsedptr, 2971 REGS *regs); 2972 void ARCH_DEP(stack_modify) (VADR lsea, U32 m1, U32 m2, REGS *regs); 2973 void ARCH_DEP(stack_extract) (VADR lsea, int r1, int code, REGS *regs); 2974 void ARCH_DEP(unstack_registers) (int gtype, VADR lsea, int r1, 2975 int r2, REGS *regs); 2976 int ARCH_DEP(program_return_unstack) (REGS *regs, RADR *lsedap, int *rc); 2977 2978 2979 /* Functions in module trace.c */ 2980 CREG ARCH_DEP(trace_br) (int amode, VADR ia, REGS *regs); 2981 #if defined(_FEATURE_ZSIE) 2982 U32 s390_trace_br (int amode, U32 ia, REGS *regs); 2983 #endif /*!defined(_FEATURE_ZSIE)*/ 2984 CREG ARCH_DEP(trace_bsg) (U32 alet, VADR ia, REGS *regs); 2985 CREG ARCH_DEP(trace_ssar) (int ssair, U16 sasn, REGS *regs); 2986 CREG ARCH_DEP(trace_pc) (U32 pcea, REGS *regs); 2987 CREG ARCH_DEP(trace_pr) (REGS *newregs, REGS *regs); 2988 CREG ARCH_DEP(trace_pt) (int pti, U16 pasn, GREG gpr2, REGS *regs); 2989 CREG ARCH_DEP(trace_tr) (int r1, int r3, U32 op, REGS *regs); 2990 CREG ARCH_DEP(trace_tg) (int r1, int r3, U32 op, REGS *regs); 2991 CREG ARCH_DEP(trace_ms) (int br_ind, VADR ia, REGS *regs); 2992 2993 2994 /* Functions in module plo.c */ 2995 int ARCH_DEP(plo_cl) (int r1, int r3, VADR effective_addr2, int b2, 2996 VADR effective_addr4, int b4, REGS *regs); 2997 int ARCH_DEP(plo_clg) (int r1, int r3, VADR effective_addr2, int b2, 2998 VADR effective_addr4, int b4, REGS *regs); 2999 int ARCH_DEP(plo_clgr) (int r1, int r3, VADR effective_addr2, int b2, 3000 VADR effective_addr4, int b4, REGS *regs); 3001 int ARCH_DEP(plo_clx) (int r1, int r3, VADR effective_addr2, int b2, 3002 VADR effective_addr4, int b4, REGS *regs); 3003 int ARCH_DEP(plo_cs) (int r1, int r3, VADR effective_addr2, int b2, 3004 VADR effective_addr4, int b4, REGS *regs); 3005 int ARCH_DEP(plo_csg) (int r1, int r3, VADR effective_addr2, int b2, 3006 VADR effective_addr4, int b4, REGS *regs); 3007 int ARCH_DEP(plo_csgr) (int r1, int r3, VADR effective_addr2, int b2, 3008 VADR effective_addr4, int b4, REGS *regs); 3009 int ARCH_DEP(plo_csx) (int r1, int r3, VADR effective_addr2, int b2, 3010 VADR effective_addr4, int b4, REGS *regs); 3011 int ARCH_DEP(plo_dcs) (int r1, int r3, VADR effective_addr2, int b2, 3012 VADR effective_addr4, int b4, REGS *regs); 3013 int ARCH_DEP(plo_dcsg) (int r1, int r3, VADR effective_addr2, int b2, 3014 VADR effective_addr4, int b4, REGS *regs); 3015 int ARCH_DEP(plo_dcsgr) (int r1, int r3, VADR effective_addr2, int b2, 3016 VADR effective_addr4, int b4, REGS *regs); 3017 int ARCH_DEP(plo_dcsx) (int r1, int r3, VADR effective_addr2, int b2, 3018 VADR effective_addr4, int b4, REGS *regs); 3019 int ARCH_DEP(plo_csst) (int r1, int r3, VADR effective_addr2, int b2, 3020 VADR effective_addr4, int b4, REGS *regs); 3021 int ARCH_DEP(plo_csstg) (int r1, int r3, VADR effective_addr2, int b2, 3022 VADR effective_addr4, int b4, REGS *regs); 3023 int ARCH_DEP(plo_csstgr) (int r1, int r3, VADR effective_addr2, int b2, 3024 VADR effective_addr4, int b4, REGS *regs); 3025 int ARCH_DEP(plo_csstx) (int r1, int r3, VADR effective_addr2, int b2, 3026 VADR effective_addr4, int b4, REGS *regs); 3027 int ARCH_DEP(plo_csdst) (int r1, int r3, VADR effective_addr2, int b2, 3028 VADR effective_addr4, int b4, REGS *regs); 3029 int ARCH_DEP(plo_csdstg) (int r1, int r3, VADR effective_addr2, int b2, 3030 VADR effective_addr4, int b4, REGS *regs); 3031 int ARCH_DEP(plo_csdstgr) (int r1, int r3, VADR effective_addr2, int b2, 3032 VADR effective_addr4, int b4, REGS *regs); 3033 int ARCH_DEP(plo_csdstx) (int r1, int r3, VADR effective_addr2, int b2, 3034 VADR effective_addr4, int b4, REGS *regs); 3035 int ARCH_DEP(plo_cstst) (int r1, int r3, VADR effective_addr2, int b2, 3036 VADR effective_addr4, int b4, REGS *regs); 3037 int ARCH_DEP(plo_cststg) (int r1, int r3, VADR effective_addr2, int b2, 3038 VADR effective_addr4, int b4, REGS *regs); 3039 int ARCH_DEP(plo_cststgr) (int r1, int r3, VADR effective_addr2, int b2, 3040 VADR effective_addr4, int b4, REGS *regs); 3041 int ARCH_DEP(plo_cststx) (int r1, int r3, VADR effective_addr2, int b2, 3042 VADR effective_addr4, int b4, REGS *regs); 3043 3044 3045 /* Instruction functions in opcode.c */ 3046 DEF_INST(execute_01xx); 3047 DEF_INST(execute_a4xx); 3048 DEF_INST(execute_a5xx); 3049 DEF_INST(execute_a6xx); 3050 DEF_INST(execute_a7xx); 3051 DEF_INST(execute_b2xx); 3052 DEF_INST(execute_b3xx); 3053 DEF_INST(execute_b9xx); 3054 DEF_INST(execute_c0xx); 3055 DEF_INST(execute_e3xx); 3056 DEF_INST(execute_e4xx); 3057 DEF_INST(execute_e5xx); 3058 DEF_INST(execute_ebxx); 3059 DEF_INST(execute_ecxx); 3060 DEF_INST(execute_edxx); 3061 DEF_INST(operation_exception); 3062 DEF_INST(dummy_instruction); 3063 3064 3065 /* Instructions in assist.c */ 3066 DEF_INST(fix_page); 3067 DEF_INST(svc_assist); 3068 DEF_INST(obtain_local_lock); 3069 DEF_INST(release_local_lock); 3070 DEF_INST(obtain_cms_lock); 3071 DEF_INST(release_cms_lock); 3072 DEF_INST(trace_svc_interruption); 3073 DEF_INST(trace_program_interruption); 3074 DEF_INST(trace_initial_srb_dispatch); 3075 DEF_INST(trace_io_interruption); 3076 DEF_INST(trace_task_dispatch); 3077 DEF_INST(trace_svc_return); 3078 3079 3080 /* Instructions in cmpsc.c */ 3081 DEF_INST(compression_call); 3082 3083 3084 /* Instructions in crypto.c */ 3085 DEF_INST(cipher_message_r); 3086 DEF_INST(cipher_message_with_chaining_r); 3087 DEF_INST(compute_intermediate_message_digest_r); 3088 DEF_INST(compute_last_message_digest_r); 3089 DEF_INST(compute_message_authentication_code_r); 3090 DEF_INST(perform_cryptographic_key_management_operation_r); 3091 DEF_INST(cipher_message_with_cipher_feedback_r); 3092 DEF_INST(cipher_message_with_counter_r); 3093 DEF_INST(cipher_message_with_output_feedback_r); 3094 DEF_INST(perform_cryptographic_computation_r); 3095 3096 3097 /* Instructions in control.c */ 3098 DEF_INST(branch_and_set_authority); 3099 DEF_INST(branch_in_subspace_group); 3100 DEF_INST(branch_and_stack); 3101 DEF_INST(compare_and_swap_and_purge); 3102 DEF_INST(diagnose); 3103 DEF_INST(extract_primary_asn); 3104 DEF_INST(extract_primary_asn_and_instance); 3105 DEF_INST(extract_secondary_asn); 3106 DEF_INST(extract_secondary_asn_and_instance); 3107 DEF_INST(extract_stacked_registers); 3108 DEF_INST(extract_stacked_state); 3109 DEF_INST(insert_address_space_control); 3110 DEF_INST(insert_psw_key); 3111 DEF_INST(insert_storage_key); 3112 DEF_INST(insert_storage_key_extended); 3113 DEF_INST(insert_virtual_storage_key); 3114 DEF_INST(invalidate_page_table_entry); 3115 DEF_INST(load_address_space_parameters); 3116 DEF_INST(load_control); 3117 DEF_INST(load_program_status_word); 3118 DEF_INST(load_real_address); 3119 DEF_INST(load_using_real_address); 3120 DEF_INST(lock_page); 3121 DEF_INST(modify_stacked_state); 3122 DEF_INST(move_to_primary); 3123 DEF_INST(move_to_secondary); 3124 DEF_INST(move_with_destination_key); 3125 DEF_INST(move_with_key); 3126 DEF_INST(move_with_optional_specifications); /*208*/ 3127 DEF_INST(move_with_source_key); 3128 DEF_INST(program_call); 3129 DEF_INST(program_return); 3130 DEF_INST(program_transfer); 3131 DEF_INST(program_transfer_with_instance); 3132 DEF_INST(purge_accesslist_lookaside_buffer); 3133 DEF_INST(purge_translation_lookaside_buffer); 3134 DEF_INST(reset_reference_bit); 3135 DEF_INST(reset_reference_bit_extended); 3136 DEF_INST(set_address_space_control); 3137 DEF_INST(set_address_space_control_fast); 3138 DEF_INST(set_clock); 3139 DEF_INST(set_clock_comparator); 3140 DEF_INST(set_clock_programmable_field); 3141 DEF_INST(set_cpu_timer); 3142 DEF_INST(set_prefix); 3143 DEF_INST(set_psw_key_from_address); 3144 DEF_INST(set_secondary_asn); 3145 DEF_INST(set_secondary_asn_with_instance); 3146 DEF_INST(set_storage_key); 3147 DEF_INST(set_storage_key_extended); 3148 DEF_INST(set_system_mask); 3149 DEF_INST(signal_processor); 3150 DEF_INST(store_clock_comparator); 3151 DEF_INST(store_control); 3152 DEF_INST(store_cpu_address); 3153 DEF_INST(store_cpu_id); 3154 DEF_INST(store_cpu_timer); 3155 DEF_INST(store_prefix); 3156 DEF_INST(store_system_information); 3157 DEF_INST(store_then_and_system_mask); 3158 DEF_INST(store_then_or_system_mask); 3159 DEF_INST(store_using_real_address); 3160 DEF_INST(test_access); 3161 DEF_INST(test_block); 3162 DEF_INST(test_protection); 3163 DEF_INST(trace); 3164 3165 3166 /* Instructions in decimal.c */ 3167 DEF_INST(add_decimal); 3168 DEF_INST(compare_decimal); 3169 DEF_INST(divide_decimal); 3170 DEF_INST(edit_x_edit_and_mark); 3171 DEF_INST(multiply_decimal); 3172 DEF_INST(shift_and_round_decimal); 3173 DEF_INST(subtract_decimal); 3174 DEF_INST(zero_and_add); 3175 DEF_INST(test_decimal); 3176 3177 3178 /* Instructions in vm.c */ 3179 DEF_INST(inter_user_communication_vehicle); 3180 3181 3182 /* Instructions in sie.c */ 3183 DEF_INST(start_interpretive_execution); 3184 DEF_INST(store_zone_parameter); 3185 DEF_INST(set_zone_parameter); 3186 DEF_INST(test_pending_zone_interrupt); 3187 3188 3189 /* Instructions in qdio.c */ 3190 DEF_INST(signal_adapter); 3191 3192 3193 /* Instructions in float.c */ 3194 DEF_INST(load_positive_float_long_reg); 3195 DEF_INST(load_negative_float_long_reg); 3196 DEF_INST(load_and_test_float_long_reg); 3197 DEF_INST(load_complement_float_long_reg); 3198 DEF_INST(halve_float_long_reg); 3199 DEF_INST(load_rounded_float_long_reg); 3200 DEF_INST(multiply_float_ext_reg); 3201 DEF_INST(multiply_float_long_to_ext_reg); 3202 DEF_INST(load_float_long_reg); 3203 DEF_INST(compare_float_long_reg); 3204 DEF_INST(add_float_long_reg); 3205 DEF_INST(subtract_float_long_reg); 3206 DEF_INST(multiply_float_long_reg); 3207 DEF_INST(divide_float_long_reg); 3208 DEF_INST(add_unnormal_float_long_reg); 3209 DEF_INST(subtract_unnormal_float_long_reg); 3210 DEF_INST(load_positive_float_short_reg); 3211 DEF_INST(load_negative_float_short_reg); 3212 DEF_INST(load_and_test_float_short_reg); 3213 DEF_INST(load_complement_float_short_reg); 3214 DEF_INST(halve_float_short_reg); 3215 DEF_INST(load_rounded_float_short_reg); 3216 DEF_INST(add_float_ext_reg); 3217 DEF_INST(subtract_float_ext_reg); 3218 DEF_INST(load_float_short_reg); 3219 DEF_INST(compare_float_short_reg); 3220 DEF_INST(add_float_short_reg); 3221 DEF_INST(subtract_float_short_reg); 3222 DEF_INST(multiply_float_short_to_long_reg); 3223 DEF_INST(divide_float_short_reg); 3224 DEF_INST(add_unnormal_float_short_reg); 3225 DEF_INST(subtract_unnormal_float_short_reg); 3226 DEF_INST(store_float_long); 3227 DEF_INST(multiply_float_long_to_ext); 3228 DEF_INST(load_float_long); 3229 DEF_INST(compare_float_long); 3230 DEF_INST(add_float_long); 3231 DEF_INST(subtract_float_long); 3232 DEF_INST(multiply_float_long); 3233 DEF_INST(divide_float_long); 3234 DEF_INST(add_unnormal_float_long); 3235 DEF_INST(subtract_unnormal_float_long); 3236 DEF_INST(store_float_short); 3237 DEF_INST(load_float_short); 3238 DEF_INST(compare_float_short); 3239 DEF_INST(add_float_short); 3240 DEF_INST(subtract_float_short); 3241 DEF_INST(multiply_float_short_to_long); 3242 DEF_INST(divide_float_short); 3243 DEF_INST(add_unnormal_float_short); 3244 DEF_INST(subtract_unnormal_float_short); 3245 DEF_INST(divide_float_ext_reg); 3246 DEF_INST(squareroot_float_long_reg); 3247 DEF_INST(squareroot_float_short_reg); 3248 DEF_INST(load_lengthened_float_short_to_long_reg); 3249 DEF_INST(load_lengthened_float_long_to_ext_reg); 3250 DEF_INST(load_lengthened_float_short_to_ext_reg); 3251 DEF_INST(squareroot_float_ext_reg); 3252 DEF_INST(multiply_float_short_reg); 3253 DEF_INST(load_positive_float_ext_reg); 3254 DEF_INST(load_negative_float_ext_reg); 3255 DEF_INST(load_and_test_float_ext_reg); 3256 DEF_INST(load_complement_float_ext_reg); 3257 DEF_INST(load_rounded_float_ext_to_short_reg); 3258 DEF_INST(load_fp_int_float_ext_reg); 3259 DEF_INST(compare_float_ext_reg); 3260 DEF_INST(load_fp_int_float_short_reg); 3261 DEF_INST(load_fp_int_float_long_reg); 3262 DEF_INST(convert_fixed_to_float_short_reg); 3263 DEF_INST(convert_fixed_to_float_long_reg); 3264 DEF_INST(convert_fixed_to_float_ext_reg); 3265 DEF_INST(convert_fix64_to_float_short_reg); 3266 DEF_INST(convert_fix64_to_float_long_reg); 3267 DEF_INST(convert_fix64_to_float_ext_reg); 3268 DEF_INST(convert_float_short_to_fixed_reg); 3269 DEF_INST(convert_float_long_to_fixed_reg); 3270 DEF_INST(convert_float_ext_to_fixed_reg); 3271 DEF_INST(convert_float_short_to_fix64_reg); /* under construction! Bernard van der Helm */ 3272 DEF_INST(convert_float_long_to_fix64_reg); /* under construction! Bernard van der Helm */ 3273 DEF_INST(convert_float_ext_to_fix64_reg); /* under construction! Bernard van der Helm */ 3274 DEF_INST(load_lengthened_float_short_to_long); 3275 DEF_INST(load_lengthened_float_long_to_ext); 3276 DEF_INST(load_lengthened_float_short_to_ext); 3277 DEF_INST(squareroot_float_short); 3278 DEF_INST(squareroot_float_long); 3279 DEF_INST(multiply_float_short); 3280 DEF_INST(load_float_ext_reg); 3281 DEF_INST(load_zero_float_short_reg); 3282 DEF_INST(load_zero_float_long_reg); 3283 DEF_INST(load_zero_float_ext_reg); 3284 DEF_INST(multiply_add_float_short_reg); 3285 DEF_INST(multiply_add_float_long_reg); 3286 DEF_INST(multiply_add_float_short); 3287 DEF_INST(multiply_add_float_long); 3288 DEF_INST(multiply_subtract_float_short_reg); 3289 DEF_INST(multiply_subtract_float_long_reg); 3290 DEF_INST(multiply_subtract_float_short); 3291 DEF_INST(multiply_subtract_float_long); 3292 DEF_INST(multiply_unnormal_float_long_to_ext_reg); /*@Z9*/ 3293 DEF_INST(multiply_unnormal_float_long_to_ext_low_reg); /*@Z9*/ 3294 DEF_INST(multiply_unnormal_float_long_to_ext_high_reg); /*@Z9*/ 3295 DEF_INST(multiply_add_unnormal_float_long_to_ext_reg); /*@Z9*/ 3296 DEF_INST(multiply_add_unnormal_float_long_to_ext_low_reg); /*@Z9*/ 3297 DEF_INST(multiply_add_unnormal_float_long_to_ext_high_reg); /*@Z9*/ 3298 DEF_INST(multiply_unnormal_float_long_to_ext); /*@Z9*/ 3299 DEF_INST(multiply_unnormal_float_long_to_ext_low); /*@Z9*/ 3300 DEF_INST(multiply_unnormal_float_long_to_ext_high); /*@Z9*/ 3301 DEF_INST(multiply_add_unnormal_float_long_to_ext); /*@Z9*/ 3302 DEF_INST(multiply_add_unnormal_float_long_to_ext_low); /*@Z9*/ 3303 DEF_INST(multiply_add_unnormal_float_long_to_ext_high); /*@Z9*/ 3304 DEF_INST(load_float_long_y); 3305 DEF_INST(load_float_short_y); 3306 DEF_INST(store_float_long_y); 3307 DEF_INST(store_float_short_y); 3308 3309 3310 /* Instructions in general1.c */ 3311 DEF_INST(add_register); 3312 DEF_INST(add); 3313 DEF_INST(add_halfword); 3314 DEF_INST(add_halfword_immediate); 3315 DEF_INST(add_logical_register); 3316 DEF_INST(add_logical); 3317 DEF_INST(and_register); 3318 DEF_INST(and); 3319 DEF_INST(and_immediate); 3320 DEF_INST(and_character); 3321 DEF_INST(branch_and_link_register); 3322 DEF_INST(branch_and_link); 3323 DEF_INST(branch_and_save_register); 3324 DEF_INST(branch_and_save); 3325 DEF_INST(branch_and_save_and_set_mode); 3326 DEF_INST(branch_and_set_mode); 3327 DEF_INST(branch_on_condition_register); 3328 DEF_INST(branch_on_condition); 3329 DEF_INST(branch_on_count_register); 3330 DEF_INST(branch_on_count); 3331 DEF_INST(branch_on_index_high); 3332 DEF_INST(branch_on_index_low_or_equal); 3333 DEF_INST(branch_relative_on_condition); 3334 DEF_INST(branch_relative_and_save); 3335 DEF_INST(branch_relative_on_count); 3336 DEF_INST(branch_relative_on_index_high); 3337 DEF_INST(branch_relative_on_index_low_or_equal); 3338 DEF_INST(checksum); 3339 DEF_INST(compare_register); 3340 DEF_INST(compare); 3341 DEF_INST(compare_and_form_codeword); 3342 DEF_INST(compare_and_swap); 3343 DEF_INST(compare_double_and_swap); 3344 DEF_INST(compare_and_swap_and_store); 3345 DEF_INST(compare_halfword); 3346 DEF_INST(compare_halfword_immediate); 3347 DEF_INST(compare_logical_register); 3348 DEF_INST(compare_logical); 3349 DEF_INST(compare_logical_immediate); 3350 DEF_INST(compare_logical_character); 3351 DEF_INST(compare_logical_characters_under_mask); 3352 DEF_INST(compare_logical_character_long); 3353 DEF_INST(compare_logical_long_extended); 3354 DEF_INST(compare_logical_string); 3355 DEF_INST(compare_until_substring_equal); 3356 DEF_INST(convert_utf16_to_utf8); 3357 DEF_INST(convert_utf16_to_utf32); 3358 DEF_INST(convert_utf32_to_utf16); 3359 DEF_INST(convert_utf32_to_utf8); 3360 DEF_INST(convert_utf8_to_utf16); 3361 DEF_INST(convert_utf8_to_utf32); 3362 DEF_INST(convert_to_binary); 3363 DEF_INST(convert_to_decimal); 3364 DEF_INST(copy_access); 3365 DEF_INST(divide_register); 3366 DEF_INST(divide); 3367 DEF_INST(exclusive_or_register); 3368 DEF_INST(exclusive_or); 3369 DEF_INST(exclusive_or_immediate); 3370 DEF_INST(exclusive_or_character); 3371 DEF_INST(execute); 3372 DEF_INST(execute_relative_long); /*208*/ 3373 DEF_INST(extract_access_register); 3374 DEF_INST(insert_character); 3375 DEF_INST(insert_characters_under_mask); 3376 DEF_INST(insert_program_mask); 3377 DEF_INST(load); 3378 DEF_INST(load_register); 3379 DEF_INST(load_access_multiple); 3380 DEF_INST(load_address); 3381 DEF_INST(load_address_extended); 3382 DEF_INST(load_and_test_register); 3383 DEF_INST(load_complement_register); 3384 DEF_INST(load_halfword); 3385 DEF_INST(load_halfword_immediate); 3386 DEF_INST(load_multiple); 3387 DEF_INST(load_negative_register); 3388 DEF_INST(load_positive_register); 3389 DEF_INST(monitor_call); 3390 DEF_INST(move_immediate); 3391 DEF_INST(move_character); 3392 DEF_INST(move_inverse); 3393 DEF_INST(move_long); 3394 DEF_INST(move_long_extended); 3395 DEF_INST(move_numerics); 3396 DEF_INST(move_string); 3397 DEF_INST(move_with_offset); 3398 DEF_INST(move_zones); 3399 DEF_INST(multiply_register); 3400 DEF_INST(multiply); 3401 DEF_INST(multiply_halfword); 3402 DEF_INST(multiply_halfword_immediate); 3403 DEF_INST(multiply_single_register); 3404 DEF_INST(multiply_single); 3405 3406 3407 /* Instructions in general2.c */ 3408 DEF_INST(or_register); 3409 DEF_INST(or); 3410 DEF_INST(or_immediate); 3411 DEF_INST(or_character); 3412 DEF_INST(perform_locked_operation); 3413 DEF_INST(pack); 3414 DEF_INST(search_string); 3415 DEF_INST(search_string_unicode); 3416 DEF_INST(set_access_register); 3417 DEF_INST(set_program_mask); 3418 DEF_INST(shift_left_double); 3419 DEF_INST(shift_left_double_logical); 3420 DEF_INST(shift_left_single); 3421 DEF_INST(shift_left_single_logical); 3422 DEF_INST(shift_right_double); 3423 DEF_INST(shift_right_double_logical); 3424 DEF_INST(shift_right_single); 3425 DEF_INST(shift_right_single_logical); 3426 DEF_INST(store); 3427 DEF_INST(store_access_multiple); 3428 DEF_INST(store_character); 3429 DEF_INST(store_characters_under_mask); 3430 DEF_INST(store_clock); 3431 DEF_INST(store_clock_extended); 3432 DEF_INST(store_clock_fast); /*@Z9*/ 3433 DEF_INST(store_halfword); 3434 DEF_INST(store_multiple); 3435 DEF_INST(subtract_register); 3436 DEF_INST(subtract); 3437 DEF_INST(subtract_halfword); 3438 DEF_INST(subtract_logical_register); 3439 DEF_INST(subtract_logical); 3440 DEF_INST(supervisor_call); 3441 DEF_INST(test_and_set); 3442 DEF_INST(test_under_mask); 3443 DEF_INST(test_under_mask_high); 3444 DEF_INST(test_under_mask_low); 3445 DEF_INST(translate); 3446 DEF_INST(translate_and_test); 3447 DEF_INST(translate_and_test_reverse); 3448 DEF_INST(translate_and_test_extended); /*208*/ 3449 DEF_INST(translate_and_test_reverse_extended); /*208*/ 3450 DEF_INST(translate_extended); 3451 DEF_INST(unpack); 3452 DEF_INST(update_tree); 3453 3454 3455 /* Instructions in general3.c */ 3456 DEF_INST(add_immediate_long_storage); /*208*/ 3457 DEF_INST(add_immediate_storage); /*208*/ 3458 DEF_INST(add_logical_with_signed_immediate); /*208*/ 3459 DEF_INST(add_logical_with_signed_immediate_long); /*208*/ 3460 DEF_INST(compare_and_branch_register); /*208*/ 3461 DEF_INST(compare_and_branch_long_register); /*208*/ 3462 DEF_INST(compare_and_branch_relative_register); /*208*/ 3463 DEF_INST(compare_and_branch_relative_long_register); /*208*/ 3464 DEF_INST(compare_and_trap_long_register); /*208*/ 3465 DEF_INST(compare_and_trap_register); /*208*/ 3466 DEF_INST(compare_halfword_immediate_halfword_storage); /*208*/ 3467 DEF_INST(compare_halfword_immediate_long_storage); /*208*/ 3468 DEF_INST(compare_halfword_immediate_storage); /*208*/ 3469 DEF_INST(compare_halfword_long); /*208*/ 3470 DEF_INST(compare_halfword_relative_long); /*208*/ 3471 DEF_INST(compare_halfword_relative_long_long); /*208*/ 3472 DEF_INST(compare_immediate_and_branch); /*208*/ 3473 DEF_INST(compare_immediate_and_branch_long); /*208*/ 3474 DEF_INST(compare_immediate_and_branch_relative); /*208*/ 3475 DEF_INST(compare_immediate_and_branch_relative_long); /*208*/ 3476 DEF_INST(compare_immediate_and_trap); /*208*/ 3477 DEF_INST(compare_immediate_and_trap_long); /*208*/ 3478 DEF_INST(compare_logical_and_branch_long_register); /*208*/ 3479 DEF_INST(compare_logical_and_branch_register); /*208*/ 3480 DEF_INST(compare_logical_and_branch_relative_long_register); /*208*/ 3481 DEF_INST(compare_logical_and_branch_relative_register); /*208*/ 3482 DEF_INST(compare_logical_and_trap_long_register); /*208*/ 3483 DEF_INST(compare_logical_and_trap_register); /*208*/ 3484 DEF_INST(compare_logical_immediate_and_branch); /*208*/ 3485 DEF_INST(compare_logical_immediate_and_branch_long); /*208*/ 3486 DEF_INST(compare_logical_immediate_and_branch_relative); /*208*/ 3487 DEF_INST(compare_logical_immediate_and_branch_relative_long); /*208*/ 3488 DEF_INST(compare_logical_immediate_and_trap_fullword); /*208*/ 3489 DEF_INST(compare_logical_immediate_and_trap_long); /*208*/ 3490 DEF_INST(compare_logical_immediate_fullword_storage); /*208*/ 3491 DEF_INST(compare_logical_immediate_halfword_storage); /*208*/ 3492 DEF_INST(compare_logical_immediate_long_storage); /*208*/ 3493 DEF_INST(compare_logical_relative_long); /*208*/ 3494 DEF_INST(compare_logical_relative_long_halfword); /*208*/ 3495 DEF_INST(compare_logical_relative_long_long); /*208*/ 3496 DEF_INST(compare_logical_relative_long_long_fullword); /*208*/ 3497 DEF_INST(compare_logical_relative_long_long_halfword); /*208*/ 3498 DEF_INST(compare_relative_long); /*208*/ 3499 DEF_INST(compare_relative_long_long); /*208*/ 3500 DEF_INST(compare_relative_long_long_fullword); /*208*/ 3501 DEF_INST(extract_cache_attribute); /*208*/ 3502 DEF_INST(load_address_extended_y); /*208*/ 3503 DEF_INST(load_and_test_long_fullword); /*208*/ 3504 DEF_INST(load_halfword_relative_long); /*208*/ 3505 DEF_INST(load_halfword_relative_long_long); /*208*/ 3506 DEF_INST(load_logical_halfword_relative_long); /*208*/ 3507 DEF_INST(load_logical_halfword_relative_long_long); /*208*/ 3508 DEF_INST(load_logical_relative_long_long_fullword); /*208*/ 3509 DEF_INST(load_relative_long); /*208*/ 3510 DEF_INST(load_relative_long_long); /*208*/ 3511 DEF_INST(load_relative_long_long_fullword); /*208*/ 3512 DEF_INST(move_fullword_from_halfword_immediate); /*208*/ 3513 DEF_INST(move_halfword_from_halfword_immediate); /*208*/ 3514 DEF_INST(move_long_from_halfword_immediate); /*208*/ 3515 DEF_INST(multiply_halfword_y); /*208*/ 3516 DEF_INST(multiply_single_immediate_fullword); /*208*/ 3517 DEF_INST(multiply_single_immediate_long_fullword); /*208*/ 3518 DEF_INST(multiply_y); /*208*/ 3519 DEF_INST(prefetch_data); /*208*/ 3520 DEF_INST(prefetch_data_relative_long); /*208*/ 3521 DEF_INST(rotate_then_and_selected_bits_long_reg); /*208*/ 3522 DEF_INST(rotate_then_exclusive_or_selected_bits_long_reg); /*208*/ 3523 DEF_INST(rotate_then_insert_selected_bits_long_reg); /*208*/ 3524 DEF_INST(rotate_then_or_selected_bits_long_reg); /*208*/ 3525 DEF_INST(store_halfword_relative_long); /*208*/ 3526 DEF_INST(store_relative_long); /*208*/ 3527 DEF_INST(store_relative_long_long); /*208*/ 3528 3529 DEF_INST(add_high_high_high_register); /*810*/ 3530 DEF_INST(add_high_high_low_register); /*810*/ 3531 DEF_INST(add_high_immediate); /*810*/ 3532 DEF_INST(add_logical_high_high_high_register); /*810*/ 3533 DEF_INST(add_logical_high_high_low_register); /*810*/ 3534 DEF_INST(add_logical_with_signed_immediate_high); /*810*/ 3535 DEF_INST(add_logical_with_signed_immediate_high_n); /*810*/ 3536 DEF_INST(branch_relative_on_count_high); /*810*/ 3537 DEF_INST(compare_high_high_register); /*810*/ 3538 DEF_INST(compare_high_low_register); /*810*/ 3539 DEF_INST(compare_high_fullword); /*810*/ 3540 DEF_INST(compare_high_immediate); /*810*/ 3541 DEF_INST(compare_logical_high_high_register); /*810*/ 3542 DEF_INST(compare_logical_high_low_register); /*810*/ 3543 DEF_INST(compare_logical_high_fullword); /*810*/ 3544 DEF_INST(compare_logical_high_immediate); /*810*/ 3545 DEF_INST(load_byte_high); /*810*/ 3546 DEF_INST(load_fullword_high); /*810*/ 3547 DEF_INST(load_halfword_high); /*810*/ 3548 DEF_INST(load_logical_character_high); /*810*/ 3549 DEF_INST(load_logical_halfword_high); /*810*/ 3550 DEF_INST(rotate_then_insert_selected_bits_high_long_reg); /*810*/ 3551 DEF_INST(rotate_then_insert_selected_bits_low_long_reg); /*810*/ 3552 DEF_INST(store_character_high); /*810*/ 3553 DEF_INST(store_fullword_high); /*810*/ 3554 DEF_INST(store_halfword_high); /*810*/ 3555 DEF_INST(subtract_high_high_high_register); /*810*/ 3556 DEF_INST(subtract_high_high_low_register); /*810*/ 3557 DEF_INST(subtract_logical_high_high_high_register); /*810*/ 3558 DEF_INST(subtract_logical_high_high_low_register); /*810*/ 3559 3560 DEF_INST(load_and_add); /*810*/ 3561 DEF_INST(load_and_add_long); /*810*/ 3562 DEF_INST(load_and_add_logical); /*810*/ 3563 DEF_INST(load_and_add_logical_long); /*810*/ 3564 DEF_INST(load_and_and); /*810*/ 3565 DEF_INST(load_and_and_long); /*810*/ 3566 DEF_INST(load_and_exclusive_or); /*810*/ 3567 DEF_INST(load_and_exclusive_or_long); /*810*/ 3568 DEF_INST(load_and_or); /*810*/ 3569 DEF_INST(load_and_or_long); /*810*/ 3570 DEF_INST(load_pair_disjoint); /*810*/ 3571 DEF_INST(load_pair_disjoint_long); /*810*/ 3572 3573 DEF_INST(load_on_condition_register); /*810*/ 3574 DEF_INST(load_on_condition_long_register); /*810*/ 3575 DEF_INST(load_on_condition); /*810*/ 3576 DEF_INST(load_on_condition_long); /*810*/ 3577 DEF_INST(store_on_condition); /*810*/ 3578 DEF_INST(store_on_condition_long); /*810*/ 3579 3580 DEF_INST(add_distinct_register); /*810*/ 3581 DEF_INST(add_distinct_long_register); /*810*/ 3582 DEF_INST(add_distinct_halfword_immediate); /*810*/ 3583 DEF_INST(add_distinct_long_halfword_immediate); /*810*/ 3584 DEF_INST(add_logical_distinct_register); /*810*/ 3585 DEF_INST(add_logical_distinct_long_register); /*810*/ 3586 DEF_INST(add_logical_distinct_signed_halfword_immediate); /*810*/ 3587 DEF_INST(add_logical_distinct_long_signed_halfword_immediate); /*810*/ 3588 DEF_INST(and_distinct_register); /*810*/ 3589 DEF_INST(and_distinct_long_register); /*810*/ 3590 DEF_INST(exclusive_or_distinct_register); /*810*/ 3591 DEF_INST(exclusive_or_distinct_long_register); /*810*/ 3592 DEF_INST(or_distinct_register); /*810*/ 3593 DEF_INST(or_distinct_long_register); /*810*/ 3594 DEF_INST(shift_right_single_distinct); /*810*/ 3595 DEF_INST(shift_left_single_distinct); /*810*/ 3596 DEF_INST(shift_right_single_logical_distinct); /*810*/ 3597 DEF_INST(shift_left_single_logical_distinct); /*810*/ 3598 DEF_INST(subtract_distinct_register); /*810*/ 3599 DEF_INST(subtract_distinct_long_register); /*810*/ 3600 DEF_INST(subtract_logical_distinct_register); /*810*/ 3601 DEF_INST(subtract_logical_distinct_long_register); /*810*/ 3602 3603 DEF_INST(population_count); /*810*/ 3604 3605 DEF_INST(load_and_trap); /*912*/ 3606 DEF_INST(load_long_and_trap); /*912*/ 3607 DEF_INST(load_fullword_high_and_trap); /*912*/ 3608 DEF_INST(load_logical_long_fullword_and_trap); /*912*/ 3609 DEF_INST(load_logical_long_thirtyone_and_trap); /*912*/ 3610 3611 DEF_INST(compare_logical_and_trap); /*912*/ 3612 DEF_INST(compare_logical_and_trap_long); /*912*/ 3613 DEF_INST(rotate_then_insert_selected_bits_long_reg_n); /*912*/ 3614 3615 DEF_INST(branch_prediction_preload); /*912*/ 3616 DEF_INST(branch_prediction_relative_preload); /*912*/ 3617 DEF_INST(next_instruction_access_intent); /*912*/ 3618 3619 3620 /* Instructions in io.c */ 3621 DEF_INST(clear_subchannel); 3622 DEF_INST(halt_subchannel); 3623 DEF_INST(modify_subchannel); 3624 DEF_INST(resume_subchannel); 3625 DEF_INST(set_address_limit); 3626 DEF_INST(set_channel_monitor); 3627 DEF_INST(reset_channel_path); 3628 DEF_INST(start_subchannel); 3629 DEF_INST(cancel_subchannel); 3630 DEF_INST(store_channel_path_status); 3631 DEF_INST(store_channel_report_word); 3632 DEF_INST(store_subchannel); 3633 DEF_INST(test_pending_interruption); 3634 DEF_INST(test_subchannel); 3635 DEF_INST(start_io); 3636 DEF_INST(test_io); 3637 DEF_INST(halt_io); 3638 DEF_INST(test_channel); 3639 DEF_INST(store_channel_id); 3640 DEF_INST(connect_channel_set); 3641 DEF_INST(disconnect_channel_set); 3642 3643 3644 /* Instructions in service.c */ 3645 DEF_INST(service_call); 3646 3647 3648 /* Instructions in chsc.c */ 3649 DEF_INST(channel_subsystem_call); 3650 3651 3652 /* Instructions in xstore.c */ 3653 DEF_INST(page_in); 3654 DEF_INST(page_out); 3655 DEF_INST(move_page); 3656 DEF_INST(invalidate_expanded_storage_block_entry); 3657 3658 3659 /* Instructions in vector.c */ 3660 DEF_INST(v_test_vmr); 3661 DEF_INST(v_complement_vmr); 3662 DEF_INST(v_count_left_zeros_in_vmr); 3663 DEF_INST(v_count_ones_in_vmr); 3664 DEF_INST(v_extract_vct); 3665 DEF_INST(v_extract_vector_modes); 3666 DEF_INST(v_restore_vr); 3667 DEF_INST(v_save_changed_vr); 3668 DEF_INST(v_save_vr); 3669 DEF_INST(v_load_vmr); 3670 DEF_INST(v_load_vmr_complement); 3671 DEF_INST(v_store_vmr); 3672 DEF_INST(v_and_to_vmr); 3673 DEF_INST(v_or_to_vmr); 3674 DEF_INST(v_exclusive_or_to_vmr); 3675 DEF_INST(v_save_vsr); 3676 DEF_INST(v_save_vmr); 3677 DEF_INST(v_restore_vsr); 3678 DEF_INST(v_restore_vmr); 3679 DEF_INST(v_load_vct_from_address); 3680 DEF_INST(v_clear_vr); 3681 DEF_INST(v_set_vector_mask_mode); 3682 DEF_INST(v_load_vix_from_address); 3683 DEF_INST(v_store_vector_parameters); 3684 DEF_INST(v_save_vac); 3685 DEF_INST(v_restore_vac); 3686 3687 3688 /* Instructions in esame.c */ 3689 DEF_INST(store_fpc); 3690 DEF_INST(load_fpc); 3691 DEF_INST(set_fpc); 3692 DEF_INST(extract_fpc); 3693 DEF_INST(set_bfp_rounding_mode_2bit); 3694 DEF_INST(set_bfp_rounding_mode_3bit); /*810*/ 3695 DEF_INST(trap2); 3696 DEF_INST(trap4); 3697 DEF_INST(resume_program); 3698 DEF_INST(trace_long); 3699 DEF_INST(convert_to_binary_long); 3700 DEF_INST(convert_to_decimal_long); 3701 DEF_INST(multiply_logical); 3702 DEF_INST(multiply_logical_long); 3703 DEF_INST(multiply_logical_register); 3704 DEF_INST(multiply_logical_long_register); 3705 DEF_INST(divide_logical); 3706 DEF_INST(divide_logical_long); 3707 DEF_INST(divide_logical_register); 3708 DEF_INST(divide_logical_long_register); 3709 DEF_INST(add_logical_carry_long_register); 3710 DEF_INST(subtract_logical_borrow_long_register); 3711 DEF_INST(add_logical_carry_long); 3712 DEF_INST(subtract_logical_borrow_long); 3713 DEF_INST(add_logical_carry_register); 3714 DEF_INST(subtract_logical_borrow_register); 3715 DEF_INST(add_logical_carry); 3716 DEF_INST(subtract_logical_borrow); 3717 DEF_INST(divide_single_long); 3718 DEF_INST(divide_single_long_fullword); 3719 DEF_INST(divide_single_long_register); 3720 DEF_INST(divide_single_long_fullword_register); 3721 DEF_INST(load_logical_long_character); 3722 DEF_INST(load_logical_long_halfword); 3723 DEF_INST(store_pair_to_quadword); 3724 DEF_INST(load_pair_from_quadword); 3725 DEF_INST(extract_stacked_registers_long); 3726 DEF_INST(extract_psw); 3727 DEF_INST(extract_and_set_extended_authority); 3728 DEF_INST(load_address_relative_long); 3729 DEF_INST(perform_frame_management_function); /*208*/ 3730 DEF_INST(perform_timing_facility_function); /*@Z9*/ 3731 DEF_INST(perform_topology_function); /*208*/ 3732 DEF_INST(reset_reference_bits_multiple); /*810*/ 3733 DEF_INST(store_facility_list); 3734 DEF_INST(store_facility_list_extended); /*@Z9*/ 3735 DEF_INST(load_long_halfword_immediate); 3736 DEF_INST(add_long_halfword_immediate); 3737 DEF_INST(multiply_long_halfword_immediate); 3738 DEF_INST(compare_long_halfword_immediate); 3739 DEF_INST(and_long); 3740 DEF_INST(or_long); 3741 DEF_INST(exclusive_or_long); 3742 DEF_INST(and_long_register); 3743 DEF_INST(or_long_register); 3744 DEF_INST(exclusive_or_long_register); 3745 DEF_INST(load_long_register); 3746 DEF_INST(add_logical_long_register); 3747 DEF_INST(add_logical_long_fullword_register); 3748 DEF_INST(subtract_logical_long_register); 3749 DEF_INST(subtract_logical_long_fullword_register); 3750 DEF_INST(load_control_long); 3751 DEF_INST(store_control_long); 3752 DEF_INST(load_multiple_disjoint); 3753 DEF_INST(load_multiple_high); 3754 DEF_INST(load_multiple_long); 3755 DEF_INST(store_multiple_high); 3756 DEF_INST(store_multiple_long); 3757 DEF_INST(load_using_real_address_long); 3758 DEF_INST(store_using_real_address_long); 3759 DEF_INST(test_addressing_mode); 3760 DEF_INST(set_addressing_mode_24); 3761 DEF_INST(set_addressing_mode_31); 3762 DEF_INST(set_addressing_mode_64); 3763 DEF_INST(load_program_status_word_extended); 3764 DEF_INST(store_long); 3765 DEF_INST(store_real_address); 3766 DEF_INST(load_long); 3767 DEF_INST(multiply_single_long_register); 3768 DEF_INST(multiply_single_long_fullword_register); 3769 DEF_INST(multiply_single_long); 3770 DEF_INST(multiply_single_long_fullword); 3771 DEF_INST(rotate_left_single_logical_long); 3772 DEF_INST(rotate_left_single_logical); 3773 DEF_INST(shift_right_single_long); 3774 DEF_INST(shift_left_single_long); 3775 DEF_INST(shift_right_single_logical_long); 3776 DEF_INST(shift_left_single_logical_long); 3777 DEF_INST(compare_logical_long); 3778 DEF_INST(compare_logical_long_fullword); 3779 DEF_INST(compare_logical_long_fullword_register); 3780 DEF_INST(load_logical_long_thirtyone_register); 3781 DEF_INST(compare_logical_long_register); 3782 DEF_INST(test_under_mask_high_high); 3783 DEF_INST(test_under_mask_high_low); 3784 DEF_INST(branch_relative_on_count_long); 3785 DEF_INST(load_positive_long_register); 3786 DEF_INST(load_negative_long_register); 3787 DEF_INST(load_and_test_long_register); 3788 DEF_INST(load_complement_long_register); 3789 DEF_INST(load_real_address_long); 3790 DEF_INST(load_long_fullword_register); 3791 DEF_INST(add_long_register); 3792 DEF_INST(add_long_fullword_register); 3793 DEF_INST(subtract_long_register); 3794 DEF_INST(subtract_long_fullword_register); 3795 DEF_INST(add_logical_long); 3796 DEF_INST(add_logical_long_fullword); 3797 DEF_INST(add_long); 3798 DEF_INST(add_long_fullword); 3799 DEF_INST(subtract_logical_long); 3800 DEF_INST(subtract_logical_long_fullword); 3801 DEF_INST(subtract_long); 3802 DEF_INST(subtract_long_fullword); 3803 DEF_INST(compare_long_register); 3804 DEF_INST(compare_long); 3805 DEF_INST(branch_on_count_long_register); 3806 DEF_INST(branch_on_count_long); 3807 DEF_INST(compare_and_swap_long); 3808 DEF_INST(compare_double_and_swap_long); 3809 DEF_INST(branch_on_index_high_long); 3810 DEF_INST(branch_on_index_low_or_equal_long); 3811 DEF_INST(branch_relative_on_index_high_long); 3812 DEF_INST(branch_relative_on_index_low_or_equal_long); 3813 DEF_INST(compare_logical_characters_under_mask_high); 3814 DEF_INST(store_characters_under_mask_high); 3815 DEF_INST(insert_characters_under_mask_high); 3816 DEF_INST(branch_relative_on_condition_long); 3817 DEF_INST(branch_relative_and_save_long); 3818 DEF_INST(compare_long_fullword_register); 3819 DEF_INST(load_positive_long_fullword_register); 3820 DEF_INST(load_negative_long_fullword_register); 3821 DEF_INST(load_and_test_long_fullword_register); 3822 DEF_INST(load_complement_long_fullword_register); 3823 DEF_INST(load_long_fullword); 3824 DEF_INST(load_long_halfword); 3825 DEF_INST(compare_long_fullword); 3826 DEF_INST(load_logical_long_fullword_register); 3827 DEF_INST(load_logical_long_fullword); 3828 DEF_INST(load_logical_long_thirtyone); 3829 DEF_INST(insert_immediate_high_high); 3830 DEF_INST(insert_immediate_high_low); 3831 DEF_INST(insert_immediate_low_high); 3832 DEF_INST(insert_immediate_low_low); 3833 DEF_INST(and_immediate_high_high); 3834 DEF_INST(and_immediate_high_low); 3835 DEF_INST(and_immediate_low_high); 3836 DEF_INST(and_immediate_low_low); 3837 DEF_INST(or_immediate_high_high); 3838 DEF_INST(or_immediate_high_low); 3839 DEF_INST(or_immediate_low_high); 3840 DEF_INST(or_immediate_low_low); 3841 DEF_INST(load_logical_immediate_high_high); 3842 DEF_INST(load_logical_immediate_high_low); 3843 DEF_INST(load_logical_immediate_low_high); 3844 DEF_INST(load_logical_immediate_low_low); 3845 DEF_INST(load_reversed_long_register); 3846 DEF_INST(load_reversed_register); 3847 DEF_INST(load_reversed_long); 3848 DEF_INST(load_reversed); 3849 DEF_INST(load_reversed_half); 3850 DEF_INST(store_reversed_long); 3851 DEF_INST(store_reversed); 3852 DEF_INST(store_reversed_half); 3853 DEF_INST(pack_ascii); 3854 DEF_INST(pack_unicode); 3855 DEF_INST(unpack_ascii); 3856 DEF_INST(unpack_unicode); 3857 DEF_INST(translate_two_to_two); 3858 DEF_INST(translate_two_to_one); 3859 DEF_INST(translate_one_to_two); 3860 DEF_INST(translate_one_to_one); 3861 DEF_INST(move_long_unicode); 3862 DEF_INST(compare_logical_long_unicode); 3863 DEF_INST(add_y); 3864 DEF_INST(add_halfword_y); 3865 DEF_INST(add_logical_y); 3866 DEF_INST(and_immediate_y); 3867 DEF_INST(and_y); 3868 DEF_INST(compare_y); 3869 DEF_INST(compare_and_swap_y); 3870 DEF_INST(compare_double_and_swap_y); 3871 DEF_INST(compare_halfword_y); 3872 DEF_INST(compare_logical_y); 3873 DEF_INST(compare_logical_immediate_y); 3874 DEF_INST(compare_logical_characters_under_mask_y); 3875 DEF_INST(convert_to_binary_y); 3876 DEF_INST(convert_to_decimal_y); 3877 DEF_INST(exclusive_or_immediate_y); 3878 DEF_INST(exclusive_or_y); 3879 DEF_INST(insert_character_y); 3880 DEF_INST(insert_characters_under_mask_y); 3881 DEF_INST(load_y); 3882 DEF_INST(load_access_multiple_y); 3883 DEF_INST(load_address_y); 3884 DEF_INST(load_byte); 3885 DEF_INST(load_byte_long); 3886 DEF_INST(load_halfword_y); 3887 DEF_INST(load_multiple_y); 3888 DEF_INST(load_real_address_y); 3889 DEF_INST(move_immediate_y); 3890 DEF_INST(multiply_single_y); 3891 DEF_INST(or_immediate_y); 3892 DEF_INST(or_y); 3893 DEF_INST(store_y); 3894 DEF_INST(store_access_multiple_y); 3895 DEF_INST(store_character_y); 3896 DEF_INST(store_characters_under_mask_y); 3897 DEF_INST(store_halfword_y); 3898 DEF_INST(store_multiple_y); 3899 DEF_INST(subtract_y); 3900 DEF_INST(subtract_halfword_y); 3901 DEF_INST(subtract_logical_y); 3902 DEF_INST(test_under_mask_y); 3903 DEF_INST(compare_and_swap_and_purge_long); 3904 DEF_INST(invalidate_dat_table_entry); 3905 DEF_INST(compare_and_replace_dat_table_entry); /*912*/ 3906 DEF_INST(load_page_table_entry_address); /*@Z9*/ 3907 DEF_INST(add_fullword_immediate); /*@Z9*/ 3908 DEF_INST(add_long_fullword_immediate); /*@Z9*/ 3909 DEF_INST(add_logical_fullword_immediate); /*@Z9*/ 3910 DEF_INST(add_logical_long_fullword_immediate); /*@Z9*/ 3911 DEF_INST(and_immediate_high_fullword); /*@Z9*/ 3912 DEF_INST(and_immediate_low_fullword); /*@Z9*/ 3913 DEF_INST(compare_fullword_immediate); /*@Z9*/ 3914 DEF_INST(compare_long_fullword_immediate); /*@Z9*/ 3915 DEF_INST(compare_logical_fullword_immediate); /*@Z9*/ 3916 DEF_INST(compare_logical_long_fullword_immediate); /*@Z9*/ 3917 DEF_INST(exclusive_or_immediate_high_fullword); /*@Z9*/ 3918 DEF_INST(exclusive_or_immediate_low_fullword); /*@Z9*/ 3919 DEF_INST(insert_immediate_high_fullword); /*@Z9*/ 3920 DEF_INST(insert_immediate_low_fullword); /*@Z9*/ 3921 DEF_INST(load_long_fullword_immediate); /*@Z9*/ 3922 DEF_INST(load_logical_immediate_high_fullword); /*@Z9*/ 3923 DEF_INST(load_logical_immediate_low_fullword); /*@Z9*/ 3924 DEF_INST(or_immediate_high_fullword); /*@Z9*/ 3925 DEF_INST(or_immediate_low_fullword); /*@Z9*/ 3926 DEF_INST(subtract_logical_fullword_immediate); /*@Z9*/ 3927 DEF_INST(subtract_logical_long_fullword_immediate); /*@Z9*/ 3928 DEF_INST(load_and_test); /*@Z9*/ 3929 DEF_INST(load_and_test_long); /*@Z9*/ 3930 DEF_INST(load_byte_register); /*@Z9*/ 3931 DEF_INST(load_long_byte_register); /*@Z9*/ 3932 DEF_INST(load_halfword_register); /*@Z9*/ 3933 DEF_INST(load_long_halfword_register); /*@Z9*/ 3934 DEF_INST(load_logical_character); /*@Z9*/ 3935 DEF_INST(load_logical_character_register); /*@Z9*/ 3936 DEF_INST(load_logical_long_character_register); /*@Z9*/ 3937 DEF_INST(load_logical_halfword); /*@Z9*/ 3938 DEF_INST(load_logical_halfword_register); /*@Z9*/ 3939 DEF_INST(load_logical_long_halfword_register); /*@Z9*/ 3940 DEF_INST(find_leftmost_one_long_register); /*@Z9*/ 3941 DEF_INST(extract_cpu_time); 3942 DEF_INST(load_program_parameter); /*810*/ 3943 3944 3945 /* Instructions in ecpsvm.c */ 3946 DEF_INST(ecpsvm_basic_freex); 3947 DEF_INST(ecpsvm_basic_fretx); 3948 DEF_INST(ecpsvm_lock_page); 3949 DEF_INST(ecpsvm_unlock_page); 3950 DEF_INST(ecpsvm_decode_next_ccw); 3951 DEF_INST(ecpsvm_free_ccwstor); 3952 DEF_INST(ecpsvm_locate_vblock); 3953 DEF_INST(ecpsvm_disp1); 3954 DEF_INST(ecpsvm_tpage); 3955 DEF_INST(ecpsvm_tpage_lock); 3956 DEF_INST(ecpsvm_inval_segtab); 3957 DEF_INST(ecpsvm_inval_ptable); 3958 DEF_INST(ecpsvm_decode_first_ccw); 3959 DEF_INST(ecpsvm_dispatch_main); 3960 DEF_INST(ecpsvm_locate_rblock); 3961 DEF_INST(ecpsvm_comm_ccwproc); 3962 DEF_INST(ecpsvm_unxlate_ccw); 3963 DEF_INST(ecpsvm_disp2); 3964 DEF_INST(ecpsvm_store_level); 3965 DEF_INST(ecpsvm_loc_chgshrpg); 3966 DEF_INST(ecpsvm_extended_freex); 3967 DEF_INST(ecpsvm_extended_fretx); 3968 DEF_INST(ecpsvm_prefmach_assist); 3969 3970 3971 /* Instructions in ieee.c */ 3972 DEF_INST(convert_bfp_long_to_float_long_reg); 3973 DEF_INST(convert_bfp_short_to_float_long_reg); 3974 DEF_INST(convert_float_long_to_bfp_long_reg); 3975 DEF_INST(convert_float_long_to_bfp_short_reg); 3976 DEF_INST(add_bfp_ext_reg); 3977 DEF_INST(add_bfp_long_reg); 3978 DEF_INST(add_bfp_long); 3979 DEF_INST(add_bfp_short_reg); 3980 DEF_INST(add_bfp_short); 3981 DEF_INST(compare_bfp_ext_reg); 3982 DEF_INST(compare_bfp_long_reg); 3983 DEF_INST(compare_bfp_long); 3984 DEF_INST(compare_bfp_short_reg); 3985 DEF_INST(compare_bfp_short); 3986 DEF_INST(compare_and_signal_bfp_ext_reg); 3987 DEF_INST(compare_and_signal_bfp_long_reg); 3988 DEF_INST(compare_and_signal_bfp_long); 3989 DEF_INST(compare_and_signal_bfp_short_reg); 3990 DEF_INST(compare_and_signal_bfp_short); 3991 DEF_INST(convert_fix32_to_bfp_ext_reg); 3992 DEF_INST(convert_fix32_to_bfp_long_reg); 3993 DEF_INST(convert_fix32_to_bfp_short_reg); 3994 DEF_INST(convert_u32_to_bfp_ext_reg); /*810*/ 3995 DEF_INST(convert_u32_to_bfp_long_reg); /*810*/ 3996 DEF_INST(convert_u32_to_bfp_short_reg); /*810*/ 3997 DEF_INST(convert_fix64_to_bfp_ext_reg); 3998 DEF_INST(convert_fix64_to_bfp_long_reg); 3999 DEF_INST(convert_fix64_to_bfp_short_reg); 4000 DEF_INST(convert_u64_to_bfp_ext_reg); /*810*/ 4001 DEF_INST(convert_u64_to_bfp_long_reg); /*810*/ 4002 DEF_INST(convert_u64_to_bfp_short_reg); /*810*/ 4003 DEF_INST(convert_bfp_ext_to_fix32_reg); 4004 DEF_INST(convert_bfp_long_to_fix32_reg); 4005 DEF_INST(convert_bfp_short_to_fix32_reg); 4006 DEF_INST(convert_bfp_ext_to_u32_reg); /*810*/ 4007 DEF_INST(convert_bfp_long_to_u32_reg); /*810*/ 4008 DEF_INST(convert_bfp_short_to_u32_reg); /*810*/ 4009 DEF_INST(convert_bfp_ext_to_fix64_reg); 4010 DEF_INST(convert_bfp_long_to_fix64_reg); 4011 DEF_INST(convert_bfp_short_to_fix64_reg); 4012 DEF_INST(convert_bfp_ext_to_u64_reg); /*810*/ 4013 DEF_INST(convert_bfp_long_to_u64_reg); /*810*/ 4014 DEF_INST(convert_bfp_short_to_u64_reg); /*810*/ 4015 DEF_INST(divide_bfp_ext_reg); 4016 DEF_INST(divide_bfp_long_reg); 4017 DEF_INST(divide_bfp_long); 4018 DEF_INST(divide_bfp_short_reg); 4019 DEF_INST(divide_bfp_short); 4020 DEF_INST(divide_integer_bfp_long_reg); 4021 DEF_INST(divide_integer_bfp_short_reg); 4022 DEF_INST(load_and_test_bfp_ext_reg); 4023 DEF_INST(load_and_test_bfp_long_reg); 4024 DEF_INST(load_and_test_bfp_short_reg); 4025 DEF_INST(load_fp_int_bfp_ext_reg); 4026 DEF_INST(load_fp_int_bfp_long_reg); 4027 DEF_INST(load_fp_int_bfp_short_reg); 4028 DEF_INST(load_lengthened_bfp_short_to_long_reg); 4029 DEF_INST(load_lengthened_bfp_short_to_long); 4030 DEF_INST(load_lengthened_bfp_long_to_ext_reg); 4031 DEF_INST(load_lengthened_bfp_long_to_ext); 4032 DEF_INST(load_lengthened_bfp_short_to_ext_reg); 4033 DEF_INST(load_lengthened_bfp_short_to_ext); 4034 DEF_INST(load_negative_bfp_ext_reg); 4035 DEF_INST(load_negative_bfp_long_reg); 4036 DEF_INST(load_negative_bfp_short_reg); 4037 DEF_INST(load_complement_bfp_ext_reg); 4038 DEF_INST(load_complement_bfp_long_reg); 4039 DEF_INST(load_complement_bfp_short_reg); 4040 DEF_INST(load_positive_bfp_ext_reg); 4041 DEF_INST(load_positive_bfp_long_reg); 4042 DEF_INST(load_positive_bfp_short_reg); 4043 DEF_INST(load_rounded_bfp_long_to_short_reg); 4044 DEF_INST(load_rounded_bfp_ext_to_long_reg); 4045 DEF_INST(load_rounded_bfp_ext_to_short_reg); 4046 DEF_INST(multiply_bfp_ext_reg); 4047 DEF_INST(multiply_bfp_long_to_ext_reg); 4048 DEF_INST(multiply_bfp_long_to_ext); 4049 DEF_INST(multiply_bfp_long_reg); 4050 DEF_INST(multiply_bfp_long); 4051 DEF_INST(multiply_bfp_short_to_long_reg); 4052 DEF_INST(multiply_bfp_short_to_long); 4053 DEF_INST(multiply_bfp_short_reg); 4054 DEF_INST(multiply_bfp_short); 4055 DEF_INST(multiply_add_bfp_long_reg); 4056 DEF_INST(multiply_add_bfp_long); 4057 DEF_INST(multiply_add_bfp_short_reg); 4058 DEF_INST(multiply_add_bfp_short); 4059 DEF_INST(multiply_subtract_bfp_long_reg); 4060 DEF_INST(multiply_subtract_bfp_long); 4061 DEF_INST(multiply_subtract_bfp_short_reg); 4062 DEF_INST(multiply_subtract_bfp_short); 4063 DEF_INST(squareroot_bfp_ext_reg); 4064 DEF_INST(squareroot_bfp_long_reg); 4065 DEF_INST(squareroot_bfp_long); 4066 DEF_INST(squareroot_bfp_short_reg); 4067 DEF_INST(squareroot_bfp_short); 4068 DEF_INST(subtract_bfp_ext_reg); 4069 DEF_INST(subtract_bfp_long_reg); 4070 DEF_INST(subtract_bfp_long); 4071 DEF_INST(subtract_bfp_short_reg); 4072 DEF_INST(subtract_bfp_short); 4073 DEF_INST(test_data_class_bfp_short); 4074 DEF_INST(test_data_class_bfp_long); 4075 DEF_INST(test_data_class_bfp_ext); 4076 4077 /* Instructions in dfp.c */ 4078 DEF_INST(copy_sign_fpr_long_reg); 4079 DEF_INST(load_complement_fpr_long_reg); 4080 DEF_INST(load_fpr_from_gr_long_reg); 4081 DEF_INST(load_gr_from_fpr_long_reg); 4082 DEF_INST(load_negative_fpr_long_reg); 4083 DEF_INST(load_positive_fpr_long_reg); 4084 DEF_INST(set_dfp_rounding_mode); 4085 DEF_INST(load_fpc_and_signal); 4086 DEF_INST(set_fpc_and_signal); 4087 DEF_INST(add_dfp_ext_reg); 4088 DEF_INST(add_dfp_long_reg); 4089 DEF_INST(compare_dfp_ext_reg); 4090 DEF_INST(compare_dfp_long_reg); 4091 DEF_INST(compare_and_signal_dfp_ext_reg); 4092 DEF_INST(compare_and_signal_dfp_long_reg); 4093 DEF_INST(compare_exponent_dfp_ext_reg); 4094 DEF_INST(compare_exponent_dfp_long_reg); 4095 DEF_INST(convert_fix32_to_dfp_ext_reg); /*810*/ 4096 DEF_INST(convert_fix32_to_dfp_long_reg); /*810*/ 4097 DEF_INST(convert_u32_to_dfp_ext_reg); /*810*/ 4098 DEF_INST(convert_u32_to_dfp_long_reg); /*810*/ 4099 DEF_INST(convert_fix64_to_dfp_ext_reg); 4100 DEF_INST(convert_fix64_to_dfp_long_reg); 4101 DEF_INST(convert_u64_to_dfp_ext_reg); /*810*/ 4102 DEF_INST(convert_u64_to_dfp_long_reg); /*810*/ 4103 DEF_INST(convert_sbcd128_to_dfp_ext_reg); 4104 DEF_INST(convert_sbcd64_to_dfp_long_reg); 4105 DEF_INST(convert_ubcd128_to_dfp_ext_reg); 4106 DEF_INST(convert_ubcd64_to_dfp_long_reg); 4107 DEF_INST(convert_zoned_to_dfp_ext); /*912*/ 4108 DEF_INST(convert_zoned_to_dfp_long); /*912*/ 4109 DEF_INST(convert_dfp_ext_to_fix32_reg); /*810*/ 4110 DEF_INST(convert_dfp_long_to_fix32_reg); /*810*/ 4111 DEF_INST(convert_dfp_ext_to_u32_reg); /*810*/ 4112 DEF_INST(convert_dfp_long_to_u32_reg); /*810*/ 4113 DEF_INST(convert_dfp_ext_to_fix64_reg); 4114 DEF_INST(convert_dfp_long_to_fix64_reg); 4115 DEF_INST(convert_dfp_ext_to_u64_reg); /*810*/ 4116 DEF_INST(convert_dfp_long_to_u64_reg); /*810*/ 4117 DEF_INST(convert_dfp_ext_to_sbcd128_reg); 4118 DEF_INST(convert_dfp_long_to_sbcd64_reg); 4119 DEF_INST(convert_dfp_ext_to_ubcd128_reg); 4120 DEF_INST(convert_dfp_long_to_ubcd64_reg); 4121 DEF_INST(convert_dfp_ext_to_zoned); /*912*/ 4122 DEF_INST(convert_dfp_long_to_zoned); /*912*/ 4123 DEF_INST(divide_dfp_ext_reg); 4124 DEF_INST(divide_dfp_long_reg); 4125 DEF_INST(extract_biased_exponent_dfp_ext_to_fix64_reg); 4126 DEF_INST(extract_biased_exponent_dfp_long_to_fix64_reg); 4127 DEF_INST(extract_significance_dfp_ext_reg); 4128 DEF_INST(extract_significance_dfp_long_reg); 4129 DEF_INST(insert_biased_exponent_fix64_to_dfp_ext_reg); 4130 DEF_INST(insert_biased_exponent_fix64_to_dfp_long_reg); 4131 DEF_INST(load_and_test_dfp_ext_reg); 4132 DEF_INST(load_and_test_dfp_long_reg); 4133 DEF_INST(load_fp_int_dfp_ext_reg); 4134 DEF_INST(load_fp_int_dfp_long_reg); 4135 DEF_INST(load_lengthened_dfp_long_to_ext_reg); 4136 DEF_INST(load_lengthened_dfp_short_to_long_reg); 4137 DEF_INST(load_rounded_dfp_ext_to_long_reg); 4138 DEF_INST(load_rounded_dfp_long_to_short_reg); 4139 DEF_INST(multiply_dfp_ext_reg); 4140 DEF_INST(multiply_dfp_long_reg); 4141 DEF_INST(quantize_dfp_ext_reg); 4142 DEF_INST(quantize_dfp_long_reg); 4143 DEF_INST(reround_dfp_ext_reg); 4144 DEF_INST(reround_dfp_long_reg); 4145 DEF_INST(shift_coefficient_left_dfp_ext); 4146 DEF_INST(shift_coefficient_left_dfp_long); 4147 DEF_INST(shift_coefficient_right_dfp_ext); 4148 DEF_INST(shift_coefficient_right_dfp_long); 4149 DEF_INST(subtract_dfp_ext_reg); 4150 DEF_INST(subtract_dfp_long_reg); 4151 DEF_INST(test_data_class_dfp_ext); 4152 DEF_INST(test_data_class_dfp_long); 4153 DEF_INST(test_data_class_dfp_short); 4154 DEF_INST(test_data_group_dfp_ext); 4155 DEF_INST(test_data_group_dfp_long); 4156 DEF_INST(test_data_group_dfp_short); 4157 4158 4159 /* Instructions in pfpo.c */ 4160 DEF_INST(perform_floating_point_operation); 4161 4162 4163 /* Instructions in transact.c */ 4164 DEF_INST(perform_processor_assist); /*912*/ 4165 DEF_INST(extract_transaction_nesting_depth); /*912*/ 4166 DEF_INST(nontransactional_store_long); /*912*/ 4167 DEF_INST(transaction_abort); /*912*/ 4168 DEF_INST(transaction_begin); /*912*/ 4169 DEF_INST(transaction_begin_constrained); /*912*/ 4170 DEF_INST(transaction_end); /*912*/ 4171 4172 /* end of OPCODE.H */ 4173