1 /**
2   ******************************************************************************
3   * @file    usb_core.c
4   * @author  MCD Application Team
5   * @version V2.0.0
6   * @date    22-July-2011
7   * @brief   USB-OTG Core Layer
8   ******************************************************************************
9   * @attention
10   *
11   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17   *
18   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
19   ******************************************************************************
20   */
21 
22 /* Includes ------------------------------------------------------------------*/
23 #include "usb_core.h"
24 #include "usb_bsp.h"
25 
26 
27 /** @addtogroup USB_OTG_DRIVER
28 * @{
29 */
30 
31 /** @defgroup USB_CORE
32 * @brief This file includes the USB-OTG Core Layer
33 * @{
34 */
35 
36 
37 /** @defgroup USB_CORE_Private_Defines
38 * @{
39 */
40 
41 /**
42 * @}
43 */
44 
45 
46 /** @defgroup USB_CORE_Private_TypesDefinitions
47 * @{
48 */
49 /**
50 * @}
51 */
52 
53 
54 
55 /** @defgroup USB_CORE_Private_Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 
62 
63 /** @defgroup USB_CORE_Private_Variables
64 * @{
65 */
66 /**
67 * @}
68 */
69 
70 
71 /** @defgroup USB_CORE_Private_FunctionPrototypes
72 * @{
73 */
74 /**
75 * @}
76 */
77 
78 
79 /** @defgroup USB_CORE_Private_Functions
80 * @{
81 */
82 
83 /**
84 * @brief  USB_OTG_EnableCommonInt
85 *         Initializes the commmon interrupts, used in both device and modes
86 * @param  pdev : Selected device
87 * @retval None
88 */
USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE * pdev)89 static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
90 {
91   USB_OTG_GINTMSK_TypeDef  int_mask;
92 
93   int_mask.d32 = 0;
94   /* Clear any pending USB_OTG Interrupts */
95 #ifndef USE_OTG_MODE
96   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
97 #endif
98   /* Clear any pending interrupts */
99   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
100   /* Enable the interrupts in the INTMSK */
101   int_mask.b.wkupintr = 1;
102   int_mask.b.usbsuspend = 1;
103 
104 #ifdef USE_OTG_MODE
105   int_mask.b.otgintr = 1;
106   int_mask.b.sessreqintr = 1;
107   int_mask.b.conidstschng = 1;
108 #endif
109   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32);
110 }
111 
112 /**
113 * @brief  USB_OTG_CoreReset : Soft reset of the core
114 * @param  pdev : Selected device
115 * @retval USB_OTG_STS : status
116 */
USB_OTG_CoreReset(USB_OTG_CORE_HANDLE * pdev)117 static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
118 {
119   USB_OTG_STS status = USB_OTG_OK;
120   __IO USB_OTG_GRSTCTL_TypeDef  greset;
121   uint32_t count = 0;
122 
123   greset.d32 = 0;
124   /* Wait for AHB master IDLE state. */
125   do
126   {
127     USB_OTG_BSP_uDelay(3);
128     greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
129     if (++count > 200000)
130     {
131       return USB_OTG_OK;
132     }
133   }
134   while (greset.b.ahbidle == 0);
135   /* Core Soft Reset */
136   count = 0;
137   greset.b.csftrst = 1;
138   USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 );
139   do
140   {
141     greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
142     if (++count > 200000)
143     {
144       break;
145     }
146   }
147   while (greset.b.csftrst == 1);
148   /* Wait for 3 PHY Clocks*/
149   USB_OTG_BSP_uDelay(3);
150   return status;
151 }
152 
153 /**
154 * @brief  USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated
155 *         with the EP
156 * @param  pdev : Selected device
157 * @param  src : source pointer
158 * @param  ch_ep_num : end point number
159 * @param  bytes : No. of bytes
160 * @retval USB_OTG_STS : status
161 */
USB_OTG_WritePacket(USB_OTG_CORE_HANDLE * pdev,uint8_t * src,uint8_t ch_ep_num,uint16_t len)162 USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev,
163                                 uint8_t             *src,
164                                 uint8_t             ch_ep_num,
165                                 uint16_t            len)
166 {
167   USB_OTG_STS status = USB_OTG_OK;
168   if (pdev->cfg.dma_enable == 0)
169   {
170     uint32_t count32b= 0 , i= 0;
171     __IO uint32_t *fifo;
172 
173     count32b =  (len + 3) / 4;
174     fifo = pdev->regs.DFIFO[ch_ep_num];
175     for (i = 0; i < count32b; i++, src+=4)
176     {
177       USB_OTG_WRITE_REG32( fifo, *((uint32_t *)src) );
178     }
179   }
180   return status;
181 }
182 
183 
184 /**
185 * @brief  USB_OTG_ReadPacket : Reads a packet from the Rx FIFO
186 * @param  pdev : Selected device
187 * @param  dest : Destination Pointer
188 * @param  bytes : No. of bytes
189 * @retval None
190 */
USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE * pdev,uint8_t * dest,uint16_t len)191 void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev,
192                          uint8_t *dest,
193                          uint16_t len)
194 {
195   uint32_t i=0;
196   uint32_t count32b = (len + 3) / 4;
197 
198   __IO uint32_t *fifo = pdev->regs.DFIFO[0];
199 
200   for ( i = 0; i < count32b; i++, dest += 4 )
201   {
202     *(uint32_t *)dest = USB_OTG_READ_REG32(fifo);
203 
204   }
205   return ((void *)dest);
206 }
207 
208 /**
209 * @brief  USB_OTG_SelectCore
210 *         Initialize core registers address.
211 * @param  pdev : Selected device
212 * @param  coreID : USB OTG Core ID
213 * @retval USB_OTG_STS : status
214 */
USB_OTG_SelectCore(USB_OTG_CORE_HANDLE * pdev,USB_OTG_CORE_ID_TypeDef coreID)215 USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev,
216                                USB_OTG_CORE_ID_TypeDef coreID)
217 {
218   uint32_t i , baseAddress = 0;
219   USB_OTG_STS status = USB_OTG_OK;
220 
221   pdev->cfg.dma_enable       = 0;
222 
223   /* at startup the core is in FS mode */
224   pdev->cfg.speed            = USB_OTG_SPEED_FULL;
225   pdev->cfg.mps              = USB_OTG_FS_MAX_PACKET_SIZE ;
226 
227   /* initialize device cfg following its address */
228   if (coreID == USB_OTG_FS_CORE_ID)
229   {
230     baseAddress                = USB_OTG_FS_BASE_ADDR;
231     pdev->cfg.coreID           = USB_OTG_FS_CORE_ID;
232     pdev->cfg.host_channels    = 8 ;
233     pdev->cfg.dev_endpoints    = 4 ;
234     pdev->cfg.TotalFifoSize    = 320; /* in 32-bits */
235     pdev->cfg.phy_itface       = USB_OTG_EMBEDDED_PHY;
236 
237 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
238     pdev->cfg.Sof_output       = 1;
239 #endif
240 
241 #ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
242     pdev->cfg.low_power        = 1;
243 #endif
244   }
245   else if (coreID == USB_OTG_HS_CORE_ID)
246   {
247     baseAddress                = USB_OTG_HS_BASE_ADDR;
248     pdev->cfg.coreID           = USB_OTG_HS_CORE_ID;
249     pdev->cfg.host_channels    = 12 ;
250     pdev->cfg.dev_endpoints    = 6 ;
251     pdev->cfg.TotalFifoSize    = 1280;/* in 32-bits */
252 
253 #ifdef USB_OTG_ULPI_PHY_ENABLED
254     pdev->cfg.phy_itface       = USB_OTG_ULPI_PHY;
255 #else
256  #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
257     pdev->cfg.phy_itface       = USB_OTG_EMBEDDED_PHY;
258  #else
259    #ifdef USB_OTG_I2C_PHY_ENABLED
260     pdev->cfg.phy_itface       = USB_OTG_I2C_PHY;
261    #endif
262  #endif
263 #endif
264 
265 #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
266     pdev->cfg.dma_enable       = 1;
267 #endif
268 
269 #ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED
270     pdev->cfg.Sof_output       = 1;
271 #endif
272 
273 #ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
274     pdev->cfg.low_power        = 1;
275 #endif
276 
277   }
278 
279   pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \
280     USB_OTG_CORE_GLOBAL_REGS_OFFSET);
281   pdev->regs.DREGS =  (USB_OTG_DREGS  *)  (baseAddress + \
282     USB_OTG_DEV_GLOBAL_REG_OFFSET);
283 
284   for (i = 0; i < pdev->cfg.dev_endpoints; i++)
285   {
286     pdev->regs.INEP_REGS[i]  = (USB_OTG_INEPREGS *)  \
287       (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \
288         (i * USB_OTG_EP_REG_OFFSET));
289     pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \
290       (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \
291         (i * USB_OTG_EP_REG_OFFSET));
292   }
293   pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \
294     USB_OTG_HOST_GLOBAL_REG_OFFSET);
295   pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
296 
297   for (i = 0; i < pdev->cfg.host_channels; i++)
298   {
299     pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \
300       USB_OTG_HOST_CHAN_REGS_OFFSET + \
301         (i * USB_OTG_CHAN_REGS_OFFSET));
302   }
303   for (i = 0; i < pdev->cfg.host_channels; i++)
304   {
305     pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\
306       (i * USB_OTG_DATA_FIFO_SIZE));
307   }
308   pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET);
309 
310   return status;
311 }
312 
313 
314 /**
315 * @brief  USB_OTG_CoreInit
316 *         Initializes the USB_OTG controller registers and prepares the core
317 *         device mode or host mode operation.
318 * @param  pdev : Selected device
319 * @retval USB_OTG_STS : status
320 */
USB_OTG_CoreInit(USB_OTG_CORE_HANDLE * pdev)321 USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
322 {
323   USB_OTG_STS status = USB_OTG_OK;
324   USB_OTG_GUSBCFG_TypeDef  usbcfg;
325   USB_OTG_GCCFG_TypeDef    gccfg;
326   USB_OTG_GI2CCTL_TypeDef  i2cctl;
327   USB_OTG_GAHBCFG_TypeDef  ahbcfg;
328 
329   usbcfg.d32 = 0;
330   gccfg.d32 = 0;
331   ahbcfg.d32 = 0;
332 
333 
334 
335   if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
336   {
337     gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG);
338     gccfg.b.pwdn = 0;
339 
340     if (pdev->cfg.Sof_output)
341     {
342       gccfg.b.sofouten = 1;
343     }
344     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
345 
346     /* Init The ULPI Interface */
347     usbcfg.d32 = 0;
348     usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
349 
350     usbcfg.b.physel            = 0; /* HS Interface */
351 #ifdef USB_OTG_INTERNAL_VBUS_ENABLED
352     usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */
353 #else
354  #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED
355     usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */
356  #endif
357 #endif
358     usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */
359     usbcfg.b.ulpi_utmi_sel     = 1; /* ULPI seleInterfacect */
360 
361     usbcfg.b.phyif             = 0; /* 8 bits */
362     usbcfg.b.ddrsel            = 0; /* single data rate */
363 
364     usbcfg.b.ulpi_fsls = 0;
365     usbcfg.b.ulpi_clk_sus_m = 0;
366     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
367 
368     /* Reset after a PHY select  */
369     USB_OTG_CoreReset(pdev);
370 
371     if(pdev->cfg.dma_enable == 1)
372     {
373 
374       ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
375       ahbcfg.b.dmaenable = 1;
376       USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
377 
378     }
379   }
380   else /* FS interface (embedded Phy or I2C Phy) */
381   {
382 
383     usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
384     usbcfg.b.physel  = 1; /* FS Interface */
385     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
386     /* Reset after a PHY select and set Host mode */
387     USB_OTG_CoreReset(pdev);
388     /* Enable the I2C interface and deactivate the power down*/
389     gccfg.d32 = 0;
390     gccfg.b.pwdn = 1;
391 
392     if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
393     {
394       gccfg.b.i2cifen = 1;
395     }
396     gccfg.b.vbussensingA = 1 ;
397     gccfg.b.vbussensingB = 1 ;
398 #ifndef VBUS_SENSING_ENABLED
399     gccfg.b.disablevbussensing = 1;
400 #endif
401 
402     if(pdev->cfg.Sof_output)
403     {
404       gccfg.b.sofouten = 1;
405     }
406 
407     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
408     USB_OTG_BSP_mDelay(20);
409     /* Program GUSBCFG.OtgUtmifsSel to I2C*/
410     usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
411 
412     if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
413     {
414       usbcfg.b.otgutmifssel = 1;
415     }
416 
417     USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
418 
419     if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
420     {
421       /*Program GI2CCTL.I2CEn*/
422       i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL);
423       i2cctl.b.i2cdevaddr = 1;
424       i2cctl.b.i2cen = 0;
425       i2cctl.b.dat_se0 = 1;
426       i2cctl.b.addr = 0x2D;
427       USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
428 
429       USB_OTG_BSP_mDelay(200);
430 
431       i2cctl.b.i2cen = 1;
432       USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
433       USB_OTG_BSP_mDelay(200);
434     }
435   }
436   /* case the HS core is working in FS mode */
437   if(pdev->cfg.dma_enable == 1)
438   {
439 
440     ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG);
441     ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
442     ahbcfg.b.dmaenable = 1;
443     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
444 
445   }
446   /* initialize OTG features */
447 #ifdef  USE_OTG_MODE
448   usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
449   usbcfg.b.hnpcap = 1;
450   usbcfg.b.srpcap = 1;
451   USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
452   USB_OTG_EnableCommonInt(pdev);
453 #endif
454   return status;
455 }
456 /**
457 * @brief  USB_OTG_EnableGlobalInt
458 *         Enables the controller's Global Int in the AHB Config reg
459 * @param  pdev : Selected device
460 * @retval USB_OTG_STS : status
461 */
USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE * pdev)462 USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
463 {
464   USB_OTG_STS status = USB_OTG_OK;
465   USB_OTG_GAHBCFG_TypeDef  ahbcfg;
466 
467   ahbcfg.d32 = 0;
468   ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
469   USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32);
470   return status;
471 }
472 
473 
474 /**
475 * @brief  USB_OTG_DisableGlobalInt
476 *         Enables the controller's Global Int in the AHB Config reg
477 * @param  pdev : Selected device
478 * @retval USB_OTG_STS : status
479 */
USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE * pdev)480 USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
481 {
482   USB_OTG_STS status = USB_OTG_OK;
483   USB_OTG_GAHBCFG_TypeDef  ahbcfg;
484   ahbcfg.d32 = 0;
485   ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
486   USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0);
487   return status;
488 }
489 
490 
491 /**
492 * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
493 * @param  pdev : Selected device
494 * @param  num : FO num
495 * @retval USB_OTG_STS : status
496 */
USB_OTG_FlushTxFifo(USB_OTG_CORE_HANDLE * pdev,uint32_t num)497 USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num )
498 {
499   USB_OTG_STS status = USB_OTG_OK;
500   __IO USB_OTG_GRSTCTL_TypeDef  greset;
501 
502   uint32_t count = 0;
503   greset.d32 = 0;
504   greset.b.txfflsh = 1;
505   greset.b.txfnum  = num;
506   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
507   do
508   {
509     greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
510     if (++count > 200000)
511     {
512       break;
513     }
514   }
515   while (greset.b.txfflsh == 1);
516   /* Wait for 3 PHY Clocks*/
517   USB_OTG_BSP_uDelay(3);
518   return status;
519 }
520 
521 
522 /**
523 * @brief  USB_OTG_FlushRxFifo : Flush a Rx FIFO
524 * @param  pdev : Selected device
525 * @retval USB_OTG_STS : status
526 */
USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE * pdev)527 USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev )
528 {
529   USB_OTG_STS status = USB_OTG_OK;
530   __IO USB_OTG_GRSTCTL_TypeDef  greset;
531   uint32_t count = 0;
532 
533   greset.d32 = 0;
534   greset.b.rxfflsh = 1;
535   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
536   do
537   {
538     greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
539     if (++count > 200000)
540     {
541       break;
542     }
543   }
544   while (greset.b.rxfflsh == 1);
545   /* Wait for 3 PHY Clocks*/
546   USB_OTG_BSP_uDelay(3);
547   return status;
548 }
549 
550 
551 /**
552 * @brief  USB_OTG_SetCurrentMode : Set ID line
553 * @param  pdev : Selected device
554 * @param  mode :  (Host/device)
555 * @retval USB_OTG_STS : status
556 */
USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE * pdev,uint8_t mode)557 USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode)
558 {
559   USB_OTG_STS status = USB_OTG_OK;
560   USB_OTG_GUSBCFG_TypeDef  usbcfg;
561 
562   usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
563 
564   usbcfg.b.force_host = 0;
565   usbcfg.b.force_dev = 0;
566 
567   if ( mode == HOST_MODE)
568   {
569     usbcfg.b.force_host = 1;
570   }
571   else if ( mode == DEVICE_MODE)
572   {
573     usbcfg.b.force_dev = 1;
574   }
575 
576   USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
577   USB_OTG_BSP_mDelay(50);
578   return status;
579 }
580 
581 
582 /**
583 * @brief  USB_OTG_GetMode : Get current mode
584 * @param  pdev : Selected device
585 * @retval current mode
586 */
USB_OTG_GetMode(USB_OTG_CORE_HANDLE * pdev)587 uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
588 {
589   return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1);
590 }
591 
592 
593 /**
594 * @brief  USB_OTG_IsDeviceMode : Check if it is device mode
595 * @param  pdev : Selected device
596 * @retval num_in_ep
597 */
USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE * pdev)598 uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
599 {
600   return (USB_OTG_GetMode(pdev) != HOST_MODE);
601 }
602 
603 
604 /**
605 * @brief  USB_OTG_IsHostMode : Check if it is host mode
606 * @param  pdev : Selected device
607 * @retval num_in_ep
608 */
USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE * pdev)609 uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
610 {
611   return (USB_OTG_GetMode(pdev) == HOST_MODE);
612 }
613 
614 
615 /**
616 * @brief  USB_OTG_ReadCoreItr : returns the Core Interrupt register
617 * @param  pdev : Selected device
618 * @retval Status
619 */
USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE * pdev)620 uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
621 {
622   uint32_t v = 0;
623   v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
624   v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
625   return v;
626 }
627 
628 
629 /**
630 * @brief  USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register
631 * @param  pdev : Selected device
632 * @retval Status
633 */
USB_OTG_ReadOtgItr(USB_OTG_CORE_HANDLE * pdev)634 uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
635 {
636   return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
637 }
638 
639 #ifdef USE_HOST_MODE
640 /**
641 * @brief  USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode
642 * @param  pdev : Selected device
643 * @retval status
644 */
USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE * pdev)645 USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
646 {
647   USB_OTG_STS                     status = USB_OTG_OK;
648   USB_OTG_FSIZ_TypeDef            nptxfifosize;
649   USB_OTG_FSIZ_TypeDef            ptxfifosize;
650   USB_OTG_HCFG_TypeDef            hcfg;
651 
652 #ifdef USE_OTG_MODE
653   USB_OTG_OTGCTL_TypeDef          gotgctl;
654 #endif
655 
656   uint32_t                        i = 0;
657 
658   nptxfifosize.d32 = 0;
659   ptxfifosize.d32 = 0;
660 #ifdef USE_OTG_MODE
661   gotgctl.d32 = 0;
662 #endif
663   hcfg.d32 = 0;
664 
665 
666   /* configure charge pump IO */
667   USB_OTG_BSP_ConfigVBUS(pdev);
668 
669   /* Restart the Phy Clock */
670   USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
671 
672   /* Initialize Host Configuration Register */
673   USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */
674 
675   hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
676   hcfg.b.fslssupp = 0;
677   USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
678 
679   /* Configure data FIFO sizes */
680   /* Rx FIFO */
681 #ifdef USB_OTG_FS_CORE
682   if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
683   {
684     /* set Rx FIFO size */
685     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
686     nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
687     nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ;
688     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
689 
690     ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ;
691     ptxfifosize.b.depth     = TXH_P_FS_FIFOSIZ;
692     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
693   }
694 #endif
695 #ifdef USB_OTG_HS_CORE
696    if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
697   {
698    /* set Rx FIFO size */
699     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
700     nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
701     nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;
702     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
703 
704     ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
705     ptxfifosize.b.depth     = TXH_P_HS_FIFOSIZ;
706     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
707   }
708 #endif
709 
710 #ifdef USE_OTG_MODE
711   /* Clear Host Set HNP Enable in the USB_OTG Control Register */
712   gotgctl.b.hstsethnpen = 1;
713   USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
714 #endif
715 
716   /* Make sure the FIFOs are flushed. */
717   USB_OTG_FlushTxFifo(pdev, 0x10 );         /* all Tx FIFOs */
718   USB_OTG_FlushRxFifo(pdev);
719 
720 
721   /* Clear all pending HC Interrupts */
722   for (i = 0; i < pdev->cfg.host_channels; i++)
723   {
724     USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
725     USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 );
726   }
727 #ifndef USE_OTG_MODE
728   USB_OTG_DriveVbus(pdev, 1);
729 #endif
730 
731   USB_OTG_EnableHostInt(pdev);
732   return status;
733 }
734 
735 /**
736 * @brief  USB_OTG_IsEvenFrame
737 *         This function returns the frame number for sof packet
738 * @param  pdev : Selected device
739 * @retval Frame number
740 */
USB_OTG_IsEvenFrame(USB_OTG_CORE_HANDLE * pdev)741 uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev)
742 {
743   return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1);
744 }
745 
746 /**
747 * @brief  USB_OTG_DriveVbus : set/reset vbus
748 * @param  pdev : Selected device
749 * @param  state : VBUS state
750 * @retval None
751 */
USB_OTG_DriveVbus(USB_OTG_CORE_HANDLE * pdev,uint8_t state)752 void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
753 {
754   USB_OTG_HPRT0_TypeDef     hprt0;
755 
756   hprt0.d32 = 0;
757 
758   /* enable disable the external charge pump */
759   USB_OTG_BSP_DriveVBUS(pdev, state);
760 
761   /* Turn on the Host port power. */
762   hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
763   if ((hprt0.b.prtpwr == 0 ) && (state == 1 ))
764   {
765     hprt0.b.prtpwr = 1;
766     USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
767   }
768   if ((hprt0.b.prtpwr == 1 ) && (state == 0 ))
769   {
770     hprt0.b.prtpwr = 0;
771     USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
772   }
773 
774   USB_OTG_BSP_mDelay(200);
775 }
776 /**
777 * @brief  USB_OTG_EnableHostInt: Enables the Host mode interrupts
778 * @param  pdev : Selected device
779 * @retval USB_OTG_STS : status
780 */
USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE * pdev)781 USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev)
782 {
783   USB_OTG_STS       status = USB_OTG_OK;
784   USB_OTG_GINTMSK_TypeDef  intmsk;
785   intmsk.d32 = 0;
786   /* Disable all interrupts. */
787   USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0);
788 
789   /* Clear any pending interrupts. */
790   USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
791 
792   /* Enable the common interrupts */
793   USB_OTG_EnableCommonInt(pdev);
794 
795   if (pdev->cfg.dma_enable == 0)
796   {
797     intmsk.b.rxstsqlvl  = 1;
798   }
799   intmsk.b.portintr   = 1;
800   intmsk.b.hcintr     = 1;
801   intmsk.b.disconnect = 1;
802   intmsk.b.sofintr    = 1;
803   intmsk.b.incomplisoout  = 1;
804   USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
805   return status;
806 }
807 
808 /**
809 * @brief  USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
810 *         HCFG register on the PHY type
811 * @param  pdev : Selected device
812 * @param  freq : clock frequency
813 * @retval None
814 */
USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE * pdev,uint8_t freq)815 void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq)
816 {
817   USB_OTG_HCFG_TypeDef   hcfg;
818 
819   hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
820   hcfg.b.fslspclksel = freq;
821   USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
822 }
823 
824 
825 /**
826 * @brief  USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later
827 * @param  pdev : Selected device
828 * @retval HPRT0 value
829 */
USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE * pdev)830 uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev)
831 {
832   USB_OTG_HPRT0_TypeDef  hprt0;
833 
834   hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
835   hprt0.b.prtena = 0;
836   hprt0.b.prtconndet = 0;
837   hprt0.b.prtenchng = 0;
838   hprt0.b.prtovrcurrchng = 0;
839   return hprt0.d32;
840 }
841 
842 
843 /**
844 * @brief  USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks
845 * @param  pdev : Selected device
846 * @retval Status
847 */
USB_OTG_ReadHostAllChannels_intr(USB_OTG_CORE_HANDLE * pdev)848 uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev)
849 {
850   return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT));
851 }
852 
853 
854 /**
855 * @brief  USB_OTG_ResetPort : Reset Host Port
856 * @param  pdev : Selected device
857 * @retval status
858 * @note : (1)The application must wait at least 10 ms (+ 10 ms security)
859 *   before clearing the reset bit.
860 */
USB_OTG_ResetPort(USB_OTG_CORE_HANDLE * pdev)861 uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev)
862 {
863   USB_OTG_HPRT0_TypeDef  hprt0;
864 
865   hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
866   hprt0.b.prtrst = 1;
867   USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
868   USB_OTG_BSP_mDelay (10);                                /* See Note #1 */
869   hprt0.b.prtrst = 0;
870   USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
871   USB_OTG_BSP_mDelay (20);
872   return 1;
873 }
874 
875 
876 /**
877 * @brief  USB_OTG_HC_Init : Prepares a host channel for transferring packets
878 * @param  pdev : Selected device
879 * @param  hc_num : channel number
880 * @retval USB_OTG_STS : status
881 */
USB_OTG_HC_Init(USB_OTG_CORE_HANDLE * pdev,uint8_t hc_num)882 USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
883 {
884   USB_OTG_STS status = USB_OTG_OK;
885   uint32_t intr_enable = 0;
886   USB_OTG_HCGINTMSK_TypeDef  hcintmsk;
887   USB_OTG_GINTMSK_TypeDef    gintmsk;
888   USB_OTG_HCCHAR_TypeDef     hcchar;
889   USB_OTG_HCINTn_TypeDef     hcint;
890 
891 
892   gintmsk.d32 = 0;
893   hcintmsk.d32 = 0;
894   hcchar.d32 = 0;
895 
896   /* Clear old interrupt conditions for this host channel. */
897   hcint.d32 = 0xFFFFFFFF;
898   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32);
899 
900   /* Enable channel interrupts required for this transfer. */
901   hcintmsk.d32 = 0;
902 
903   if (pdev->cfg.dma_enable == 1)
904   {
905     hcintmsk.b.ahberr = 1;
906   }
907 
908   switch (pdev->host.hc[hc_num].ep_type)
909   {
910   case EP_TYPE_CTRL:
911   case EP_TYPE_BULK:
912     hcintmsk.b.xfercompl = 1;
913     hcintmsk.b.stall = 1;
914     hcintmsk.b.xacterr = 1;
915     hcintmsk.b.datatglerr = 1;
916     hcintmsk.b.nak = 1;
917     if (pdev->host.hc[hc_num].ep_is_in)
918     {
919       hcintmsk.b.bblerr = 1;
920     }
921     else
922     {
923       hcintmsk.b.nyet = 1;
924       if (pdev->host.hc[hc_num].do_ping)
925       {
926         hcintmsk.b.ack = 1;
927       }
928     }
929     break;
930   case EP_TYPE_INTR:
931     hcintmsk.b.xfercompl = 1;
932     hcintmsk.b.nak = 1;
933     hcintmsk.b.stall = 1;
934     hcintmsk.b.xacterr = 1;
935     hcintmsk.b.datatglerr = 1;
936     hcintmsk.b.frmovrun = 1;
937 
938     if (pdev->host.hc[hc_num].ep_is_in)
939     {
940       hcintmsk.b.bblerr = 1;
941     }
942 
943     break;
944   case EP_TYPE_ISOC:
945     hcintmsk.b.xfercompl = 1;
946     hcintmsk.b.frmovrun = 1;
947     hcintmsk.b.ack = 1;
948 
949     if (pdev->host.hc[hc_num].ep_is_in)
950     {
951       hcintmsk.b.xacterr = 1;
952       hcintmsk.b.bblerr = 1;
953     }
954     break;
955   }
956 
957 
958   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32);
959 
960 
961   /* Enable the top level host channel interrupt. */
962   intr_enable = (1 << hc_num);
963   USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable);
964 
965   /* Make sure host channel interrupts are enabled. */
966   gintmsk.b.hcintr = 1;
967   USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32);
968 
969   /* Program the HCCHAR register */
970   hcchar.d32 = 0;
971   hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr;
972   hcchar.b.epnum   = pdev->host.hc[hc_num].ep_num;
973   hcchar.b.epdir   = pdev->host.hc[hc_num].ep_is_in;
974   hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED);
975   hcchar.b.eptype  = pdev->host.hc[hc_num].ep_type;
976   hcchar.b.mps     = pdev->host.hc[hc_num].max_packet;
977   if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR)
978   {
979     hcchar.b.oddfrm  = 1;
980   }
981   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
982   return status;
983 }
984 
985 
986 /**
987 * @brief  USB_OTG_HC_StartXfer : Start transfer
988 * @param  pdev : Selected device
989 * @param  hc_num : channel number
990 * @retval USB_OTG_STS : status
991 */
USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE * pdev,uint8_t hc_num)992 USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
993 {
994   USB_OTG_STS status = USB_OTG_OK;
995   USB_OTG_HCCHAR_TypeDef   hcchar;
996   USB_OTG_HCTSIZn_TypeDef  hctsiz;
997   USB_OTG_HNPTXSTS_TypeDef hnptxsts;
998   USB_OTG_HPTXSTS_TypeDef  hptxsts;
999   USB_OTG_GINTMSK_TypeDef  intmsk;
1000   uint16_t                 len_words = 0;
1001 
1002   uint16_t num_packets;
1003   uint16_t max_hc_pkt_count;
1004 
1005   max_hc_pkt_count = 256;
1006   hctsiz.d32 = 0;
1007   hcchar.d32 = 0;
1008   intmsk.d32 = 0;
1009 
1010   /* Compute the expected number of packets associated to the transfer */
1011   if (pdev->host.hc[hc_num].xfer_len > 0)
1012   {
1013     num_packets = (pdev->host.hc[hc_num].xfer_len + \
1014       pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
1015 
1016     if (num_packets > max_hc_pkt_count)
1017     {
1018       num_packets = max_hc_pkt_count;
1019       pdev->host.hc[hc_num].xfer_len = num_packets * \
1020         pdev->host.hc[hc_num].max_packet;
1021     }
1022   }
1023   else
1024   {
1025     num_packets = 1;
1026   }
1027   if (pdev->host.hc[hc_num].ep_is_in)
1028   {
1029     pdev->host.hc[hc_num].xfer_len = num_packets * \
1030       pdev->host.hc[hc_num].max_packet;
1031   }
1032   /* Initialize the HCTSIZn register */
1033   hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len;
1034   hctsiz.b.pktcnt = num_packets;
1035   hctsiz.b.pid = pdev->host.hc[hc_num].data_pid;
1036   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
1037 
1038   if (pdev->cfg.dma_enable == 1)
1039   {
1040     USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff);
1041   }
1042 
1043 
1044   hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1045   hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev);
1046 
1047   /* Set host channel enable */
1048   hcchar.b.chen = 1;
1049   hcchar.b.chdis = 0;
1050   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1051 
1052   if (pdev->cfg.dma_enable == 0) /* Slave mode */
1053   {
1054     if((pdev->host.hc[hc_num].ep_is_in == 0) &&
1055         (pdev->host.hc[hc_num].xfer_len > 0))
1056     {
1057       switch(pdev->host.hc[hc_num].ep_type)
1058       {
1059         /* Non periodic transfer */
1060       case EP_TYPE_CTRL:
1061       case EP_TYPE_BULK:
1062 
1063         hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
1064         len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1065 
1066         /* check if there is enough space in FIFO space */
1067         if(len_words > hnptxsts.b.nptxfspcavail)
1068         {
1069           /* need to process data in nptxfempty interrupt */
1070           intmsk.b.nptxfempty = 1;
1071           USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
1072         }
1073 
1074         break;
1075         /* Periodic transfer */
1076       case EP_TYPE_INTR:
1077       case EP_TYPE_ISOC:
1078         hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
1079         len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
1080         /* check if there is enough space in FIFO space */
1081         if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */
1082         {
1083           /* need to process data in ptxfempty interrupt */
1084           intmsk.b.ptxfempty = 1;
1085           USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
1086         }
1087         break;
1088 
1089       default:
1090         break;
1091       }
1092 
1093       /* Write packet into the Tx FIFO. */
1094       USB_OTG_WritePacket(pdev,
1095                           pdev->host.hc[hc_num].xfer_buff ,
1096                           hc_num, pdev->host.hc[hc_num].xfer_len);
1097     }
1098   }
1099   return status;
1100 }
1101 
1102 
1103 /**
1104 * @brief  USB_OTG_HC_Halt : Halt channel
1105 * @param  pdev : Selected device
1106 * @param  hc_num : channel number
1107 * @retval USB_OTG_STS : status
1108 */
USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE * pdev,uint8_t hc_num)1109 USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
1110 {
1111   USB_OTG_STS status = USB_OTG_OK;
1112   USB_OTG_HNPTXSTS_TypeDef            nptxsts;
1113   USB_OTG_HPTXSTS_TypeDef             hptxsts;
1114   USB_OTG_HCCHAR_TypeDef              hcchar;
1115 
1116   nptxsts.d32 = 0;
1117   hptxsts.d32 = 0;
1118   hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1119   hcchar.b.chen = 1;
1120   hcchar.b.chdis = 1;
1121 
1122   /* Check for space in the request queue to issue the halt. */
1123   if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK)
1124   {
1125     nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
1126     if (nptxsts.b.nptxqspcavail == 0)
1127     {
1128       hcchar.b.chen = 0;
1129     }
1130   }
1131   else
1132   {
1133     hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
1134     if (hptxsts.b.ptxqspcavail == 0)
1135     {
1136       hcchar.b.chen = 0;
1137     }
1138   }
1139   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1140   return status;
1141 }
1142 
1143 /**
1144 * @brief  Issue a ping token
1145 * @param  None
1146 * @retval : None
1147 */
USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE * pdev,uint8_t hc_num)1148 USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
1149 {
1150   USB_OTG_STS               status = USB_OTG_OK;
1151   USB_OTG_HCCHAR_TypeDef    hcchar;
1152   USB_OTG_HCTSIZn_TypeDef   hctsiz;
1153 
1154   hctsiz.d32 = 0;
1155   hctsiz.b.dopng = 1;
1156   hctsiz.b.pktcnt = 1;
1157   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
1158 
1159   hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
1160   hcchar.b.chen = 1;
1161   hcchar.b.chdis = 0;
1162   USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
1163   return status;
1164 }
1165 
1166 /**
1167 * @brief  Stop the device and clean up fifo's
1168 * @param  None
1169 * @retval : None
1170 */
USB_OTG_StopHost(USB_OTG_CORE_HANDLE * pdev)1171 void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
1172 {
1173   USB_OTG_HCCHAR_TypeDef  hcchar;
1174   uint32_t                i;
1175 
1176   USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
1177   USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT,      0xFFFFFFFF);
1178   /* Flush out any leftover queued requests. */
1179 
1180   for (i = 0; i < pdev->cfg.host_channels; i++)
1181   {
1182     hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
1183     hcchar.b.chen = 0;
1184     hcchar.b.chdis = 1;
1185     hcchar.b.epdir = 0;
1186     USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
1187   }
1188 
1189   /* Flush the FIFO */
1190   USB_OTG_FlushRxFifo(pdev);
1191   USB_OTG_FlushTxFifo(pdev ,  0x10 );
1192 }
1193 #endif
1194 #ifdef USE_DEVICE_MODE
1195 /*         PCD Core Layer       */
1196 
1197 /**
1198 * @brief  USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register
1199 *         depending the PHY type and the enumeration speed of the device.
1200 * @param  pdev : Selected device
1201 * @retval : None
1202 */
USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE * pdev,uint8_t speed)1203 void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed)
1204 {
1205   USB_OTG_DCFG_TypeDef   dcfg;
1206 
1207   dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
1208   dcfg.b.devspd = speed;
1209   USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
1210 }
1211 
1212 
1213 /**
1214 * @brief  USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers
1215 *         for device mode
1216 * @param  pdev : Selected device
1217 * @retval USB_OTG_STS : status
1218 */
USB_OTG_CoreInitDev(USB_OTG_CORE_HANDLE * pdev)1219 USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev)
1220 {
1221   USB_OTG_STS             status       = USB_OTG_OK;
1222   USB_OTG_DEPCTL_TypeDef  depctl;
1223   uint32_t i;
1224   USB_OTG_DCFG_TypeDef    dcfg;
1225   USB_OTG_FSIZ_TypeDef    nptxfifosize;
1226   USB_OTG_FSIZ_TypeDef    txfifosize;
1227   USB_OTG_DIEPMSK_TypeDef msk;
1228   USB_OTG_DTHRCTL_TypeDef dthrctl;
1229 
1230   depctl.d32 = 0;
1231   dcfg.d32 = 0;
1232   nptxfifosize.d32 = 0;
1233   txfifosize.d32 = 0;
1234   msk.d32 = 0;
1235 
1236   /* Restart the Phy Clock */
1237   USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
1238   /* Device configuration register */
1239   dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
1240   dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
1241   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 );
1242 
1243 #ifdef USB_OTG_FS_CORE
1244   if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID  )
1245   {
1246 
1247     /* Set Full speed phy */
1248     USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL);
1249 
1250     /* set Rx FIFO size */
1251     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
1252 
1253     /* EP0 TX*/
1254     nptxfifosize.b.depth     = TX0_FIFO_FS_SIZE;
1255     nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
1256     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
1257 
1258 
1259     /* EP1 TX*/
1260     txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1261     txfifosize.b.depth = TX1_FIFO_FS_SIZE;
1262     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
1263 
1264 
1265     /* EP2 TX*/
1266     txfifosize.b.startaddr += txfifosize.b.depth;
1267     txfifosize.b.depth = TX2_FIFO_FS_SIZE;
1268     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
1269 
1270 
1271     /* EP3 TX*/
1272     txfifosize.b.startaddr += txfifosize.b.depth;
1273     txfifosize.b.depth = TX3_FIFO_FS_SIZE;
1274     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
1275   }
1276 #endif
1277 #ifdef USB_OTG_HS_CORE
1278   if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID  )
1279   {
1280 
1281     /* Set High speed phy */
1282 
1283     if(pdev->cfg.phy_itface  == USB_OTG_ULPI_PHY)
1284     {
1285        USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH);
1286     }
1287     else /* set High speed phy in Full speed mode */
1288     {
1289       USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL);
1290     }
1291 
1292     /* set Rx FIFO size */
1293     USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
1294 
1295     /* EP0 TX*/
1296     nptxfifosize.b.depth     = TX0_FIFO_HS_SIZE;
1297     nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
1298     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
1299 
1300 
1301     /* EP1 TX*/
1302     txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1303     txfifosize.b.depth = TX1_FIFO_HS_SIZE;
1304     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
1305 
1306 
1307     /* EP2 TX*/
1308     txfifosize.b.startaddr += txfifosize.b.depth;
1309     txfifosize.b.depth = TX2_FIFO_HS_SIZE;
1310     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
1311 
1312 
1313     /* EP3 TX*/
1314     txfifosize.b.startaddr += txfifosize.b.depth;
1315     txfifosize.b.depth = TX3_FIFO_HS_SIZE;
1316     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
1317 
1318     /* EP4 TX*/
1319     txfifosize.b.startaddr += txfifosize.b.depth;
1320     txfifosize.b.depth = TX4_FIFO_HS_SIZE;
1321     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 );
1322 
1323 
1324     /* EP5 TX*/
1325     txfifosize.b.startaddr += txfifosize.b.depth;
1326     txfifosize.b.depth = TX5_FIFO_HS_SIZE;
1327     USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 );
1328   }
1329 #endif
1330   /* Flush the FIFOs */
1331   USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
1332   USB_OTG_FlushRxFifo(pdev);
1333   /* Clear all pending Device Interrupts */
1334   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
1335   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
1336   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
1337   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
1338 
1339   for (i = 0; i < pdev->cfg.dev_endpoints; i++)
1340   {
1341     depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
1342     if (depctl.b.epena)
1343     {
1344       depctl.d32 = 0;
1345       depctl.b.epdis = 1;
1346       depctl.b.snak = 1;
1347     }
1348     else
1349     {
1350       depctl.d32 = 0;
1351     }
1352     USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
1353     USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
1354     USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
1355   }
1356   for (i = 0; i <  pdev->cfg.dev_endpoints; i++)
1357   {
1358     USB_OTG_DEPCTL_TypeDef  depctl;
1359     depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
1360     if (depctl.b.epena)
1361     {
1362       depctl.d32 = 0;
1363       depctl.b.epdis = 1;
1364       depctl.b.snak = 1;
1365     }
1366     else
1367     {
1368       depctl.d32 = 0;
1369     }
1370     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
1371     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
1372     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
1373   }
1374   msk.d32 = 0;
1375   msk.b.txfifoundrn = 1;
1376   USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
1377 
1378   if (pdev->cfg.dma_enable == 1)
1379   {
1380     dthrctl.d32 = 0;
1381     dthrctl.b.non_iso_thr_en = 1;
1382     dthrctl.b.iso_thr_en = 1;
1383     dthrctl.b.tx_thr_len = 64;
1384     dthrctl.b.rx_thr_en = 1;
1385     dthrctl.b.rx_thr_len = 64;
1386     USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);
1387   }
1388   USB_OTG_EnableDevInt(pdev);
1389   return status;
1390 }
1391 
1392 
1393 /**
1394 * @brief  USB_OTG_EnableDevInt : Enables the Device mode interrupts
1395 * @param  pdev : Selected device
1396 * @retval USB_OTG_STS : status
1397 */
USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE * pdev)1398 USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
1399 {
1400   USB_OTG_STS status = USB_OTG_OK;
1401   USB_OTG_GINTMSK_TypeDef  intmsk;
1402 
1403   intmsk.d32 = 0;
1404 
1405   /* Disable all interrupts. */
1406   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
1407   /* Clear any pending interrupts */
1408   USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
1409   /* Enable the common interrupts */
1410   USB_OTG_EnableCommonInt(pdev);
1411 
1412   if (pdev->cfg.dma_enable == 0)
1413   {
1414     intmsk.b.rxstsqlvl = 1;
1415   }
1416 
1417   /* Enable interrupts matching to the Device mode ONLY */
1418   intmsk.b.usbsuspend = 1;
1419   intmsk.b.usbreset   = 1;
1420   intmsk.b.enumdone   = 1;
1421   intmsk.b.inepintr   = 1;
1422   intmsk.b.outepintr  = 1;
1423   intmsk.b.sofintr    = 1;
1424 
1425   intmsk.b.incomplisoin    = 1;
1426   intmsk.b.incomplisoout    = 1;
1427 #ifdef VBUS_SENSING_ENABLED
1428   intmsk.b.sessreqintr    = 1;
1429   intmsk.b.otgintr    = 1;
1430 #endif
1431   USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
1432   return status;
1433 }
1434 
1435 
1436 /**
1437 * @brief  USB_OTG_GetDeviceSpeed
1438 *         Get the device speed from the device status register
1439 * @param  None
1440 * @retval status
1441 */
USB_OTG_GetDeviceSpeed(USB_OTG_CORE_HANDLE * pdev)1442 enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev)
1443 {
1444   USB_OTG_DSTS_TypeDef  dsts;
1445   enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN;
1446 
1447 
1448   dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1449 
1450   switch (dsts.b.enumspd)
1451   {
1452   case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
1453     speed = USB_SPEED_HIGH;
1454     break;
1455   case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
1456   case DSTS_ENUMSPD_FS_PHY_48MHZ:
1457     speed = USB_SPEED_FULL;
1458     break;
1459 
1460   case DSTS_ENUMSPD_LS_PHY_6MHZ:
1461     speed = USB_SPEED_LOW;
1462     break;
1463   }
1464 
1465   return speed;
1466 }
1467 /**
1468 * @brief  enables EP0 OUT to receive SETUP packets and configures EP0
1469 *   for transmitting packets
1470 * @param  None
1471 * @retval USB_OTG_STS : status
1472 */
USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE * pdev)1473 USB_OTG_STS  USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev)
1474 {
1475   USB_OTG_STS             status = USB_OTG_OK;
1476   USB_OTG_DSTS_TypeDef    dsts;
1477   USB_OTG_DEPCTL_TypeDef  diepctl;
1478   USB_OTG_DCTL_TypeDef    dctl;
1479 
1480   dctl.d32 = 0;
1481   /* Read the Device Status and Endpoint 0 Control registers */
1482   dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1483   diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL);
1484   /* Set the MPS of the IN EP based on the enumeration speed */
1485   switch (dsts.b.enumspd)
1486   {
1487   case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
1488   case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
1489   case DSTS_ENUMSPD_FS_PHY_48MHZ:
1490     diepctl.b.mps = DEP0CTL_MPS_64;
1491     break;
1492   case DSTS_ENUMSPD_LS_PHY_6MHZ:
1493     diepctl.b.mps = DEP0CTL_MPS_8;
1494     break;
1495   }
1496   USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32);
1497   dctl.b.cgnpinnak = 1;
1498   USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32);
1499   return status;
1500 }
1501 
1502 
1503 /**
1504 * @brief  USB_OTG_EPActivate : Activates an EP
1505 * @param  pdev : Selected device
1506 * @retval USB_OTG_STS : status
1507 */
USB_OTG_EPActivate(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1508 USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1509 {
1510   USB_OTG_STS status = USB_OTG_OK;
1511   USB_OTG_DEPCTL_TypeDef  depctl;
1512   USB_OTG_DAINT_TypeDef  daintmsk;
1513   __IO uint32_t *addr;
1514 
1515 
1516   depctl.d32 = 0;
1517   daintmsk.d32 = 0;
1518   /* Read DEPCTLn register */
1519   if (ep->is_in == 1)
1520   {
1521     addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
1522     daintmsk.ep.in = 1 << ep->num;
1523   }
1524   else
1525   {
1526     addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
1527     daintmsk.ep.out = 1 << ep->num;
1528   }
1529   /* If the EP is already active don't change the EP Control
1530   * register. */
1531   depctl.d32 = USB_OTG_READ_REG32(addr);
1532   if (!depctl.b.usbactep)
1533   {
1534     depctl.b.mps    = ep->maxpacket;
1535     depctl.b.eptype = ep->type;
1536     depctl.b.txfnum = ep->tx_fifo_num;
1537     depctl.b.setd0pid = 1;
1538     depctl.b.usbactep = 1;
1539     USB_OTG_WRITE_REG32(addr, depctl.d32);
1540   }
1541   /* Enable the Interrupt for this EP */
1542 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
1543   if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
1544   {
1545     USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32);
1546   }
1547   else
1548 #endif
1549     USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32);
1550   return status;
1551 }
1552 
1553 
1554 /**
1555 * @brief  USB_OTG_EPDeactivate : Deactivates an EP
1556 * @param  pdev : Selected device
1557 * @retval USB_OTG_STS : status
1558 */
USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1559 USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1560 {
1561   USB_OTG_STS status = USB_OTG_OK;
1562   USB_OTG_DEPCTL_TypeDef  depctl;
1563   USB_OTG_DAINT_TypeDef  daintmsk;
1564   __IO uint32_t *addr;
1565 
1566   depctl.d32 = 0;
1567   daintmsk.d32 = 0;
1568   /* Read DEPCTLn register */
1569   if (ep->is_in == 1)
1570   {
1571     addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
1572     daintmsk.ep.in = 1 << ep->num;
1573   }
1574   else
1575   {
1576     addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
1577     daintmsk.ep.out = 1 << ep->num;
1578   }
1579   depctl.b.usbactep = 0;
1580   USB_OTG_WRITE_REG32(addr, depctl.d32);
1581   /* Disable the Interrupt for this EP */
1582 
1583 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
1584   if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
1585   {
1586     USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0);
1587   }
1588   else
1589 #endif
1590     USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0);
1591   return status;
1592 }
1593 
1594 
1595 /**
1596 * @brief  USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and
1597 *         starts the xfer
1598 * @param  pdev : Selected device
1599 * @retval USB_OTG_STS : status
1600 */
USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1601 USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1602 {
1603   USB_OTG_STS status = USB_OTG_OK;
1604   USB_OTG_DEPCTL_TypeDef     depctl;
1605   USB_OTG_DEPXFRSIZ_TypeDef  deptsiz;
1606   USB_OTG_DSTS_TypeDef       dsts;
1607   uint32_t fifoemptymsk = 0;
1608 
1609   depctl.d32 = 0;
1610   deptsiz.d32 = 0;
1611   /* IN endpoint */
1612   if (ep->is_in == 1)
1613   {
1614     depctl.d32  = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL));
1615     deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ));
1616     /* Zero Length Packet? */
1617     if (ep->xfer_len == 0)
1618     {
1619       deptsiz.b.xfersize = 0;
1620       deptsiz.b.pktcnt = 1;
1621     }
1622     else
1623     {
1624       /* Program the transfer size and packet count
1625       * as follows: xfersize = N * maxpacket +
1626       * short_packet pktcnt = N + (short_packet
1627       * exist ? 1 : 0)
1628       */
1629       deptsiz.b.xfersize = ep->xfer_len;
1630       deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
1631 
1632       if (ep->type == EP_TYPE_ISOC)
1633       {
1634         deptsiz.b.mc = 1;
1635       }
1636     }
1637     USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32);
1638 
1639     if (pdev->cfg.dma_enable == 1)
1640     {
1641       USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
1642     }
1643     else
1644     {
1645       if (ep->type != EP_TYPE_ISOC)
1646       {
1647         /* Enable the Tx FIFO Empty Interrupt for this EP */
1648         if (ep->xfer_len > 0)
1649         {
1650           fifoemptymsk = 1 << ep->num;
1651           USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
1652         }
1653       }
1654     }
1655 
1656 
1657     if (ep->type == EP_TYPE_ISOC)
1658     {
1659       dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1660 
1661       if (((dsts.b.soffn)&0x1) == 0)
1662       {
1663         depctl.b.setd1pid = 1;
1664       }
1665       else
1666       {
1667         depctl.b.setd0pid = 1;
1668       }
1669     }
1670 
1671     /* EP enable, IN data in FIFO */
1672     depctl.b.cnak = 1;
1673     depctl.b.epena = 1;
1674     USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32);
1675 
1676     if (ep->type == EP_TYPE_ISOC)
1677     {
1678       USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len);
1679     }
1680   }
1681   else
1682   {
1683     /* OUT endpoint */
1684     depctl.d32  = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL));
1685     deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ));
1686     /* Program the transfer size and packet count as follows:
1687     * pktcnt = N
1688     * xfersize = N * maxpacket
1689     */
1690     if (ep->xfer_len == 0)
1691     {
1692       deptsiz.b.xfersize = ep->maxpacket;
1693       deptsiz.b.pktcnt = 1;
1694     }
1695     else
1696     {
1697       deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
1698       deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
1699     }
1700     USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
1701 
1702     if (pdev->cfg.dma_enable == 1)
1703     {
1704       USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
1705     }
1706 
1707     if (ep->type == EP_TYPE_ISOC)
1708     {
1709       if (ep->even_odd_frame)
1710       {
1711         depctl.b.setd1pid = 1;
1712       }
1713       else
1714       {
1715         depctl.b.setd0pid = 1;
1716       }
1717     }
1718     /* EP enable */
1719     depctl.b.cnak = 1;
1720     depctl.b.epena = 1;
1721     USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32);
1722   }
1723   return status;
1724 }
1725 
1726 
1727 /**
1728 * @brief  USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and
1729 *         starts the xfer
1730 * @param  pdev : Selected device
1731 * @retval USB_OTG_STS : status
1732 */
USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1733 USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1734 {
1735   USB_OTG_STS                 status = USB_OTG_OK;
1736   USB_OTG_DEPCTL_TypeDef      depctl;
1737   USB_OTG_DEP0XFRSIZ_TypeDef  deptsiz;
1738   USB_OTG_INEPREGS          *in_regs;
1739   uint32_t fifoemptymsk = 0;
1740 
1741   depctl.d32   = 0;
1742   deptsiz.d32  = 0;
1743   /* IN endpoint */
1744   if (ep->is_in == 1)
1745   {
1746     in_regs = pdev->regs.INEP_REGS[0];
1747     depctl.d32  = USB_OTG_READ_REG32(&in_regs->DIEPCTL);
1748     deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ);
1749     /* Zero Length Packet? */
1750     if (ep->xfer_len == 0)
1751     {
1752       deptsiz.b.xfersize = 0;
1753       deptsiz.b.pktcnt = 1;
1754 
1755     }
1756     else
1757     {
1758       if (ep->xfer_len > ep->maxpacket)
1759       {
1760         ep->xfer_len = ep->maxpacket;
1761         deptsiz.b.xfersize = ep->maxpacket;
1762       }
1763       else
1764       {
1765         deptsiz.b.xfersize = ep->xfer_len;
1766       }
1767       deptsiz.b.pktcnt = 1;
1768     }
1769     USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32);
1770 
1771     if (pdev->cfg.dma_enable == 1)
1772     {
1773       USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
1774     }
1775 
1776     /* EP enable, IN data in FIFO */
1777     depctl.b.cnak = 1;
1778     depctl.b.epena = 1;
1779     USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32);
1780 
1781 
1782 
1783     if (pdev->cfg.dma_enable == 0)
1784     {
1785       /* Enable the Tx FIFO Empty Interrupt for this EP */
1786       if (ep->xfer_len > 0)
1787       {
1788         {
1789           fifoemptymsk |= 1 << ep->num;
1790           USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
1791         }
1792       }
1793     }
1794   }
1795   else
1796   {
1797     /* OUT endpoint */
1798     depctl.d32  = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1799     deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ);
1800     /* Program the transfer size and packet count as follows:
1801     * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
1802     * pktcnt = N           */
1803     if (ep->xfer_len == 0)
1804     {
1805       deptsiz.b.xfersize = ep->maxpacket;
1806       deptsiz.b.pktcnt = 1;
1807     }
1808     else
1809     {
1810       ep->xfer_len = ep->maxpacket;
1811       deptsiz.b.xfersize = ep->maxpacket;
1812       deptsiz.b.pktcnt = 1;
1813     }
1814     USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
1815     if (pdev->cfg.dma_enable == 1)
1816     {
1817       USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
1818     }
1819     /* EP enable */
1820     depctl.b.cnak = 1;
1821     depctl.b.epena = 1;
1822     USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32);
1823 
1824   }
1825   return status;
1826 }
1827 
1828 
1829 /**
1830 * @brief  USB_OTG_EPSetStall : Set the EP STALL
1831 * @param  pdev : Selected device
1832 * @retval USB_OTG_STS : status
1833 */
USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1834 USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1835 {
1836   USB_OTG_STS status = USB_OTG_OK;
1837   USB_OTG_DEPCTL_TypeDef  depctl;
1838   __IO uint32_t *depctl_addr;
1839 
1840   depctl.d32 = 0;
1841   if (ep->is_in == 1)
1842   {
1843     depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
1844     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1845     /* set the disable and stall bits */
1846     if (depctl.b.epena)
1847     {
1848       depctl.b.epdis = 1;
1849     }
1850     depctl.b.stall = 1;
1851     USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1852   }
1853   else
1854   {
1855     depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1856     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1857     /* set the stall bit */
1858     depctl.b.stall = 1;
1859     USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1860   }
1861   return status;
1862 }
1863 
1864 
1865 /**
1866 * @brief  Clear the EP STALL
1867 * @param  pdev : Selected device
1868 * @retval USB_OTG_STS : status
1869 */
USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)1870 USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
1871 {
1872   USB_OTG_STS status = USB_OTG_OK;
1873   USB_OTG_DEPCTL_TypeDef  depctl;
1874   __IO uint32_t *depctl_addr;
1875 
1876   depctl.d32 = 0;
1877 
1878   if (ep->is_in == 1)
1879   {
1880     depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
1881   }
1882   else
1883   {
1884     depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
1885   }
1886   depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
1887   /* clear the stall bits */
1888   depctl.b.stall = 0;
1889   if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
1890   {
1891     depctl.b.setd0pid = 1; /* DATA0 */
1892   }
1893   USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
1894   return status;
1895 }
1896 
1897 
1898 /**
1899 * @brief  USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits
1900 * @param  pdev : Selected device
1901 * @retval OUT endpoint interrupt bits
1902 */
USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE * pdev)1903 uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev)
1904 {
1905   uint32_t v;
1906   v  = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
1907   v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
1908   return ((v & 0xffff0000) >> 16);
1909 }
1910 
1911 
1912 /**
1913 * @brief  USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register
1914 * @param  pdev : Selected device
1915 * @param  ep : end point number
1916 * @retval Device OUT EP Interrupt register
1917 */
USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE * pdev,uint8_t epnum)1918 uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
1919 {
1920   uint32_t v;
1921   v  = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT);
1922   v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK);
1923   return v;
1924 }
1925 
1926 
1927 /**
1928 * @brief  USB_OTG_ReadDevAllInEPItr : Get int status register
1929 * @param  pdev : Selected device
1930 * @retval int status register
1931 */
USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE * pdev)1932 uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev)
1933 {
1934   uint32_t v;
1935   v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
1936   v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
1937   return (v & 0xffff);
1938 }
1939 
1940 /**
1941 * @brief  configures EPO to receive SETUP packets
1942 * @param  None
1943 * @retval : None
1944 */
USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE * pdev)1945 void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev)
1946 {
1947   USB_OTG_DEP0XFRSIZ_TypeDef  doeptsize0;
1948   doeptsize0.d32 = 0;
1949   doeptsize0.b.supcnt = 3;
1950   doeptsize0.b.pktcnt = 1;
1951   doeptsize0.b.xfersize = 8 * 3;
1952   USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 );
1953 
1954   if (pdev->cfg.dma_enable == 1)
1955   {
1956     USB_OTG_DEPCTL_TypeDef  doepctl;
1957     doepctl.d32 = 0;
1958     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA,
1959                         (uint32_t)&pdev->dev.setup_packet);
1960 
1961     /* EP enable */
1962     doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
1963     doepctl.b.epena = 1;
1964     doepctl.d32 = 0x80008000;
1965     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
1966   }
1967 }
1968 
1969 /**
1970 * @brief  USB_OTG_RemoteWakeup : active remote wakeup signalling
1971 * @param  None
1972 * @retval : None
1973 */
USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE * pdev)1974 void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
1975 {
1976 
1977   USB_OTG_DCTL_TypeDef     dctl;
1978   USB_OTG_DSTS_TypeDef     dsts;
1979   USB_OTG_PCGCCTL_TypeDef  power;
1980 
1981   if (pdev->dev.DevRemoteWakeup)
1982   {
1983     dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
1984     if(dsts.b.suspsts == 1)
1985     {
1986       if(pdev->cfg.low_power)
1987       {
1988         /* un-gate USB Core clock */
1989         power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL);
1990         power.b.gatehclk = 0;
1991         power.b.stoppclk = 0;
1992         USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
1993       }
1994       /* active Remote wakeup signaling */
1995       dctl.d32 = 0;
1996       dctl.b.rmtwkupsig = 1;
1997       USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32);
1998       USB_OTG_BSP_mDelay(5);
1999       USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
2000     }
2001   }
2002 }
2003 
2004 
2005 /**
2006 * @brief  USB_OTG_UngateClock : active USB Core clock
2007 * @param  None
2008 * @retval : None
2009 */
USB_OTG_UngateClock(USB_OTG_CORE_HANDLE * pdev)2010 void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
2011 {
2012   if(pdev->cfg.low_power)
2013   {
2014 
2015     USB_OTG_DSTS_TypeDef     dsts;
2016     USB_OTG_PCGCCTL_TypeDef  power;
2017 
2018     dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
2019 
2020     if(dsts.b.suspsts == 1)
2021     {
2022       /* un-gate USB Core clock */
2023       power.d32 = USB_OTG_READ_REG32(pdev->regs.PCGCCTL);
2024       power.b.gatehclk = 0;
2025       power.b.stoppclk = 0;
2026       USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
2027 
2028     }
2029   }
2030 }
2031 
2032 /**
2033 * @brief  Stop the device and clean up fifo's
2034 * @param  None
2035 * @retval : None
2036 */
USB_OTG_StopDevice(USB_OTG_CORE_HANDLE * pdev)2037 void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev)
2038 {
2039   uint32_t i;
2040 
2041   pdev->dev.device_status = 1;
2042 
2043   for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
2044   {
2045     USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
2046     USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
2047   }
2048 
2049   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
2050   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
2051   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
2052   USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
2053 
2054   /* Flush the FIFO */
2055   USB_OTG_FlushRxFifo(pdev);
2056   USB_OTG_FlushTxFifo(pdev ,  0x10 );
2057 }
2058 
2059 /**
2060 * @brief  returns the EP Status
2061 * @param  pdev : Selected device
2062 *         ep : endpoint structure
2063 * @retval : EP status
2064 */
2065 
USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep)2066 uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep)
2067 {
2068   USB_OTG_DEPCTL_TypeDef  depctl;
2069   __IO uint32_t *depctl_addr;
2070   uint32_t Status = 0;
2071 
2072   depctl.d32 = 0;
2073   if (ep->is_in == 1)
2074   {
2075     depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
2076     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2077 
2078     if (depctl.b.stall == 1)
2079       Status = USB_OTG_EP_TX_STALL;
2080     else if (depctl.b.naksts == 1)
2081       Status = USB_OTG_EP_TX_NAK;
2082     else
2083       Status = USB_OTG_EP_TX_VALID;
2084 
2085   }
2086   else
2087   {
2088     depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
2089     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2090     if (depctl.b.stall == 1)
2091       Status = USB_OTG_EP_RX_STALL;
2092     else if (depctl.b.naksts == 1)
2093       Status = USB_OTG_EP_RX_NAK;
2094     else
2095       Status = USB_OTG_EP_RX_VALID;
2096   }
2097 
2098   /* Return the current status */
2099   return Status;
2100 }
2101 
2102 /**
2103 * @brief  Set the EP Status
2104 * @param  pdev : Selected device
2105 *         Status : new Status
2106 *         ep : EP structure
2107 * @retval : None
2108 */
USB_OTG_SetEPStatus(USB_OTG_CORE_HANDLE * pdev,USB_OTG_EP * ep,uint32_t Status)2109 void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status)
2110 {
2111   USB_OTG_DEPCTL_TypeDef  depctl;
2112   __IO uint32_t *depctl_addr;
2113 
2114   depctl.d32 = 0;
2115 
2116   /* Process for IN endpoint */
2117   if (ep->is_in == 1)
2118   {
2119     depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
2120     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2121 
2122     if (Status == USB_OTG_EP_TX_STALL)
2123     {
2124       USB_OTG_EPSetStall(pdev, ep); return;
2125     }
2126     else if (Status == USB_OTG_EP_TX_NAK)
2127       depctl.b.snak = 1;
2128     else if (Status == USB_OTG_EP_TX_VALID)
2129     {
2130       if (depctl.b.stall == 1)
2131       {
2132         ep->even_odd_frame = 0;
2133         USB_OTG_EPClearStall(pdev, ep);
2134         return;
2135       }
2136       depctl.b.cnak = 1;
2137       depctl.b.usbactep = 1;
2138       depctl.b.epena = 1;
2139     }
2140     else if (Status == USB_OTG_EP_TX_DIS)
2141       depctl.b.usbactep = 0;
2142   }
2143   else /* Process for OUT endpoint */
2144   {
2145     depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
2146     depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
2147 
2148     if (Status == USB_OTG_EP_RX_STALL)  {
2149       depctl.b.stall = 1;
2150     }
2151     else if (Status == USB_OTG_EP_RX_NAK)
2152       depctl.b.snak = 1;
2153     else if (Status == USB_OTG_EP_RX_VALID)
2154     {
2155       if (depctl.b.stall == 1)
2156       {
2157         ep->even_odd_frame = 0;
2158         USB_OTG_EPClearStall(pdev, ep);
2159         return;
2160       }
2161       depctl.b.cnak = 1;
2162       depctl.b.usbactep = 1;
2163       depctl.b.epena = 1;
2164     }
2165     else if (Status == USB_OTG_EP_RX_DIS)
2166     {
2167       depctl.b.usbactep = 0;
2168     }
2169   }
2170 
2171   USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
2172 }
2173 
2174 #endif
2175 /**
2176 * @}
2177 */
2178 
2179 /**
2180 * @}
2181 */
2182 
2183 /**
2184 * @}
2185 */
2186 
2187 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
2188