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Searched defs:UVD_POWER_STATUS__UVD_PG_MODE_MASK (Results 1 – 24 of 24) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h37 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
H A Duvd_6_0_sh_mask.h917 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h37 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
H A Duvd_6_0_sh_mask.h917 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h37 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h929 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
H A Duvd_6_0_sh_mask.h917 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h1521 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h1521 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_5_sh_mask.h1521 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1518 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2959 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2055 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK … macro