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Searched defs:UVD_SUVD_CGC_GATE__SDB_HEVC_MASK (Results 1 – 24 of 24) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h238 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Duvd_5_0_sh_mask.h747 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
H A Duvd_6_0_sh_mask.h749 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h238 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Duvd_5_0_sh_mask.h747 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
H A Duvd_6_0_sh_mask.h749 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h238 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Duvd_5_0_sh_mask.h747 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
H A Duvd_6_0_sh_mask.h749 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h466 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_5_sh_mask.h2095 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3221 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3766 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2831 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h466 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_5_sh_mask.h2095 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3221 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3766 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2831 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h466 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_5_sh_mask.h2095 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3221 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3766 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2831 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK … macro