1 /* 2 * COPYRIGHT: GPL - See COPYING in the top level directory 3 * PROJECT: ReactOS Virtual DOS Machine 4 * FILE: subsystems/mvdm/ntvdm/hardware/video/svga.h 5 * PURPOSE: SuperVGA hardware emulation (Cirrus Logic CL-GD5434 compatible) 6 * PROGRAMMERS: Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org> 7 */ 8 9 #ifndef _SVGA_H_ 10 #define _SVGA_H_ 11 12 /* DEFINES ********************************************************************/ 13 14 #define VGA_NUM_BANKS 4 15 #define VGA_BANK_SIZE 0x10000 16 #define VGA_MAX_COLORS 256 17 #define VGA_PALETTE_SIZE (VGA_MAX_COLORS * 3) 18 #define VGA_BITMAP_INFO_SIZE (sizeof(BITMAPINFOHEADER) + 2 * (VGA_PALETTE_SIZE / 3)) 19 #define VGA_MINIMUM_WIDTH 400 20 #define VGA_MINIMUM_HEIGHT 300 21 #define VGA_DAC_TO_COLOR(x) (((x) << 2) | ((x) >> 4)) 22 #define VGA_COLOR_TO_DAC(x) ((x) >> 2) 23 #define VGA_INTERLACE_HIGH_BIT (1 << 13) 24 #define VGA_FONT_BANK 2 25 #define VGA_FONT_CHARACTERS 256 26 #define VGA_MAX_FONT_HEIGHT 32 27 #define VGA_FONT_SIZE (VGA_FONT_CHARACTERS * VGA_MAX_FONT_HEIGHT) 28 #define VGA_CLOCK_BASE 14318181 29 30 #define SVGA_IS_UNLOCKED (VgaSeqRegisters[SVGA_SEQ_UNLOCK_REG] == SVGA_SEQ_UNLOCKED) 31 #define SVGA_BANK_SIZE 0x100000 32 33 #define SVGA_SEQ_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_SEQ_MAX_REG : SVGA_SEQ_EXT_MODE_REG) 34 #define SVGA_CRTC_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_CRTC_MAX_REG : VGA_CRTC_MAX_REG) 35 #define SVGA_GC_MAX_UNLOCKED_REG (SVGA_IS_UNLOCKED ? SVGA_GC_MAX_REG : VGA_GC_MAX_REG) 36 37 /* Register I/O ports */ 38 39 #define VGA_MISC_READ 0x3CC 40 #define VGA_MISC_WRITE 0x3C2 41 42 #define VGA_INSTAT0_READ 0x3C2 43 44 #define VGA_INSTAT1_READ_MONO 0x3BA 45 #define VGA_INSTAT1_READ_COLOR 0x3DA 46 47 #define VGA_FEATURE_READ 0x3CA 48 #define VGA_FEATURE_WRITE_MONO 0x3BA 49 #define VGA_FEATURE_WRITE_COLOR 0x3DA 50 51 #define VGA_AC_INDEX 0x3C0 52 #define VGA_AC_WRITE 0x3C0 53 #define VGA_AC_READ 0x3C1 54 55 #define VGA_SEQ_INDEX 0x3C4 56 #define VGA_SEQ_DATA 0x3C5 57 58 #define VGA_DAC_MASK 0x3C6 59 #define VGA_DAC_READ_INDEX 0x3C7 60 #define VGA_DAC_WRITE_INDEX 0x3C8 61 #define VGA_DAC_DATA 0x3C9 62 63 #define VGA_CRTC_INDEX_MONO 0x3B4 64 #define VGA_CRTC_DATA_MONO 0x3B5 65 #define VGA_CRTC_INDEX_COLOR 0x3D4 66 #define VGA_CRTC_DATA_COLOR 0x3D5 67 68 #define VGA_GC_INDEX 0x3CE 69 #define VGA_GC_DATA 0x3CF 70 71 #define VGA_SEQ_INDEX_MASK 0x1F 72 #define VGA_GC_INDEX_MASK 0x3F 73 #define VGA_CRTC_INDEX_MASK 0x3F 74 75 76 77 // 78 // Miscellaneous and Status Registers 79 // 80 81 /* Miscellaneous register bits */ 82 #define VGA_MISC_COLOR (1 << 0) 83 #define VGA_MISC_RAM_ENABLED (1 << 1) 84 // #define VGA_MISC_CSEL1 (1 << 2) 85 // #define VGA_MISC_CSEL2 (1 << 3) 86 #define VGA_MISC_OE_PAGESEL (1 << 5) 87 #define VGA_MISC_HSYNCP (1 << 6) 88 #define VGA_MISC_VSYNCP (1 << 7) 89 90 /* Status register flags */ 91 #define VGA_STAT_DD (1 << 0) 92 #define VGA_STAT_VRETRACE (1 << 3) 93 94 95 // 96 // Sequencer Registers 97 // 98 99 /* Sequencer reset register bits */ 100 #define VGA_SEQ_RESET_AR (1 << 0) 101 #define VGA_SEQ_RESET_SR (1 << 1) 102 103 /* Sequencer clock register bits */ 104 #define VGA_SEQ_CLOCK_98DM (1 << 0) 105 #define VGA_SEQ_CLOCK_SLR (1 << 2) 106 #define VGA_SEQ_CLOCK_DCR (1 << 3) 107 #define VGA_SEQ_CLOCK_S4 (1 << 4) 108 #define VGA_SEQ_CLOCK_SD (1 << 5) 109 110 /* Sequencer memory register bits */ 111 #define VGA_SEQ_MEM_EXT (1 << 1) 112 #define VGA_SEQ_MEM_OE_DIS (1 << 2) 113 #define VGA_SEQ_MEM_C4 (1 << 3) 114 115 #define SVGA_SEQ_LOCKED 0x0F 116 #define SVGA_SEQ_UNLOCK_MASK 0x17 117 #define SVGA_SEQ_UNLOCKED 0x12 118 119 /* Sequencer extended mode register bits */ 120 #define SVGA_SEQ_EXT_MODE_HIGH_RES (1 << 0) 121 122 /* Sequencer extended control register bits */ 123 #define SVGA_SEQ_EXT_CONTROL_MMIO (1 << 2) 124 #define SVGA_SEQ_EXT_CONTROL_MMIO_HIGH (1 << 6) 125 126 /* MCLK register bits */ 127 #define SVGA_SEQ_MCLK_VCLK (1 << 6) 128 129 enum 130 { 131 VGA_SEQ_RESET_REG, 132 VGA_SEQ_CLOCK_REG, 133 VGA_SEQ_MASK_REG, 134 VGA_SEQ_CHAR_REG, 135 VGA_SEQ_MEM_REG, 136 VGA_SEQ_MAX_REG, 137 SVGA_SEQ_UNLOCK_REG, 138 SVGA_SEQ_EXT_MODE_REG, 139 SVGA_SEQ_EEPROM_REG, 140 SVGA_SEQ_SCRATCH_0_REG, 141 SVGA_SEQ_SCRATCH_1_REG, 142 SVGA_SEQ_VCLK0_NUMERATOR_REG, 143 SVGA_SEQ_VCLK1_NUMERATOR_REG, 144 SVGA_SEQ_VCLK2_NUMERATOR_REG, 145 SVGA_SEQ_VCLK3_NUMERATOR_REG, 146 SVGA_SEQ_DRAM_REG, 147 SVGA_SEQ_CURSOR_X_REG, 148 SVGA_SEQ_CURSOR_Y_REG, 149 SVGA_SEQ_CURSOR_ATTR_REG, 150 SVGA_SEQ_CURSOR_PATTERN_REG, 151 SVGA_SEQ_SCRATCH_2_REG, 152 SVGA_SEQ_SCRATCH_3_REG, 153 SVGA_SEQ_PERFORMANCE_REG, 154 SVGA_SEQ_EXT_CONTROL_REG, 155 SVGA_SEQ_SIG_GEN_CONTROL_REG, 156 SVGA_SEQ_SIG_GEN_RESULT_LOW_REG, 157 SVGA_SEQ_SIG_GEN_RESULT_HIGH_REG, 158 SVGA_SEQ_VCLK0_DENOMINATOR_REG, 159 SVGA_SEQ_VCLK1_DENOMINATOR_REG, 160 SVGA_SEQ_VCLK2_DENOMINATOR_REG, 161 SVGA_SEQ_VCLK3_DENOMINATOR_REG, 162 SVGA_SEQ_MCLK_REG, 163 SVGA_SEQ_MAX_REG 164 }; 165 166 // 167 // CRT Controller Registers 168 // 169 170 /* CRTC overflow register bits */ 171 #define VGA_CRTC_OVERFLOW_VT8 (1 << 0) 172 #define VGA_CRTC_OVERFLOW_VDE8 (1 << 1) 173 #define VGA_CRTC_OVERFLOW_VRS8 (1 << 2) 174 #define VGA_CRTC_OVERFLOW_SVB8 (1 << 3) 175 #define VGA_CRTC_OVERFLOW_LC8 (1 << 4) 176 #define VGA_CRTC_OVERFLOW_VT9 (1 << 5) 177 #define VGA_CRTC_OVERFLOW_VDE9 (1 << 6) 178 #define VGA_CRTC_OVERFLOW_VRS9 (1 << 7) 179 180 /* CRTC underline register bits */ 181 #define VGA_CRTC_UNDERLINE_DWORD (1 << 6) 182 183 /* CRTC max scanline register bits */ 184 #define VGA_CRTC_MAXSCANLINE_DOUBLE (1 << 7) 185 #define VGA_CRTC_MAXSCANLINE_LC9 (1 << 6) 186 187 /* CRTC mode control register bits */ 188 #define VGA_CRTC_MODE_CONTROL_WRAP (1 << 5) 189 #define VGA_CRTC_MODE_CONTROL_BYTE (1 << 6) 190 #define VGA_CRTC_MODE_CONTROL_SYNC (1 << 7) 191 192 /* CRTC extended display register bits */ 193 #define SVGA_CRTC_EXT_ADDR_BIT16 (1 << 0) 194 #define SVGA_CRTC_EXT_ADDR_WRAP (1 << 1) 195 #define SVGA_CRTC_EXT_ADDR_BITS1718 ((1 << 2) | (1 << 3)) 196 #define SVGA_CRTC_EXT_OFFSET_BIT8 (1 << 4) 197 198 /* CRTC extended overlay register bits */ 199 #define SVGA_CRTC_EXT_ADDR_BIT19 (1 << 7) 200 201 enum 202 { 203 VGA_CRTC_HORZ_TOTAL_REG, 204 VGA_CRTC_END_HORZ_DISP_REG, 205 VGA_CRTC_START_HORZ_BLANKING_REG, 206 VGA_CRTC_END_HORZ_BLANKING_REG, 207 VGA_CRTC_START_HORZ_RETRACE_REG, 208 VGA_CRTC_END_HORZ_RETRACE_REG, 209 VGA_CRTC_VERT_TOTAL_REG, 210 VGA_CRTC_OVERFLOW_REG, 211 VGA_CRTC_PRESET_ROW_SCAN_REG, 212 VGA_CRTC_MAX_SCAN_LINE_REG, 213 VGA_CRTC_CURSOR_START_REG, 214 VGA_CRTC_CURSOR_END_REG, 215 VGA_CRTC_START_ADDR_HIGH_REG, 216 VGA_CRTC_START_ADDR_LOW_REG, 217 VGA_CRTC_CURSOR_LOC_HIGH_REG, 218 VGA_CRTC_CURSOR_LOC_LOW_REG, 219 VGA_CRTC_START_VERT_RETRACE_REG, 220 VGA_CRTC_END_VERT_RETRACE_REG, 221 VGA_CRTC_VERT_DISP_END_REG, 222 VGA_CRTC_OFFSET_REG, 223 VGA_CRTC_UNDERLINE_REG, 224 VGA_CRTC_START_VERT_BLANKING_REG, 225 VGA_CRTC_END_VERT_BLANKING_REG, 226 VGA_CRTC_MODE_CONTROL_REG, 227 VGA_CRTC_LINE_COMPARE_REG, 228 VGA_CRTC_MAX_REG, 229 SVGA_CRTC_INTERLACE_END_REG = VGA_CRTC_MAX_REG, 230 SVGA_CRTC_MISC_CONTROL_REG, 231 SVGA_CRTC_EXT_DISPLAY_REG, 232 SVGA_CRTC_SYNC_ADJUST_REG, 233 SVGA_CRTC_OVERLAY_REG, 234 SVGA_CRTC_UNUSED0_REG, 235 SVGA_CRTC_UNUSED1_REG, 236 SVGA_CRTC_UNUSED2_REG, 237 SVGA_CRTC_UNUSED3_REG, 238 SVGA_CRTC_UNUSED4_REG, 239 SVGA_CRTC_UNUSED5_REG, 240 SVGA_CRTC_UNUSED6_REG, 241 SVGA_CRTC_PART_STATUS_REG, 242 SVGA_CRTC_UNUSED7_REG, 243 SVGA_CRTC_ID_REG, 244 SVGA_CRTC_MAX_REG 245 }; 246 247 248 // 249 // Graphics Controller Registers 250 // 251 252 /* Graphics controller mode register bits */ 253 #define VGA_GC_MODE_READ (1 << 3) 254 #define VGA_GC_MODE_OE (1 << 4) 255 #define VGA_GC_MODE_SHIFTREG (1 << 5) 256 #define VGA_GC_MODE_SHIFT256 (1 << 6) 257 258 /* Graphics controller miscellaneous register bits */ 259 #define VGA_GC_MISC_NOALPHA (1 << 0) 260 #define VGA_GC_MISC_OE (1 << 1) 261 262 /* Graphics controller extended mode register bits */ 263 #define SVGA_GC_EXT_MODE_WND_B (1 << 0) 264 #define SVGA_GC_EXT_MODE_GRAN (1 << 5) 265 266 enum 267 { 268 VGA_GC_RESET_REG, 269 VGA_GC_ENABLE_RESET_REG, 270 VGA_GC_COLOR_COMPARE_REG, 271 VGA_GC_ROTATE_REG, 272 VGA_GC_READ_MAP_SEL_REG, 273 VGA_GC_MODE_REG, 274 VGA_GC_MISC_REG, 275 VGA_GC_COLOR_IGNORE_REG, 276 VGA_GC_BITMASK_REG, 277 VGA_GC_MAX_REG, 278 SVGA_GC_OFFSET_0_REG = VGA_GC_MAX_REG, 279 SVGA_GC_OFFSET_1_REG, 280 SVGA_GC_EXT_MODE_REG, 281 SVGA_GC_COLOR_COMPARE_REG, 282 SVGA_GC_BITMASK_REG, 283 SVGA_GC_POWER_MANAGEMENT_REG, 284 SVGA_GC_UNUSED0_REG, 285 SVGA_GC_BACKGROUND_1_REG, 286 SVGA_GC_FOREGROUND_1_REG, 287 SVGA_GC_BACKGROUND_2_REG, 288 SVGA_GC_FOREGROUND_2_REG, 289 SVGA_GC_BACKGROUND_3_REG, 290 SVGA_GC_FOREGROUND_3_REG, 291 SVGA_GC_UNUSED1_REG, 292 SVGA_GC_UNUSED2_REG, 293 SVGA_GC_UNUSED3_REG, 294 SVGA_GC_UNUSED4_REG, 295 SVGA_GC_UNUSED5_REG, 296 SVGA_GC_UNUSED6_REG, 297 SVGA_GC_UNUSED7_REG, 298 SVGA_GC_UNUSED8_REG, 299 SVGA_GC_UNUSED9_REG, 300 SVGA_GC_UNUSED10_REG, 301 SVGA_GC_BLT_WIDTH_LOW_REG, 302 SVGA_GC_BLT_WIDTH_HIGH_REG, 303 SVGA_GC_BLT_HEIGHT_LOW_REG, 304 SVGA_GC_BLT_HEIGHT_HIGH_REG, 305 SVGA_GC_BLT_DEST_PITCH_LOW_REG, 306 SVGA_GC_BLT_DEST_PITCH_HIGH_REG, 307 SVGA_GC_BLT_SRC_PITCH_LOW_REG, 308 SVGA_GC_BLT_SRC_PITCH_HIGH_REG, 309 SVGA_GC_BLT_DEST_START_0_REG, 310 SVGA_GC_BLT_DEST_START_1_REG, 311 SVGA_GC_BLT_DEST_START_2_REG, 312 SVGA_GC_UNUSED11_REG, 313 SVGA_GC_BLT_SRC_START_0_REG, 314 SVGA_GC_BLT_SRC_START_1_REG, 315 SVGA_GC_BLT_SRC_START_2_REG, 316 SVGA_GC_BLT_DEST_MASK_REG, 317 SVGA_GC_BLT_MODE_REG, 318 SVGA_GC_BLT_STATUS_REG, 319 SVGA_GC_BLT_ROP_REG, 320 SVGA_GC_BLT_EXT_MODE_REG, 321 SVGA_GC_MAX_REG 322 }; 323 324 325 // 326 // Attribute Controller Registers 327 // They are a relinquish of the CGA/EGA era. 328 // 329 330 /* AC mode control register bits */ 331 #define VGA_AC_CONTROL_ATGE (1 << 0) 332 #define VGA_AC_CONTROL_MONO (1 << 1) 333 #define VGA_AC_CONTROL_LGE (1 << 2) 334 #define VGA_AC_CONTROL_BLINK (1 << 3) 335 #define VGA_AC_CONTROL_PPM (1 << 5) 336 #define VGA_AC_CONTROL_8BIT (1 << 6) 337 #define VGA_AC_CONTROL_P54S (1 << 7) 338 339 enum 340 { 341 VGA_AC_PAL_0_REG, 342 VGA_AC_PAL_1_REG, 343 VGA_AC_PAL_2_REG, 344 VGA_AC_PAL_3_REG, 345 VGA_AC_PAL_4_REG, 346 VGA_AC_PAL_5_REG, 347 VGA_AC_PAL_6_REG, 348 VGA_AC_PAL_7_REG, 349 VGA_AC_PAL_8_REG, 350 VGA_AC_PAL_9_REG, 351 VGA_AC_PAL_A_REG, 352 VGA_AC_PAL_B_REG, 353 VGA_AC_PAL_C_REG, 354 VGA_AC_PAL_D_REG, 355 VGA_AC_PAL_E_REG, 356 VGA_AC_PAL_F_REG, 357 VGA_AC_CONTROL_REG, 358 VGA_AC_OVERSCAN_REG, 359 VGA_AC_COLOR_PLANE_REG, 360 VGA_AC_HORZ_PANNING_REG, 361 VGA_AC_COLOR_SEL_REG, 362 VGA_AC_MAX_REG 363 }; 364 365 366 typedef struct _VGA_REGISTERS 367 { 368 UCHAR Misc; 369 UCHAR Sequencer[VGA_SEQ_MAX_REG]; 370 UCHAR CRT[VGA_CRTC_MAX_REG]; 371 UCHAR Graphics[VGA_GC_MAX_REG]; 372 UCHAR Attribute[VGA_AC_MAX_REG]; 373 } VGA_REGISTERS, *PVGA_REGISTERS; 374 375 typedef struct _SVGA_REGISTERS 376 { 377 UCHAR Misc; 378 UCHAR Hidden; 379 UCHAR Sequencer[SVGA_SEQ_MAX_REG]; 380 UCHAR CRT[SVGA_CRTC_MAX_REG]; 381 UCHAR Graphics[SVGA_GC_MAX_REG]; 382 UCHAR Attribute[VGA_AC_MAX_REG]; 383 } SVGA_REGISTERS, *PSVGA_REGISTERS; 384 385 386 /* 387 * Console interface -- VGA-mode-agnostic 388 */ 389 // WARNING! This structure *MUST BE* in sync with the one in consrv/include/conio_winsrv.h 390 typedef struct _CHAR_CELL 391 { 392 CHAR Char; 393 BYTE Attributes; 394 } CHAR_CELL, *PCHAR_CELL; 395 C_ASSERT(sizeof(CHAR_CELL) == 2); 396 397 /* FUNCTIONS ******************************************************************/ 398 399 COORD VgaGetDisplayResolution(VOID); 400 VOID VgaRefreshDisplay(VOID); 401 VOID FASTCALL VgaReadMemory(ULONG Address, PVOID Buffer, ULONG Size); 402 BOOLEAN FASTCALL VgaWriteMemory(ULONG Address, PVOID Buffer, ULONG Size); 403 VOID VgaWriteTextModeFont(UINT FontNumber, CONST UCHAR *FontData, UINT Height); 404 VOID VgaClearMemory(VOID); 405 406 BOOLEAN VgaInitialize(HANDLE TextHandle); 407 VOID VgaCleanup(VOID); 408 409 #endif /* _SVGA_H_ */ 410