1 /* $NetBSD: if_vge.c,v 1.86 2022/09/24 18:12:43 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.86 2022/09/24 18:12:43 thorpej Exp $");
39
40 /*
41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
42 *
43 * Written by Bill Paul <wpaul@windriver.com>
44 * Senior Networking Software Engineer
45 * Wind River Systems
46 */
47
48 /*
49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that
50 * combines a tri-speed ethernet MAC and PHY, with the following
51 * features:
52 *
53 * o Jumbo frame support up to 16K
54 * o Transmit and receive flow control
55 * o IPv4 checksum offload
56 * o VLAN tag insertion and stripping
57 * o TCP large send
58 * o 64-bit multicast hash table filter
59 * o 64 entry CAM filter
60 * o 16K RX FIFO and 48K TX FIFO memory
61 * o Interrupt moderation
62 *
63 * The VT6122 supports up to four transmit DMA queues. The descriptors
64 * in the transmit ring can address up to 7 data fragments; frames which
65 * span more than 7 data buffers must be coalesced, but in general the
66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
67 * long. The receive descriptors address only a single buffer.
68 *
69 * There are two peculiar design issues with the VT6122. One is that
70 * receive data buffers must be aligned on a 32-bit boundary. This is
71 * not a problem where the VT6122 is used as a LOM device in x86-based
72 * systems, but on architectures that generate unaligned access traps, we
73 * have to do some copying.
74 *
75 * The other issue has to do with the way 64-bit addresses are handled.
76 * The DMA descriptors only allow you to specify 48 bits of addressing
77 * information. The remaining 16 bits are specified using one of the
78 * I/O registers (VGE_DATABUF_HIADDR). If you only have a 32-bit system,
79 * then this isn't an issue, but if you have a 64-bit system and more than
80 * 4GB of memory, you must have to make sure your network data buffers reside
81 * in the same 48-bit 'segment.'
82 *
83 * Furthermore, the descriptors must also all reside within the same 32-bit
84 * 'segment' (see VGE_TXDESC_HIADDR).
85 *
86 * Special thanks to Ryan Fu at VIA Networking for providing documentation
87 * and sample NICs for testing.
88 */
89
90
91 #include <sys/param.h>
92 #include <sys/endian.h>
93 #include <sys/systm.h>
94 #include <sys/device.h>
95 #include <sys/sockio.h>
96 #include <sys/mbuf.h>
97 #include <sys/kernel.h>
98 #include <sys/socket.h>
99
100 #include <net/if.h>
101 #include <net/if_arp.h>
102 #include <net/if_ether.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105
106 #include <net/bpf.h>
107
108 #include <sys/bus.h>
109
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
112
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
115 #include <dev/pci/pcidevs.h>
116
117 #include <dev/pci/if_vgereg.h>
118
119 #define VGE_IFQ_MAXLEN 64
120
121 #define VGE_RING_ALIGN 256
122
123 #define VGE_NTXDESC 256
124 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1)
125 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK)
126 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK)
127
128 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */
129 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1)
130 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK)
131 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK)
132
133 #define VGE_ADDR_LO(y) BUS_ADDR_LO32(y)
134 #define VGE_ADDR_HI(y) BUS_ADDR_HI32(y)
135 #define VGE_BUFLEN(y) ((y) & 0x7FFF)
136 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
137
138 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */
139
140 /*
141 * Mbuf adjust factor to force 32-bit alignment of IP header.
142 * Drivers should pad ETHER_ALIGN bytes when setting up a
143 * RX mbuf so the upper layers get the IP header properly aligned
144 * past the 14-byte Ethernet header.
145 *
146 * See also comment in vge_encap().
147 */
148
149 #ifdef __NO_STRICT_ALIGNMENT
150 #define VGE_RX_BUFSIZE MCLBYTES
151 #else
152 #define VGE_RX_PAD sizeof(uint32_t)
153 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD)
154 #endif
155
156 /*
157 * Control structures are DMA'd to the vge chip. We allocate them in
158 * a single clump that maps to a single DMA segment to make several things
159 * easier.
160 */
161 struct vge_control_data {
162 /* TX descriptors */
163 struct vge_txdesc vcd_txdescs[VGE_NTXDESC];
164 /* RX descriptors */
165 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC];
166 /* dummy data for TX padding */
167 uint8_t vcd_pad[ETHER_PAD_LEN];
168 };
169
170 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x)
171 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)])
172 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)])
173 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0])
174
175 /*
176 * Software state for TX jobs.
177 */
178 struct vge_txsoft {
179 struct mbuf *txs_mbuf; /* head of our mbuf chain */
180 bus_dmamap_t txs_dmamap; /* our DMA map */
181 };
182
183 /*
184 * Software state for RX jobs.
185 */
186 struct vge_rxsoft {
187 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
188 bus_dmamap_t rxs_dmamap; /* our DMA map */
189 };
190
191
192 struct vge_softc {
193 device_t sc_dev;
194
195 bus_space_tag_t sc_bst; /* bus space tag */
196 bus_space_handle_t sc_bsh; /* bus space handle */
197 bus_dma_tag_t sc_dmat;
198
199 struct ethercom sc_ethercom; /* interface info */
200 uint8_t sc_eaddr[ETHER_ADDR_LEN];
201
202 void *sc_intrhand;
203 struct mii_data sc_mii;
204 uint8_t sc_type;
205 u_short sc_if_flags;
206 int sc_link;
207 int sc_camidx;
208 callout_t sc_timeout;
209
210 bus_dmamap_t sc_cddmamap;
211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
212
213 struct vge_txsoft sc_txsoft[VGE_NTXDESC];
214 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC];
215 struct vge_control_data *sc_control_data;
216 #define sc_txdescs sc_control_data->vcd_txdescs
217 #define sc_rxdescs sc_control_data->vcd_rxdescs
218
219 int sc_tx_prodidx;
220 int sc_tx_considx;
221 int sc_tx_free;
222
223 struct mbuf *sc_rx_mhead;
224 struct mbuf *sc_rx_mtail;
225 int sc_rx_prodidx;
226 int sc_rx_consumed;
227
228 int sc_suspended; /* 0 = normal 1 = suspended */
229 uint32_t sc_saved_maps[5]; /* pci data */
230 uint32_t sc_saved_biosaddr;
231 uint8_t sc_saved_intline;
232 uint8_t sc_saved_cachelnsz;
233 uint8_t sc_saved_lattimer;
234 };
235
236 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x))
237 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x))
238 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF())
239
240 #define VGE_TXDESCSYNC(sc, idx, ops) \
241 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \
242 VGE_CDTXOFF(idx), \
243 offsetof(struct vge_txdesc, td_frag[0]), \
244 (ops))
245 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \
246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
247 VGE_CDTXOFF(idx) + \
248 offsetof(struct vge_txdesc, td_frag[0]), \
249 sizeof(struct vge_txfrag) * (nsegs), \
250 (ops))
251 #define VGE_RXDESCSYNC(sc, idx, ops) \
252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
253 VGE_CDRXOFF(idx), \
254 sizeof(struct vge_rxdesc), \
255 (ops))
256
257 /*
258 * register space access macros
259 */
260 #define CSR_WRITE_4(sc, reg, val) \
261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
262 #define CSR_WRITE_2(sc, reg, val) \
263 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
264 #define CSR_WRITE_1(sc, reg, val) \
265 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
266
267 #define CSR_READ_4(sc, reg) \
268 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
269 #define CSR_READ_2(sc, reg) \
270 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
271 #define CSR_READ_1(sc, reg) \
272 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg))
273
274 #define CSR_SETBIT_1(sc, reg, x) \
275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
276 #define CSR_SETBIT_2(sc, reg, x) \
277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
278 #define CSR_SETBIT_4(sc, reg, x) \
279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))
280
281 #define CSR_CLRBIT_1(sc, reg, x) \
282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
283 #define CSR_CLRBIT_2(sc, reg, x) \
284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
285 #define CSR_CLRBIT_4(sc, reg, x) \
286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))
287
288 #define VGE_TIMEOUT 10000
289
290 #define VGE_PCI_LOIO 0x10
291 #define VGE_PCI_LOMEM 0x14
292
293 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t);
294 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t);
295
296 static int vge_ifflags_cb(struct ethercom *);
297
298 static int vge_match(device_t, cfdata_t, void *);
299 static void vge_attach(device_t, device_t, void *);
300
301 static int vge_encap(struct vge_softc *, struct mbuf *, int);
302
303 static int vge_allocmem(struct vge_softc *);
304 static int vge_newbuf(struct vge_softc *, int, struct mbuf *);
305 #ifndef __NO_STRICT_ALIGNMENT
306 static inline void vge_fixup_rx(struct mbuf *);
307 #endif
308 static void vge_rxeof(struct vge_softc *);
309 static void vge_txeof(struct vge_softc *);
310 static int vge_intr(void *);
311 static void vge_tick(void *);
312 static void vge_start(struct ifnet *);
313 static int vge_ioctl(struct ifnet *, u_long, void *);
314 static int vge_init(struct ifnet *);
315 static void vge_stop(struct ifnet *, int);
316 static void vge_watchdog(struct ifnet *);
317 #if VGE_POWER_MANAGEMENT
318 static int vge_suspend(device_t);
319 static int vge_resume(device_t);
320 #endif
321 static bool vge_shutdown(device_t, int);
322
323 static uint16_t vge_read_eeprom(struct vge_softc *, int);
324
325 static void vge_miipoll_start(struct vge_softc *);
326 static void vge_miipoll_stop(struct vge_softc *);
327 static int vge_miibus_readreg(device_t, int, int, uint16_t *);
328 static int vge_miibus_writereg(device_t, int, int, uint16_t);
329 static void vge_miibus_statchg(struct ifnet *);
330
331 static void vge_cam_clear(struct vge_softc *);
332 static int vge_cam_set(struct vge_softc *, uint8_t *);
333 static void vge_clrwol(struct vge_softc *);
334 static void vge_setmulti(struct vge_softc *);
335 static void vge_reset(struct vge_softc *);
336
337 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc),
338 vge_match, vge_attach, NULL, NULL);
339
340 static inline void
vge_set_txaddr(struct vge_txfrag * f,bus_addr_t daddr)341 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr)
342 {
343
344 f->tf_addrlo = htole32((uint32_t)daddr);
345 if (sizeof(bus_addr_t) == sizeof(uint64_t))
346 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF);
347 else
348 f->tf_addrhi = 0;
349 }
350
351 static inline void
vge_set_rxaddr(struct vge_rxdesc * rxd,bus_addr_t daddr)352 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr)
353 {
354
355 rxd->rd_addrlo = htole32((uint32_t)daddr);
356 if (sizeof(bus_addr_t) == sizeof(uint64_t))
357 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF);
358 else
359 rxd->rd_addrhi = 0;
360 }
361
362 /*
363 * Read a word of data stored in the EEPROM at address 'addr.'
364 */
365 static uint16_t
vge_read_eeprom(struct vge_softc * sc,int addr)366 vge_read_eeprom(struct vge_softc *sc, int addr)
367 {
368 int i;
369 uint16_t word = 0;
370
371 /*
372 * Enter EEPROM embedded programming mode. In order to
373 * access the EEPROM at all, we first have to set the
374 * EELOAD bit in the CHIPCFG2 register.
375 */
376 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
377 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/);
378
379 /* Select the address of the word we want to read */
380 CSR_WRITE_1(sc, VGE_EEADDR, addr);
381
382 /* Issue read command */
383 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
384
385 /* Wait for the done bit to be set. */
386 for (i = 0; i < VGE_TIMEOUT; i++) {
387 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
388 break;
389 }
390
391 if (i == VGE_TIMEOUT) {
392 printf("%s: EEPROM read timed out\n", device_xname(sc->sc_dev));
393 return 0;
394 }
395
396 /* Read the result */
397 word = CSR_READ_2(sc, VGE_EERDDAT);
398
399 /* Turn off EEPROM access mode. */
400 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/);
401 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
402
403 return word;
404 }
405
406 static void
vge_miipoll_stop(struct vge_softc * sc)407 vge_miipoll_stop(struct vge_softc *sc)
408 {
409 int i;
410
411 CSR_WRITE_1(sc, VGE_MIICMD, 0);
412
413 for (i = 0; i < VGE_TIMEOUT; i++) {
414 DELAY(1);
415 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
416 break;
417 }
418
419 if (i == VGE_TIMEOUT) {
420 printf("%s: failed to idle MII autopoll\n",
421 device_xname(sc->sc_dev));
422 }
423 }
424
425 static void
vge_miipoll_start(struct vge_softc * sc)426 vge_miipoll_start(struct vge_softc *sc)
427 {
428 int i;
429
430 /* First, make sure we're idle. */
431
432 CSR_WRITE_1(sc, VGE_MIICMD, 0);
433 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
434
435 for (i = 0; i < VGE_TIMEOUT; i++) {
436 DELAY(1);
437 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
438 break;
439 }
440
441 if (i == VGE_TIMEOUT) {
442 printf("%s: failed to idle MII autopoll\n",
443 device_xname(sc->sc_dev));
444 return;
445 }
446
447 /* Now enable auto poll mode. */
448
449 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
450
451 /* And make sure it started. */
452
453 for (i = 0; i < VGE_TIMEOUT; i++) {
454 DELAY(1);
455 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
456 break;
457 }
458
459 if (i == VGE_TIMEOUT) {
460 printf("%s: failed to start MII autopoll\n",
461 device_xname(sc->sc_dev));
462 }
463 }
464
465 static int
vge_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)466 vge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
467 {
468 struct vge_softc *sc;
469 int i, s;
470 int rv = 0;
471
472 sc = device_private(dev);
473 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
474 return -1;
475
476 s = splnet();
477 vge_miipoll_stop(sc);
478
479 /* Specify the register we want to read. */
480 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
481
482 /* Issue read command. */
483 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
484
485 /* Wait for the read command bit to self-clear. */
486 for (i = 0; i < VGE_TIMEOUT; i++) {
487 DELAY(1);
488 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
489 break;
490 }
491
492 if (i == VGE_TIMEOUT) {
493 printf("%s: MII read timed out\n", device_xname(sc->sc_dev));
494 rv = ETIMEDOUT;
495 } else
496 *val = CSR_READ_2(sc, VGE_MIIDATA);
497
498 vge_miipoll_start(sc);
499 splx(s);
500
501 return rv;
502 }
503
504 static int
vge_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)505 vge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
506 {
507 struct vge_softc *sc;
508 int i, s, rv = 0;
509
510 sc = device_private(dev);
511 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
512 return -1;
513
514 s = splnet();
515 vge_miipoll_stop(sc);
516
517 /* Specify the register we want to write. */
518 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
519
520 /* Specify the data we want to write. */
521 CSR_WRITE_2(sc, VGE_MIIDATA, val);
522
523 /* Issue write command. */
524 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
525
526 /* Wait for the write command bit to self-clear. */
527 for (i = 0; i < VGE_TIMEOUT; i++) {
528 DELAY(1);
529 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
530 break;
531 }
532
533 if (i == VGE_TIMEOUT) {
534 printf("%s: MII write timed out\n", device_xname(sc->sc_dev));
535 rv = ETIMEDOUT;
536 }
537
538 vge_miipoll_start(sc);
539 splx(s);
540
541 return rv;
542 }
543
544 static void
vge_cam_clear(struct vge_softc * sc)545 vge_cam_clear(struct vge_softc *sc)
546 {
547 int i;
548
549 /*
550 * Turn off all the mask bits. This tells the chip
551 * that none of the entries in the CAM filter are valid.
552 * desired entries will be enabled as we fill the filter in.
553 */
554
555 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
556 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
557 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
558 for (i = 0; i < 8; i++)
559 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
560
561 /* Clear the VLAN filter too. */
562
563 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_AVSEL);
564 for (i = 0; i < 8; i++)
565 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
566
567 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
568 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
569 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
570
571 sc->sc_camidx = 0;
572 }
573
574 static int
vge_cam_set(struct vge_softc * sc,uint8_t * addr)575 vge_cam_set(struct vge_softc *sc, uint8_t *addr)
576 {
577 int i, error;
578
579 error = 0;
580
581 if (sc->sc_camidx == VGE_CAM_MAXADDRS)
582 return ENOSPC;
583
584 /* Select the CAM data page. */
585 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
586 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
587
588 /* Set the filter entry we want to update and enable writing. */
589 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx);
590
591 /* Write the address to the CAM registers */
592 for (i = 0; i < ETHER_ADDR_LEN; i++)
593 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
594
595 /* Issue a write command. */
596 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
597
598 /* Wake for it to clear. */
599 for (i = 0; i < VGE_TIMEOUT; i++) {
600 DELAY(1);
601 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
602 break;
603 }
604
605 if (i == VGE_TIMEOUT) {
606 printf("%s: setting CAM filter failed\n",
607 device_xname(sc->sc_dev));
608 error = EIO;
609 goto fail;
610 }
611
612 /* Select the CAM mask page. */
613 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
614 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
615
616 /* Set the mask bit that enables this filter. */
617 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8),
618 1 << (sc->sc_camidx & 7));
619
620 sc->sc_camidx++;
621
622 fail:
623 /* Turn off access to CAM. */
624 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
625 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
626 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
627
628 return error;
629 }
630
631 /*
632 * Program the multicast filter. We use the 64-entry CAM filter
633 * for perfect filtering. If there's more than 64 multicast addresses,
634 * we use the hash filter instead.
635 */
636 static void
vge_setmulti(struct vge_softc * sc)637 vge_setmulti(struct vge_softc *sc)
638 {
639 struct ethercom *ec = &sc->sc_ethercom;
640 struct ifnet *ifp = &ec->ec_if;
641 int error;
642 uint32_t h, hashes[2] = { 0, 0 };
643 struct ether_multi *enm;
644 struct ether_multistep step;
645
646 error = 0;
647
648 /* First, zot all the multicast entries. */
649 vge_cam_clear(sc);
650 CSR_WRITE_4(sc, VGE_MAR0, 0);
651 CSR_WRITE_4(sc, VGE_MAR1, 0);
652 ifp->if_flags &= ~IFF_ALLMULTI;
653
654 /*
655 * If the user wants allmulti or promisc mode, enable reception
656 * of all multicast frames.
657 */
658 if (ifp->if_flags & IFF_PROMISC) {
659 allmulti:
660 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
661 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
662 ifp->if_flags |= IFF_ALLMULTI;
663 return;
664 }
665
666 /* Now program new ones */
667 ETHER_LOCK(ec);
668 ETHER_FIRST_MULTI(step, ec, enm);
669 while (enm != NULL) {
670 /*
671 * If multicast range, fall back to ALLMULTI.
672 */
673 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
674 ETHER_ADDR_LEN) != 0) {
675 ETHER_UNLOCK(ec);
676 goto allmulti;
677 }
678
679 error = vge_cam_set(sc, enm->enm_addrlo);
680 if (error)
681 break;
682
683 ETHER_NEXT_MULTI(step, enm);
684 }
685 ETHER_UNLOCK(ec);
686
687 /* If there were too many addresses, use the hash filter. */
688 if (error) {
689 vge_cam_clear(sc);
690
691 ETHER_LOCK(ec);
692 ETHER_FIRST_MULTI(step, ec, enm);
693 while (enm != NULL) {
694 /*
695 * If multicast range, fall back to ALLMULTI.
696 */
697 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
698 ETHER_ADDR_LEN) != 0) {
699 ETHER_UNLOCK(ec);
700 goto allmulti;
701 }
702
703 h = ether_crc32_be(enm->enm_addrlo,
704 ETHER_ADDR_LEN) >> 26;
705 hashes[h >> 5] |= 1 << (h & 0x1f);
706
707 ETHER_NEXT_MULTI(step, enm);
708 }
709 ETHER_UNLOCK(ec);
710
711 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]);
712 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]);
713 }
714 }
715
716 static void
vge_reset(struct vge_softc * sc)717 vge_reset(struct vge_softc *sc)
718 {
719 int i;
720
721 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
722
723 for (i = 0; i < VGE_TIMEOUT; i++) {
724 DELAY(5);
725 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
726 break;
727 }
728
729 if (i == VGE_TIMEOUT) {
730 printf("%s: soft reset timed out", device_xname(sc->sc_dev));
731 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
732 DELAY(2000);
733 }
734
735 DELAY(5000);
736
737 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
738
739 for (i = 0; i < VGE_TIMEOUT; i++) {
740 DELAY(5);
741 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
742 break;
743 }
744
745 if (i == VGE_TIMEOUT) {
746 printf("%s: EEPROM reload timed out\n",
747 device_xname(sc->sc_dev));
748 return;
749 }
750
751 /*
752 * On some machine, the first read data from EEPROM could be
753 * messed up, so read one dummy data here to avoid the mess.
754 */
755 (void)vge_read_eeprom(sc, 0);
756
757 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
758 }
759
760 /*
761 * Probe for a VIA gigabit chip. Check the PCI vendor and device
762 * IDs against our list and return a device name if we find a match.
763 */
764 static int
vge_match(device_t parent,cfdata_t match,void * aux)765 vge_match(device_t parent, cfdata_t match, void *aux)
766 {
767 struct pci_attach_args *pa = aux;
768
769 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH
770 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X)
771 return 1;
772
773 return 0;
774 }
775
776 static int
vge_allocmem(struct vge_softc * sc)777 vge_allocmem(struct vge_softc *sc)
778 {
779 int error;
780 int nseg;
781 int i;
782 bus_dma_segment_t seg;
783
784 /*
785 * Allocate memory for control data.
786 *
787 * NOTE: This must all fit within the same 4GB segment. The
788 * "boundary" argument to bus_dmamem_alloc() will end up as
789 * 4GB on 64-bit platforms and 0 ("no boundary constraint") on
790 * 32-bit platformds.
791 */
792
793 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data),
794 VGE_RING_ALIGN,
795 (bus_size_t)(1ULL << 32),
796 &seg, 1, &nseg, BUS_DMA_NOWAIT);
797 if (error) {
798 aprint_error_dev(sc->sc_dev,
799 "could not allocate control data dma memory\n");
800 goto fail_1;
801 }
802
803 /* Map the memory to kernel VA space */
804
805 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg,
806 sizeof(struct vge_control_data), (void **)&sc->sc_control_data,
807 BUS_DMA_NOWAIT);
808 if (error) {
809 aprint_error_dev(sc->sc_dev,
810 "could not map control data dma memory\n");
811 goto fail_2;
812 }
813 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data));
814
815 /*
816 * Create map for control data.
817 */
818 error = bus_dmamap_create(sc->sc_dmat,
819 sizeof(struct vge_control_data), 1,
820 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT,
821 &sc->sc_cddmamap);
822 if (error) {
823 aprint_error_dev(sc->sc_dev,
824 "could not create control data dmamap\n");
825 goto fail_3;
826 }
827
828 /* Load the map for the control data. */
829 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
830 sc->sc_control_data, sizeof(struct vge_control_data), NULL,
831 BUS_DMA_NOWAIT);
832 if (error) {
833 aprint_error_dev(sc->sc_dev,
834 "could not load control data dma memory\n");
835 goto fail_4;
836 }
837
838 /* Create DMA maps for TX buffers */
839
840 for (i = 0; i < VGE_NTXDESC; i++) {
841 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN,
842 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT,
843 &sc->sc_txsoft[i].txs_dmamap);
844 if (error) {
845 aprint_error_dev(sc->sc_dev,
846 "can't create DMA map for TX descs\n");
847 goto fail_5;
848 }
849 }
850
851 /* Create DMA maps for RX buffers */
852
853 for (i = 0; i < VGE_NRXDESC; i++) {
854 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
855 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
856 &sc->sc_rxsoft[i].rxs_dmamap);
857 if (error) {
858 aprint_error_dev(sc->sc_dev,
859 "can't create DMA map for RX descs\n");
860 goto fail_6;
861 }
862 sc->sc_rxsoft[i].rxs_mbuf = NULL;
863 }
864
865 return 0;
866
867 fail_6:
868 for (i = 0; i < VGE_NRXDESC; i++) {
869 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
870 bus_dmamap_destroy(sc->sc_dmat,
871 sc->sc_rxsoft[i].rxs_dmamap);
872 }
873 fail_5:
874 for (i = 0; i < VGE_NTXDESC; i++) {
875 if (sc->sc_txsoft[i].txs_dmamap != NULL)
876 bus_dmamap_destroy(sc->sc_dmat,
877 sc->sc_txsoft[i].txs_dmamap);
878 }
879 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
880 fail_4:
881 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
882 fail_3:
883 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
884 sizeof(struct vge_control_data));
885 fail_2:
886 bus_dmamem_free(sc->sc_dmat, &seg, nseg);
887 fail_1:
888 return ENOMEM;
889 }
890
891 /*
892 * Attach the interface. Allocate softc structures, do ifmedia
893 * setup and ethernet/BPF attach.
894 */
895 static void
vge_attach(device_t parent,device_t self,void * aux)896 vge_attach(device_t parent, device_t self, void *aux)
897 {
898 uint8_t *eaddr;
899 struct vge_softc *sc = device_private(self);
900 struct ifnet *ifp;
901 struct mii_data * const mii = &sc->sc_mii;
902 struct pci_attach_args *pa = aux;
903 pci_chipset_tag_t pc = pa->pa_pc;
904 const char *intrstr;
905 pci_intr_handle_t ih;
906 uint16_t val;
907 char intrbuf[PCI_INTRSTR_LEN];
908
909 sc->sc_dev = self;
910
911 pci_aprint_devinfo_fancy(pa, NULL, "VIA VT612X Gigabit Ethernet", 1);
912
913 /* Make sure bus-mastering is enabled */
914 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
915 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
916 PCI_COMMAND_MASTER_ENABLE);
917
918 /*
919 * Map control/status registers.
920 */
921 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
922 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) {
923 aprint_error_dev(self, "couldn't map memory\n");
924 return;
925 }
926
927 /*
928 * Map and establish our interrupt.
929 */
930 if (pci_intr_map(pa, &ih)) {
931 aprint_error_dev(self, "unable to map interrupt\n");
932 return;
933 }
934 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
935 sc->sc_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, vge_intr,
936 sc, device_xname(self));
937 if (sc->sc_intrhand == NULL) {
938 aprint_error_dev(self, "unable to establish interrupt");
939 if (intrstr != NULL)
940 aprint_error(" at %s", intrstr);
941 aprint_error("\n");
942 return;
943 }
944 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
945
946 /* Reset the adapter. */
947 vge_reset(sc);
948
949 /*
950 * Get station address from the EEPROM.
951 */
952 eaddr = sc->sc_eaddr;
953 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0);
954 eaddr[0] = val & 0xff;
955 eaddr[1] = val >> 8;
956 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1);
957 eaddr[2] = val & 0xff;
958 eaddr[3] = val >> 8;
959 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2);
960 eaddr[4] = val & 0xff;
961 eaddr[5] = val >> 8;
962
963 aprint_normal_dev(self, "Ethernet address %s\n",
964 ether_sprintf(eaddr));
965
966 /* Clear WOL and take hardware from powerdown. */
967 vge_clrwol(sc);
968
969 /*
970 * The hardware supports 64-bit DMA addresses, but it's a little
971 * complicated (see large comment about the hardware near the top
972 * of the file). TL;DR -- restrict ourselves to 48-bit.
973 */
974 if (pci_dma64_available(pa)) {
975 if (bus_dmatag_subregion(pa->pa_dmat64,
976 0,
977 (bus_addr_t)__MASK(48),
978 &sc->sc_dmat,
979 BUS_DMA_WAITOK) != 0) {
980 aprint_error_dev(self,
981 "WARNING: failed to restrict dma range,"
982 " falling back to parent bus dma range\n");
983 sc->sc_dmat = pa->pa_dmat64;
984 }
985 } else {
986 sc->sc_dmat = pa->pa_dmat;
987 }
988
989 if (vge_allocmem(sc) != 0)
990 return;
991
992 ifp = &sc->sc_ethercom.ec_if;
993 ifp->if_softc = sc;
994 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
995 ifp->if_mtu = ETHERMTU;
996 ifp->if_baudrate = IF_Gbps(1);
997 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
998 ifp->if_ioctl = vge_ioctl;
999 ifp->if_start = vge_start;
1000 ifp->if_init = vge_init;
1001 ifp->if_stop = vge_stop;
1002
1003 /*
1004 * We can support 802.1Q VLAN-sized frames and jumbo
1005 * Ethernet frames.
1006 */
1007 sc->sc_ethercom.ec_capabilities |=
1008 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU |
1009 ETHERCAP_VLAN_HWTAGGING;
1010 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
1011
1012 /*
1013 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
1014 */
1015 ifp->if_capabilities |=
1016 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1017 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1018 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
1019
1020 #ifdef DEVICE_POLLING
1021 #ifdef IFCAP_POLLING
1022 ifp->if_capabilities |= IFCAP_POLLING;
1023 #endif
1024 #endif
1025 ifp->if_watchdog = vge_watchdog;
1026 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(VGE_IFQ_MAXLEN, IFQ_MAXLEN));
1027 IFQ_SET_READY(&ifp->if_snd);
1028
1029 /*
1030 * Initialize our media structures and probe the MII.
1031 */
1032 mii->mii_ifp = ifp;
1033 mii->mii_readreg = vge_miibus_readreg;
1034 mii->mii_writereg = vge_miibus_writereg;
1035 mii->mii_statchg = vge_miibus_statchg;
1036
1037 sc->sc_ethercom.ec_mii = mii;
1038 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
1039 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
1040 MII_OFFSET_ANY, MIIF_DOPAUSE);
1041 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1042 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1043 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1044 } else
1045 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1046
1047 /*
1048 * Attach the interface.
1049 */
1050 if_attach(ifp);
1051 if_deferred_start_init(ifp, NULL);
1052 ether_ifattach(ifp, eaddr);
1053 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb);
1054
1055 callout_init(&sc->sc_timeout, 0);
1056 callout_setfunc(&sc->sc_timeout, vge_tick, sc);
1057
1058 /*
1059 * Make sure the interface is shutdown during reboot.
1060 */
1061 if (pmf_device_register1(self, NULL, NULL, vge_shutdown))
1062 pmf_class_network_register(self, ifp);
1063 else
1064 aprint_error_dev(self, "couldn't establish power handler\n");
1065 }
1066
1067 static int
vge_newbuf(struct vge_softc * sc,int idx,struct mbuf * m)1068 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m)
1069 {
1070 struct mbuf *m_new;
1071 struct vge_rxdesc *rxd;
1072 struct vge_rxsoft *rxs;
1073 bus_dmamap_t map;
1074 int i;
1075 #ifdef DIAGNOSTIC
1076 uint32_t rd_sts;
1077 #endif
1078
1079 m_new = NULL;
1080 if (m == NULL) {
1081 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1082 if (m_new == NULL)
1083 return ENOBUFS;
1084
1085 MCLGET(m_new, M_DONTWAIT);
1086 if ((m_new->m_flags & M_EXT) == 0) {
1087 m_freem(m_new);
1088 return ENOBUFS;
1089 }
1090
1091 m = m_new;
1092 } else
1093 m->m_data = m->m_ext.ext_buf;
1094
1095
1096 /*
1097 * This is part of an evil trick to deal with non-x86 platforms.
1098 * The VIA chip requires RX buffers to be aligned on 32-bit
1099 * boundaries, but that will hose non-x86 machines. To get around
1100 * this, we leave some empty space at the start of each buffer
1101 * and for non-x86 hosts, we copy the buffer back two bytes
1102 * to achieve word alignment. This is slightly more efficient
1103 * than allocating a new buffer, copying the contents, and
1104 * discarding the old buffer.
1105 */
1106 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE;
1107 #ifndef __NO_STRICT_ALIGNMENT
1108 m->m_data += VGE_RX_PAD;
1109 #endif
1110 rxs = &sc->sc_rxsoft[idx];
1111 map = rxs->rxs_dmamap;
1112
1113 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0)
1114 goto out;
1115
1116 rxd = &sc->sc_rxdescs[idx];
1117
1118 #ifdef DIAGNOSTIC
1119 /* If this descriptor is still owned by the chip, bail. */
1120 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1121 rd_sts = le32toh(rxd->rd_sts);
1122 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1123 if (rd_sts & VGE_RDSTS_OWN) {
1124 panic("%s: tried to map busy RX descriptor",
1125 device_xname(sc->sc_dev));
1126 }
1127 #endif
1128
1129 rxs->rxs_mbuf = m;
1130 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1131 BUS_DMASYNC_PREREAD);
1132
1133 rxd->rd_buflen =
1134 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I);
1135 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr);
1136 rxd->rd_sts = 0;
1137 rxd->rd_ctl = 0;
1138 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1139
1140 /*
1141 * Note: the manual fails to document the fact that for
1142 * proper operation, the driver needs to replentish the RX
1143 * DMA ring 4 descriptors at a time (rather than one at a
1144 * time, like most chips). We can allocate the new buffers
1145 * but we should not set the OWN bits until we're ready
1146 * to hand back 4 of them in one shot.
1147 */
1148
1149 #define VGE_RXCHUNK 4
1150 sc->sc_rx_consumed++;
1151 if (sc->sc_rx_consumed == VGE_RXCHUNK) {
1152 for (i = idx; i != idx - VGE_RXCHUNK; i--) {
1153 KASSERT(i >= 0);
1154 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN);
1155 VGE_RXDESCSYNC(sc, i,
1156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1157 }
1158 sc->sc_rx_consumed = 0;
1159 }
1160
1161 return 0;
1162 out:
1163 if (m_new != NULL)
1164 m_freem(m_new);
1165 return ENOMEM;
1166 }
1167
1168 #ifndef __NO_STRICT_ALIGNMENT
1169 static inline void
vge_fixup_rx(struct mbuf * m)1170 vge_fixup_rx(struct mbuf *m)
1171 {
1172 int i;
1173 uint16_t *src, *dst;
1174
1175 src = mtod(m, uint16_t *);
1176 dst = src - 1;
1177
1178 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1179 *dst++ = *src++;
1180
1181 m->m_data -= ETHER_ALIGN;
1182 }
1183 #endif
1184
1185 /*
1186 * RX handler. We support the reception of jumbo frames that have
1187 * been fragmented across multiple 2K mbuf cluster buffers.
1188 */
1189 static void
vge_rxeof(struct vge_softc * sc)1190 vge_rxeof(struct vge_softc *sc)
1191 {
1192 struct mbuf *m;
1193 struct ifnet *ifp;
1194 int idx, total_len, lim;
1195 struct vge_rxdesc *cur_rxd;
1196 struct vge_rxsoft *rxs;
1197 uint32_t rxstat, rxctl;
1198
1199 ifp = &sc->sc_ethercom.ec_if;
1200 lim = 0;
1201
1202 /* Invalidate the descriptor memory */
1203
1204 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) {
1205 cur_rxd = &sc->sc_rxdescs[idx];
1206
1207 VGE_RXDESCSYNC(sc, idx,
1208 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1209 rxstat = le32toh(cur_rxd->rd_sts);
1210 if ((rxstat & VGE_RDSTS_OWN) != 0) {
1211 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1212 break;
1213 }
1214
1215 rxctl = le32toh(cur_rxd->rd_ctl);
1216 rxs = &sc->sc_rxsoft[idx];
1217 m = rxs->rxs_mbuf;
1218 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16;
1219
1220 /* Invalidate the RX mbuf and unload its map */
1221
1222 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap,
1223 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1224 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1225
1226 /*
1227 * If the 'start of frame' bit is set, this indicates
1228 * either the first fragment in a multi-fragment receive,
1229 * or an intermediate fragment. Either way, we want to
1230 * accumulate the buffers.
1231 */
1232 if (rxstat & VGE_RXPKT_SOF) {
1233 m->m_len = VGE_RX_BUFSIZE;
1234 if (sc->sc_rx_mhead == NULL)
1235 sc->sc_rx_mhead = sc->sc_rx_mtail = m;
1236 else {
1237 m->m_flags &= ~M_PKTHDR;
1238 sc->sc_rx_mtail->m_next = m;
1239 sc->sc_rx_mtail = m;
1240 }
1241 vge_newbuf(sc, idx, NULL);
1242 continue;
1243 }
1244
1245 /*
1246 * Bad/error frames will have the RXOK bit cleared.
1247 * However, there's one error case we want to allow:
1248 * if a VLAN tagged frame arrives and the chip can't
1249 * match it against the CAM filter, it considers this
1250 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1251 * We don't want to drop the frame though: our VLAN
1252 * filtering is done in software.
1253 */
1254 if ((rxstat & VGE_RDSTS_RXOK) == 0 &&
1255 (rxstat & VGE_RDSTS_VIDM) == 0 &&
1256 (rxstat & VGE_RDSTS_CSUMERR) == 0) {
1257 if_statinc(ifp, if_ierrors);
1258 /*
1259 * If this is part of a multi-fragment packet,
1260 * discard all the pieces.
1261 */
1262 if (sc->sc_rx_mhead != NULL) {
1263 m_freem(sc->sc_rx_mhead);
1264 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1265 }
1266 vge_newbuf(sc, idx, m);
1267 continue;
1268 }
1269
1270 /*
1271 * If allocating a replacement mbuf fails,
1272 * reload the current one.
1273 */
1274
1275 if (vge_newbuf(sc, idx, NULL)) {
1276 if_statinc(ifp, if_ierrors);
1277 if (sc->sc_rx_mhead != NULL) {
1278 m_freem(sc->sc_rx_mhead);
1279 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1280 }
1281 vge_newbuf(sc, idx, m);
1282 continue;
1283 }
1284
1285 if (sc->sc_rx_mhead != NULL) {
1286 m->m_len = total_len % VGE_RX_BUFSIZE;
1287 /*
1288 * Special case: if there's 4 bytes or less
1289 * in this buffer, the mbuf can be discarded:
1290 * the last 4 bytes is the CRC, which we don't
1291 * care about anyway.
1292 */
1293 if (m->m_len <= ETHER_CRC_LEN) {
1294 sc->sc_rx_mtail->m_len -=
1295 (ETHER_CRC_LEN - m->m_len);
1296 m_freem(m);
1297 } else {
1298 m->m_len -= ETHER_CRC_LEN;
1299 m->m_flags &= ~M_PKTHDR;
1300 sc->sc_rx_mtail->m_next = m;
1301 }
1302 m = sc->sc_rx_mhead;
1303 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1304 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1305 } else
1306 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN;
1307
1308 #ifndef __NO_STRICT_ALIGNMENT
1309 vge_fixup_rx(m);
1310 #endif
1311 m_set_rcvif(m, ifp);
1312
1313 /* Do RX checksumming if enabled */
1314 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) {
1315
1316 /* Check IP header checksum */
1317 if (rxctl & VGE_RDCTL_IPPKT)
1318 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1319 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0)
1320 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1321 }
1322
1323 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) {
1324 /* Check UDP checksum */
1325 if (rxctl & VGE_RDCTL_TCPPKT)
1326 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1327
1328 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0)
1329 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
1330 }
1331
1332 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) {
1333 /* Check UDP checksum */
1334 if (rxctl & VGE_RDCTL_UDPPKT)
1335 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1336
1337 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0)
1338 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
1339 }
1340
1341 if (rxstat & VGE_RDSTS_VTAG) {
1342 /*
1343 * We use bswap16() here because:
1344 * On LE machines, tag is stored in BE as stream data.
1345 * On BE machines, tag is stored in BE as stream data
1346 * but it was already swapped by le32toh() above.
1347 */
1348 vlan_set_tag(m, bswap16(rxctl & VGE_RDCTL_VLANID));
1349 }
1350
1351 if_percpuq_enqueue(ifp->if_percpuq, m);
1352
1353 lim++;
1354 if (lim == VGE_NRXDESC)
1355 break;
1356 }
1357
1358 sc->sc_rx_prodidx = idx;
1359 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1360 }
1361
1362 static void
vge_txeof(struct vge_softc * sc)1363 vge_txeof(struct vge_softc *sc)
1364 {
1365 struct ifnet *ifp;
1366 struct vge_txsoft *txs;
1367 uint32_t txstat;
1368 int idx;
1369
1370 ifp = &sc->sc_ethercom.ec_if;
1371
1372 for (idx = sc->sc_tx_considx;
1373 sc->sc_tx_free < VGE_NTXDESC;
1374 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) {
1375 VGE_TXDESCSYNC(sc, idx,
1376 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1377 txstat = le32toh(sc->sc_txdescs[idx].td_sts);
1378 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1379 if (txstat & VGE_TDSTS_OWN) {
1380 break;
1381 }
1382
1383 txs = &sc->sc_txsoft[idx];
1384 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0,
1385 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1386 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
1387 m_freem(txs->txs_mbuf);
1388 txs->txs_mbuf = NULL;
1389 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1390 if (txstat & (VGE_TDSTS_EXCESSCOLL | VGE_TDSTS_COLL))
1391 if_statinc_ref(nsr, if_collisions);
1392 if (txstat & VGE_TDSTS_TXERR)
1393 if_statinc_ref(nsr, if_oerrors);
1394 else
1395 if_statinc_ref(nsr, if_opackets);
1396 IF_STAT_PUTREF(ifp);
1397 }
1398
1399 sc->sc_tx_considx = idx;
1400
1401 /*
1402 * If not all descriptors have been released reaped yet,
1403 * reload the timer so that we will eventually get another
1404 * interrupt that will cause us to re-enter this routine.
1405 * This is done in case the transmitter has gone idle.
1406 */
1407 if (sc->sc_tx_free < VGE_NTXDESC)
1408 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1409 else
1410 ifp->if_timer = 0;
1411 }
1412
1413 static void
vge_tick(void * arg)1414 vge_tick(void *arg)
1415 {
1416 struct vge_softc *sc;
1417 struct ifnet *ifp;
1418 struct mii_data *mii;
1419 int s;
1420
1421 sc = arg;
1422 ifp = &sc->sc_ethercom.ec_if;
1423 mii = &sc->sc_mii;
1424
1425 s = splnet();
1426
1427 callout_schedule(&sc->sc_timeout, hz);
1428
1429 mii_tick(mii);
1430 if (sc->sc_link) {
1431 if ((mii->mii_media_status & IFM_ACTIVE) == 0)
1432 sc->sc_link = 0;
1433 } else {
1434 if (mii->mii_media_status & IFM_ACTIVE &&
1435 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1436 sc->sc_link = 1;
1437 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1438 vge_start(ifp);
1439 }
1440 }
1441
1442 splx(s);
1443 }
1444
1445 static int
vge_intr(void * arg)1446 vge_intr(void *arg)
1447 {
1448 struct vge_softc *sc;
1449 struct ifnet *ifp;
1450 uint32_t status;
1451 int claim;
1452
1453 sc = arg;
1454 claim = 0;
1455 if (sc->sc_suspended) {
1456 return claim;
1457 }
1458
1459 ifp = &sc->sc_ethercom.ec_if;
1460
1461 if ((ifp->if_flags & IFF_UP) == 0) {
1462 return claim;
1463 }
1464
1465 /* Disable interrupts */
1466 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1467
1468 for (;;) {
1469
1470 status = CSR_READ_4(sc, VGE_ISR);
1471 /* If the card has gone away the read returns 0xffffffff. */
1472 if (status == 0xFFFFFFFF)
1473 break;
1474
1475 if (status) {
1476 claim = 1;
1477 CSR_WRITE_4(sc, VGE_ISR, status);
1478 }
1479
1480 if ((status & VGE_INTRS) == 0)
1481 break;
1482
1483 if (status & (VGE_ISR_RXOK | VGE_ISR_RXOK_HIPRIO))
1484 vge_rxeof(sc);
1485
1486 if (status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) {
1487 vge_rxeof(sc);
1488 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1489 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1490 }
1491
1492 if (status & (VGE_ISR_TXOK0 | VGE_ISR_TIMER0))
1493 vge_txeof(sc);
1494
1495 if (status & (VGE_ISR_TXDMA_STALL | VGE_ISR_RXDMA_STALL))
1496 vge_init(ifp);
1497
1498 if (status & VGE_ISR_LINKSTS)
1499 vge_tick(sc);
1500 }
1501
1502 /* Re-enable interrupts */
1503 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1504
1505 if (claim)
1506 if_schedule_deferred_start(ifp);
1507
1508 return claim;
1509 }
1510
1511 static int
vge_encap(struct vge_softc * sc,struct mbuf * m_head,int idx)1512 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx)
1513 {
1514 struct vge_txsoft *txs;
1515 struct vge_txdesc *txd;
1516 struct vge_txfrag *f;
1517 struct mbuf *m_new;
1518 bus_dmamap_t map;
1519 int m_csumflags, seg, error, flags;
1520 size_t sz;
1521 uint32_t td_sts, td_ctl;
1522
1523 KASSERT(sc->sc_tx_free > 0);
1524
1525 txd = &sc->sc_txdescs[idx];
1526
1527 #ifdef DIAGNOSTIC
1528 /* If this descriptor is still owned by the chip, bail. */
1529 VGE_TXDESCSYNC(sc, idx,
1530 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1531 td_sts = le32toh(txd->td_sts);
1532 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1533 if (td_sts & VGE_TDSTS_OWN) {
1534 return ENOBUFS;
1535 }
1536 #endif
1537
1538 /*
1539 * Preserve m_pkthdr.csum_flags here since m_head might be
1540 * updated by m_defrag()
1541 */
1542 m_csumflags = m_head->m_pkthdr.csum_flags;
1543
1544 txs = &sc->sc_txsoft[idx];
1545 map = txs->txs_dmamap;
1546 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT);
1547
1548 /* If too many segments to map, coalesce */
1549 if (error == EFBIG ||
1550 (m_head->m_pkthdr.len < ETHER_PAD_LEN &&
1551 map->dm_nsegs == VGE_TX_FRAGS)) {
1552 m_new = m_defrag(m_head, M_DONTWAIT);
1553 if (m_new == NULL)
1554 return EFBIG;
1555
1556 error = bus_dmamap_load_mbuf(sc->sc_dmat, map,
1557 m_new, BUS_DMA_NOWAIT);
1558 if (error) {
1559 m_freem(m_new);
1560 return error;
1561 }
1562
1563 m_head = m_new;
1564 } else if (error)
1565 return error;
1566
1567 txs->txs_mbuf = m_head;
1568
1569 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1570 BUS_DMASYNC_PREWRITE);
1571
1572 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) {
1573 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len));
1574 vge_set_txaddr(f, map->dm_segs[seg].ds_addr);
1575 }
1576
1577 /* Argh. This chip does not autopad short frames */
1578 sz = m_head->m_pkthdr.len;
1579 if (sz < ETHER_PAD_LEN) {
1580 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz));
1581 vge_set_txaddr(f, VGE_CDPADADDR(sc));
1582 sz = ETHER_PAD_LEN;
1583 seg++;
1584 }
1585 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE);
1586
1587 /*
1588 * When telling the chip how many segments there are, we
1589 * must use nsegs + 1 instead of just nsegs. Darned if I
1590 * know why.
1591 */
1592 seg++;
1593
1594 flags = 0;
1595 if (m_csumflags & M_CSUM_IPv4)
1596 flags |= VGE_TDCTL_IPCSUM;
1597 if (m_csumflags & M_CSUM_TCPv4)
1598 flags |= VGE_TDCTL_TCPCSUM;
1599 if (m_csumflags & M_CSUM_UDPv4)
1600 flags |= VGE_TDCTL_UDPCSUM;
1601 td_sts = sz << 16;
1602 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM;
1603
1604 if (sz > ETHERMTU + ETHER_HDR_LEN)
1605 td_ctl |= VGE_TDCTL_JUMBO;
1606
1607 /*
1608 * Set up hardware VLAN tagging.
1609 */
1610 if (vlan_has_tag(m_head)) {
1611 /*
1612 * No need htons() here since vge(4) chip assumes
1613 * that tags are written in little endian and
1614 * we already use htole32() here.
1615 */
1616 td_ctl |= vlan_get_tag(m_head) | VGE_TDCTL_VTAG;
1617 }
1618 txd->td_ctl = htole32(td_ctl);
1619 txd->td_sts = htole32(td_sts);
1620 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1621
1622 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts);
1623 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1624
1625 sc->sc_tx_free--;
1626
1627 return 0;
1628 }
1629
1630 /*
1631 * Main transmit routine.
1632 */
1633
1634 static void
vge_start(struct ifnet * ifp)1635 vge_start(struct ifnet *ifp)
1636 {
1637 struct vge_softc *sc;
1638 struct vge_txsoft *txs;
1639 struct mbuf *m_head;
1640 int idx, pidx, ofree, error;
1641
1642 sc = ifp->if_softc;
1643
1644 if (!sc->sc_link ||
1645 (ifp->if_flags & IFF_RUNNING) == 0) {
1646 return;
1647 }
1648
1649 m_head = NULL;
1650 idx = sc->sc_tx_prodidx;
1651 pidx = VGE_PREV_TXDESC(idx);
1652 ofree = sc->sc_tx_free;
1653
1654 /*
1655 * Loop through the send queue, setting up transmit descriptors
1656 * until we drain the queue, or use up all available transmit
1657 * descriptors.
1658 */
1659 while (sc->sc_tx_free != 0) {
1660 /* Grab a packet off the queue. */
1661 IFQ_POLL(&ifp->if_snd, m_head);
1662 if (m_head == NULL)
1663 break;
1664
1665 txs = &sc->sc_txsoft[idx];
1666 KASSERT(txs->txs_mbuf == NULL);
1667
1668 if ((error = vge_encap(sc, m_head, idx))) {
1669 if (error == EFBIG) {
1670 printf("%s: Tx packet consumes too many "
1671 "DMA segments, dropping...\n",
1672 device_xname(sc->sc_dev));
1673 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1674 m_freem(m_head);
1675 continue;
1676 }
1677
1678 /*
1679 * Short on resources, just stop for now.
1680 */
1681 break;
1682 }
1683
1684 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1685
1686 /*
1687 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1688 */
1689
1690 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |=
1691 htole16(VGE_TXDESC_Q);
1692 VGE_TXFRAGSYNC(sc, pidx, 1,
1693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1694
1695 if (txs->txs_mbuf != m_head) {
1696 m_freem(m_head);
1697 m_head = txs->txs_mbuf;
1698 }
1699
1700 pidx = idx;
1701 idx = VGE_NEXT_TXDESC(idx);
1702
1703 /*
1704 * If there's a BPF listener, bounce a copy of this frame
1705 * to him.
1706 */
1707 bpf_mtap(ifp, m_head, BPF_D_OUT);
1708 }
1709
1710 if (sc->sc_tx_free < ofree) {
1711 /* TX packet queued */
1712
1713 sc->sc_tx_prodidx = idx;
1714
1715 /* Issue a transmit command. */
1716 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1717
1718 /*
1719 * Use the countdown timer for interrupt moderation.
1720 * 'TX done' interrupts are disabled. Instead, we reset the
1721 * countdown timer, which will begin counting until it hits
1722 * the value in the SSTIMER register, and then trigger an
1723 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1724 * the timer count is reloaded. Only when the transmitter
1725 * is idle will the timer hit 0 and an interrupt fire.
1726 */
1727 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1728
1729 /*
1730 * Set a timeout in case the chip goes out to lunch.
1731 */
1732 ifp->if_timer = 5;
1733 }
1734 }
1735
1736 static int
vge_init(struct ifnet * ifp)1737 vge_init(struct ifnet *ifp)
1738 {
1739 struct vge_softc *sc;
1740 int i, rc = 0;
1741
1742 sc = ifp->if_softc;
1743
1744 /*
1745 * Cancel pending I/O and free all RX/TX buffers.
1746 */
1747 vge_stop(ifp, 0);
1748 vge_reset(sc);
1749
1750 /* Initialize the RX descriptors and mbufs. */
1751 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
1752 sc->sc_rx_consumed = 0;
1753 for (i = 0; i < VGE_NRXDESC; i++) {
1754 if (vge_newbuf(sc, i, NULL) == ENOBUFS) {
1755 printf("%s: unable to allocate or map rx buffer\n",
1756 device_xname(sc->sc_dev));
1757 return 1; /* XXX */
1758 }
1759 }
1760 sc->sc_rx_prodidx = 0;
1761 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
1762
1763 /* Initialize the TX descriptors and mbufs. */
1764 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1765 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
1766 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs),
1767 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1768 for (i = 0; i < VGE_NTXDESC; i++)
1769 sc->sc_txsoft[i].txs_mbuf = NULL;
1770
1771 sc->sc_tx_prodidx = 0;
1772 sc->sc_tx_considx = 0;
1773 sc->sc_tx_free = VGE_NTXDESC;
1774
1775 /* Set our station address */
1776 for (i = 0; i < ETHER_ADDR_LEN; i++)
1777 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]);
1778
1779 /*
1780 * Set receive FIFO threshold. Also allow transmission and
1781 * reception of VLAN tagged frames.
1782 */
1783 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR | VGE_RXCFG_VTAGOPT);
1784 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES | VGE_VTAG_OPT2);
1785
1786 /* Set DMA burst length */
1787 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1788 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1789
1790 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO | VGE_TXCFG_NONBLK);
1791
1792 /* Set collision backoff algorithm */
1793 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM |
1794 VGE_CHIPCFG1_CAP | VGE_CHIPCFG1_MBA | VGE_CHIPCFG1_BAKOPT);
1795 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFFSET);
1796
1797 /* Disable LPSEL field in priority resolution */
1798 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
1799
1800 /*
1801 * Load the addresses of the DMA queues into the chip.
1802 * Note that we only use one transmit queue.
1803 */
1804
1805 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, VGE_ADDR_HI(VGE_CDTXADDR(sc, 0)));
1806 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0)));
1807 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
1808
1809 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0)));
1810 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
1811 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
1812
1813 /* Enable and wake up the RX descriptor queue */
1814 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1815 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1816
1817 /* Enable the TX descriptor queue */
1818 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
1819
1820 /* Set up the receive filter -- allow large frames for VLANs. */
1821 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST | VGE_RXCTL_RX_GIANT);
1822
1823 /* If we want promiscuous mode, set the allframes bit. */
1824 if (ifp->if_flags & IFF_PROMISC) {
1825 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1826 }
1827
1828 /* Set capture broadcast bit to capture broadcast frames. */
1829 if (ifp->if_flags & IFF_BROADCAST) {
1830 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
1831 }
1832
1833 /* Set multicast bit to capture multicast frames. */
1834 if (ifp->if_flags & IFF_MULTICAST) {
1835 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
1836 }
1837
1838 /* Init the cam filter. */
1839 vge_cam_clear(sc);
1840
1841 /* Init the multicast filter. */
1842 vge_setmulti(sc);
1843
1844 /* Enable flow control */
1845
1846 CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
1847
1848 /* Enable jumbo frame reception (if desired) */
1849
1850 /* Start the MAC. */
1851 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1852 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1853 CSR_WRITE_1(sc, VGE_CRS0,
1854 VGE_CR0_TX_ENABLE | VGE_CR0_RX_ENABLE | VGE_CR0_START);
1855
1856 /*
1857 * Configure one-shot timer for microsecond
1858 * resulution and load it for 500 usecs.
1859 */
1860 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
1861 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
1862
1863 /*
1864 * Configure interrupt moderation for receive. Enable
1865 * the holdoff counter and load it, and set the RX
1866 * suppression count to the number of descriptors we
1867 * want to allow before triggering an interrupt.
1868 * The holdoff timer is in units of 20 usecs.
1869 */
1870
1871 #ifdef notyet
1872 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1873 /* Select the interrupt holdoff timer page. */
1874 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1875 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
1876 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1877
1878 /* Enable use of the holdoff timer. */
1879 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1880 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1881
1882 /* Select the RX suppression threshold page. */
1883 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1884 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
1885 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1886
1887 /* Restore the page select bits. */
1888 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
1889 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
1890 #endif
1891
1892 #ifdef DEVICE_POLLING
1893 /*
1894 * Disable interrupts if we are polling.
1895 */
1896 if (ifp->if_flags & IFF_POLLING) {
1897 CSR_WRITE_4(sc, VGE_IMR, 0);
1898 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1899 } else /* otherwise ... */
1900 #endif /* DEVICE_POLLING */
1901 {
1902 /*
1903 * Enable interrupts.
1904 */
1905 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
1906 CSR_WRITE_4(sc, VGE_ISR, 0);
1907 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1908 }
1909
1910 if ((rc = ether_mediachange(ifp)) != 0)
1911 goto out;
1912
1913 ifp->if_flags |= IFF_RUNNING;
1914
1915 sc->sc_if_flags = 0;
1916 sc->sc_link = 0;
1917
1918 callout_schedule(&sc->sc_timeout, hz);
1919
1920 out:
1921 return rc;
1922 }
1923
1924 static void
vge_miibus_statchg(struct ifnet * ifp)1925 vge_miibus_statchg(struct ifnet *ifp)
1926 {
1927 struct vge_softc *sc = ifp->if_softc;
1928 struct mii_data *mii = &sc->sc_mii;
1929 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
1930 uint8_t dctl;
1931
1932 /*
1933 * If the user manually selects a media mode, we need to turn
1934 * on the forced MAC mode bit in the DIAGCTL register. If the
1935 * user happens to choose a full duplex mode, we also need to
1936 * set the 'force full duplex' bit. This applies only to
1937 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
1938 * mode is disabled, and in 1000baseT mode, full duplex is
1939 * always implied, so we turn on the forced mode bit but leave
1940 * the FDX bit cleared.
1941 */
1942 dctl = CSR_READ_1(sc, VGE_DIAGCTL);
1943
1944 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1945 dctl &= ~VGE_DIAGCTL_MACFORCE;
1946 dctl &= ~VGE_DIAGCTL_FDXFORCE;
1947 } else {
1948 u_int ifmword;
1949
1950 /* If the link is up, use the current active media. */
1951 if ((mii->mii_media_status & IFM_ACTIVE) != 0)
1952 ifmword = mii->mii_media_active;
1953 else
1954 ifmword = ife->ifm_media;
1955
1956 dctl |= VGE_DIAGCTL_MACFORCE;
1957 if ((ifmword & IFM_FDX) != 0)
1958 dctl |= VGE_DIAGCTL_FDXFORCE;
1959 else
1960 dctl &= ~VGE_DIAGCTL_FDXFORCE;
1961
1962 if (IFM_SUBTYPE(ifmword) == IFM_1000_T) {
1963 /*
1964 * It means the user setting is not auto but it's
1965 * 1000baseT-FDX or 1000baseT.
1966 */
1967 dctl |= VGE_DIAGCTL_GMII;
1968 } else
1969 dctl &= ~VGE_DIAGCTL_GMII;
1970 }
1971
1972 CSR_WRITE_1(sc, VGE_DIAGCTL, dctl);
1973 }
1974
1975 static int
vge_ifflags_cb(struct ethercom * ec)1976 vge_ifflags_cb(struct ethercom *ec)
1977 {
1978 struct ifnet *ifp = &ec->ec_if;
1979 struct vge_softc *sc = ifp->if_softc;
1980 u_short change = ifp->if_flags ^ sc->sc_if_flags;
1981
1982 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0)
1983 return ENETRESET;
1984 else if ((change & IFF_PROMISC) == 0)
1985 return 0;
1986
1987 if ((ifp->if_flags & IFF_PROMISC) == 0)
1988 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1989 else
1990 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
1991 vge_setmulti(sc);
1992 return 0;
1993 }
1994
1995 static int
vge_ioctl(struct ifnet * ifp,u_long command,void * data)1996 vge_ioctl(struct ifnet *ifp, u_long command, void *data)
1997 {
1998 struct vge_softc *sc;
1999 int s, error;
2000
2001 sc = ifp->if_softc;
2002 error = 0;
2003
2004 s = splnet();
2005
2006 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) {
2007 error = 0;
2008 if (command != SIOCADDMULTI && command != SIOCDELMULTI)
2009 ;
2010 else if (ifp->if_flags & IFF_RUNNING) {
2011 /*
2012 * Multicast list has changed; set the hardware filter
2013 * accordingly.
2014 */
2015 vge_setmulti(sc);
2016 }
2017 }
2018 sc->sc_if_flags = ifp->if_flags;
2019
2020 splx(s);
2021 return error;
2022 }
2023
2024 static void
vge_watchdog(struct ifnet * ifp)2025 vge_watchdog(struct ifnet *ifp)
2026 {
2027 struct vge_softc *sc;
2028 int s;
2029
2030 sc = ifp->if_softc;
2031 s = splnet();
2032 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
2033 if_statinc(ifp, if_oerrors);
2034
2035 vge_txeof(sc);
2036 vge_rxeof(sc);
2037
2038 vge_init(ifp);
2039
2040 splx(s);
2041 }
2042
2043 /*
2044 * Stop the adapter and free any mbufs allocated to the
2045 * RX and TX lists.
2046 */
2047 static void
vge_stop(struct ifnet * ifp,int disable)2048 vge_stop(struct ifnet *ifp, int disable)
2049 {
2050 struct vge_softc *sc = ifp->if_softc;
2051 struct vge_txsoft *txs;
2052 struct vge_rxsoft *rxs;
2053 int i, s;
2054
2055 s = splnet();
2056 ifp->if_timer = 0;
2057
2058 ifp->if_flags &= ~IFF_RUNNING;
2059 #ifdef DEVICE_POLLING
2060 ether_poll_deregister(ifp);
2061 #endif /* DEVICE_POLLING */
2062
2063 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2064 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2065 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2066 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2067 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2068 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2069
2070 if (sc->sc_rx_mhead != NULL) {
2071 m_freem(sc->sc_rx_mhead);
2072 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL;
2073 }
2074
2075 /* Free the TX list buffers. */
2076
2077 for (i = 0; i < VGE_NTXDESC; i++) {
2078 txs = &sc->sc_txsoft[i];
2079 if (txs->txs_mbuf != NULL) {
2080 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2081 m_freem(txs->txs_mbuf);
2082 txs->txs_mbuf = NULL;
2083 }
2084 }
2085
2086 /* Free the RX list buffers. */
2087
2088 for (i = 0; i < VGE_NRXDESC; i++) {
2089 rxs = &sc->sc_rxsoft[i];
2090 if (rxs->rxs_mbuf != NULL) {
2091 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2092 m_freem(rxs->rxs_mbuf);
2093 rxs->rxs_mbuf = NULL;
2094 }
2095 }
2096
2097 splx(s);
2098 }
2099
2100 #if VGE_POWER_MANAGEMENT
2101 /*
2102 * Device suspend routine. Stop the interface and save some PCI
2103 * settings in case the BIOS doesn't restore them properly on
2104 * resume.
2105 */
2106 static int
vge_suspend(device_t dev)2107 vge_suspend(device_t dev)
2108 {
2109 struct vge_softc *sc;
2110 int i;
2111
2112 sc = device_get_softc(dev);
2113
2114 vge_stop(sc);
2115
2116 for (i = 0; i < 5; i++)
2117 sc->sc_saved_maps[i] =
2118 pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2119 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2120 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2121 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2122 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2123
2124 sc->suspended = 1;
2125
2126 return 0;
2127 }
2128
2129 /*
2130 * Device resume routine. Restore some PCI settings in case the BIOS
2131 * doesn't, re-enable busmastering, and restart the interface if
2132 * appropriate.
2133 */
2134 static int
vge_resume(device_t dev)2135 vge_resume(device_t dev)
2136 {
2137 struct vge_softc *sc;
2138 struct ifnet *ifp;
2139 int i;
2140
2141 sc = device_private(dev);
2142 ifp = &sc->sc_ethercom.ec_if;
2143
2144 /* better way to do this? */
2145 for (i = 0; i < 5; i++)
2146 pci_write_config(dev, PCIR_MAPS + i * 4,
2147 sc->sc_saved_maps[i], 4);
2148 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4);
2149 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1);
2150 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1);
2151 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1);
2152
2153 /* reenable busmastering */
2154 pci_enable_busmaster(dev);
2155 pci_enable_io(dev, SYS_RES_MEMORY);
2156
2157 /* reinitialize interface if necessary */
2158 if (ifp->if_flags & IFF_UP)
2159 vge_init(sc);
2160
2161 sc->suspended = 0;
2162
2163 return 0;
2164 }
2165 #endif
2166
2167 /*
2168 * Stop all chip I/O so that the kernel's probe routines don't
2169 * get confused by errant DMAs when rebooting.
2170 */
2171 static bool
vge_shutdown(device_t self,int howto)2172 vge_shutdown(device_t self, int howto)
2173 {
2174 struct vge_softc *sc;
2175
2176 sc = device_private(self);
2177 vge_stop(&sc->sc_ethercom.ec_if, 1);
2178
2179 return true;
2180 }
2181
2182 static void
vge_clrwol(struct vge_softc * sc)2183 vge_clrwol(struct vge_softc *sc)
2184 {
2185 uint8_t val;
2186
2187 val = CSR_READ_1(sc, VGE_PWRSTAT);
2188 val &= ~VGE_STICKHW_SWPTAG;
2189 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2190 /* Disable WOL and clear power state indicator. */
2191 val = CSR_READ_1(sc, VGE_PWRSTAT);
2192 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1);
2193 CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2194
2195 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
2196 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2197
2198 /* Clear WOL on pattern match. */
2199 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2200 /* Disable WOL on magic/unicast packet. */
2201 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2202 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2203 VGE_WOLCFG_PMEOVR);
2204 /* Clear WOL status on pattern match. */
2205 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2206 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
2207 }
2208