1 /*
2 * Copyright © 2022 Imagination Technologies Ltd.
3 *
4 * based in part on anv driver which is:
5 * Copyright © 2015 Intel Corporation
6 *
7 * based in part on radv driver which is:
8 * Copyright © 2016 Red Hat.
9 * Copyright © 2016 Bas Nieuwenhuizen
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
20 * Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
25 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 * SOFTWARE.
29 */
30
31 #ifndef PVR_PRIVATE_H
32 #define PVR_PRIVATE_H
33
34 #include <assert.h>
35 #include <stdbool.h>
36 #include <stdint.h>
37 #include <vulkan/vulkan.h>
38
39 #include "compiler/shader_enums.h"
40 #include "hwdef/rogue_hw_defs.h"
41 #include "pvr_csb.h"
42 #include "pvr_device_info.h"
43 #include "pvr_entrypoints.h"
44 #include "pvr_hw_pass.h"
45 #include "pvr_job_render.h"
46 #include "pvr_limits.h"
47 #include "pvr_pds.h"
48 #include "pvr_winsys.h"
49 #include "rogue/rogue.h"
50 #include "util/bitscan.h"
51 #include "util/format/u_format.h"
52 #include "util/log.h"
53 #include "util/macros.h"
54 #include "util/u_dynarray.h"
55 #include "vk_command_buffer.h"
56 #include "vk_device.h"
57 #include "vk_image.h"
58 #include "vk_instance.h"
59 #include "vk_log.h"
60 #include "vk_physical_device.h"
61 #include "vk_queue.h"
62 #include "wsi_common.h"
63
64 #ifdef HAVE_VALGRIND
65 # include <valgrind/valgrind.h>
66 # include <valgrind/memcheck.h>
67 # define VG(x) x
68 #else
69 # define VG(x) ((void)0)
70 #endif
71
72 #define VK_VENDOR_ID_IMAGINATION 0x1010
73
74 #define PVR_STATE_PBE_DWORDS 2U
75
76 #define PVR_PIPELINE_LAYOUT_SUPPORTED_DESCRIPTOR_TYPE_COUNT \
77 (uint32_t)(VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT + 1U)
78
79 /* TODO: move into a common surface library? */
80 enum pvr_memlayout {
81 PVR_MEMLAYOUT_UNDEFINED = 0, /* explicitly treat 0 as undefined */
82 PVR_MEMLAYOUT_LINEAR,
83 PVR_MEMLAYOUT_TWIDDLED,
84 PVR_MEMLAYOUT_3DTWIDDLED,
85 };
86
87 enum pvr_cmd_buffer_status {
88 PVR_CMD_BUFFER_STATUS_INVALID = 0, /* explicitly treat 0 as invalid */
89 PVR_CMD_BUFFER_STATUS_INITIAL,
90 PVR_CMD_BUFFER_STATUS_RECORDING,
91 PVR_CMD_BUFFER_STATUS_EXECUTABLE,
92 };
93
94 enum pvr_texture_state {
95 PVR_TEXTURE_STATE_SAMPLE,
96 PVR_TEXTURE_STATE_STORAGE,
97 PVR_TEXTURE_STATE_ATTACHMENT,
98 PVR_TEXTURE_STATE_MAX_ENUM,
99 };
100
101 enum pvr_sub_cmd_type {
102 PVR_SUB_CMD_TYPE_INVALID = 0, /* explicitly treat 0 as invalid */
103 PVR_SUB_CMD_TYPE_GRAPHICS,
104 PVR_SUB_CMD_TYPE_COMPUTE,
105 PVR_SUB_CMD_TYPE_TRANSFER,
106 };
107
108 enum pvr_depth_stencil_usage {
109 PVR_DEPTH_STENCIL_USAGE_UNDEFINED = 0, /* explicitly treat 0 as undefined */
110 PVR_DEPTH_STENCIL_USAGE_NEEDED,
111 PVR_DEPTH_STENCIL_USAGE_NEVER,
112 };
113
114 enum pvr_job_type {
115 PVR_JOB_TYPE_GEOM,
116 PVR_JOB_TYPE_FRAG,
117 PVR_JOB_TYPE_COMPUTE,
118 PVR_JOB_TYPE_TRANSFER,
119 PVR_JOB_TYPE_MAX
120 };
121
122 enum pvr_pipeline_type {
123 PVR_PIPELINE_TYPE_INVALID = 0, /* explicitly treat 0 as undefined */
124 PVR_PIPELINE_TYPE_GRAPHICS,
125 PVR_PIPELINE_TYPE_COMPUTE,
126 };
127
128 enum pvr_pipeline_stage_bits {
129 PVR_PIPELINE_STAGE_GEOM_BIT = BITFIELD_BIT(PVR_JOB_TYPE_GEOM),
130 PVR_PIPELINE_STAGE_FRAG_BIT = BITFIELD_BIT(PVR_JOB_TYPE_FRAG),
131 PVR_PIPELINE_STAGE_COMPUTE_BIT = BITFIELD_BIT(PVR_JOB_TYPE_COMPUTE),
132 PVR_PIPELINE_STAGE_TRANSFER_BIT = BITFIELD_BIT(PVR_JOB_TYPE_TRANSFER),
133 };
134
135 #define PVR_PIPELINE_STAGE_ALL_GRAPHICS_BITS \
136 (PVR_PIPELINE_STAGE_GEOM_BIT | PVR_PIPELINE_STAGE_FRAG_BIT)
137
138 #define PVR_PIPELINE_STAGE_ALL_BITS \
139 (PVR_PIPELINE_STAGE_ALL_GRAPHICS_BITS | PVR_PIPELINE_STAGE_TRANSFER_BIT)
140
141 /* TODO: This number must be changed when we add compute support. */
142 #define PVR_NUM_SYNC_PIPELINE_STAGES 3U
143
144 /* Warning: Do not define an invalid stage as 0 since other code relies on 0
145 * being the first shader stage. This allows for stages to be split or added
146 * in the future. Defining 0 as invalid will very likely cause problems.
147 */
148 enum pvr_stage_allocation {
149 PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY,
150 PVR_STAGE_ALLOCATION_FRAGMENT,
151 PVR_STAGE_ALLOCATION_COMPUTE,
152 PVR_STAGE_ALLOCATION_COUNT
153 };
154
155 /* Scissor accumulation state defines
156 * - Disabled means that a clear has been detected, and scissor accumulation
157 * should stop.
158 * - Check for clear is when there's no clear loadops, but there could be
159 * another clear call that would be broken via scissoring
160 * - Enabled means that a scissor has been set in the pipeline, and
161 * accumulation can continue
162 */
163 enum pvr_scissor_accum_state {
164 PVR_SCISSOR_ACCUM_INVALID = 0, /* Explicitly treat 0 as invalid */
165 PVR_SCISSOR_ACCUM_DISABLED,
166 PVR_SCISSOR_ACCUM_CHECK_FOR_CLEAR,
167 PVR_SCISSOR_ACCUM_ENABLED,
168 };
169
170 struct pvr_bo;
171 struct pvr_compute_ctx;
172 struct pvr_compute_pipeline;
173 struct pvr_free_list;
174 struct pvr_graphics_pipeline;
175 struct pvr_instance;
176 struct pvr_render_ctx;
177 struct rogue_compiler;
178
179 struct pvr_descriptor_limits {
180 uint32_t max_per_stage_resources;
181 uint32_t max_per_stage_samplers;
182 uint32_t max_per_stage_uniform_buffers;
183 uint32_t max_per_stage_storage_buffers;
184 uint32_t max_per_stage_sampled_images;
185 uint32_t max_per_stage_storage_images;
186 uint32_t max_per_stage_input_attachments;
187 };
188
189 struct pvr_physical_device {
190 struct vk_physical_device vk;
191
192 /* Back-pointer to instance */
193 struct pvr_instance *instance;
194
195 char *name;
196 int master_fd;
197 int render_fd;
198 char *master_path;
199 char *render_path;
200
201 struct pvr_winsys *ws;
202 struct pvr_device_info dev_info;
203
204 VkPhysicalDeviceMemoryProperties memory;
205
206 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
207
208 struct wsi_device wsi_device;
209
210 struct rogue_compiler *compiler;
211 };
212
213 struct pvr_instance {
214 struct vk_instance vk;
215
216 int physical_devices_count;
217 struct pvr_physical_device physical_device;
218 };
219
220 struct pvr_queue {
221 struct vk_queue vk;
222
223 struct pvr_device *device;
224
225 struct pvr_render_ctx *gfx_ctx;
226 struct pvr_compute_ctx *compute_ctx;
227
228 struct pvr_winsys_syncobj *completion[PVR_JOB_TYPE_MAX];
229 };
230
231 struct pvr_semaphore {
232 struct vk_object_base base;
233
234 struct pvr_winsys_syncobj *syncobj;
235 };
236
237 struct pvr_fence {
238 struct vk_object_base base;
239
240 struct pvr_winsys_syncobj *syncobj;
241 };
242
243 struct pvr_vertex_binding {
244 struct pvr_buffer *buffer;
245 VkDeviceSize offset;
246 };
247
248 struct pvr_pds_upload {
249 struct pvr_bo *pvr_bo;
250 /* Offset from the pds heap base address. */
251 uint32_t data_offset;
252 /* Offset from the pds heap base address. */
253 uint32_t code_offset;
254
255 /* data_size + code_size = program_size. */
256 uint32_t data_size;
257 uint32_t code_size;
258 };
259
260 struct pvr_device {
261 struct vk_device vk;
262 struct pvr_instance *instance;
263 struct pvr_physical_device *pdevice;
264
265 int master_fd;
266 int render_fd;
267
268 struct pvr_winsys *ws;
269 struct pvr_winsys_heaps heaps;
270
271 struct pvr_free_list *global_free_list;
272
273 struct pvr_queue *queues;
274 uint32_t queue_count;
275
276 /* Running count of the number of job submissions across all queue. */
277 uint32_t global_queue_job_count;
278
279 /* Running count of the number of presentations across all queues. */
280 uint32_t global_queue_present_count;
281
282 uint32_t pixel_event_data_size_in_dwords;
283
284 struct pvr_pds_upload pds_compute_fence_program;
285
286 VkPhysicalDeviceFeatures features;
287 };
288
289 struct pvr_device_memory {
290 struct vk_object_base base;
291 struct pvr_winsys_bo *bo;
292 };
293
294 struct pvr_mip_level {
295 /* Offset of the mip level in bytes */
296 uint32_t offset;
297
298 /* Aligned mip level size in bytes */
299 uint32_t size;
300
301 /* Aligned row length in bytes */
302 uint32_t pitch;
303
304 /* Aligned height in bytes */
305 uint32_t height_pitch;
306 };
307
308 struct pvr_image {
309 struct vk_image vk;
310
311 /* vma this image is bound to */
312 struct pvr_winsys_vma *vma;
313
314 /* Device address the image is mapped to in device virtual address space */
315 pvr_dev_addr_t dev_addr;
316
317 /* Derived and other state */
318 VkExtent3D physical_extent;
319 enum pvr_memlayout memlayout;
320 VkDeviceSize layer_size;
321 VkDeviceSize size;
322
323 VkDeviceSize alignment;
324
325 struct pvr_mip_level mip_levels[14];
326 };
327
328 struct pvr_buffer {
329 struct vk_object_base base;
330
331 /* Saved information from pCreateInfo */
332 VkDeviceSize size;
333
334 /* Derived and other state */
335 uint32_t alignment;
336 /* vma this buffer is bound to */
337 struct pvr_winsys_vma *vma;
338 /* Device address the buffer is mapped to in device virtual address space */
339 pvr_dev_addr_t dev_addr;
340 };
341
342 struct pvr_image_view {
343 struct vk_image_view vk;
344
345 /* Saved information from pCreateInfo. */
346 const struct pvr_image *image;
347
348 /* Prepacked Texture Image dword 0 and 1. It will be copied to the
349 * descriptor info during pvr_UpdateDescriptorSets.
350 *
351 * We create separate texture states for sampling, storage and input
352 * attachment cases.
353 */
354 uint64_t texture_state[PVR_TEXTURE_STATE_MAX_ENUM][2];
355 };
356
357 struct pvr_sampler {
358 struct vk_object_base base;
359
360 uint64_t sampler_word;
361 };
362
363 struct pvr_descriptor_size_info {
364 /* Non-spillable size for storage in the common store. */
365 uint32_t primary;
366
367 /* Spillable size to accommodate limitation of the common store. */
368 uint32_t secondary;
369
370 uint32_t alignment;
371 };
372
373 struct pvr_descriptor_set_layout_binding {
374 VkDescriptorType type;
375
376 /* "M" in layout(set = N, binding = M)
377 * Can be used to index bindings in the descriptor_set_layout. Not the
378 * original user specified binding number as those might be non-contiguous.
379 */
380 uint32_t binding_number;
381
382 uint32_t descriptor_count;
383
384 /* Index into the flattened descriptor set */
385 uint16_t descriptor_index;
386
387 VkShaderStageFlags shader_stages;
388 /* Mask composed by shifted PVR_STAGE_ALLOCATION_...
389 * Makes it easier to check active shader stages by just shifting and
390 * ANDing instead of using VkShaderStageFlags and match the PVR_STAGE_...
391 */
392 uint32_t shader_stage_mask;
393
394 struct {
395 uint32_t primary;
396 uint32_t secondary;
397 } per_stage_offset_in_dwords[PVR_STAGE_ALLOCATION_COUNT];
398
399 /* Index at which the samplers can be found in the descriptor_set_layout.
400 * 0 when the samplers are at index 0 or no samplers are present.
401 * Check descriptor_count to differentiate. It will be 0 for 0 samplers.
402 */
403 uint32_t immutable_samplers_index;
404 };
405
406 /* All sizes are in dwords. */
407 struct pvr_descriptor_set_layout_mem_layout {
408 uint32_t primary_offset;
409 uint32_t primary_size;
410
411 uint32_t secondary_offset;
412 uint32_t secondary_size;
413
414 uint32_t primary_dynamic_size;
415 uint32_t secondary_dynamic_size;
416 };
417
418 struct pvr_descriptor_set_layout {
419 struct vk_object_base base;
420
421 /* Total amount of descriptors contained in this set. */
422 uint32_t descriptor_count;
423
424 /* Count of dynamic buffers. */
425 uint32_t dynamic_buffer_count;
426
427 uint32_t binding_count;
428 struct pvr_descriptor_set_layout_binding *bindings;
429
430 uint32_t immutable_sampler_count;
431 struct pvr_sampler **immutable_samplers;
432
433 /* Shader stages requiring access to descriptors in this set. */
434 VkShaderStageFlags shader_stages;
435
436 /* Count of each VkDescriptorType per shader stage. Dynamically allocated
437 * arrays per stage as to not hard code the max descriptor type here.
438 *
439 * Note: when adding a new type, it might not numerically follow the
440 * previous type so a sparse array will be created. You might want to
441 * readjust how these arrays are created and accessed.
442 */
443 uint32_t *per_stage_descriptor_count[PVR_STAGE_ALLOCATION_COUNT];
444
445 uint32_t total_size_in_dwords;
446 struct pvr_descriptor_set_layout_mem_layout
447 memory_layout_in_dwords_per_stage[PVR_STAGE_ALLOCATION_COUNT];
448 };
449
450 struct pvr_descriptor_pool {
451 struct vk_object_base base;
452
453 VkAllocationCallbacks alloc;
454
455 /* Saved information from pCreateInfo. */
456 uint32_t max_sets;
457
458 uint32_t total_size_in_dwords;
459 uint32_t current_size_in_dwords;
460
461 /* Derived and other state. */
462 /* List of the descriptor sets created using this pool. */
463 struct list_head descriptor_sets;
464 };
465
466 struct pvr_descriptor {
467 VkDescriptorType type;
468
469 /* TODO: Follow anv_descriptor layout when adding support for
470 * other descriptor types.
471 */
472 pvr_dev_addr_t buffer_dev_addr;
473 VkDeviceSize buffer_desc_range;
474 VkDeviceSize buffer_create_info_size;
475 };
476
477 struct pvr_descriptor_set {
478 struct vk_object_base base;
479
480 const struct pvr_descriptor_set_layout *layout;
481 const struct pvr_descriptor_pool *pool;
482
483 struct pvr_bo *pvr_bo;
484
485 /* Links this descriptor set into pvr_descriptor_pool::descriptor_sets list.
486 */
487 struct list_head link;
488
489 /* Array of size layout::descriptor_count. */
490 struct pvr_descriptor descriptors[0];
491 };
492
493 struct pvr_descriptor_state {
494 struct pvr_descriptor_set *descriptor_sets[PVR_MAX_DESCRIPTOR_SETS];
495 uint32_t valid_mask;
496 };
497
498 struct pvr_transfer_cmd {
499 /* Node to link this cmd into the transfer_cmds list in
500 * pvr_sub_cmd::transfer structure.
501 */
502 struct list_head link;
503
504 struct pvr_buffer *src;
505 struct pvr_buffer *dst;
506 uint32_t region_count;
507 VkBufferCopy2 regions[0];
508 };
509
510 struct pvr_sub_cmd {
511 /* This links the subcommand in pvr_cmd_buffer:sub_cmds list. */
512 struct list_head link;
513
514 enum pvr_sub_cmd_type type;
515
516 union {
517 struct {
518 const struct pvr_framebuffer *framebuffer;
519
520 struct pvr_render_job job;
521
522 struct pvr_bo *depth_bias_bo;
523 struct pvr_bo *scissor_bo;
524
525 /* Tracking how the loaded depth/stencil values are being used. */
526 enum pvr_depth_stencil_usage depth_usage;
527 enum pvr_depth_stencil_usage stencil_usage;
528
529 /* Tracking whether the subcommand modifies depth/stencil. */
530 bool modifies_depth;
531 bool modifies_stencil;
532
533 /* Control stream builder object */
534 struct pvr_csb control_stream;
535
536 uint32_t hw_render_idx;
537
538 uint32_t max_tiles_in_flight;
539
540 bool empty_cmd;
541
542 /* True if any fragment shader used in this sub command uses atomic
543 * operations.
544 */
545 bool frag_uses_atomic_ops;
546
547 bool disable_compute_overlap;
548
549 /* True if any fragment shader used in this sub command has side
550 * effects.
551 */
552 bool frag_has_side_effects;
553
554 /* True if any vertex shader used in this sub command contains both
555 * texture reads and texture writes.
556 */
557 bool vertex_uses_texture_rw;
558
559 /* True if any fragment shader used in this sub command contains
560 * both texture reads and texture writes.
561 */
562 bool frag_uses_texture_rw;
563 } gfx;
564
565 struct {
566 /* Control stream builder object. */
567 struct pvr_csb control_stream;
568
569 struct pvr_winsys_compute_submit_info submit_info;
570
571 uint32_t num_shared_regs;
572
573 /* True if any shader used in this sub command uses atomic
574 * operations.
575 */
576 bool uses_atomic_ops;
577
578 bool uses_barrier;
579 } compute;
580
581 struct {
582 /* List of pvr_transfer_cmd type structures. */
583 struct list_head transfer_cmds;
584 } transfer;
585 };
586 };
587
588 struct pvr_render_pass_info {
589 const struct pvr_render_pass *pass;
590 struct pvr_framebuffer *framebuffer;
591
592 struct pvr_image_view **attachments;
593
594 uint32_t subpass_idx;
595 uint32_t current_hw_subpass;
596
597 VkRect2D render_area;
598
599 uint32_t clear_value_count;
600 VkClearValue *clear_values;
601
602 VkPipelineBindPoint pipeline_bind_point;
603
604 bool process_empty_tiles;
605 bool enable_bg_tag;
606 uint32_t userpass_spawn;
607
608 /* Have we had to scissor a depth/stencil clear because render area was not
609 * tile aligned?
610 */
611 bool scissor_ds_clear;
612 };
613
614 struct pvr_emit_state {
615 bool ppp_control : 1;
616 bool isp : 1;
617 bool isp_fb : 1;
618 bool isp_ba : 1;
619 bool isp_bb : 1;
620 bool isp_dbsc : 1;
621 bool pds_fragment_stateptr0 : 1;
622 bool pds_fragment_stateptr1 : 1;
623 bool pds_fragment_stateptr2 : 1;
624 bool pds_fragment_stateptr3 : 1;
625 bool region_clip : 1;
626 bool viewport : 1;
627 bool wclamp : 1;
628 bool output_selects : 1;
629 bool varying_word0 : 1;
630 bool varying_word1 : 1;
631 bool varying_word2 : 1;
632 bool stream_out : 1;
633 };
634
635 struct pvr_ppp_state {
636 uint32_t header;
637
638 struct {
639 /* TODO: Can we get rid of the "control" field? */
640 struct pvr_cmd_struct(TA_STATE_ISPCTL) control_struct;
641 uint32_t control;
642
643 uint32_t front_a;
644 uint32_t front_b;
645 uint32_t back_a;
646 uint32_t back_b;
647 } isp;
648
649 struct {
650 uint16_t scissor_index;
651 uint16_t depthbias_index;
652 } depthbias_scissor_indices;
653
654 struct {
655 uint32_t pixel_shader_base;
656 uint32_t texture_uniform_code_base;
657 uint32_t size_info1;
658 uint32_t size_info2;
659 uint32_t varying_base;
660 uint32_t texture_state_data_base;
661 uint32_t uniform_state_data_base;
662 } pds;
663
664 struct {
665 uint32_t word0;
666 uint32_t word1;
667 } region_clipping;
668
669 struct {
670 uint32_t a0;
671 uint32_t m0;
672 uint32_t a1;
673 uint32_t m1;
674 uint32_t a2;
675 uint32_t m2;
676 } viewports[PVR_MAX_VIEWPORTS];
677
678 uint32_t viewport_count;
679
680 uint32_t output_selects;
681
682 uint32_t varying_word[2];
683
684 uint32_t ppp_control;
685 };
686
687 #define PVR_DYNAMIC_STATE_BIT_VIEWPORT BITFIELD_BIT(0U)
688 #define PVR_DYNAMIC_STATE_BIT_SCISSOR BITFIELD_BIT(1U)
689 #define PVR_DYNAMIC_STATE_BIT_LINE_WIDTH BITFIELD_BIT(2U)
690 #define PVR_DYNAMIC_STATE_BIT_DEPTH_BIAS BITFIELD_BIT(3U)
691 #define PVR_DYNAMIC_STATE_BIT_STENCIL_COMPARE_MASK BITFIELD_BIT(4U)
692 #define PVR_DYNAMIC_STATE_BIT_STENCIL_WRITE_MASK BITFIELD_BIT(5U)
693 #define PVR_DYNAMIC_STATE_BIT_STENCIL_REFERENCE BITFIELD_BIT(6U)
694 #define PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS BITFIELD_BIT(7U)
695
696 #define PVR_DYNAMIC_STATE_ALL_BITS \
697 ((PVR_DYNAMIC_STATE_BIT_BLEND_CONSTANTS << 1U) - 1U)
698
699 struct pvr_dynamic_state {
700 /* Identifies which pipeline state is static or dynamic.
701 * To test for dynamic: & PVR_STATE_BITS_...
702 */
703 uint32_t mask;
704
705 struct {
706 /* TODO: fixme in the original code - figure out what. */
707 uint32_t count;
708 VkViewport viewports[PVR_MAX_VIEWPORTS];
709 } viewport;
710
711 struct {
712 /* TODO: fixme in the original code - figure out what. */
713 uint32_t count;
714 VkRect2D scissors[PVR_MAX_VIEWPORTS];
715 } scissor;
716
717 /* Saved information from pCreateInfo. */
718 float line_width;
719
720 struct {
721 /* Saved information from pCreateInfo. */
722 float constant_factor;
723 float clamp;
724 float slope_factor;
725 } depth_bias;
726 float blend_constants[4];
727 struct {
728 uint32_t front;
729 uint32_t back;
730 } compare_mask;
731 struct {
732 uint32_t front;
733 uint32_t back;
734 } write_mask;
735 struct {
736 uint32_t front;
737 uint32_t back;
738 } reference;
739 };
740
741 struct pvr_cmd_buffer_draw_state {
742 uint32_t base_instance;
743 uint32_t base_vertex;
744 bool draw_indirect;
745 bool draw_indexed;
746 };
747
748 struct pvr_cmd_buffer_state {
749 VkResult status;
750
751 /* Pipeline binding. */
752 const struct pvr_graphics_pipeline *gfx_pipeline;
753
754 const struct pvr_compute_pipeline *compute_pipeline;
755
756 struct pvr_render_pass_info render_pass_info;
757
758 struct pvr_sub_cmd *current_sub_cmd;
759
760 struct pvr_ppp_state ppp_state;
761
762 union {
763 struct pvr_emit_state emit_state;
764 /* This is intended to allow setting and clearing of all bits. This
765 * shouldn't be used to access specific bits of ppp_state.
766 */
767 uint32_t emit_state_bits;
768 };
769
770 struct {
771 /* FIXME: Check if we need a dirty state flag for the given scissor
772 * accumulation state.
773 * Check whether these members should be moved in the top level struct
774 * and this struct replaces with just pvr_dynamic_state "dynamic".
775 */
776 enum pvr_scissor_accum_state scissor_accum_state;
777 VkRect2D scissor_accum_bounds;
778
779 struct pvr_dynamic_state common;
780 } dynamic;
781
782 struct pvr_vertex_binding vertex_bindings[PVR_MAX_VERTEX_INPUT_BINDINGS];
783
784 struct {
785 struct pvr_buffer *buffer;
786 VkDeviceSize offset;
787 VkIndexType type;
788 } index_buffer_binding;
789
790 struct {
791 uint8_t data[PVR_MAX_PUSH_CONSTANTS_SIZE];
792 VkShaderStageFlags dirty_stages;
793 } push_constants;
794
795 /* Array size of barriers_needed is based on number of sync pipeline
796 * stages.
797 */
798 uint32_t barriers_needed[4];
799
800 struct pvr_descriptor_state gfx_desc_state;
801 struct pvr_descriptor_state compute_desc_state;
802
803 VkFormat depth_format;
804
805 struct {
806 bool viewport : 1;
807 bool scissor : 1;
808
809 bool compute_pipeline_binding : 1;
810 bool compute_desc_dirty : 1;
811
812 bool gfx_pipeline_binding : 1;
813 bool gfx_desc_dirty : 1;
814
815 bool vertex_bindings : 1;
816 bool index_buffer_binding : 1;
817 bool vertex_descriptors : 1;
818 bool fragment_descriptors : 1;
819
820 bool line_width : 1;
821
822 bool depth_bias : 1;
823
824 bool blend_constants : 1;
825
826 bool compare_mask : 1;
827 bool write_mask : 1;
828 bool reference : 1;
829
830 bool userpass_spawn : 1;
831
832 /* Some draw state needs to be tracked for changes between draw calls
833 * i.e. if we get a draw with baseInstance=0, followed by a call with
834 * baseInstance=1 that needs to cause us to select a different PDS
835 * attrib program and update the BASE_INSTANCE PDS const. If only
836 * baseInstance changes then we just have to update the data section.
837 */
838 bool draw_base_instance : 1;
839 bool draw_variant : 1;
840 } dirty;
841
842 struct pvr_cmd_buffer_draw_state draw_state;
843
844 struct {
845 uint32_t code_offset;
846 const struct pvr_pds_info *info;
847 } pds_shader;
848
849 uint32_t max_shared_regs;
850
851 /* Address of data segment for vertex attrib upload program. */
852 uint32_t pds_vertex_attrib_offset;
853
854 uint32_t pds_fragment_uniform_data_offset;
855 };
856
857 static_assert(
858 sizeof(((struct pvr_cmd_buffer_state *)(0))->emit_state) <=
859 sizeof(((struct pvr_cmd_buffer_state *)(0))->emit_state_bits),
860 "Size of emit_state_bits must be greater that or equal to emit_state.");
861
862 struct pvr_cmd_buffer {
863 struct vk_command_buffer vk;
864
865 struct pvr_device *device;
866
867 /* Buffer status, invalid/initial/recording/executable */
868 enum pvr_cmd_buffer_status status;
869
870 /* Buffer usage flags */
871 VkCommandBufferUsageFlags usage_flags;
872
873 struct util_dynarray depth_bias_array;
874
875 struct util_dynarray scissor_array;
876 uint32_t scissor_words[2];
877
878 struct pvr_cmd_buffer_state state;
879
880 /* List of pvr_bo structs associated with this cmd buffer. */
881 struct list_head bo_list;
882
883 struct list_head sub_cmds;
884 };
885
886 struct pvr_pipeline_layout {
887 struct vk_object_base base;
888
889 uint32_t set_count;
890 /* Contains set_count amount of descriptor set layouts. */
891 struct pvr_descriptor_set_layout *set_layout[PVR_MAX_DESCRIPTOR_SETS];
892
893 VkShaderStageFlags push_constants_shader_stages;
894
895 VkShaderStageFlags shader_stages;
896
897 /* Per stage masks indicating which set in the layout contains any
898 * descriptor of the appropriate types: VK..._{SAMPLER, SAMPLED_IMAGE,
899 * UNIFORM_TEXEL_BUFFER, UNIFORM_BUFFER, STORAGE_BUFFER}.
900 * Shift by the set's number to check the mask (1U << set_num).
901 */
902 uint32_t per_stage_descriptor_masks[PVR_STAGE_ALLOCATION_COUNT];
903
904 /* Array of descriptor offsets at which the set's descriptors' start, per
905 * stage, within all the sets in the pipeline layout per descriptor type.
906 * Note that we only store into for specific descriptor types
907 * VK_DESCRIPTOR_TYPE_{SAMPLER, SAMPLED_IMAGE, UNIFORM_TEXEL_BUFFER,
908 * UNIFORM_BUFFER, STORAGE_BUFFER}, the rest will be 0.
909 */
910 uint32_t
911 descriptor_offsets[PVR_MAX_DESCRIPTOR_SETS][PVR_STAGE_ALLOCATION_COUNT]
912 [PVR_PIPELINE_LAYOUT_SUPPORTED_DESCRIPTOR_TYPE_COUNT];
913
914 /* There is no accounting for dynamics in here. They will be garbage values.
915 */
916 struct pvr_descriptor_set_layout_mem_layout
917 register_layout_in_dwords_per_stage[PVR_STAGE_ALLOCATION_COUNT]
918 [PVR_MAX_DESCRIPTOR_SETS];
919
920 /* All sizes in dwords. */
921 struct pvr_pipeline_layout_reg_info {
922 uint32_t primary_dynamic_size_in_dwords;
923 uint32_t secondary_dynamic_size_in_dwords;
924 } per_stage_reg_info[PVR_STAGE_ALLOCATION_COUNT];
925 };
926
927 struct pvr_pipeline_cache {
928 struct vk_object_base base;
929
930 struct pvr_device *device;
931 };
932
933 struct pvr_stage_allocation_uniform_state {
934 struct pvr_pds_upload pds_code;
935 /* Since we upload the code segment separately from the data segment
936 * pds_code->data_size might be 0 whilst
937 * pds_info->data_size_in_dwords might be >0 in the case of this struct
938 * referring to the code upload.
939 */
940 struct pvr_pds_info pds_info;
941 };
942
943 struct pvr_pds_attrib_program {
944 struct pvr_pds_info info;
945 /* The uploaded PDS program stored here only contains the code segment,
946 * meaning the data size will be 0, unlike the data size stored in the
947 * 'info' member above.
948 */
949 struct pvr_pds_upload program;
950 };
951
952 struct pvr_pipeline_stage_state {
953 uint32_t const_shared_reg_count;
954 uint32_t const_shared_reg_offset;
955 uint32_t temps_count;
956
957 uint32_t coefficient_size;
958
959 /* True if this shader uses any atomic operations. */
960 bool uses_atomic_ops;
961
962 /* True if this shader uses both texture reads and texture writes. */
963 bool uses_texture_rw;
964
965 /* Only used for compute stage. */
966 bool uses_barrier;
967
968 /* True if this shader has side effects */
969 bool has_side_effects;
970
971 /* True if this shader is simply a nop.end. */
972 bool empty_program;
973 };
974
975 struct pvr_vertex_shader_state {
976 /* Pointer to a buffer object that contains the shader binary. */
977 struct pvr_bo *bo;
978 uint32_t entry_offset;
979
980 /* 2 since we only need STATE_VARYING{0,1} state words. */
981 uint32_t varying[2];
982
983 struct pvr_pds_attrib_program
984 pds_attrib_programs[PVR_PDS_VERTEX_ATTRIB_PROGRAM_COUNT];
985
986 struct pvr_pipeline_stage_state stage_state;
987 /* FIXME: Move this into stage_state? */
988 struct pvr_stage_allocation_uniform_state uniform_state;
989 uint32_t vertex_input_size;
990 uint32_t vertex_output_size;
991 uint32_t output_selects;
992 uint32_t user_clip_planes_mask;
993 };
994
995 struct pvr_fragment_shader_state {
996 /* Pointer to a buffer object that contains the shader binary. */
997 struct pvr_bo *bo;
998 uint32_t entry_offset;
999
1000 struct pvr_pipeline_stage_state stage_state;
1001 /* FIXME: Move this into stage_state? */
1002 struct pvr_stage_allocation_uniform_state uniform_state;
1003 uint32_t pass_type;
1004
1005 struct pvr_pds_upload pds_coeff_program;
1006 struct pvr_pds_upload pds_fragment_program;
1007 };
1008
1009 struct pvr_pipeline {
1010 struct vk_object_base base;
1011
1012 enum pvr_pipeline_type type;
1013
1014 /* Saved information from pCreateInfo. */
1015 struct pvr_pipeline_layout *layout;
1016 };
1017
1018 struct pvr_compute_pipeline {
1019 struct pvr_pipeline base;
1020
1021 struct {
1022 /* Pointer to a buffer object that contains the shader binary. */
1023 struct pvr_bo *bo;
1024
1025 struct {
1026 uint32_t base_workgroup : 1;
1027 } flags;
1028
1029 struct pvr_stage_allocation_uniform_state uniform;
1030
1031 struct pvr_pds_upload primary_program;
1032 struct pvr_pds_info primary_program_info;
1033
1034 struct pvr_pds_upload primary_program_base_workgroup_variant;
1035 struct pvr_pds_info primary_program_base_workgroup_variant_info;
1036 /* Offset within the PDS data section at which the base workgroup id
1037 * resides.
1038 */
1039 uint32_t base_workgroup_ids_dword_offset;
1040 } state;
1041 };
1042
1043 struct pvr_graphics_pipeline {
1044 struct pvr_pipeline base;
1045
1046 VkSampleCountFlagBits rasterization_samples;
1047 struct pvr_raster_state {
1048 /* Derived and other state. */
1049 /* Indicates whether primitives are discarded immediately before the
1050 * rasterization stage.
1051 */
1052 bool discard_enable;
1053 VkCullModeFlags cull_mode;
1054 VkFrontFace front_face;
1055 bool depth_bias_enable;
1056 bool depth_clamp_enable;
1057 } raster_state;
1058 struct {
1059 VkPrimitiveTopology topology;
1060 bool primitive_restart;
1061 } input_asm_state;
1062 uint32_t sample_mask;
1063
1064 struct pvr_dynamic_state dynamic_state;
1065
1066 VkCompareOp depth_compare_op;
1067 bool depth_write_disable;
1068
1069 struct {
1070 VkCompareOp compare_op;
1071 /* SOP1 */
1072 VkStencilOp fail_op;
1073 /* SOP2 */
1074 VkStencilOp depth_fail_op;
1075 /* SOP3 */
1076 VkStencilOp pass_op;
1077 } stencil_front, stencil_back;
1078
1079 /* Derived and other state */
1080 size_t stage_indices[MESA_SHADER_FRAGMENT + 1];
1081
1082 struct pvr_vertex_shader_state vertex_shader_state;
1083 struct pvr_fragment_shader_state fragment_shader_state;
1084 };
1085
1086 struct pvr_render_target {
1087 struct pvr_rt_dataset *rt_dataset;
1088
1089 pthread_mutex_t mutex;
1090
1091 bool valid;
1092 };
1093
1094 struct pvr_framebuffer {
1095 struct vk_object_base base;
1096
1097 /* Saved information from pCreateInfo. */
1098 uint32_t width;
1099 uint32_t height;
1100 uint32_t layers;
1101
1102 uint32_t attachment_count;
1103 struct pvr_image_view **attachments;
1104
1105 /* Derived and other state. */
1106 struct pvr_bo *ppp_state_bo;
1107 /* PPP state size in dwords. */
1108 size_t ppp_state_size;
1109
1110 uint32_t render_targets_count;
1111 struct pvr_render_target *render_targets;
1112 };
1113
1114 struct pvr_render_pass_attachment {
1115 /* Saved information from pCreateInfo. */
1116 VkAttachmentLoadOp load_op;
1117
1118 VkAttachmentStoreOp store_op;
1119
1120 VkAttachmentLoadOp stencil_load_op;
1121
1122 VkAttachmentStoreOp stencil_store_op;
1123
1124 VkFormat vk_format;
1125 uint32_t sample_count;
1126 VkImageLayout initial_layout;
1127
1128 /* Derived and other state. */
1129 /* True if the attachment format includes a stencil component. */
1130 bool has_stencil;
1131
1132 /* Can this surface be resolved by the PBE. */
1133 bool is_pbe_downscalable;
1134
1135 uint32_t index;
1136 };
1137
1138 struct pvr_render_subpass {
1139 /* Saved information from pCreateInfo. */
1140 /* The number of samples per color attachment (or depth attachment if
1141 * z-only).
1142 */
1143 /* FIXME: rename to 'samples' to match struct pvr_image */
1144 uint32_t sample_count;
1145
1146 uint32_t color_count;
1147 uint32_t *color_attachments;
1148 uint32_t *resolve_attachments;
1149
1150 uint32_t input_count;
1151 uint32_t *input_attachments;
1152
1153 uint32_t *depth_stencil_attachment;
1154
1155 /* Derived and other state. */
1156 uint32_t dep_count;
1157 uint32_t *dep_list;
1158
1159 /* Array with dep_count elements. flush_on_dep[x] is true if this subpass
1160 * and the subpass dep_list[x] can't be in the same hardware render.
1161 */
1162 bool *flush_on_dep;
1163
1164 uint32_t index;
1165
1166 uint32_t userpass_spawn;
1167
1168 VkPipelineBindPoint pipeline_bind_point;
1169 };
1170
1171 struct pvr_render_pass {
1172 struct vk_object_base base;
1173
1174 /* Saved information from pCreateInfo. */
1175 uint32_t attachment_count;
1176
1177 struct pvr_render_pass_attachment *attachments;
1178
1179 uint32_t subpass_count;
1180
1181 struct pvr_render_subpass *subpasses;
1182
1183 struct pvr_renderpass_hwsetup *hw_setup;
1184
1185 /* Derived and other state. */
1186 /* FIXME: rename to 'max_samples' as we use 'samples' elsewhere */
1187 uint32_t max_sample_count;
1188
1189 /* The maximum number of tile buffers to use in any subpass. */
1190 uint32_t max_tilebuffer_count;
1191 };
1192
1193 struct pvr_load_op {
1194 bool is_hw_object;
1195
1196 uint32_t clear_mask;
1197
1198 struct pvr_bo *usc_frag_prog_bo;
1199 uint32_t const_shareds_count;
1200 uint32_t shareds_dest_offset;
1201 uint32_t shareds_count;
1202
1203 struct pvr_pds_upload pds_frag_prog;
1204
1205 struct pvr_pds_upload pds_tex_state_prog;
1206 uint32_t temps_count;
1207 };
1208
1209 VkResult pvr_wsi_init(struct pvr_physical_device *pdevice);
1210 void pvr_wsi_finish(struct pvr_physical_device *pdevice);
1211
1212 VkResult pvr_queues_create(struct pvr_device *device,
1213 const VkDeviceCreateInfo *pCreateInfo);
1214 void pvr_queues_destroy(struct pvr_device *device);
1215
1216 VkResult pvr_bind_memory(struct pvr_device *device,
1217 struct pvr_device_memory *mem,
1218 VkDeviceSize offset,
1219 VkDeviceSize size,
1220 VkDeviceSize alignment,
1221 struct pvr_winsys_vma **const vma_out,
1222 pvr_dev_addr_t *const dev_addr_out);
1223 void pvr_unbind_memory(struct pvr_device *device, struct pvr_winsys_vma *vma);
1224
1225 VkResult pvr_gpu_upload(struct pvr_device *device,
1226 struct pvr_winsys_heap *heap,
1227 const void *data,
1228 size_t size,
1229 uint64_t alignment,
1230 struct pvr_bo **const pvr_bo_out);
1231 VkResult pvr_gpu_upload_pds(struct pvr_device *device,
1232 const uint32_t *data,
1233 uint32_t data_size_dwords,
1234 uint32_t data_alignment,
1235 const uint32_t *code,
1236 uint32_t code_size_dwords,
1237 uint32_t code_alignment,
1238 uint64_t min_alignment,
1239 struct pvr_pds_upload *const pds_upload_out);
1240
1241 VkResult pvr_gpu_upload_usc(struct pvr_device *device,
1242 const void *code,
1243 size_t code_size,
1244 uint64_t code_alignment,
1245 struct pvr_bo **const pvr_bo_out);
1246
1247 VkResult pvr_cmd_buffer_add_transfer_cmd(struct pvr_cmd_buffer *cmd_buffer,
1248 struct pvr_transfer_cmd *transfer_cmd);
1249
1250 VkResult pvr_cmd_buffer_alloc_mem(struct pvr_cmd_buffer *cmd_buffer,
1251 struct pvr_winsys_heap *heap,
1252 uint64_t size,
1253 uint32_t flags,
1254 struct pvr_bo **const pvr_bo_out);
1255
1256 static inline struct pvr_compute_pipeline *
to_pvr_compute_pipeline(struct pvr_pipeline * pipeline)1257 to_pvr_compute_pipeline(struct pvr_pipeline *pipeline)
1258 {
1259 assert(pipeline->type == PVR_PIPELINE_TYPE_COMPUTE);
1260 return container_of(pipeline, struct pvr_compute_pipeline, base);
1261 }
1262
1263 static inline struct pvr_graphics_pipeline *
to_pvr_graphics_pipeline(struct pvr_pipeline * pipeline)1264 to_pvr_graphics_pipeline(struct pvr_pipeline *pipeline)
1265 {
1266 assert(pipeline->type == PVR_PIPELINE_TYPE_GRAPHICS);
1267 return container_of(pipeline, struct pvr_graphics_pipeline, base);
1268 }
1269
1270 /* FIXME: Place this in USC specific header? */
1271 /* clang-format off */
PVRX(PDSINST_DOUTU_SAMPLE_RATE)1272 static inline enum PVRX(PDSINST_DOUTU_SAMPLE_RATE)
1273 pvr_sample_rate_from_usc_msaa_mode(enum rogue_msaa_mode msaa_mode)
1274 /* clang-format on */
1275 {
1276 switch (msaa_mode) {
1277 case ROGUE_MSAA_MODE_PIXEL:
1278 return PVRX(PDSINST_DOUTU_SAMPLE_RATE_INSTANCE);
1279 case ROGUE_MSAA_MODE_SELECTIVE:
1280 return PVRX(PDSINST_DOUTU_SAMPLE_RATE_SELECTIVE);
1281 case ROGUE_MSAA_MODE_FULL:
1282 return PVRX(PDSINST_DOUTU_SAMPLE_RATE_FULL);
1283 default:
1284 unreachable("Undefined MSAA mode.");
1285 }
1286 }
1287
1288 VkResult pvr_pds_fragment_program_create_and_upload(
1289 struct pvr_device *device,
1290 const VkAllocationCallbacks *allocator,
1291 const struct pvr_bo *fragment_shader_bo,
1292 uint32_t fragment_temp_count,
1293 enum rogue_msaa_mode msaa_mode,
1294 bool has_phase_rate_change,
1295 struct pvr_pds_upload *const pds_upload_out);
1296
1297 #define PVR_FROM_HANDLE(__pvr_type, __name, __handle) \
1298 VK_FROM_HANDLE(__pvr_type, __name, __handle)
1299
1300 VK_DEFINE_HANDLE_CASTS(pvr_cmd_buffer,
1301 vk.base,
1302 VkCommandBuffer,
1303 VK_OBJECT_TYPE_COMMAND_BUFFER)
1304 VK_DEFINE_HANDLE_CASTS(pvr_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
1305 VK_DEFINE_HANDLE_CASTS(pvr_instance,
1306 vk.base,
1307 VkInstance,
1308 VK_OBJECT_TYPE_INSTANCE)
1309 VK_DEFINE_HANDLE_CASTS(pvr_physical_device,
1310 vk.base,
1311 VkPhysicalDevice,
1312 VK_OBJECT_TYPE_PHYSICAL_DEVICE)
1313 VK_DEFINE_HANDLE_CASTS(pvr_queue, vk.base, VkQueue, VK_OBJECT_TYPE_QUEUE)
1314
1315 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_device_memory,
1316 base,
1317 VkDeviceMemory,
1318 VK_OBJECT_TYPE_DEVICE_MEMORY)
1319 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
1320 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_pipeline_cache,
1321 base,
1322 VkPipelineCache,
1323 VK_OBJECT_TYPE_PIPELINE_CACHE)
1324 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_buffer, base, VkBuffer, VK_OBJECT_TYPE_BUFFER)
1325 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_image_view,
1326 vk.base,
1327 VkImageView,
1328 VK_OBJECT_TYPE_IMAGE_VIEW)
1329 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_descriptor_set_layout,
1330 base,
1331 VkDescriptorSetLayout,
1332 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT)
1333 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_descriptor_set,
1334 base,
1335 VkDescriptorSet,
1336 VK_OBJECT_TYPE_DESCRIPTOR_SET)
1337 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_descriptor_pool,
1338 base,
1339 VkDescriptorPool,
1340 VK_OBJECT_TYPE_DESCRIPTOR_POOL)
1341 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_sampler,
1342 base,
1343 VkSampler,
1344 VK_OBJECT_TYPE_SAMPLER)
1345 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_semaphore,
1346 base,
1347 VkSemaphore,
1348 VK_OBJECT_TYPE_SEMAPHORE)
1349 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_fence, base, VkFence, VK_OBJECT_TYPE_FENCE)
1350 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_pipeline_layout,
1351 base,
1352 VkPipelineLayout,
1353 VK_OBJECT_TYPE_PIPELINE_LAYOUT)
1354 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_pipeline,
1355 base,
1356 VkPipeline,
1357 VK_OBJECT_TYPE_PIPELINE)
1358 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_framebuffer,
1359 base,
1360 VkFramebuffer,
1361 VK_OBJECT_TYPE_FRAMEBUFFER)
1362 VK_DEFINE_NONDISP_HANDLE_CASTS(pvr_render_pass,
1363 base,
1364 VkRenderPass,
1365 VK_OBJECT_TYPE_RENDER_PASS)
1366
1367 /**
1368 * Warn on ignored extension structs.
1369 *
1370 * The Vulkan spec requires us to ignore unsupported or unknown structs in
1371 * a pNext chain. In debug mode, emitting warnings for ignored structs may
1372 * help us discover structs that we should not have ignored.
1373 *
1374 *
1375 * From the Vulkan 1.0.38 spec:
1376 *
1377 * Any component of the implementation (the loader, any enabled layers,
1378 * and drivers) must skip over, without processing (other than reading the
1379 * sType and pNext members) any chained structures with sType values not
1380 * defined by extensions supported by that component.
1381 */
1382 #define pvr_debug_ignored_stype(sType) \
1383 mesa_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
1384
1385 /* Debug helper macros. */
1386 #define PVR_CHECK_COMMAND_BUFFER_BUILDING_STATE(cmd_buffer) \
1387 do { \
1388 struct pvr_cmd_buffer *const _cmd_buffer = (cmd_buffer); \
1389 if (_cmd_buffer->status != PVR_CMD_BUFFER_STATUS_RECORDING) { \
1390 vk_errorf(_cmd_buffer, \
1391 VK_ERROR_OUT_OF_DEVICE_MEMORY, \
1392 "Command buffer is not in recording state"); \
1393 return; \
1394 } else if (_cmd_buffer->state.status < VK_SUCCESS) { \
1395 vk_errorf(_cmd_buffer, \
1396 _cmd_buffer->state.status, \
1397 "Skipping function as command buffer has " \
1398 "previous build error"); \
1399 return; \
1400 } \
1401 } while (0)
1402
1403 /**
1404 * Print a FINISHME message, including its source location.
1405 */
1406 #define pvr_finishme(format, ...) \
1407 do { \
1408 static bool reported = false; \
1409 if (!reported) { \
1410 mesa_logw("%s:%d: FINISHME: " format, \
1411 __FILE__, \
1412 __LINE__, \
1413 ##__VA_ARGS__); \
1414 reported = true; \
1415 } \
1416 } while (false)
1417
1418 /* A non-fatal assert. Useful for debugging. */
1419 #ifdef DEBUG
1420 # define pvr_assert(x) \
1421 ({ \
1422 if (unlikely(!(x))) \
1423 mesa_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
1424 })
1425 #else
1426 # define pvr_assert(x)
1427 #endif
1428
1429 #endif /* PVR_PRIVATE_H */
1430