xref: /qemu/hw/net/vmxnet3.h (revision 2431f4f1)
1 /*
2  * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions
3  *
4  * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5  *
6  * Developed by Daynix Computing LTD (http://www.daynix.com)
7  *
8  * Authors:
9  * Dmitry Fleytman <dmitry@daynix.com>
10  * Tamir Shomer <tamirs@daynix.com>
11  * Yan Vugenfirer <yan@daynix.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.
14  * See the COPYING file in the top-level directory.
15  *
16  */
17 
18 #ifndef QEMU_VMXNET3_H
19 #define QEMU_VMXNET3_H
20 
21 #define VMXNET3_DEVICE_MAX_TX_QUEUES 8
22 #define VMXNET3_DEVICE_MAX_RX_QUEUES 8   /* Keep this value as a power of 2 */
23 
24 /*
25  * VMWARE headers we got from Linux kernel do not fully comply QEMU coding
26  * standards in sense of types and defines used.
27  * Since we didn't want to change VMWARE code, following set of typedefs
28  * and defines needed to compile these headers with QEMU introduced.
29  */
30 #define u64     uint64_t
31 #define u32     uint32_t
32 #define u16     uint16_t
33 #define u8      uint8_t
34 #define __le16  uint16_t
35 #define __le32  uint32_t
36 #define __le64  uint64_t
37 
38 #if HOST_BIG_ENDIAN
39 #define __BIG_ENDIAN_BITFIELD
40 #else
41 #endif
42 
43 /*
44  * Following is an interface definition for
45  * VMXNET3 device as provided by VMWARE
46  * See original copyright from Linux kernel v3.2.8
47  * header file drivers/net/vmxnet3/vmxnet3_defs.h below.
48  */
49 
50 /*
51  * Linux driver for VMware's vmxnet3 ethernet NIC.
52  *
53  * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
54  *
55  * This program is free software; you can redistribute it and/or modify it
56  * under the terms of the GNU General Public License as published by the
57  * Free Software Foundation; version 2 of the License and no later version.
58  *
59  * This program is distributed in the hope that it will be useful, but
60  * WITHOUT ANY WARRANTY; without even the implied warranty of
61  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
62  * NON INFRINGEMENT.  See the GNU General Public License for more
63  * details.
64  *
65  * You should have received a copy of the GNU General Public License
66  * along with this program; if not, write to the Free Software
67  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
68  *
69  * The full GNU General Public License is included in this distribution in
70  * the file called "COPYING".
71  *
72  * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
73  *
74  */
75 
76 struct UPT1_TxStats {
77     u64            TSOPktsTxOK;  /* TSO pkts post-segmentation */
78     u64            TSOBytesTxOK;
79     u64            ucastPktsTxOK;
80     u64            ucastBytesTxOK;
81     u64            mcastPktsTxOK;
82     u64            mcastBytesTxOK;
83     u64            bcastPktsTxOK;
84     u64            bcastBytesTxOK;
85     u64            pktsTxError;
86     u64            pktsTxDiscard;
87 };
88 
89 struct UPT1_RxStats {
90     u64            LROPktsRxOK;    /* LRO pkts */
91     u64            LROBytesRxOK;   /* bytes from LRO pkts */
92     /* the following counters are for pkts from the wire, i.e., pre-LRO */
93     u64            ucastPktsRxOK;
94     u64            ucastBytesRxOK;
95     u64            mcastPktsRxOK;
96     u64            mcastBytesRxOK;
97     u64            bcastPktsRxOK;
98     u64            bcastBytesRxOK;
99     u64            pktsRxOutOfBuf;
100     u64            pktsRxError;
101 };
102 
103 /* interrupt moderation level */
104 enum {
105     UPT1_IML_NONE        = 0, /* no interrupt moderation */
106     UPT1_IML_HIGHEST    = 7, /* least intr generated */
107     UPT1_IML_ADAPTIVE    = 8, /* adpative intr moderation */
108 };
109 /* values for UPT1_RSSConf.hashFunc */
110 enum {
111     UPT1_RSS_HASH_TYPE_NONE      = 0x0,
112     UPT1_RSS_HASH_TYPE_IPV4      = 0x01,
113     UPT1_RSS_HASH_TYPE_TCP_IPV4  = 0x02,
114     UPT1_RSS_HASH_TYPE_IPV6      = 0x04,
115     UPT1_RSS_HASH_TYPE_TCP_IPV6  = 0x08,
116 };
117 
118 enum {
119     UPT1_RSS_HASH_FUNC_NONE      = 0x0,
120     UPT1_RSS_HASH_FUNC_TOEPLITZ  = 0x01,
121 };
122 
123 #define UPT1_RSS_MAX_KEY_SIZE        40
124 #define UPT1_RSS_MAX_IND_TABLE_SIZE  128
125 
126 struct UPT1_RSSConf {
127     u16            hashType;
128     u16            hashFunc;
129     u16            hashKeySize;
130     u16            indTableSize;
131     u8            hashKey[UPT1_RSS_MAX_KEY_SIZE];
132     u8            indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];
133 };
134 
135 /* features */
136 enum {
137     UPT1_F_RXCSUM        = 0x0001, /* rx csum verification */
138     UPT1_F_RSS           = 0x0002,
139     UPT1_F_RXVLAN        = 0x0004, /* VLAN tag stripping */
140     UPT1_F_LRO           = 0x0008,
141 };
142 
143 /* all registers are 32 bit wide */
144 /* BAR 1 */
145 enum {
146     VMXNET3_REG_VRRS    = 0x0,    /* Vmxnet3 Revision Report Selection */
147     VMXNET3_REG_UVRS    = 0x8,    /* UPT Version Report Selection */
148     VMXNET3_REG_DSAL    = 0x10,    /* Driver Shared Address Low */
149     VMXNET3_REG_DSAH    = 0x18,    /* Driver Shared Address High */
150     VMXNET3_REG_CMD        = 0x20,    /* Command */
151     VMXNET3_REG_MACL    = 0x28,    /* MAC Address Low */
152     VMXNET3_REG_MACH    = 0x30,    /* MAC Address High */
153     VMXNET3_REG_ICR        = 0x38,    /* Interrupt Cause Register */
154     VMXNET3_REG_ECR        = 0x40    /* Event Cause Register */
155 };
156 
157 /* BAR 0 */
158 enum {
159     VMXNET3_REG_IMR        = 0x0,     /* Interrupt Mask Register */
160     VMXNET3_REG_TXPROD    = 0x600, /* Tx Producer Index */
161     VMXNET3_REG_RXPROD    = 0x800, /* Rx Producer Index for ring 1 */
162     VMXNET3_REG_RXPROD2    = 0xA00     /* Rx Producer Index for ring 2 */
163 };
164 
165 #define VMXNET3_PT_REG_SIZE     4096    /* BAR 0 */
166 #define VMXNET3_VD_REG_SIZE     4096    /* BAR 1 */
167 
168 #define VMXNET3_REG_ALIGN       8    /* All registers are 8-byte aligned. */
169 #define VMXNET3_REG_ALIGN_MASK  0x7
170 
171 /* I/O Mapped access to registers */
172 #define VMXNET3_IO_TYPE_PT              0
173 #define VMXNET3_IO_TYPE_VD              1
174 #define VMXNET3_IO_ADDR(type, reg)      (((type) << 24) | ((reg) & 0xFFFFFF))
175 #define VMXNET3_IO_TYPE(addr)           ((addr) >> 24)
176 #define VMXNET3_IO_REG(addr)            ((addr) & 0xFFFFFF)
177 
178 enum {
179     VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
180     VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */
181     VMXNET3_CMD_QUIESCE_DEV,                          /* 0xCAFE0001 */
182     VMXNET3_CMD_RESET_DEV,                            /* 0xCAFE0002 */
183     VMXNET3_CMD_UPDATE_RX_MODE,                       /* 0xCAFE0003 */
184     VMXNET3_CMD_UPDATE_MAC_FILTERS,                   /* 0xCAFE0004 */
185     VMXNET3_CMD_UPDATE_VLAN_FILTERS,                  /* 0xCAFE0005 */
186     VMXNET3_CMD_UPDATE_RSSIDT,                        /* 0xCAFE0006 */
187     VMXNET3_CMD_UPDATE_IML,                           /* 0xCAFE0007 */
188     VMXNET3_CMD_UPDATE_PMCFG,                         /* 0xCAFE0008 */
189     VMXNET3_CMD_UPDATE_FEATURE,                       /* 0xCAFE0009 */
190     VMXNET3_CMD_LOAD_PLUGIN,                          /* 0xCAFE000A */
191 
192     VMXNET3_CMD_FIRST_GET = 0xF00D0000,
193     VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */
194     VMXNET3_CMD_GET_STATS,                                /* 0xF00D0001 */
195     VMXNET3_CMD_GET_LINK,                                 /* 0xF00D0002 */
196     VMXNET3_CMD_GET_PERM_MAC_LO,                          /* 0xF00D0003 */
197     VMXNET3_CMD_GET_PERM_MAC_HI,                          /* 0xF00D0004 */
198     VMXNET3_CMD_GET_DID_LO,                               /* 0xF00D0005 */
199     VMXNET3_CMD_GET_DID_HI,                               /* 0xF00D0006 */
200     VMXNET3_CMD_GET_DEV_EXTRA_INFO,                       /* 0xF00D0007 */
201     VMXNET3_CMD_GET_CONF_INTR,                            /* 0xF00D0008 */
202     VMXNET3_CMD_GET_ADAPTIVE_RING_INFO                    /* 0xF00D0009 */
203 };
204 
205 /* Adaptive Ring Info Flags */
206 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
207 
208 /*
209  *    Little Endian layout of bitfields -
210  *    Byte 0 :    7.....len.....0
211  *    Byte 1 :    rsvd gen 13.len.8
212  *    Byte 2 :     5.msscof.0 ext1  dtype
213  *    Byte 3 :     13...msscof...6
214  *
215  *    Big Endian layout of bitfields -
216  *    Byte 0:        13...msscof...6
217  *    Byte 1 :     5.msscof.0 ext1  dtype
218  *    Byte 2 :    rsvd gen 13.len.8
219  *    Byte 3 :    7.....len.....0
220  *
221  *    Thus, le32_to_cpu on the dword will allow the big endian driver to read
222  *    the bit fields correctly. And cpu_to_le32 will convert bitfields
223  *    bit fields written by big endian driver to format required by device.
224  */
225 
226 struct Vmxnet3_TxDesc {
227     __le64 addr;
228 
229     union {
230         struct {
231 #ifdef __BIG_ENDIAN_BITFIELD
232             u32 msscof:14;  /* MSS, checksum offset, flags */
233             u32 ext1:1;
234             u32 dtype:1;    /* descriptor type */
235             u32 rsvd:1;
236             u32 gen:1;      /* generation bit */
237             u32 len:14;
238 #else
239             u32 len:14;
240             u32 gen:1;      /* generation bit */
241             u32 rsvd:1;
242             u32 dtype:1;    /* descriptor type */
243             u32 ext1:1;
244             u32 msscof:14;  /* MSS, checksum offset, flags */
245 #endif  /* __BIG_ENDIAN_BITFIELD */
246         };
247         u32 val1;
248     };
249 
250     union {
251         struct {
252 #ifdef __BIG_ENDIAN_BITFIELD
253             u32 tci:16;     /* Tag to Insert */
254             u32 ti:1;       /* VLAN Tag Insertion */
255             u32 ext2:1;
256             u32 cq:1;       /* completion request */
257             u32 eop:1;      /* End Of Packet */
258             u32 om:2;       /* offload mode */
259             u32 hlen:10;    /* header len */
260 #else
261             u32 hlen:10;    /* header len */
262             u32 om:2;       /* offload mode */
263             u32 eop:1;      /* End Of Packet */
264             u32 cq:1;       /* completion request */
265             u32 ext2:1;
266             u32 ti:1;       /* VLAN Tag Insertion */
267             u32 tci:16;     /* Tag to Insert */
268 #endif  /* __BIG_ENDIAN_BITFIELD */
269         };
270         u32 val2;
271     };
272 };
273 
274 /* TxDesc.OM values */
275 #define VMXNET3_OM_NONE        0
276 #define VMXNET3_OM_CSUM        2
277 #define VMXNET3_OM_TSO        3
278 
279 /* fields in TxDesc we access w/o using bit fields */
280 #define VMXNET3_TXD_EOP_SHIFT    12
281 #define VMXNET3_TXD_CQ_SHIFT    13
282 #define VMXNET3_TXD_GEN_SHIFT    14
283 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
284 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
285 
286 #define VMXNET3_TXD_CQ        (1 << VMXNET3_TXD_CQ_SHIFT)
287 #define VMXNET3_TXD_EOP        (1 << VMXNET3_TXD_EOP_SHIFT)
288 #define VMXNET3_TXD_GEN        (1 << VMXNET3_TXD_GEN_SHIFT)
289 
290 #define VMXNET3_HDR_COPY_SIZE   128
291 
292 
293 struct Vmxnet3_TxDataDesc {
294     u8        data[VMXNET3_HDR_COPY_SIZE];
295 };
296 
297 #define VMXNET3_TCD_GEN_SHIFT    31
298 #define VMXNET3_TCD_GEN_SIZE    1
299 #define VMXNET3_TCD_TXIDX_SHIFT    0
300 #define VMXNET3_TCD_TXIDX_SIZE    12
301 #define VMXNET3_TCD_GEN_DWORD_SHIFT    3
302 
303 struct Vmxnet3_TxCompDesc {
304     union {
305         struct {
306 #ifdef __BIG_ENDIAN_BITFIELD
307             u32 ext1:20;
308             u32 txdIdx:12;    /* Index of the EOP TxDesc */
309 #else
310             u32 txdIdx:12;    /* Index of the EOP TxDesc */
311             u32 ext1:20;
312 #endif
313         };
314         u32 val1;
315     };
316     __le32        ext2;
317     __le32        ext3;
318 
319     union {
320         struct {
321 #ifdef __BIG_ENDIAN_BITFIELD
322             u32 gen:1;        /* generation bit */
323             u32 type:7;       /* completion type */
324             u32 rsvd:24;
325 #else
326             u32 rsvd:24;
327             u32 type:7;       /* completion type */
328             u32 gen:1;        /* generation bit */
329 #endif
330         };
331         u32 val2;
332     };
333 };
334 
335 struct Vmxnet3_RxDesc {
336     __le64        addr;
337     union {
338         struct {
339 #ifdef __BIG_ENDIAN_BITFIELD
340             u32 gen:1;        /* Generation bit */
341             u32 rsvd:15;
342             u32 dtype:1;      /* Descriptor type */
343             u32 btype:1;      /* Buffer Type */
344             u32 len:14;
345 #else
346             u32 len:14;
347             u32 btype:1;      /* Buffer Type */
348             u32 dtype:1;      /* Descriptor type */
349             u32 rsvd:15;
350             u32 gen:1;        /* Generation bit */
351 #endif
352         };
353         u32 val1;
354     };
355     u32        ext1;
356 };
357 
358 /* values of RXD.BTYPE */
359 #define VMXNET3_RXD_BTYPE_HEAD   0    /* head only */
360 #define VMXNET3_RXD_BTYPE_BODY   1    /* body only */
361 
362 /* fields in RxDesc we access w/o using bit fields */
363 #define VMXNET3_RXD_BTYPE_SHIFT  14
364 #define VMXNET3_RXD_GEN_SHIFT    31
365 
366 struct Vmxnet3_RxCompDesc {
367     union {
368         struct {
369 #ifdef __BIG_ENDIAN_BITFIELD
370             u32 ext2:1;
371             u32 cnc:1;        /* Checksum Not Calculated */
372             u32 rssType:4;    /* RSS hash type used */
373             u32 rqID:10;      /* rx queue/ring ID */
374             u32 sop:1;        /* Start of Packet */
375             u32 eop:1;        /* End of Packet */
376             u32 ext1:2;
377             u32 rxdIdx:12;    /* Index of the RxDesc */
378 #else
379             u32 rxdIdx:12;    /* Index of the RxDesc */
380             u32 ext1:2;
381             u32 eop:1;        /* End of Packet */
382             u32 sop:1;        /* Start of Packet */
383             u32 rqID:10;      /* rx queue/ring ID */
384             u32 rssType:4;    /* RSS hash type used */
385             u32 cnc:1;        /* Checksum Not Calculated */
386             u32 ext2:1;
387 #endif  /* __BIG_ENDIAN_BITFIELD */
388         };
389         u32 val1;
390     };
391 
392     __le32        rssHash;      /* RSS hash value */
393 
394     union {
395         struct {
396 #ifdef __BIG_ENDIAN_BITFIELD
397             u32 tci:16;       /* Tag stripped */
398             u32 ts:1;         /* Tag is stripped */
399             u32 err:1;        /* Error */
400             u32 len:14;       /* data length */
401 #else
402             u32 len:14;       /* data length */
403             u32 err:1;        /* Error */
404             u32 ts:1;         /* Tag is stripped */
405             u32 tci:16;       /* Tag stripped */
406 #endif  /* __BIG_ENDIAN_BITFIELD */
407         };
408         u32 val2;
409     };
410 
411     union {
412         struct {
413 #ifdef __BIG_ENDIAN_BITFIELD
414             u32 gen:1;        /* generation bit */
415             u32 type:7;       /* completion type */
416             u32 fcs:1;        /* Frame CRC correct */
417             u32 frg:1;        /* IP Fragment */
418             u32 v4:1;         /* IPv4 */
419             u32 v6:1;         /* IPv6 */
420             u32 ipc:1;        /* IP Checksum Correct */
421             u32 tcp:1;        /* TCP packet */
422             u32 udp:1;        /* UDP packet */
423             u32 tuc:1;        /* TCP/UDP Checksum Correct */
424             u32 csum:16;
425 #else
426             u32 csum:16;
427             u32 tuc:1;        /* TCP/UDP Checksum Correct */
428             u32 udp:1;        /* UDP packet */
429             u32 tcp:1;        /* TCP packet */
430             u32 ipc:1;        /* IP Checksum Correct */
431             u32 v6:1;         /* IPv6 */
432             u32 v4:1;         /* IPv4 */
433             u32 frg:1;        /* IP Fragment */
434             u32 fcs:1;        /* Frame CRC correct */
435             u32 type:7;       /* completion type */
436             u32 gen:1;        /* generation bit */
437 #endif  /* __BIG_ENDIAN_BITFIELD */
438         };
439         u32 val3;
440     };
441 };
442 
443 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
444 #define VMXNET3_RCD_TUC_SHIFT    16
445 #define VMXNET3_RCD_IPC_SHIFT    19
446 
447 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
448 #define VMXNET3_RCD_TYPE_SHIFT    56
449 #define VMXNET3_RCD_GEN_SHIFT    63
450 
451 /* csum OK for TCP/UDP pkts over IP */
452 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
453                      1 << VMXNET3_RCD_IPC_SHIFT)
454 #define VMXNET3_TXD_GEN_SIZE 1
455 #define VMXNET3_TXD_EOP_SIZE 1
456 
457 /* value of RxCompDesc.rssType */
458 enum {
459     VMXNET3_RCD_RSS_TYPE_NONE     = 0,
460     VMXNET3_RCD_RSS_TYPE_IPV4     = 1,
461     VMXNET3_RCD_RSS_TYPE_TCPIPV4  = 2,
462     VMXNET3_RCD_RSS_TYPE_IPV6     = 3,
463     VMXNET3_RCD_RSS_TYPE_TCPIPV6  = 4,
464 };
465 
466 
467 /* a union for accessing all cmd/completion descriptors */
468 union Vmxnet3_GenericDesc {
469     __le64                qword[2];
470     __le32                dword[4];
471     __le16                word[8];
472     struct Vmxnet3_TxDesc        txd;
473     struct Vmxnet3_RxDesc        rxd;
474     struct Vmxnet3_TxCompDesc    tcd;
475     struct Vmxnet3_RxCompDesc    rcd;
476 };
477 
478 #define VMXNET3_INIT_GEN       1
479 
480 /* Max size of a single tx buffer */
481 #define VMXNET3_MAX_TX_BUF_SIZE  (1 << 14)
482 
483 /* # of tx desc needed for a tx buffer size */
484 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
485                     VMXNET3_MAX_TX_BUF_SIZE)
486 
487 /* max # of tx descs for a non-tso pkt */
488 #define VMXNET3_MAX_TXD_PER_PKT 16
489 
490 /* Max size of a single rx buffer */
491 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
492 /* Minimum size of a type 0 buffer */
493 #define VMXNET3_MIN_T0_BUF_SIZE  128
494 #define VMXNET3_MAX_CSUM_OFFSET  1024
495 
496 /* Ring base address alignment */
497 #define VMXNET3_RING_BA_ALIGN   512
498 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
499 
500 /* Ring size must be a multiple of 32 */
501 #define VMXNET3_RING_SIZE_ALIGN 32
502 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
503 
504 /* Max ring size */
505 #define VMXNET3_TX_RING_MAX_SIZE   4096
506 #define VMXNET3_TC_RING_MAX_SIZE   4096
507 #define VMXNET3_RX_RING_MAX_SIZE   4096
508 #define VMXNET3_RC_RING_MAX_SIZE   8192
509 
510 /* a list of reasons for queue stop */
511 
512 enum {
513  VMXNET3_ERR_NOEOP        = 0x80000000, /* cannot find the EOP desc of a pkt */
514  VMXNET3_ERR_TXD_REUSE    = 0x80000001, /* reuse TxDesc before tx completion */
515  VMXNET3_ERR_BIG_PKT      = 0x80000002, /* too many TxDesc for a pkt */
516  VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
517  VMXNET3_ERR_SMALL_BUF    = 0x80000004, /* type 0 buffer too small */
518  VMXNET3_ERR_STRESS       = 0x80000005, /* stress option firing in vmkernel */
519  VMXNET3_ERR_SWITCH       = 0x80000006, /* mode switch failure */
520  VMXNET3_ERR_TXD_INVALID  = 0x80000007, /* invalid TxDesc */
521 };
522 
523 /* completion descriptor types */
524 #define VMXNET3_CDTYPE_TXCOMP      0    /* Tx Completion Descriptor */
525 #define VMXNET3_CDTYPE_RXCOMP      3    /* Rx Completion Descriptor */
526 
527 enum {
528     VMXNET3_GOS_BITS_UNK    = 0,   /* unknown */
529     VMXNET3_GOS_BITS_32     = 1,
530     VMXNET3_GOS_BITS_64     = 2,
531 };
532 
533 #define VMXNET3_GOS_TYPE_UNK        0 /* unknown */
534 #define VMXNET3_GOS_TYPE_LINUX      1
535 #define VMXNET3_GOS_TYPE_WIN        2
536 #define VMXNET3_GOS_TYPE_SOLARIS    3
537 #define VMXNET3_GOS_TYPE_FREEBSD    4
538 #define VMXNET3_GOS_TYPE_PXE        5
539 
540 struct Vmxnet3_GOSInfo {
541 #ifdef __BIG_ENDIAN_BITFIELD
542     u32        gosMisc:10;    /* other info about gos */
543     u32        gosVer:16;     /* gos version */
544     u32        gosType:4;     /* which guest */
545     u32        gosBits:2;    /* 32-bit or 64-bit? */
546 #else
547     u32        gosBits:2;     /* 32-bit or 64-bit? */
548     u32        gosType:4;     /* which guest */
549     u32        gosVer:16;     /* gos version */
550     u32        gosMisc:10;    /* other info about gos */
551 #endif  /* __BIG_ENDIAN_BITFIELD */
552 };
553 
554 struct Vmxnet3_DriverInfo {
555     __le32                version;
556     struct Vmxnet3_GOSInfo        gos;
557     __le32                vmxnet3RevSpt;
558     __le32                uptVerSpt;
559 };
560 
561 
562 #define VMXNET3_REV1_MAGIC  0xbabefee1
563 
564 /*
565  * QueueDescPA must be 128 bytes aligned. It points to an array of
566  * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
567  * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
568  * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
569  */
570 #define VMXNET3_QUEUE_DESC_ALIGN  128
571 
572 
573 struct Vmxnet3_MiscConf {
574     struct Vmxnet3_DriverInfo driverInfo;
575     __le64        uptFeatures;
576     __le64        ddPA;         /* driver data PA */
577     __le64        queueDescPA;  /* queue descriptor table PA */
578     __le32        ddLen;        /* driver data len */
579     __le32        queueDescLen; /* queue desc. table len in bytes */
580     __le32        mtu;
581     __le16        maxNumRxSG;
582     u8        numTxQueues;
583     u8        numRxQueues;
584     __le32        reserved[4];
585 };
586 
587 
588 struct Vmxnet3_TxQueueConf {
589     __le64        txRingBasePA;
590     __le64        dataRingBasePA;
591     __le64        compRingBasePA;
592     __le64        ddPA;         /* driver data */
593     __le64        reserved;
594     __le32        txRingSize;   /* # of tx desc */
595     __le32        dataRingSize; /* # of data desc */
596     __le32        compRingSize; /* # of comp desc */
597     __le32        ddLen;        /* size of driver data */
598     u8        intrIdx;
599     u8        _pad[7];
600 };
601 
602 
603 struct Vmxnet3_RxQueueConf {
604     __le64        rxRingBasePA[2];
605     __le64        compRingBasePA;
606     __le64        ddPA;            /* driver data */
607     __le64        reserved;
608     __le32        rxRingSize[2];   /* # of rx desc */
609     __le32        compRingSize;    /* # of rx comp desc */
610     __le32        ddLen;           /* size of driver data */
611     u8        intrIdx;
612     u8        _pad[7];
613 };
614 
615 
616 enum vmxnet3_intr_mask_mode {
617     VMXNET3_IMM_AUTO   = 0,
618     VMXNET3_IMM_ACTIVE = 1,
619     VMXNET3_IMM_LAZY   = 2
620 };
621 
622 enum vmxnet3_intr_type {
623     VMXNET3_IT_AUTO = 0,
624     VMXNET3_IT_INTX = 1,
625     VMXNET3_IT_MSI  = 2,
626     VMXNET3_IT_MSIX = 3
627 };
628 
629 #define VMXNET3_MAX_TX_QUEUES  8
630 #define VMXNET3_MAX_RX_QUEUES  16
631 /* addition 1 for events */
632 #define VMXNET3_MAX_INTRS      25
633 
634 /* value of intrCtrl */
635 #define VMXNET3_IC_DISABLE_ALL  0x1   /* bit 0 */
636 
637 
638 struct Vmxnet3_IntrConf {
639     bool        autoMask;
640     u8        numIntrs;      /* # of interrupts */
641     u8        eventIntrIdx;
642     u8        modLevels[VMXNET3_MAX_INTRS];    /* moderation level for
643                              * each intr */
644     __le32        intrCtrl;
645     __le32        reserved[2];
646 };
647 
648 /* one bit per VLAN ID, the size is in the units of u32 */
649 #define VMXNET3_VFT_SIZE  (4096/(sizeof(uint32_t)*8))
650 
651 
652 struct Vmxnet3_QueueStatus {
653     bool        stopped;
654     u8        _pad[3];
655     __le32        error;
656 };
657 
658 
659 struct Vmxnet3_TxQueueCtrl {
660     __le32        txNumDeferred;
661     __le32        txThreshold;
662     __le64        reserved;
663 };
664 
665 
666 struct Vmxnet3_RxQueueCtrl {
667     bool        updateRxProd;
668     u8        _pad[7];
669     __le64        reserved;
670 };
671 
672 enum {
673     VMXNET3_RXM_UCAST     = 0x01,  /* unicast only */
674     VMXNET3_RXM_MCAST     = 0x02,  /* multicast passing the filters */
675     VMXNET3_RXM_BCAST     = 0x04,  /* broadcast only */
676     VMXNET3_RXM_ALL_MULTI = 0x08,  /* all multicast */
677     VMXNET3_RXM_PROMISC   = 0x10  /* promiscuous */
678 };
679 
680 struct Vmxnet3_RxFilterConf {
681     __le32        rxMode;       /* VMXNET3_RXM_xxx */
682     __le16        mfTableLen;   /* size of the multicast filter table */
683     __le16        _pad1;
684     __le64        mfTablePA;    /* PA of the multicast filters table */
685     __le32        vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
686 };
687 
688 
689 #define VMXNET3_PM_MAX_FILTERS        6
690 #define VMXNET3_PM_MAX_PATTERN_SIZE   128
691 #define VMXNET3_PM_MAX_MASK_SIZE      (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
692 
693 #define VMXNET3_PM_WAKEUP_MAGIC  cpu_to_le16(0x01)  /* wake up on magic pkts */
694 #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02)  /* wake up on pkts matching
695                                                      * filters */
696 
697 
698 struct Vmxnet3_PM_PktFilter {
699     u8        maskSize;
700     u8        patternSize;
701     u8        mask[VMXNET3_PM_MAX_MASK_SIZE];
702     u8        pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
703     u8        pad[6];
704 };
705 
706 
707 struct Vmxnet3_PMConf {
708     __le16        wakeUpEvents;  /* VMXNET3_PM_WAKEUP_xxx */
709     u8        numFilters;
710     u8        pad[5];
711     struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
712 };
713 
714 
715 struct Vmxnet3_VariableLenConfDesc {
716     __le32        confVer;
717     __le32        confLen;
718     __le64        confPA;
719 };
720 
721 
722 struct Vmxnet3_TxQueueDesc {
723     struct Vmxnet3_TxQueueCtrl        ctrl;
724     struct Vmxnet3_TxQueueConf        conf;
725 
726     /* Driver read after a GET command */
727     struct Vmxnet3_QueueStatus        status;
728     struct UPT1_TxStats            stats;
729     u8                    _pad[88]; /* 128 aligned */
730 };
731 
732 
733 struct Vmxnet3_RxQueueDesc {
734     struct Vmxnet3_RxQueueCtrl        ctrl;
735     struct Vmxnet3_RxQueueConf        conf;
736     /* Driver read after a GET command */
737     struct Vmxnet3_QueueStatus        status;
738     struct UPT1_RxStats            stats;
739     u8                      __pad[88]; /* 128 aligned */
740 };
741 
742 
743 struct Vmxnet3_DSDevRead {
744     /* read-only region for device, read by dev in response to a SET cmd */
745     struct Vmxnet3_MiscConf            misc;
746     struct Vmxnet3_IntrConf            intrConf;
747     struct Vmxnet3_RxFilterConf        rxFilterConf;
748     struct Vmxnet3_VariableLenConfDesc    rssConfDesc;
749     struct Vmxnet3_VariableLenConfDesc    pmConfDesc;
750     struct Vmxnet3_VariableLenConfDesc    pluginConfDesc;
751 };
752 
753 /* All structures in DriverShared are padded to multiples of 8 bytes */
754 struct Vmxnet3_DriverShared {
755     __le32              magic;
756     /* make devRead start at 64bit boundaries */
757     __le32              pad;
758     struct Vmxnet3_DSDevRead    devRead;
759     __le32              ecr;
760     __le32              reserved[5];
761 };
762 
763 
764 #define VMXNET3_ECR_RQERR       (1 << 0)
765 #define VMXNET3_ECR_TQERR       (1 << 1)
766 #define VMXNET3_ECR_LINK        (1 << 2)
767 #define VMXNET3_ECR_DIC         (1 << 3)
768 #define VMXNET3_ECR_DEBUG       (1 << 4)
769 
770 /* flip the gen bit of a ring */
771 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
772 
773 /* only use this if moving the idx won't affect the gen bit */
774 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
775     do {\
776         (idx)++;\
777         if (unlikely((idx) == (ring_size))) {\
778             (idx) = 0;\
779         } \
780     } while (0)
781 
782 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
783     (vfTable[vid >> 5] |= (1 << (vid & 31)))
784 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
785     (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
786 
787 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
788     ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
789 
790 #define VMXNET3_MAX_MTU     9000
791 #define VMXNET3_MIN_MTU     60
792 
793 #define VMXNET3_LINK_UP         (10000 << 16 | 1)    /* 10 Gbps, up */
794 #define VMXNET3_LINK_DOWN       0
795 
796 #undef u64
797 #undef u32
798 #undef u16
799 #undef u8
800 #undef __le16
801 #undef __le32
802 #undef __le64
803 #if HOST_BIG_ENDIAN
804 #undef __BIG_ENDIAN_BITFIELD
805 #endif
806 
807 #endif
808