VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK (definition) in projects: dports

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Searched defs:VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK (Results 1 – 25 of 39) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A D	gmc_7_0_sh_mask.h	`5279 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_2_sh_mask.h	`6401 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_6_0_sh_mask.h	`11844 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L macro`
H A D	gmc_7_1_sh_mask.h	`5921 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_1_sh_mask.h	`6523 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A D	gmc_7_0_sh_mask.h	`5279 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_2_sh_mask.h	`6401 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_6_0_sh_mask.h	`11844 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L macro`
H A D	gmc_7_1_sh_mask.h	`5921 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_1_sh_mask.h	`6523 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A D	gmc_7_0_sh_mask.h	`5279 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_2_sh_mask.h	`6401 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_6_0_sh_mask.h	`11844 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L macro`
H A D	gmc_7_1_sh_mask.h	`5921 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
H A D	gmc_8_1_sh_mask.h	`6523 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 macro`
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A D	mmhub_1_0_sh_mask.h	`7760 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_9_1_sh_mask.h	`7423 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_9_3_0_sh_mask.h	`7850 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A D	mmhub_9_1_sh_mask.h	`7423 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_1_0_sh_mask.h	`7760 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_9_3_0_sh_mask.h	`7850 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A D	mmhub_1_0_sh_mask.h	`7760 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_9_1_sh_mask.h	`7423 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
H A D	mmhub_9_3_0_sh_mask.h	`7850 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A D	gc_9_0_sh_mask.h	`6688 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … macro`