1 /* pdp11_defs.h: PDP-11 simulator definitions 2 3 Copyright (c) 1993-2011, Robert M Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 The author gratefully acknowledges the help of Max Burnet, Megan Gentry, 27 and John Wilson in resolving questions about the PDP-11 28 29 11-Dec-11 RMS Fixed priority of PIRQ vs IO; added INT_INTERNALn 30 22-May-10 RMS Added check for 64b definitions 31 19-Nov-08 RMS Moved I/O support routines to I/O library 32 16-May-08 RMS Added KE11A, DC11 support 33 02-Feb-08 RMS Fixed DMA memory address limit test (found by John Dundas) 34 25-Jan-08 RMS Added RC11, KG11A support (from John Dundas) 35 16-Dec-06 RMS Added TA11 support 36 29-Oct-06 RMS Added clock coscheduling 37 06-Jul-06 RMS Added multiple KL11/DL11 support 38 26-Jun-06 RMS Added RF11 support 39 24-May-06 RMS Added 11/44 DR support (from CIS diagnostic) 40 17-May-06 RMS Added CR11/CD11 support (from John Dundas) 41 30-Sep-04 RMS Added Massbus support 42 Removed Map_Addr prototype 43 Removed map argument from Unibus routines 44 Added framework for model selection 45 28-May-04 RMS Added DHQ support 46 25-Jan-04 RMS Removed local debug logging support 47 22-Dec-03 RMS Added second DEUNA/DELUA support 48 18-Oct-03 RMS Added DECtape off reel message 49 19-May-03 RMS Revised for new conditional compilation 50 05-Apr-03 RMS Fixed bug in MMR1 update (found by Tim Stark) 51 28-Feb-03 RMS Added TM logging support 52 19-Jan-03 RMS Changed mode definitions for Apple Dev Kit conflict 53 11-Nov-02 RMS Changed log definitions to be VAX compatible 54 10-Oct-02 RMS Added vector information to DIB 55 Changed DZ11 vector to Unibus standard 56 Added DEQNA/DELQA, DEUNA/DELUA support 57 Added multiple RQDX3, autoconfigure support 58 12-Sep-02 RMS Added TMSCP, KW11P,and RX211 support 59 28-Apr-02 RMS Clarified PDF ACF mnemonics 60 22-Apr-02 RMS Added HTRAP, BPOK maint register flags, MT_MAXFR 61 06-Mar-02 RMS Changed system type to KDJ11A 62 20-Jan-02 RMS Added multiboard DZ11 support 63 09-Nov-01 RMS Added bus map support 64 07-Nov-01 RMS Added RQDX3 support 65 26-Oct-01 RMS Added symbolic definitions for IO page 66 19-Oct-01 RMS Added DZ definitions 67 15-Oct-01 RMS Added logging capabilities 68 07-Sep-01 RMS Revised for multilevel interrupts 69 01-Jun-01 RMS Added DZ11 support 70 23-Apr-01 RMS Added RK611 support 71 05-Apr-01 RMS Added TS11/TSV05 support 72 10-Feb-01 RMS Added DECtape support 73 */ 74 75 #ifndef _PDP11_DEFS_H 76 #define _PDP11_DEFS_H 0 77 78 #ifndef VM_PDP11 79 #define VM_PDP11 0 80 #endif 81 82 #include "sim_defs.h" /* simulator defns */ 83 #include <setjmp.h> 84 85 #if defined(USE_INT64) || defined(USE_ADDR64) 86 #error "PDP-11 does not support 64b values!" 87 #endif 88 89 /* Architectural constants */ 90 91 #define STKL_R 0340 /* stack limit */ 92 #define STKL_Y 0400 93 #define VASIZE 0200000 /* 2**16 */ 94 #define VAMASK (VASIZE - 1) /* 2**16 - 1 */ 95 #define MEMSIZE64K 0200000 /* 2**16 */ 96 #define INIMEMSIZE 001000000 /* 2**18 */ 97 #define UNIMEMSIZE 001000000 /* 2**18 */ 98 #define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */ 99 #define IOPAGEBASE 017760000 /* 2**22 - 2**13 */ 100 #define IOPAGESIZE 000020000 /* 2**13 */ 101 #define IOPAGEMASK (IOPAGESIZE - 1) /* 2**13 - 1 */ 102 #define MAXMEMSIZE 020000000 /* 2**22 */ 103 #define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */ 104 #define MEMSIZE (cpu_unit.capac) 105 #define ADDR_IS_MEM(x) (((t_addr) (x)) < cpu_memsize) /* use only in sim! */ 106 #define DMASK 0177777 107 108 /* CPU models */ 109 110 #define MOD_1103 0 111 #define MOD_1104 1 112 #define MOD_1105 2 113 #define MOD_1120 3 114 #define MOD_1123 4 115 #define MOD_1123P 5 116 #define MOD_1124 6 117 #define MOD_1134 7 118 #define MOD_1140 8 119 #define MOD_1144 9 120 #define MOD_1145 10 121 #define MOD_1160 11 122 #define MOD_1170 12 123 #define MOD_1173 13 124 #define MOD_1153 14 125 #define MOD_1173B 15 126 #define MOD_1183 16 127 #define MOD_1184 17 128 #define MOD_1193 18 129 #define MOD_1194 19 130 #define MOD_T 20 131 132 #define CPUT_03 (1u << MOD_1103) /* LSI-11 */ 133 #define CPUT_04 (1u << MOD_1104) /* 11/04 */ 134 #define CPUT_05 (1u << MOD_1105) /* 11/05 */ 135 #define CPUT_20 (1u << MOD_1120) /* 11/20 */ 136 #define CPUT_23 (1u << MOD_1123) /* 11/23 */ 137 #define CPUT_23P (1u << MOD_1123P) /* 11/23+ */ 138 #define CPUT_24 (1u << MOD_1124) /* 11/24 */ 139 #define CPUT_34 (1u << MOD_1134) /* 11/34 */ 140 #define CPUT_40 (1u << MOD_1140) /* 11/40 */ 141 #define CPUT_44 (1u << MOD_1144) /* 11/44 */ 142 #define CPUT_45 (1u << MOD_1145) /* 11/45 */ 143 #define CPUT_60 (1u << MOD_1160) /* 11/60 */ 144 #define CPUT_70 (1u << MOD_1170) /* 11/70 */ 145 #define CPUT_73 (1u << MOD_1173) /* 11/73 */ 146 #define CPUT_53 (1u << MOD_1153) /* 11/53 */ 147 #define CPUT_73B (1u << MOD_1173B) /* 11/73B */ 148 #define CPUT_83 (1u << MOD_1183) /* 11/83 */ 149 #define CPUT_84 (1u << MOD_1184) /* 11/84 */ 150 #define CPUT_93 (1u << MOD_1193) /* 11/93 */ 151 #define CPUT_94 (1u << MOD_1194) /* 11/94 */ 152 #define CPUT_T (1u << MOD_T) /* T-11 */ 153 154 #define CPUT_F (CPUT_23|CPUT_23P|CPUT_24) /* all F11's */ 155 #define CPUT_J (CPUT_53|CPUT_73|CPUT_73B| \ 156 CPUT_83|CPUT_84|CPUT_93|CPUT_94) 157 #define CPUT_JB (CPUT_73B|CPUT_83|CPUT_84) /* KDJ11B */ 158 #define CPUT_JE (CPUT_93|CPUT_94) /* KDJ11E */ 159 #define CPUT_JU (CPUT_84|CPUT_94) /* KTJ11B UBA */ 160 #define CPUT_ALL 0xFFFFFFFF 161 162 /* CPU options */ 163 164 #define BUS_U (1u << 0) /* Unibus */ 165 #define BUS_Q (0) /* Qbus */ 166 #define OPT_EIS (1u << 1) /* EIS */ 167 #define OPT_FIS (1u << 2) /* FIS */ 168 #define OPT_FPP (1u << 3) /* FPP */ 169 #define OPT_CIS (1u << 4) /* CIS */ 170 #define OPT_MMU (1u << 5) /* MMU */ 171 #define OPT_RH11 (1u << 6) /* RH11 */ 172 #define OPT_PAR (1u << 7) /* parity */ 173 #define OPT_UBM (1u << 8) /* UBM */ 174 175 #define CPUT(x) ((cpu_type & (x)) != 0) 176 #define CPUO(x) ((cpu_opt & (x)) != 0) 177 #define UNIBUS (cpu_opt & BUS_U) 178 179 /* Feature sets 180 181 SDSD source addr, dest addr, source fetch, dest fetch 182 SR switch register 183 DR display register 184 RTT RTT instruction 185 SXS SXT, XOR, SOB instructions 186 MARK MARK instruction 187 SPL SPL instruction 188 MXPY MTPI, MTPD, MFPI, MFPD instructions 189 MXPS MTPS, MFPS instructions 190 MFPT MFPT instruction 191 CSM CSM instruction 192 TSWLK TSTSET, WRLCK instructions 193 PSW PSW register 194 EXPT explicit PSW writes can alter T-bit 195 IOSR general registers readable from programs in IO space 196 2REG dual register set 197 MMR3 MMR3 register 198 MMTR mem mgt traps 199 STKLR STKLIM register 200 STKLF fixed stack limit 201 SID supervisor mode, I/D spaces 202 ODD odd address trap 203 HALT4 halt in kernel mode traps to 4 204 JREG4 JMP/JSR R traps to 4 205 STKA stop on stack abort 206 LTCR LTC CSR 207 LTCM LTC CSR<7> 208 */ 209 210 #define IS_SDSD (CPUT_20|CPUT_F|CPUT_40|CPUT_60|CPUT_J|CPUT_T) 211 #define HAS_SR (CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_40| \ 212 CPUT_44|CPUT_45|CPUT_60|CPUT_70) 213 #define HAS_DR (CPUT_04|CPUT_05|CPUT_20|CPUT_24|CPUT_34| \ 214 CPUT_40|CPUT_44|CPUT_45|CPUT_60|CPUT_70) 215 #define HAS_RTT (CPUT_03|CPUT_04|CPUT_F|CPUT_34|CPUT_40| \ 216 CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J|CPUT_T) 217 #define HAS_SXS (CPUT_03|CPUT_F|CPUT_34|CPUT_40|CPUT_44| \ 218 CPUT_45|CPUT_60|CPUT_70|CPUT_J|CPUT_T) 219 #define HAS_MARK (CPUT_03|CPUT_F|CPUT_34|CPUT_40|CPUT_44| \ 220 CPUT_45|CPUT_60|CPUT_70|CPUT_J) 221 #define HAS_SPL (CPUT_44|CPUT_45|CPUT_70|CPUT_J) 222 #define HAS_MXPY (CPUT_F|CPUT_34|CPUT_40|CPUT_44|CPUT_45| \ 223 CPUT_60|CPUT_70|CPUT_J) 224 #define HAS_MXPS (CPUT_03|CPUT_F|CPUT_34|CPUT_J|CPUT_T) 225 #define HAS_MFPT (CPUT_F|CPUT_44|CPUT_J|CPUT_T) 226 #define HAS_CSM (CPUT_44|CPUT_J) 227 #define HAS_TSWLK (CPUT_J) 228 #define HAS_PSW (CPUT_04|CPUT_05|CPUT_20|CPUT_F|CPUT_34|CPUT_40| \ 229 CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J) 230 #define HAS_EXPT (CPUT_04|CPUT_05|CPUT_20) 231 #define HAS_IOSR (CPUT_04|CPUT_05) 232 #define HAS_2REG (CPUT_45|CPUT_70|CPUT_J) 233 #define HAS_MMR3 (CPUT_F|CPUT_44|CPUT_45|CPUT_70|CPUT_J) 234 #define HAS_MMTR (CPUT_45|CPUT_70) 235 #define HAS_STKLR (CPUT_45|CPUT_60|CPUT_70) 236 #define HAS_STKLF (CPUT_04|CPUT_05|CPUT_20|CPUT_F|CPUT_34| \ 237 CPUT_40|CPUT_44|CPUT_J) 238 #define HAS_SID (CPUT_44|CPUT_45|CPUT_70|CPUT_J) 239 #define HAS_ODD (CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_40| \ 240 CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J) 241 #define HAS_HALT4 (CPUT_44|CPUT_45|CPUT_70|CPUT_J) 242 #define HAS_JREG4 (CPUT_03|CPUT_04|CPUT_05|CPUT_20|CPUT_F| \ 243 CPUT_34|CPUT_40|CPUT_60|CPUT_T) 244 #define STOP_STKA (CPUT_03|CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_44) 245 #define HAS_LTCR (CPUT_04|CPUT_05|CPUT_20|CPUT_23P|CPUT_24| \ 246 CPUT_34|CPUT_40|CPUT_44|CPUT_45|CPUT_60| \ 247 CPUT_70|CPUT_J) 248 #define HAS_LTCM (CPUT_04|CPUT_05|CPUT_20|CPUT_24|CPUT_34| \ 249 CPUT_40|CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J) 250 251 /* Protection modes */ 252 253 #define MD_KER 0 254 #define MD_SUP 1 255 #define MD_UND 2 256 #define MD_USR 3 257 258 /* I/O access modes */ 259 260 #define READ 0 261 #define READC 1 /* read console */ 262 #define WRITE 2 263 #define WRITEC 3 /* write console */ 264 #define WRITEB 4 265 266 /* PSW */ 267 268 #define PSW_V_C 0 /* condition codes */ 269 #define PSW_V_V 1 270 #define PSW_V_Z 2 271 #define PSW_V_N 3 272 #define PSW_V_TBIT 4 /* trace trap */ 273 #define PSW_V_IPL 5 /* int priority */ 274 #define PSW_V_FPD 8 /* first part done */ 275 #define PSW_V_RS 11 /* register set */ 276 #define PSW_V_PM 12 /* previous mode */ 277 #define PSW_V_CM 14 /* current mode */ 278 #define PSW_CC 017 279 #define PSW_TBIT (1 << PSW_V_TBIT) 280 #define PSW_PM (3 << PSW_V_PM) 281 282 /* FPS */ 283 284 #define FPS_V_C 0 /* condition codes */ 285 #define FPS_V_V 1 286 #define FPS_V_Z 2 287 #define FPS_V_N 3 288 #define FPS_V_T 5 /* truncate */ 289 #define FPS_V_L 6 /* long */ 290 #define FPS_V_D 7 /* double */ 291 #define FPS_V_IC 8 /* ic err int */ 292 #define FPS_V_IV 9 /* overflo err int */ 293 #define FPS_V_IU 10 /* underflo err int */ 294 #define FPS_V_IUV 11 /* undef var err int */ 295 #define FPS_V_ID 14 /* int disable */ 296 #define FPS_V_ER 15 /* error */ 297 298 /* PIRQ */ 299 300 #define PIRQ_PIR1 0001000 301 #define PIRQ_PIR2 0002000 302 #define PIRQ_PIR3 0004000 303 #define PIRQ_PIR4 0010000 304 #define PIRQ_PIR5 0020000 305 #define PIRQ_PIR6 0040000 306 #define PIRQ_PIR7 0100000 307 #define PIRQ_IMP 0177356 /* implemented bits */ 308 #define PIRQ_RW 0177000 /* read/write bits */ 309 310 /* STKLIM */ 311 312 #define STKLIM_RW 0177400 313 314 /* MMR0 */ 315 316 #define MMR0_MME 0000001 /* mem mgt enable */ 317 #define MMR0_V_PAGE 1 /* offset to pageno */ 318 #define MMR0_M_PAGE 077 /* mask for pageno */ 319 #define MMR0_PAGE (MMR0_M_PAGE << MMR0_V_PAGE) 320 #define MMR0_IC 0000200 /* instr complete */ 321 #define MMR0_MAINT 0000400 /* maintenance */ 322 #define MMR0_TENB 0001000 /* trap enable */ 323 #define MMR0_TRAP 0010000 /* mem mgt trap */ 324 #define MMR0_RO 0020000 /* read only error */ 325 #define MMR0_PL 0040000 /* page lnt error */ 326 #define MMR0_NR 0100000 /* no access error */ 327 #define MMR0_FREEZE 0160000 /* if set, no update */ 328 #define MMR0_WR 0171401 /* writeable bits */ 329 330 /* MMR3 */ 331 332 #define MMR3_UDS 001 /* user dspace enbl */ 333 #define MMR3_SDS 002 /* super dspace enbl */ 334 #define MMR3_KDS 004 /* krnl dspace enbl */ 335 #define MMR3_CSM 010 /* CSM enable */ 336 #define MMR3_M22E 020 /* 22b mem mgt enbl */ 337 #define MMR3_BME 040 /* DMA bus map enbl */ 338 339 /* PAR */ 340 341 #define PAR_18B 0007777 /* 18b addressing */ 342 #define PAR_22B 0177777 /* 22b addressing */ 343 344 /* PDR */ 345 346 #define PDR_ACF 0000007 /* access control */ 347 #define PDR_ACS 0000006 /* 2b access control */ 348 #define PDR_ED 0000010 /* expansion dir */ 349 #define PDR_W 0000100 /* written flag */ 350 #define PDR_A 0000200 /* access flag */ 351 #define PDR_PLF 0077400 /* page lnt field */ 352 #define PDR_NOC 0100000 /* don't cache */ 353 354 #define PDR_PRD 0000003 /* page readable if 2 */ 355 356 /* Virtual address */ 357 358 #define VA_DF 0017777 /* displacement */ 359 #define VA_BN 0017700 /* block number */ 360 #define VA_V_APF 13 /* offset to APF */ 361 #define VA_V_DS 16 /* offset to space */ 362 #define VA_V_MODE 17 /* offset to mode */ 363 #define VA_DS (1u << VA_V_DS) /* data space flag */ 364 365 /* Unibus map (if present) */ 366 367 #define UBM_LNT_LW 32 /* size in LW */ 368 #define UBM_V_PN 13 /* page number */ 369 #define UBM_M_PN 037 370 #define UBM_V_OFF 0 /* offset */ 371 #define UBM_M_OFF 017777 372 #define UBM_PAGSIZE (UBM_M_OFF + 1) /* page size */ 373 #define UBM_GETPN(x) (((x) >> UBM_V_PN) & UBM_M_PN) 374 #define UBM_GETOFF(x) ((x) & UBM_M_OFF) 375 376 /* CPUERR */ 377 378 #define CPUE_RED 0004 /* red stack */ 379 #define CPUE_YEL 0010 /* yellow stack */ 380 #define CPUE_TMO 0020 /* IO page nxm */ 381 #define CPUE_NXM 0040 /* memory nxm */ 382 #define CPUE_ODD 0100 /* odd address */ 383 #define CPUE_HALT 0200 /* HALT not kernel */ 384 #define CPUE_IMP 0374 /* implemented bits */ 385 386 /* Floating point accumulators */ 387 388 typedef struct { 389 uint32 l; /* low 32b */ 390 uint32 h; /* high 32b */ 391 } fpac_t; 392 393 /* Device CSRs */ 394 395 #define CSR_V_GO 0 /* go */ 396 #define CSR_V_IE 6 /* interrupt enable */ 397 #define CSR_V_DONE 7 /* done */ 398 #define CSR_V_BUSY 11 /* busy */ 399 #define CSR_V_ERR 15 /* error */ 400 #define CSR_GO (1u << CSR_V_GO) 401 #define CSR_IE (1u << CSR_V_IE) 402 #define CSR_DONE (1u << CSR_V_DONE) 403 #define CSR_BUSY (1u << CSR_V_BUSY) 404 #define CSR_ERR (1u << CSR_V_ERR) 405 406 /* Trap masks, descending priority order, following J-11 407 An interrupt summary bit is kept with traps, to minimize overhead 408 */ 409 410 #define TRAP_V_RED 0 /* red stk abort 4 */ 411 #define TRAP_V_ODD 1 /* odd address 4 */ 412 #define TRAP_V_MME 2 /* mem mgt 250 */ 413 #define TRAP_V_NXM 3 /* nx memory 4 */ 414 #define TRAP_V_PAR 4 /* parity err 114 */ 415 #define TRAP_V_PRV 5 /* priv inst 4 */ 416 #define TRAP_V_ILL 6 /* illegal inst 10 */ 417 #define TRAP_V_BPT 7 /* BPT 14 */ 418 #define TRAP_V_IOT 8 /* IOT 20 */ 419 #define TRAP_V_EMT 9 /* EMT 30 */ 420 #define TRAP_V_TRAP 10 /* TRAP 34 */ 421 #define TRAP_V_TRC 11 /* T bit 14 */ 422 #define TRAP_V_YEL 12 /* stack 4 */ 423 #define TRAP_V_PWRFL 13 /* power fail 24 */ 424 #define TRAP_V_FPE 14 /* fpe 244 */ 425 #define TRAP_V_MAX 15 /* intr = max trp # */ 426 #define TRAP_RED (1u << TRAP_V_RED) 427 #define TRAP_ODD (1u << TRAP_V_ODD) 428 #define TRAP_MME (1u << TRAP_V_MME) 429 #define TRAP_NXM (1u << TRAP_V_NXM) 430 #define TRAP_PAR (1u << TRAP_V_PAR) 431 #define TRAP_PRV (1u << TRAP_V_PRV) 432 #define TRAP_ILL (1u << TRAP_V_ILL) 433 #define TRAP_BPT (1u << TRAP_V_BPT) 434 #define TRAP_IOT (1u << TRAP_V_IOT) 435 #define TRAP_EMT (1u << TRAP_V_EMT) 436 #define TRAP_TRAP (1u << TRAP_V_TRAP) 437 #define TRAP_TRC (1u << TRAP_V_TRC) 438 #define TRAP_YEL (1u << TRAP_V_YEL) 439 #define TRAP_PWRFL (1u << TRAP_V_PWRFL) 440 #define TRAP_FPE (1u << TRAP_V_FPE) 441 #define TRAP_INT (1u << TRAP_V_MAX) 442 #define TRAP_ALL ((1u << TRAP_V_MAX) - 1) /* all traps */ 443 444 #define VEC_RED 0004 /* trap vectors */ 445 #define VEC_ODD 0004 446 #define VEC_MME 0250 447 #define VEC_NXM 0004 448 #define VEC_PAR 0114 449 #define VEC_PRV 0004 450 #define VEC_ILL 0010 451 #define VEC_BPT 0014 452 #define VEC_IOT 0020 453 #define VEC_EMT 0030 454 #define VEC_TRAP 0034 455 #define VEC_TRC 0014 456 #define VEC_YEL 0004 457 #define VEC_PWRFL 0024 458 #define VEC_FPE 0244 459 460 /* Simulator stop codes; codes 1:TRAP_V_MAX correspond to traps 0:TRAPMAX-1 */ 461 462 #define STOP_HALT (TRAP_V_MAX + 1) /* HALT instruction */ 463 #define STOP_IBKPT (TRAP_V_MAX + 2) /* instruction bkpt */ 464 #define STOP_WAIT (TRAP_V_MAX + 3) /* wait, no events */ 465 #define STOP_VECABORT (TRAP_V_MAX + 4) /* abort vector read */ 466 #define STOP_SPABORT (TRAP_V_MAX + 5) /* abort trap push */ 467 #define STOP_RQ (TRAP_V_MAX + 6) /* RQDX3 panic */ 468 #define STOP_SANITY (TRAP_V_MAX + 7) /* sanity timer exp */ 469 #define STOP_DTOFF (TRAP_V_MAX + 8) /* DECtape off reel */ 470 #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ 471 472 /* Timers */ 473 474 #define TMR_CLK 0 /* line clock */ 475 #define TMR_PCLK 1 /* KW11P */ 476 477 /* IO parameters */ 478 479 #define DZ_MUXES 4 /* max # of DZ muxes */ 480 #define DZ_LINES 8 /* lines per DZ mux */ 481 #define VH_MUXES 4 /* max # of VH muxes */ 482 #define DLX_LINES 16 /* max # of KL11/DL11's */ 483 #define DCX_LINES 16 /* max # of DC11's */ 484 #define MT_MAXFR (1 << 16) /* magtape max rec */ 485 #define AUTO_LNT 34 /* autoconfig ranks */ 486 #define DIB_MAX 100 /* max DIBs */ 487 488 #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ 489 #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */ 490 #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus with <= 256KB */ 491 #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */ 492 #define DEV_V_MBUS (DEV_V_UF + 4) /* Massbus */ 493 #define DEV_V_FFUF (DEV_V_UF + 5) /* first free flag */ 494 #define DEV_UBUS (1u << DEV_V_UBUS) 495 #define DEV_QBUS (1u << DEV_V_QBUS) 496 #define DEV_Q18 (1u << DEV_V_Q18) 497 #define DEV_FLTA (1u << DEV_V_FLTA) 498 #define DEV_MBUS (1u << DEV_V_MBUS) 499 500 #define DEV_RDX 8 /* default device radix */ 501 502 /* Device information block */ 503 504 #define VEC_DEVMAX 4 /* max device vec */ 505 506 struct pdp_dib { 507 uint32 ba; /* base addr */ 508 uint32 lnt; /* length */ 509 t_stat (*rd)(int32 *dat, int32 ad, int32 md); 510 t_stat (*wr)(int32 dat, int32 ad, int32 md); 511 int32 vnum; /* vectors: number */ 512 int32 vloc; /* locator */ 513 int32 vec; /* value */ 514 int32 (*ack[VEC_DEVMAX])(void); /* ack routines */ 515 }; 516 517 typedef struct pdp_dib DIB; 518 519 /* I/O page layout - XUB, RQB,RQC,RQD float based on number of DZ's */ 520 521 #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */ 522 #define IOLN_DZ 010 523 #define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2))) 524 #define IOLN_XUB 010 525 #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2))) 526 #define IOLN_RQB 004 527 #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB) 528 #define IOLN_RQC 004 529 #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC) 530 #define IOLN_RQD 004 531 #define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */ 532 #define IOLN_VH 020 533 #define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */ 534 #define IOLN_UBM (UBM_LNT_LW * sizeof (int32)) 535 #define IOBA_KG (IOPAGEBASE + 010700) /* KG11-A */ 536 #define IOLN_KG 006 537 #define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */ 538 #define IOLN_RQ 004 539 #define IOBA_SUP (IOPAGEBASE + 012200) /* supervisor APR's */ 540 #define IOLN_SUP 0100 541 #define IOBA_KIPDR (IOPAGEBASE + 012300) /* kernel APR's */ 542 #define IOLN_KIPDR 020 543 #define IOBA_KDPDR (IOPAGEBASE + 012320) 544 #define IOLN_KDPDR 020 545 #define IOBA_KIPAR (IOPAGEBASE + 012340) 546 #define IOLN_KIPAR 020 547 #define IOBA_KDPAR (IOPAGEBASE + 012360) 548 #define IOLN_KDPAR 020 549 #define IOBA_TU (IOPAGEBASE + 012440) /* TU */ 550 #define IOLN_TU 040 551 #define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */ 552 #define IOLN_MMR3 002 553 #define IOBA_TM (IOPAGEBASE + 012520) /* TM11 */ 554 #define IOLN_TM 014 555 #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */ 556 #define IOLN_TS 004 557 #define IOBA_PCLK (IOPAGEBASE + 012540) /* KW11P */ 558 #define IOLN_PCLK 006 559 #define IOBA_DC (IOPAGEBASE + 014000) /* DC11 */ 560 #define IOLN_DC (DCX_LINES * 010) 561 #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */ 562 #define IOLN_RL 012 563 #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */ 564 #define IOLN_XQ 020 565 #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */ 566 #define IOLN_XQB 020 567 #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */ 568 #define IOLN_TQ 004 569 #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */ 570 #define IOLN_XU 010 571 #define IOBA_DL (IOPAGEBASE + 016500) /* extra KL11/DL11 */ 572 #define IOLN_DL (DLX_LINES * 010) 573 #define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */ 574 #define IOLN_RP 054 575 #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */ 576 #define IOLN_CR 010 577 #define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */ 578 #define IOLN_RX 004 579 #define IOBA_RY (IOPAGEBASE + 017170) /* RY11 */ 580 #define IOLN_RY 004 581 #define IOBA_KE (IOPAGEBASE + 017300) /* KE11-A */ 582 #define IOLN_KE 020 583 #define IOBA_TC (IOPAGEBASE + 017340) /* TC11 */ 584 #define IOLN_TC 012 585 #define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */ 586 #define IOLN_QDSS 002 587 #define IOBA_RK (IOPAGEBASE + 017400) /* RK11 */ 588 #define IOLN_RK 020 589 #define IOBA_RC (IOPAGEBASE + 017440) /* RC11/RS64 */ 590 #define IOLN_RC 020 591 #define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */ 592 #define IOLN_HK 040 593 #define IOBA_RF (IOPAGEBASE + 017460) /* RF11 */ 594 #define IOLN_RF 020 595 #define IOBA_TA (IOPAGEBASE + 017500) /* TA11 */ 596 #define IOLN_TA 004 597 #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */ 598 #define IOLN_LPT 004 599 #define IOBA_CTL (IOPAGEBASE + 017520) /* board ctrl */ 600 #define IOLN_CTL 010 601 #define IOBA_CLK (IOPAGEBASE + 017546) /* KW11L */ 602 #define IOLN_CLK 002 603 #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */ 604 #define IOLN_PTR 004 605 #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ 606 #define IOLN_PTP 004 607 #define IOBA_TTI (IOPAGEBASE + 017560) /* DL11 rcv */ 608 #define IOLN_TTI 004 609 #define IOBA_TTO (IOPAGEBASE + 017564) /* DL11 xmt */ 610 #define IOLN_TTO 004 611 #define IOBA_SR (IOPAGEBASE + 017570) /* SR */ 612 #define IOLN_SR 002 613 #define IOBA_MMR012 (IOPAGEBASE + 017572) /* MMR0-2 */ 614 #define IOLN_MMR012 006 615 #define IOBA_UIPDR (IOPAGEBASE + 017600) /* user APR's */ 616 #define IOLN_UIPDR 020 617 #define IOBA_UDPDR (IOPAGEBASE + 017620) 618 #define IOLN_UDPDR 020 619 #define IOBA_UIPAR (IOPAGEBASE + 017640) 620 #define IOLN_UIPAR 020 621 #define IOBA_UDPAR (IOPAGEBASE + 017660) 622 #define IOLN_UDPAR 020 623 #define IOBA_GPR (IOPAGEBASE + 017700) /* GPR's */ 624 #define IOLN_GPR 010 625 #define IOBA_UCTL (IOPAGEBASE + 017730) /* UBA ctrl */ 626 #define IOLN_UCTL 010 627 #define IOBA_CPU (IOPAGEBASE + 017740) /* CPU reg */ 628 #define IOLN_CPU 036 629 #define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */ 630 #define IOLN_PSW 002 631 632 /* Interrupt assignments; within each level, priority is right to left 633 PIRQn has the highest priority with a level and is always bit <0> 634 On level 6, the clock is second highest priority */ 635 636 #define IPL_HLVL 8 /* # int levels */ 637 #define IPL_HMIN 4 /* lowest IO int level */ 638 639 #define INT_V_PIR7 0 /* BR7 */ 640 641 #define INT_V_PIR6 0 /* BR6 */ 642 #define INT_V_CLK 1 643 #define INT_V_PCLK 2 644 #define INT_V_DTA 3 645 #define INT_V_TA 4 646 647 #define INT_V_PIR5 0 /* BR5 */ 648 #define INT_V_RK 1 649 #define INT_V_RL 2 650 #define INT_V_RX 3 651 #define INT_V_TM 4 652 #define INT_V_RP 5 653 #define INT_V_TS 6 654 #define INT_V_HK 7 655 #define INT_V_RQ 8 656 #define INT_V_DZRX 9 657 #define INT_V_DZTX 10 658 #define INT_V_TQ 11 659 #define INT_V_RY 12 660 #define INT_V_XQ 13 661 #define INT_V_XU 14 662 #define INT_V_TU 15 663 #define INT_V_RF 16 664 #define INT_V_RC 17 665 666 #define INT_V_PIR4 0 /* BR4 */ 667 #define INT_V_TTI 1 668 #define INT_V_TTO 2 669 #define INT_V_PTR 3 670 #define INT_V_PTP 4 671 #define INT_V_LPT 5 672 #define INT_V_VHRX 6 673 #define INT_V_VHTX 7 674 #define INT_V_CR 8 675 #define INT_V_DLI 9 676 #define INT_V_DLO 10 677 #define INT_V_DCI 11 678 #define INT_V_DCO 12 679 680 #define INT_V_PIR3 0 /* BR3 */ 681 #define INT_V_PIR2 0 /* BR2 */ 682 #define INT_V_PIR1 0 /* BR1 */ 683 684 #define INT_PIR7 (1u << INT_V_PIR7) 685 #define INT_PIR6 (1u << INT_V_PIR6) 686 #define INT_CLK (1u << INT_V_CLK) 687 #define INT_PCLK (1u << INT_V_PCLK) 688 #define INT_DTA (1u << INT_V_DTA) 689 #define INT_TA (1u << INT_V_TA) 690 #define INT_PIR5 (1u << INT_V_PIR5) 691 #define INT_RK (1u << INT_V_RK) 692 #define INT_RL (1u << INT_V_RL) 693 #define INT_RX (1u << INT_V_RX) 694 #define INT_TM (1u << INT_V_TM) 695 #define INT_RP (1u << INT_V_RP) 696 #define INT_TS (1u << INT_V_TS) 697 #define INT_HK (1u << INT_V_HK) 698 #define INT_RQ (1u << INT_V_RQ) 699 #define INT_DZRX (1u << INT_V_DZRX) 700 #define INT_DZTX (1u << INT_V_DZTX) 701 #define INT_TQ (1u << INT_V_TQ) 702 #define INT_RY (1u << INT_V_RY) 703 #define INT_XQ (1u << INT_V_XQ) 704 #define INT_XU (1u << INT_V_XU) 705 #define INT_TU (1u << INT_V_TU) 706 #define INT_RF (1u << INT_V_RF) 707 #define INT_RC (1u << INT_V_RC) 708 #define INT_PIR4 (1u << INT_V_PIR4) 709 #define INT_TTI (1u << INT_V_TTI) 710 #define INT_TTO (1u << INT_V_TTO) 711 #define INT_PTR (1u << INT_V_PTR) 712 #define INT_PTP (1u << INT_V_PTP) 713 #define INT_LPT (1u << INT_V_LPT) 714 #define INT_VHRX (1u << INT_V_VHRX) 715 #define INT_VHTX (1u << INT_V_VHTX) 716 #define INT_CR (1u << INT_V_CR) 717 #define INT_DLI (1u << INT_V_DLI) 718 #define INT_DLO (1u << INT_V_DLO) 719 #define INT_DCI (1u << INT_V_DCI) 720 #define INT_DCO (1u << INT_V_DCO) 721 #define INT_PIR3 (1u << INT_V_PIR3) 722 #define INT_PIR2 (1u << INT_V_PIR2) 723 #define INT_PIR1 (1u << INT_V_PIR1) 724 725 #define INT_INTERNAL7 (INT_PIR7) 726 #define INT_INTERNAL6 (INT_PIR6 | INT_CLK) 727 #define INT_INTERNAL5 (INT_PIR5) 728 #define INT_INTERNAL4 (INT_PIR4) 729 #define INT_INTERNAL3 (INT_PIR3) 730 #define INT_INTERNAL2 (INT_PIR2) 731 #define INT_INTERNAL1 (INT_PIR1) 732 733 #define IPL_CLK 6 /* int pri levels */ 734 #define IPL_PCLK 6 735 #define IPL_DTA 6 736 #define IPL_TA 6 737 #define IPL_RK 5 738 #define IPL_RL 5 739 #define IPL_RX 5 740 #define IPL_TM 5 741 #define IPL_RP 5 742 #define IPL_TS 5 743 #define IPL_HK 5 744 #define IPL_RQ 5 745 #define IPL_DZRX 5 746 #define IPL_DZTX 5 747 #define IPL_TQ 5 748 #define IPL_RY 5 749 #define IPL_XQ 5 750 #define IPL_XU 5 751 #define IPL_TU 5 752 #define IPL_RF 5 753 #define IPL_RC 5 754 #define IPL_PTR 4 755 #define IPL_PTP 4 756 #define IPL_TTI 4 757 #define IPL_TTO 4 758 #define IPL_LPT 4 759 #define IPL_VHRX 4 760 #define IPL_VHTX 4 761 #define IPL_CR 4 762 #define IPL_DLI 4 763 #define IPL_DLO 4 764 #define IPL_DCI 4 765 #define IPL_DCO 4 766 767 #define IPL_PIR7 7 768 #define IPL_PIR6 6 769 #define IPL_PIR5 5 770 #define IPL_PIR4 4 771 #define IPL_PIR3 3 772 #define IPL_PIR2 2 773 #define IPL_PIR1 1 774 775 /* Device vectors */ 776 777 #define VEC_Q 0000 /* vector base */ 778 #define VEC_PIRQ 0240 779 #define VEC_TTI 0060 780 #define VEC_TTO 0064 781 #define VEC_PTR 0070 782 #define VEC_PTP 0074 783 #define VEC_CLK 0100 784 #define VEC_PCLK 0104 785 #define VEC_XQ 0120 786 #define VEC_XU 0120 787 #define VEC_RQ 0154 788 #define VEC_RL 0160 789 #define VEC_LPT 0200 790 #define VEC_RF 0204 791 #define VEC_HK 0210 792 #define VEC_RC 0210 793 #define VEC_RK 0220 794 #define VEC_DTA 0214 795 #define VEC_TM 0224 796 #define VEC_TS 0224 797 #define VEC_TU 0224 798 #define VEC_CR 0230 799 #define VEC_RP 0254 800 #define VEC_TQ 0260 801 #define VEC_TA 0260 802 #define VEC_RX 0264 803 #define VEC_RY 0264 804 #define VEC_DLI 0300 805 #define VEC_DLO 0304 806 #define VEC_DCI 0300 807 #define VEC_DCO 0304 808 #define VEC_DZRX 0300 809 #define VEC_DZTX 0304 810 #define VEC_VHRX 0310 811 #define VEC_VHTX 0314 812 813 /* Interrupt macros */ 814 815 #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) 816 #define IREQ(dv) int_req[IPL_##dv] 817 #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) 818 #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) 819 820 /* Massbus definitions */ 821 822 #define MBA_NUM 2 /* number of MBA's */ 823 #define MBA_RP 0 /* MBA for RP */ 824 #define MBA_TU 1 /* MBA for TU */ 825 #define MBA_RMASK 037 /* max 32 reg */ 826 #define MBE_NXD 1 /* nx drive */ 827 #define MBE_NXR 2 /* nx reg */ 828 #define MBE_GOE 3 /* err on GO */ 829 830 /* CPU and FPU macros */ 831 832 #define update_MM ((MMR0 & MMR0_FREEZE) == 0) 833 #define setTRAP(name) trap_req = trap_req | (name) 834 #define setCPUERR(name) CPUERR = CPUERR | (name) 835 #define ABORT(val) longjmp (save_env, (val)) 836 #define SP R[6] 837 #define PC R[7] 838 839 /* Function prototypes */ 840 841 int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); 842 int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); 843 int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); 844 int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); 845 846 int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf); 847 int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf); 848 int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf); 849 int32 mba_get_bc (uint32 mbus); 850 int32 mba_get_csr (uint32 mbus); 851 void mba_upd_ata (uint32 mbus, uint32 val); 852 void mba_set_exc (uint32 mbus); 853 void mba_set_don (uint32 mbus); 854 void mba_set_enbdis (uint32 mb, t_bool dis); 855 t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); 856 857 int32 clk_cosched (int32 wait); 858 859 #include "pdp11_io_lib.h" 860 861 #endif 862