xref: /openbsd/sys/arch/i386/pci/via82c586reg.h (revision 2041eff9)
1 /*	$OpenBSD: via82c586reg.h,v 1.5 2001/06/08 03:18:04 mickey Exp $	*/
2 /*	$NetBSD: via82c586reg.h,v 1.2 2000/04/22 15:00:41 uch Exp $	*/
3 
4 /*
5  * Copyright (c) 1999, by UCHIYAMA Yasushi
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. The name of the developer may NOT be used to endorse or promote products
14  *    derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /*
30  * Register definitions for the VIA 82c586 PCI-ISA bridge interrupt controller.
31  */
32 
33 #define	VP3_CFG_PIRQ_REG		0x54	/* PCI configuration space */
34 #define	VP3_CFG_KBDMISCCTRL12_REG	0x44
35 #define	VP3_CFG_IDEMISCCTRL3_REG	0x48
36 
37 #define	VP3_CFG_MISCCTRL2_SHIFT		24
38 #define	VP3_CFG_MISCCTRL2_MASK		0x0f
39 #define	VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE 0x20
40 #define	VP3_CFG_MISCCTRL2_REG(reg)					\
41 	(((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK)
42 
43 #define	VP3_CFG_TRIGGER_LEVEL		0
44 #define	VP3_CFG_TRIGGER_EDGE		1
45 
46 #define	VP3_CFG_TRIGGER_MASK		0x01
47 #define	VP3_CFG_TRIGGER_SHIFT_PIRQA	3
48 #define	VP3_CFG_TRIGGER_SHIFT_PIRQB	2
49 #define	VP3_CFG_TRIGGER_SHIFT_PIRQC	1
50 #define	VP3_CFG_TRIGGER_SHIFT_PIRQD	0
51 
52 #define	VP3_CFG_INTR_MASK		0x0f
53 #define	VP3_PIRQ_MASK			0xdefa
54 
55 #define	VP3_CFG_INTR_SHIFT_PIRQA	0x14
56 #define	VP3_CFG_INTR_SHIFT_PIRQB	0x10
57 #define	VP3_CFG_INTR_SHIFT_PIRQC	0x1c
58 #define	VP3_CFG_INTR_SHIFT_PIRQD	0x0c
59 #define	VP3_CFG_INTR_SHIFT_PIRQ0	0x10
60 #define	VP3_CFG_INTR_SHIFT_PIRQ1	0x08
61 #define	VP3_CFG_INTR_SHIFT_PIRQ2	0x00
62 
63 #define	VP3_PIRQ_NONE			0
64 #define	VP3_LEGAL_LINK(link)		((link) >= 0 && (link) <= 6)
65 #define	VP3_LEGAL_IRQ(irq)		((irq) >= 0 && (irq) <= 15 &&	\
66 					 ((1 << (irq)) & VP3_PIRQ_MASK) != 0)
67