1 /* 2 * Copyright � 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Li Xiaowei <xiaowei.a.li@intel.com> 26 * 27 */ 28 29 #ifndef _GEN75_VPP_VEBOX_H 30 #define _GEN75_VPP_VEBOX_H 31 32 #include <xf86drm.h> 33 #include <drm.h> 34 #include <i915_drm.h> 35 #include <intel_bufmgr.h> 36 #include <va/va_vpp.h> 37 #include "i965_drv_video.h" 38 39 #include "gen75_vpp_gpe.h" 40 41 #define INPUT_SURFACE 0 42 #define OUTPUT_SURFACE 1 43 44 #define VPP_DNDI_DN 0x00000001 45 #define VPP_DNDI_DI 0x00000002 46 #define VPP_DNDI_MASK 0x000000ff 47 #define VPP_IECP_STD_STE 0x00000100 48 #define VPP_IECP_ACE 0x00000200 49 #define VPP_IECP_TCC 0x00000400 50 #define VPP_IECP_PRO_AMP 0x00000800 51 #define VPP_IECP_CSC 0x00001000 52 #define VPP_IECP_AOI 0x00002000 53 #define VPP_IECP_CSC_TRANSFORM 0x00004000 54 #define VPP_IECP_MASK 0x0000ff00 55 #define VPP_SHARP 0x00010000 56 #define VPP_SHARP_MASK 0x000f0000 57 #define MAX_FILTER_SUM 8 58 59 #define PRE_FORMAT_CONVERT 0x01 60 #define POST_FORMAT_CONVERT 0x02 61 #define POST_SCALING_CONVERT 0x04 62 #define POST_COPY_CONVERT 0x08 63 64 enum { 65 FRAME_IN_CURRENT = 0, 66 FRAME_IN_PREVIOUS, 67 FRAME_IN_STMM, 68 FRAME_OUT_STMM, 69 FRAME_OUT_CURRENT_DN, 70 FRAME_OUT_CURRENT, 71 FRAME_OUT_PREVIOUS, 72 FRAME_OUT_STATISTIC, 73 FRAME_STORE_COUNT, 74 }; 75 76 enum SURFACE_FORMAT { 77 YCRCB_NORMAL = 0, 78 YCRCB_SWAPUVY, 79 YCRCB_SWAPUV, 80 YCRCB_SWAPY, 81 PLANAR_420_8, //NV12 82 PACKED_444A_8, 83 PACKED_422_16, 84 R10G10B10A2_UNORM_SRGB, 85 R8G8B8A8_UNORM_SRGB, 86 PACKED_444_16, 87 PLANAR_422_16, 88 Y8_UNORM, 89 PLANAR_420_16, 90 R16G16B16A16, 91 SURFACE_FORMAT_SUM 92 }; 93 94 typedef struct veb_frame_store { 95 struct object_surface *obj_surface; 96 VASurfaceID surface_id; /* always relative to the input surface */ 97 unsigned int is_internal_surface : 1; 98 unsigned int is_scratch_surface : 1; 99 } VEBFrameStore; 100 101 typedef struct veb_buffer { 102 dri_bo *bo; 103 char * ptr; 104 unsigned char valid; 105 } VEBBuffer; 106 107 struct intel_vebox_context { 108 struct intel_batchbuffer *batch; 109 110 struct object_surface *surface_input_object; 111 struct object_surface *surface_output_object; 112 VASurfaceID surface_input_vebox; 113 struct object_surface *surface_input_vebox_object; 114 VASurfaceID surface_output_vebox; 115 struct object_surface *surface_output_vebox_object; 116 VASurfaceID surface_output_scaled; 117 struct object_surface *surface_output_scaled_object; 118 119 unsigned int fourcc_input; 120 unsigned int fourcc_output; 121 122 int width_input; 123 int height_input; 124 int width_output; 125 int height_output; 126 127 VEBFrameStore frame_store[FRAME_STORE_COUNT]; 128 129 VEBBuffer dndi_state_table; 130 VEBBuffer iecp_state_table; 131 VEBBuffer gamut_state_table; 132 VEBBuffer vertex_state_table; 133 134 unsigned int filters_mask; 135 int current_output; 136 int current_output_type; /* 0:Both, 1:Previous, 2:Current */ 137 138 VAProcPipelineParameterBuffer * pipeline_param; 139 void * filter_dn; 140 void * filter_di; 141 void * filter_iecp_std; 142 void * filter_iecp_ace; 143 void * filter_iecp_tcc; 144 void * filter_iecp_amp; 145 146 unsigned int filter_iecp_amp_num_elements; 147 unsigned char format_convert_flags; 148 149 /* Temporary flags live until the current picture is processed */ 150 unsigned int is_iecp_enabled : 1; 151 unsigned int is_dn_enabled : 1; 152 unsigned int is_di_enabled : 1; 153 unsigned int is_di_adv_enabled : 1; 154 unsigned int is_first_frame : 1; 155 unsigned int is_second_field : 1; 156 157 struct vpp_gpe_context *vpp_gpe_ctx; 158 }; 159 160 VAStatus gen75_vebox_process_picture(VADriverContextP ctx, 161 struct intel_vebox_context *proc_ctx); 162 163 void gen75_vebox_context_destroy(VADriverContextP ctx, 164 struct intel_vebox_context *proc_ctx); 165 166 struct intel_vebox_context * gen75_vebox_context_init(VADriverContextP ctx); 167 168 VAStatus gen8_vebox_process_picture(VADriverContextP ctx, 169 struct intel_vebox_context *proc_ctx); 170 171 VAStatus gen9_vebox_process_picture(VADriverContextP ctx, 172 struct intel_vebox_context *proc_ctx); 173 174 VAStatus gen10_vebox_process_picture(VADriverContextP ctx, 175 struct intel_vebox_context *proc_ctx); 176 177 #endif 178