1 /*-
2 * Copyright (c) 2012-2017 Chelsio Communications, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28 #ifndef _T4FW_INTERFACE_H_
29 #define _T4FW_INTERFACE_H_
30
31 /******************************************************************************
32 * R E T U R N V A L U E S
33 ********************************/
34
35 enum fw_retval {
36 FW_SUCCESS = 0, /* completed successfully */
37 FW_EPERM = 1, /* operation not permitted */
38 FW_ENOENT = 2, /* no such file or directory */
39 FW_EIO = 5, /* input/output error; hw bad */
40 FW_ENOEXEC = 8, /* exec format error; inv microcode */
41 FW_EAGAIN = 11, /* try again */
42 FW_ENOMEM = 12, /* out of memory */
43 FW_EFAULT = 14, /* bad address; fw bad */
44 FW_EBUSY = 16, /* resource busy */
45 FW_EEXIST = 17, /* file exists */
46 FW_ENODEV = 19, /* no such device */
47 FW_EINVAL = 22, /* invalid argument */
48 FW_ENOSPC = 28, /* no space left on device */
49 FW_ENOSYS = 38, /* functionality not implemented */
50 FW_ENODATA = 61, /* no data available */
51 FW_EPROTO = 71, /* protocol error */
52 FW_EADDRINUSE = 98, /* address already in use */
53 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
54 FW_ENETDOWN = 100, /* network is down */
55 FW_ENETUNREACH = 101, /* network is unreachable */
56 FW_ENOBUFS = 105, /* no buffer space available */
57 FW_ETIMEDOUT = 110, /* timeout */
58 FW_EINPROGRESS = 115, /* fw internal */
59 FW_SCSI_ABORT_REQUESTED = 128, /* */
60 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
61 FW_SCSI_ABORTED = 130, /* */
62 FW_SCSI_CLOSE_REQUESTED = 131, /* */
63 FW_ERR_LINK_DOWN = 132, /* */
64 FW_RDEV_NOT_READY = 133, /* */
65 FW_ERR_RDEV_LOST = 134, /* */
66 FW_ERR_RDEV_LOGO = 135, /* */
67 FW_FCOE_NO_XCHG = 136, /* */
68 FW_SCSI_RSP_ERR = 137, /* */
69 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
70 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
71 FW_SCSI_OVER_FLOW_ERR = 140, /* */
72 FW_SCSI_DDP_ERR = 141, /* DDP error*/
73 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
74 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */
75 };
76
77 /******************************************************************************
78 * M E M O R Y T Y P E s
79 ******************************/
80
81 enum fw_memtype {
82 FW_MEMTYPE_EDC0 = 0x0,
83 FW_MEMTYPE_EDC1 = 0x1,
84 FW_MEMTYPE_EXTMEM = 0x2,
85 FW_MEMTYPE_FLASH = 0x4,
86 FW_MEMTYPE_INTERNAL = 0x5,
87 FW_MEMTYPE_EXTMEM1 = 0x6,
88 FW_MEMTYPE_HMA = 0x7,
89 };
90
91 /******************************************************************************
92 * W O R K R E Q U E S T s
93 ********************************/
94
95 enum fw_wr_opcodes {
96 FW_FRAG_WR = 0x1d,
97 FW_FILTER_WR = 0x02,
98 FW_ULPTX_WR = 0x04,
99 FW_TP_WR = 0x05,
100 FW_ETH_TX_PKT_WR = 0x08,
101 FW_ETH_TX_PKT2_WR = 0x44,
102 FW_ETH_TX_PKTS_WR = 0x09,
103 FW_ETH_TX_PKTS2_WR = 0x78,
104 FW_ETH_TX_EO_WR = 0x1c,
105 FW_EQ_FLUSH_WR = 0x1b,
106 FW_OFLD_CONNECTION_WR = 0x2f,
107 FW_FLOWC_WR = 0x0a,
108 FW_OFLD_TX_DATA_WR = 0x0b,
109 FW_CMD_WR = 0x10,
110 FW_ETH_TX_PKT_VM_WR = 0x11,
111 FW_ETH_TX_PKTS_VM_WR = 0x12,
112 FW_RI_RES_WR = 0x0c,
113 FW_RI_RDMA_WRITE_WR = 0x14,
114 FW_RI_SEND_WR = 0x15,
115 FW_RI_RDMA_READ_WR = 0x16,
116 FW_RI_RECV_WR = 0x17,
117 FW_RI_BIND_MW_WR = 0x18,
118 FW_RI_FR_NSMR_WR = 0x19,
119 FW_RI_FR_NSMR_TPTE_WR = 0x20,
120 FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
121 FW_RI_INV_LSTAG_WR = 0x1a,
122 FW_RI_SEND_IMMEDIATE_WR = 0x15,
123 FW_RI_ATOMIC_WR = 0x16,
124 FW_RI_WR = 0x0d,
125 FW_CHNET_IFCONF_WR = 0x6b,
126 FW_RDEV_WR = 0x38,
127 FW_FOISCSI_NODE_WR = 0x60,
128 FW_FOISCSI_CTRL_WR = 0x6a,
129 FW_FOISCSI_CHAP_WR = 0x6c,
130 FW_FCOE_ELS_CT_WR = 0x30,
131 FW_SCSI_WRITE_WR = 0x31,
132 FW_SCSI_READ_WR = 0x32,
133 FW_SCSI_CMD_WR = 0x33,
134 FW_SCSI_ABRT_CLS_WR = 0x34,
135 FW_SCSI_TGT_ACC_WR = 0x35,
136 FW_SCSI_TGT_XMIT_WR = 0x36,
137 FW_SCSI_TGT_RSP_WR = 0x37,
138 FW_POFCOE_TCB_WR = 0x42,
139 FW_POFCOE_ULPTX_WR = 0x43,
140 FW_ISCSI_TX_DATA_WR = 0x45,
141 FW_PTP_TX_PKT_WR = 0x46,
142 FW_TLSTX_DATA_WR = 0x68,
143 FW_TLS_TUNNEL_OFLD_WR = 0x69,
144 FW_CRYPTO_LOOKASIDE_WR = 0x6d,
145 FW_COISCSI_TGT_WR = 0x70,
146 FW_COISCSI_TGT_CONN_WR = 0x71,
147 FW_COISCSI_TGT_XMIT_WR = 0x72,
148 FW_COISCSI_STATS_WR = 0x73,
149 FW_ISNS_WR = 0x75,
150 FW_ISNS_XMIT_WR = 0x76,
151 FW_FILTER2_WR = 0x77,
152 FW_LASTC2E_WR = 0x80
153 };
154
155 /*
156 * Generic work request header flit0
157 */
158 struct fw_wr_hdr {
159 __be32 hi;
160 __be32 lo;
161 };
162
163 /* work request opcode (hi)
164 */
165 #define S_FW_WR_OP 24
166 #define M_FW_WR_OP 0xff
167 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
168 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
169
170 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
171 */
172 #define S_FW_WR_ATOMIC 23
173 #define M_FW_WR_ATOMIC 0x1
174 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
175 #define G_FW_WR_ATOMIC(x) \
176 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
177 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U)
178
179 /* flush flag (hi) - firmware flushes flushable work request buffered
180 * in the flow context.
181 */
182 #define S_FW_WR_FLUSH 22
183 #define M_FW_WR_FLUSH 0x1
184 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH)
185 #define G_FW_WR_FLUSH(x) \
186 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
187 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U)
188
189 /* completion flag (hi) - firmware generates a cpl_fw6_ack
190 */
191 #define S_FW_WR_COMPL 21
192 #define M_FW_WR_COMPL 0x1
193 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL)
194 #define G_FW_WR_COMPL(x) \
195 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
196 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U)
197
198
199 /* work request immediate data lengh (hi)
200 */
201 #define S_FW_WR_IMMDLEN 0
202 #define M_FW_WR_IMMDLEN 0xff
203 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
204 #define G_FW_WR_IMMDLEN(x) \
205 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
206
207 /* egress queue status update to associated ingress queue entry (lo)
208 */
209 #define S_FW_WR_EQUIQ 31
210 #define M_FW_WR_EQUIQ 0x1
211 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ)
212 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
213 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U)
214
215 /* egress queue status update to egress queue status entry (lo)
216 */
217 #define S_FW_WR_EQUEQ 30
218 #define M_FW_WR_EQUEQ 0x1
219 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
220 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
221 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
222
223 /* flow context identifier (lo)
224 */
225 #define S_FW_WR_FLOWID 8
226 #define M_FW_WR_FLOWID 0xfffff
227 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
228 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
229
230 /* length in units of 16-bytes (lo)
231 */
232 #define S_FW_WR_LEN16 0
233 #define M_FW_WR_LEN16 0xff
234 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
235 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
236
237 struct fw_frag_wr {
238 __be32 op_to_fragoff16;
239 __be32 flowid_len16;
240 __be64 r4;
241 };
242
243 #define S_FW_FRAG_WR_EOF 15
244 #define M_FW_FRAG_WR_EOF 0x1
245 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF)
246 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
247 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U)
248
249 #define S_FW_FRAG_WR_FRAGOFF16 8
250 #define M_FW_FRAG_WR_FRAGOFF16 0x7f
251 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16)
252 #define G_FW_FRAG_WR_FRAGOFF16(x) \
253 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
254
255 /* valid filter configurations for compressed tuple
256 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
257 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
258 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
259 * OV - Outer VLAN/VNIC_ID,
260 */
261 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3
262 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3
263 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B
264 #define HW_TPL_FR_MT_M_OV_P_FC 0x387
265 #define HW_TPL_FR_MT_E_PR_T 0x370
266 #define HW_TPL_FR_MT_E_PR_P_FC 0X363
267 #define HW_TPL_FR_MT_E_T_P_FC 0X353
268 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
269 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
270 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B
271 #define HW_TPL_FR_MT_T_OV_P_FC 0X317
272 #define HW_TPL_FR_M_E_PR_FC 0X2E1
273 #define HW_TPL_FR_M_E_T_FC 0X2D1
274 #define HW_TPL_FR_M_PR_IV_FC 0X2A9
275 #define HW_TPL_FR_M_PR_OV_FC 0X2A5
276 #define HW_TPL_FR_M_T_IV_FC 0X299
277 #define HW_TPL_FR_M_T_OV_FC 0X295
278 #define HW_TPL_FR_E_PR_T_P 0X272
279 #define HW_TPL_FR_E_PR_T_FC 0X271
280 #define HW_TPL_FR_E_IV_FC 0X249
281 #define HW_TPL_FR_E_OV_FC 0X245
282 #define HW_TPL_FR_PR_T_IV_FC 0X239
283 #define HW_TPL_FR_PR_T_OV_FC 0X235
284 #define HW_TPL_FR_IV_OV_FC 0X20D
285 #define HW_TPL_MT_M_E_PR 0X1E0
286 #define HW_TPL_MT_M_E_T 0X1D0
287 #define HW_TPL_MT_E_PR_T_FC 0X171
288 #define HW_TPL_MT_E_IV 0X148
289 #define HW_TPL_MT_E_OV 0X144
290 #define HW_TPL_MT_PR_T_IV 0X138
291 #define HW_TPL_MT_PR_T_OV 0X134
292 #define HW_TPL_M_E_PR_P 0X0E2
293 #define HW_TPL_M_E_T_P 0X0D2
294 #define HW_TPL_E_PR_T_P_FC 0X073
295 #define HW_TPL_E_IV_P 0X04A
296 #define HW_TPL_E_OV_P 0X046
297 #define HW_TPL_PR_T_IV_P 0X03A
298 #define HW_TPL_PR_T_OV_P 0X036
299
300 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
301 enum fw_filter_wr_cookie {
302 FW_FILTER_WR_SUCCESS,
303 FW_FILTER_WR_FLT_ADDED,
304 FW_FILTER_WR_FLT_DELETED,
305 FW_FILTER_WR_SMT_TBL_FULL,
306 FW_FILTER_WR_EINVAL,
307 };
308
309 enum fw_filter_wr_nat_mode {
310 FW_FILTER_WR_NATMODE_NONE = 0,
311 FW_FILTER_WR_NATMODE_DIP ,
312 FW_FILTER_WR_NATMODE_DIPDP,
313 FW_FILTER_WR_NATMODE_DIPDPSIP,
314 FW_FILTER_WR_NATMODE_DIPDPSP,
315 FW_FILTER_WR_NATMODE_SIPSP,
316 FW_FILTER_WR_NATMODE_DIPSIPSP,
317 FW_FILTER_WR_NATMODE_FOURTUPLE,
318 };
319
320 struct fw_filter_wr {
321 __be32 op_pkd;
322 __be32 len16_pkd;
323 __be64 r3;
324 __be32 tid_to_iq;
325 __be32 del_filter_to_l2tix;
326 __be16 ethtype;
327 __be16 ethtypem;
328 __u8 frag_to_ovlan_vldm;
329 __u8 smac_sel;
330 __be16 rx_chan_rx_rpl_iq;
331 __be32 maci_to_matchtypem;
332 __u8 ptcl;
333 __u8 ptclm;
334 __u8 ttyp;
335 __u8 ttypm;
336 __be16 ivlan;
337 __be16 ivlanm;
338 __be16 ovlan;
339 __be16 ovlanm;
340 __u8 lip[16];
341 __u8 lipm[16];
342 __u8 fip[16];
343 __u8 fipm[16];
344 __be16 lp;
345 __be16 lpm;
346 __be16 fp;
347 __be16 fpm;
348 __be16 r7;
349 __u8 sma[6];
350 };
351
352 struct fw_filter2_wr {
353 __be32 op_pkd;
354 __be32 len16_pkd;
355 __be64 r3;
356 __be32 tid_to_iq;
357 __be32 del_filter_to_l2tix;
358 __be16 ethtype;
359 __be16 ethtypem;
360 __u8 frag_to_ovlan_vldm;
361 __u8 smac_sel;
362 __be16 rx_chan_rx_rpl_iq;
363 __be32 maci_to_matchtypem;
364 __u8 ptcl;
365 __u8 ptclm;
366 __u8 ttyp;
367 __u8 ttypm;
368 __be16 ivlan;
369 __be16 ivlanm;
370 __be16 ovlan;
371 __be16 ovlanm;
372 __u8 lip[16];
373 __u8 lipm[16];
374 __u8 fip[16];
375 __u8 fipm[16];
376 __be16 lp;
377 __be16 lpm;
378 __be16 fp;
379 __be16 fpm;
380 __be16 r7;
381 __u8 sma[6];
382 __be16 r8;
383 __u8 filter_type_swapmac;
384 __u8 natmode_to_ulp_type;
385 __be16 newlport;
386 __be16 newfport;
387 __u8 newlip[16];
388 __u8 newfip[16];
389 __be32 natseqcheck;
390 __be32 r9;
391 __be64 r10;
392 __be64 r11;
393 __be64 r12;
394 __be64 r13;
395 };
396
397 #define S_FW_FILTER_WR_TID 12
398 #define M_FW_FILTER_WR_TID 0xfffff
399 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
400 #define G_FW_FILTER_WR_TID(x) \
401 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
402
403 #define S_FW_FILTER_WR_RQTYPE 11
404 #define M_FW_FILTER_WR_RQTYPE 0x1
405 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
406 #define G_FW_FILTER_WR_RQTYPE(x) \
407 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
408 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
409
410 #define S_FW_FILTER_WR_NOREPLY 10
411 #define M_FW_FILTER_WR_NOREPLY 0x1
412 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
413 #define G_FW_FILTER_WR_NOREPLY(x) \
414 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
415 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
416
417 #define S_FW_FILTER_WR_IQ 0
418 #define M_FW_FILTER_WR_IQ 0x3ff
419 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
420 #define G_FW_FILTER_WR_IQ(x) \
421 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
422
423 #define S_FW_FILTER_WR_DEL_FILTER 31
424 #define M_FW_FILTER_WR_DEL_FILTER 0x1
425 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
426 #define G_FW_FILTER_WR_DEL_FILTER(x) \
427 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
428 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
429
430 #define S_FW_FILTER2_WR_DROP_ENCAP 30
431 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1
432 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP)
433 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \
434 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
435 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U)
436
437 #define S_FW_FILTER2_WR_TX_LOOP 29
438 #define M_FW_FILTER2_WR_TX_LOOP 0x1
439 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP)
440 #define G_FW_FILTER2_WR_TX_LOOP(x) \
441 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
442 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U)
443
444 #define S_FW_FILTER_WR_RPTTID 25
445 #define M_FW_FILTER_WR_RPTTID 0x1
446 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
447 #define G_FW_FILTER_WR_RPTTID(x) \
448 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
449 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
450
451 #define S_FW_FILTER_WR_DROP 24
452 #define M_FW_FILTER_WR_DROP 0x1
453 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
454 #define G_FW_FILTER_WR_DROP(x) \
455 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
456 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
457
458 #define S_FW_FILTER_WR_DIRSTEER 23
459 #define M_FW_FILTER_WR_DIRSTEER 0x1
460 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
461 #define G_FW_FILTER_WR_DIRSTEER(x) \
462 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
463 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
464
465 #define S_FW_FILTER_WR_MASKHASH 22
466 #define M_FW_FILTER_WR_MASKHASH 0x1
467 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
468 #define G_FW_FILTER_WR_MASKHASH(x) \
469 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
470 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
471
472 #define S_FW_FILTER_WR_DIRSTEERHASH 21
473 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
474 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
475 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
476 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
477 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
478
479 #define S_FW_FILTER_WR_LPBK 20
480 #define M_FW_FILTER_WR_LPBK 0x1
481 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
482 #define G_FW_FILTER_WR_LPBK(x) \
483 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
484 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
485
486 #define S_FW_FILTER_WR_DMAC 19
487 #define M_FW_FILTER_WR_DMAC 0x1
488 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
489 #define G_FW_FILTER_WR_DMAC(x) \
490 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
491 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
492
493 #define S_FW_FILTER_WR_SMAC 18
494 #define M_FW_FILTER_WR_SMAC 0x1
495 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
496 #define G_FW_FILTER_WR_SMAC(x) \
497 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
498 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
499
500 #define S_FW_FILTER_WR_INSVLAN 17
501 #define M_FW_FILTER_WR_INSVLAN 0x1
502 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
503 #define G_FW_FILTER_WR_INSVLAN(x) \
504 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
505 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
506
507 #define S_FW_FILTER_WR_RMVLAN 16
508 #define M_FW_FILTER_WR_RMVLAN 0x1
509 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
510 #define G_FW_FILTER_WR_RMVLAN(x) \
511 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
512 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
513
514 #define S_FW_FILTER_WR_HITCNTS 15
515 #define M_FW_FILTER_WR_HITCNTS 0x1
516 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
517 #define G_FW_FILTER_WR_HITCNTS(x) \
518 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
519 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
520
521 #define S_FW_FILTER_WR_TXCHAN 13
522 #define M_FW_FILTER_WR_TXCHAN 0x3
523 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
524 #define G_FW_FILTER_WR_TXCHAN(x) \
525 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
526
527 #define S_FW_FILTER_WR_PRIO 12
528 #define M_FW_FILTER_WR_PRIO 0x1
529 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
530 #define G_FW_FILTER_WR_PRIO(x) \
531 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
532 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
533
534 #define S_FW_FILTER_WR_L2TIX 0
535 #define M_FW_FILTER_WR_L2TIX 0xfff
536 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
537 #define G_FW_FILTER_WR_L2TIX(x) \
538 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
539
540 #define S_FW_FILTER_WR_FRAG 7
541 #define M_FW_FILTER_WR_FRAG 0x1
542 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
543 #define G_FW_FILTER_WR_FRAG(x) \
544 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
545 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
546
547 #define S_FW_FILTER_WR_FRAGM 6
548 #define M_FW_FILTER_WR_FRAGM 0x1
549 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
550 #define G_FW_FILTER_WR_FRAGM(x) \
551 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
552 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
553
554 #define S_FW_FILTER_WR_IVLAN_VLD 5
555 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
556 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
557 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
558 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
559 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
560
561 #define S_FW_FILTER_WR_OVLAN_VLD 4
562 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
563 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
564 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
565 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
566 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
567
568 #define S_FW_FILTER_WR_IVLAN_VLDM 3
569 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
570 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
571 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
572 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
573 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
574
575 #define S_FW_FILTER_WR_OVLAN_VLDM 2
576 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
577 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
578 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
579 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
580 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
581
582 #define S_FW_FILTER_WR_RX_CHAN 15
583 #define M_FW_FILTER_WR_RX_CHAN 0x1
584 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
585 #define G_FW_FILTER_WR_RX_CHAN(x) \
586 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
587 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
588
589 #define S_FW_FILTER_WR_RX_RPL_IQ 0
590 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
591 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
592 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
593 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
594
595 #define S_FW_FILTER2_WR_FILTER_TYPE 1
596 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1
597 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE)
598 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \
599 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
600 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U)
601
602 #define S_FW_FILTER2_WR_SWAPMAC 0
603 #define M_FW_FILTER2_WR_SWAPMAC 0x1
604 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
605 #define G_FW_FILTER2_WR_SWAPMAC(x) \
606 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
607 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U)
608
609 #define S_FW_FILTER2_WR_NATMODE 5
610 #define M_FW_FILTER2_WR_NATMODE 0x7
611 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
612 #define G_FW_FILTER2_WR_NATMODE(x) \
613 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
614
615 #define S_FW_FILTER2_WR_NATFLAGCHECK 4
616 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1
617 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
618 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \
619 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
620 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U)
621
622 #define S_FW_FILTER2_WR_ULP_TYPE 0
623 #define M_FW_FILTER2_WR_ULP_TYPE 0xf
624 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
625 #define G_FW_FILTER2_WR_ULP_TYPE(x) \
626 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
627
628 #define S_FW_FILTER_WR_MACI 23
629 #define M_FW_FILTER_WR_MACI 0x1ff
630 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
631 #define G_FW_FILTER_WR_MACI(x) \
632 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
633
634 #define S_FW_FILTER_WR_MACIM 14
635 #define M_FW_FILTER_WR_MACIM 0x1ff
636 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
637 #define G_FW_FILTER_WR_MACIM(x) \
638 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
639
640 #define S_FW_FILTER_WR_FCOE 13
641 #define M_FW_FILTER_WR_FCOE 0x1
642 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
643 #define G_FW_FILTER_WR_FCOE(x) \
644 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
645 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
646
647 #define S_FW_FILTER_WR_FCOEM 12
648 #define M_FW_FILTER_WR_FCOEM 0x1
649 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
650 #define G_FW_FILTER_WR_FCOEM(x) \
651 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
652 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
653
654 #define S_FW_FILTER_WR_PORT 9
655 #define M_FW_FILTER_WR_PORT 0x7
656 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
657 #define G_FW_FILTER_WR_PORT(x) \
658 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
659
660 #define S_FW_FILTER_WR_PORTM 6
661 #define M_FW_FILTER_WR_PORTM 0x7
662 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
663 #define G_FW_FILTER_WR_PORTM(x) \
664 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
665
666 #define S_FW_FILTER_WR_MATCHTYPE 3
667 #define M_FW_FILTER_WR_MATCHTYPE 0x7
668 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
669 #define G_FW_FILTER_WR_MATCHTYPE(x) \
670 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
671
672 #define S_FW_FILTER_WR_MATCHTYPEM 0
673 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
674 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
675 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
676 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
677
678 struct fw_ulptx_wr {
679 __be32 op_to_compl;
680 __be32 flowid_len16;
681 __u64 cookie;
682 };
683
684 /* flag for packet type - control packet (0), data packet (1)
685 */
686 #define S_FW_ULPTX_WR_DATA 28
687 #define M_FW_ULPTX_WR_DATA 0x1
688 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA)
689 #define G_FW_ULPTX_WR_DATA(x) \
690 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
691 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U)
692
693 struct fw_tp_wr {
694 __be32 op_to_immdlen;
695 __be32 flowid_len16;
696 __u64 cookie;
697 };
698
699 struct fw_eth_tx_pkt_wr {
700 __be32 op_immdlen;
701 __be32 equiq_to_len16;
702 __be64 r3;
703 };
704
705 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
706 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
707 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
708 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
709 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
710
711 struct fw_eth_tx_pkt2_wr {
712 __be32 op_immdlen;
713 __be32 equiq_to_len16;
714 __be32 r3;
715 __be32 L4ChkDisable_to_IpHdrLen;
716 };
717
718 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
719 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
720 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
721 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
722 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
723
724 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
725 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
726 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
727 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
728 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
729 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
730 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
731 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
732 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
733
734 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
735 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
736 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
737 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
738 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
739 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
740 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
741 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
742 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
743
744 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28
745 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
746 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
747 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
748 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
749 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
750
751 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
752 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
753 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
754 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
755 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
756
757 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
758 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
759 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
760 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
761 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
762
763 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
764 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
765 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
766 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
767 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
768
769 struct fw_eth_tx_pkts_wr {
770 __be32 op_pkd;
771 __be32 equiq_to_len16;
772 __be32 r3;
773 __be16 plen;
774 __u8 npkt;
775 __u8 type;
776 };
777
778 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0
779 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff
780 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
781 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \
782 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
783
784 struct fw_eth_tx_pkt_ptp_wr {
785 __be32 op_immdlen;
786 __be32 equiq_to_len16;
787 __be64 r3;
788 };
789
790 enum fw_eth_tx_eo_type {
791 FW_ETH_TX_EO_TYPE_UDPSEG,
792 FW_ETH_TX_EO_TYPE_TCPSEG,
793 FW_ETH_TX_EO_TYPE_NVGRESEG,
794 FW_ETH_TX_EO_TYPE_VXLANSEG,
795 FW_ETH_TX_EO_TYPE_GENEVESEG,
796 };
797
798 struct fw_eth_tx_eo_wr {
799 __be32 op_immdlen;
800 __be32 equiq_to_len16;
801 __be64 r3;
802 union fw_eth_tx_eo {
803 struct fw_eth_tx_eo_udpseg {
804 __u8 type;
805 __u8 ethlen;
806 __be16 iplen;
807 __u8 udplen;
808 __u8 rtplen;
809 __be16 r4;
810 __be16 mss;
811 __be16 schedpktsize;
812 __be32 plen;
813 } udpseg;
814 struct fw_eth_tx_eo_tcpseg {
815 __u8 type;
816 __u8 ethlen;
817 __be16 iplen;
818 __u8 tcplen;
819 __u8 tsclk_tsoff;
820 __be16 r4;
821 __be16 mss;
822 __be16 r5;
823 __be32 plen;
824 } tcpseg;
825 struct fw_eth_tx_eo_nvgreseg {
826 __u8 type;
827 __u8 iphdroffout;
828 __be16 grehdroff;
829 __be16 iphdroffin;
830 __be16 tcphdroffin;
831 __be16 mss;
832 __be16 r4;
833 __be32 plen;
834 } nvgreseg;
835 struct fw_eth_tx_eo_vxlanseg {
836 __u8 type;
837 __u8 iphdroffout;
838 __be16 vxlanhdroff;
839 __be16 iphdroffin;
840 __be16 tcphdroffin;
841 __be16 mss;
842 __be16 r4;
843 __be32 plen;
844
845 } vxlanseg;
846 struct fw_eth_tx_eo_geneveseg {
847 __u8 type;
848 __u8 iphdroffout;
849 __be16 genevehdroff;
850 __be16 iphdroffin;
851 __be16 tcphdroffin;
852 __be16 mss;
853 __be16 r4;
854 __be32 plen;
855 } geneveseg;
856 } u;
857 };
858
859 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0
860 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
861 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
862 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
863 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
864
865 #define S_FW_ETH_TX_EO_WR_TSCLK 6
866 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3
867 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
868 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \
869 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
870
871 #define S_FW_ETH_TX_EO_WR_TSOFF 0
872 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
873 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
874 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \
875 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
876
877 struct fw_eq_flush_wr {
878 __u8 opcode;
879 __u8 r1[3];
880 __be32 equiq_to_len16;
881 __be64 r3;
882 };
883
884 struct fw_ofld_connection_wr {
885 __be32 op_compl;
886 __be32 len16_pkd;
887 __u64 cookie;
888 __be64 r2;
889 __be64 r3;
890 struct fw_ofld_connection_le {
891 __be32 version_cpl;
892 __be32 filter;
893 __be32 r1;
894 __be16 lport;
895 __be16 pport;
896 union fw_ofld_connection_leip {
897 struct fw_ofld_connection_le_ipv4 {
898 __be32 pip;
899 __be32 lip;
900 __be64 r0;
901 __be64 r1;
902 __be64 r2;
903 } ipv4;
904 struct fw_ofld_connection_le_ipv6 {
905 __be64 pip_hi;
906 __be64 pip_lo;
907 __be64 lip_hi;
908 __be64 lip_lo;
909 } ipv6;
910 } u;
911 } le;
912 struct fw_ofld_connection_tcb {
913 __be32 t_state_to_astid;
914 __be16 cplrxdataack_cplpassacceptrpl;
915 __be16 rcv_adv;
916 __be32 rcv_nxt;
917 __be32 tx_max;
918 __be64 opt0;
919 __be32 opt2;
920 __be32 r1;
921 __be64 r2;
922 __be64 r3;
923 } tcb;
924 };
925
926 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
927 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
928 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
929 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
930 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
931 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
932 M_FW_OFLD_CONNECTION_WR_VERSION)
933 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)
934
935 #define S_FW_OFLD_CONNECTION_WR_CPL 30
936 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
937 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
938 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
939 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
940 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
941
942 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
943 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
944 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
945 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
946 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
947 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
948 M_FW_OFLD_CONNECTION_WR_T_STATE)
949
950 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
951 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
952 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
953 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
954 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
955 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
956 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
957
958 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
959 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
960 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
961 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
962 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
963 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
964
965 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
966 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
967 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
968 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
969 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
970 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
971 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
972 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
973 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
974
975 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
976 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
977 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
978 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
979 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
980 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
981 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
982 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
983 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
984
985 enum fw_flowc_mnem_tcpstate {
986 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
987 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
988 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
989 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
990 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
991 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
992 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
993 * will resend FIN - equiv ESTAB
994 */
995 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
996 * will resend FIN but have
997 * received FIN
998 */
999 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
1000 * will resend FIN but have
1001 * received FIN
1002 */
1003 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
1004 * waiting for FIN
1005 */
1006 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
1007 };
1008
1009 enum fw_flowc_mnem_eostate {
1010 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
1011 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
1012 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
1013 * outstanding payload
1014 */
1015 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
1016 * discarding outstanding payload
1017 */
1018 };
1019
1020 enum fw_flowc_mnem {
1021 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
1022 FW_FLOWC_MNEM_CH = 1,
1023 FW_FLOWC_MNEM_PORT = 2,
1024 FW_FLOWC_MNEM_IQID = 3,
1025 FW_FLOWC_MNEM_SNDNXT = 4,
1026 FW_FLOWC_MNEM_RCVNXT = 5,
1027 FW_FLOWC_MNEM_SNDBUF = 6,
1028 FW_FLOWC_MNEM_MSS = 7,
1029 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
1030 FW_FLOWC_MNEM_TCPSTATE = 9,
1031 FW_FLOWC_MNEM_EOSTATE = 10,
1032 FW_FLOWC_MNEM_SCHEDCLASS = 11,
1033 FW_FLOWC_MNEM_DCBPRIO = 12,
1034 FW_FLOWC_MNEM_SND_SCALE = 13,
1035 FW_FLOWC_MNEM_RCV_SCALE = 14,
1036 FW_FLOWC_MNEM_ULP_MODE = 15,
1037 FW_FLOWC_MNEM_MAX = 16,
1038 };
1039
1040 struct fw_flowc_mnemval {
1041 __u8 mnemonic;
1042 __u8 r4[3];
1043 __be32 val;
1044 };
1045
1046 struct fw_flowc_wr {
1047 __be32 op_to_nparams;
1048 __be32 flowid_len16;
1049 #ifndef C99_NOT_SUPPORTED
1050 struct fw_flowc_mnemval mnemval[0];
1051 #endif
1052 };
1053
1054 #define S_FW_FLOWC_WR_NPARAMS 0
1055 #define M_FW_FLOWC_WR_NPARAMS 0xff
1056 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS)
1057 #define G_FW_FLOWC_WR_NPARAMS(x) \
1058 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1059
1060 struct fw_ofld_tx_data_wr {
1061 __be32 op_to_immdlen;
1062 __be32 flowid_len16;
1063 __be32 plen;
1064 __be32 lsodisable_to_flags;
1065 };
1066
1067 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
1068 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
1069 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1070 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1071 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1072 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1073 M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1074 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1075
1076 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
1077 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
1078 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1079 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1080 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1081 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1082 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1083
1084 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
1085 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
1086 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1087 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1088 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1089 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1090 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1091 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
1092 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1093
1094 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0
1095 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff
1096 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1097 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \
1098 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1099
1100
1101 /* Use fw_ofld_tx_data_wr structure */
1102 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10
1103 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff
1104 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1105 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1106 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1107 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1108
1109 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9
1110 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1
1111 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1112 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1113 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1114 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1115 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1116 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \
1117 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1118
1119 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8
1120 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1
1121 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1122 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1123 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1124 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1125 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1126 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \
1127 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1128
1129 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7
1130 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1
1131 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1132 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1133 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1134 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1135 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1136 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \
1137 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1138
1139 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6
1140 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1
1141 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1142 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1143 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1144 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1145 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1146 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \
1147 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1148
1149 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0
1150 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f
1151 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1152 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1153 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1154 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1155
1156 struct fw_cmd_wr {
1157 __be32 op_dma;
1158 __be32 len16_pkd;
1159 __be64 cookie_daddr;
1160 };
1161
1162 #define S_FW_CMD_WR_DMA 17
1163 #define M_FW_CMD_WR_DMA 0x1
1164 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA)
1165 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1166 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)
1167
1168 struct fw_eth_tx_pkt_vm_wr {
1169 __be32 op_immdlen;
1170 __be32 equiq_to_len16;
1171 __be32 r3[2];
1172 __u8 ethmacdst[6];
1173 __u8 ethmacsrc[6];
1174 __be16 ethtype;
1175 __be16 vlantci;
1176 };
1177
1178 struct fw_eth_tx_pkts_vm_wr {
1179 __be32 op_pkd;
1180 __be32 equiq_to_len16;
1181 __be32 r3;
1182 __be16 plen;
1183 __u8 npkt;
1184 __u8 r4;
1185 __u8 ethmacdst[6];
1186 __u8 ethmacsrc[6];
1187 __be16 ethtype;
1188 __be16 vlantci;
1189 };
1190
1191 /******************************************************************************
1192 * R I W O R K R E Q U E S T s
1193 **************************************/
1194
1195 enum fw_ri_wr_opcode {
1196 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
1197 FW_RI_READ_REQ = 0x1,
1198 FW_RI_READ_RESP = 0x2,
1199 FW_RI_SEND = 0x3,
1200 FW_RI_SEND_WITH_INV = 0x4,
1201 FW_RI_SEND_WITH_SE = 0x5,
1202 FW_RI_SEND_WITH_SE_INV = 0x6,
1203 FW_RI_TERMINATE = 0x7,
1204 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
1205 FW_RI_BIND_MW = 0x9,
1206 FW_RI_FAST_REGISTER = 0xa,
1207 FW_RI_LOCAL_INV = 0xb,
1208 FW_RI_QP_MODIFY = 0xc,
1209 FW_RI_BYPASS = 0xd,
1210 FW_RI_RECEIVE = 0xe,
1211 #if 0
1212 FW_RI_SEND_IMMEDIATE = 0x8,
1213 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9,
1214 FW_RI_ATOMIC_REQUEST = 0xa,
1215 FW_RI_ATOMIC_RESPONSE = 0xb,
1216
1217 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */
1218 FW_RI_FAST_REGISTER = 0xd,
1219 FW_RI_LOCAL_INV = 0xe,
1220 #endif
1221 FW_RI_SGE_EC_CR_RETURN = 0xf,
1222 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT,
1223 };
1224
1225 enum fw_ri_wr_flags {
1226 FW_RI_COMPLETION_FLAG = 0x01,
1227 FW_RI_NOTIFICATION_FLAG = 0x02,
1228 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
1229 FW_RI_READ_FENCE_FLAG = 0x08,
1230 FW_RI_LOCAL_FENCE_FLAG = 0x10,
1231 FW_RI_RDMA_READ_INVALIDATE = 0x20,
1232 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
1233 };
1234
1235 enum fw_ri_mpa_attrs {
1236 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
1237 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
1238 FW_RI_MPA_CRC_ENABLE = 0x04,
1239 FW_RI_MPA_IETF_ENABLE = 0x08
1240 };
1241
1242 enum fw_ri_qp_caps {
1243 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
1244 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
1245 FW_RI_QP_BIND_ENABLE = 0x04,
1246 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
1247 FW_RI_QP_STAG0_ENABLE = 0x10,
1248 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1249 };
1250
1251 enum fw_ri_addr_type {
1252 FW_RI_ZERO_BASED_TO = 0x00,
1253 FW_RI_VA_BASED_TO = 0x01
1254 };
1255
1256 enum fw_ri_mem_perms {
1257 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
1258 FW_RI_MEM_ACCESS_REM_READ = 0x02,
1259 FW_RI_MEM_ACCESS_REM = 0x03,
1260 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
1261 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
1262 FW_RI_MEM_ACCESS_LOCAL = 0x0C
1263 };
1264
1265 enum fw_ri_stag_type {
1266 FW_RI_STAG_NSMR = 0x00,
1267 FW_RI_STAG_SMR = 0x01,
1268 FW_RI_STAG_MW = 0x02,
1269 FW_RI_STAG_MW_RELAXED = 0x03
1270 };
1271
1272 enum fw_ri_data_op {
1273 FW_RI_DATA_IMMD = 0x81,
1274 FW_RI_DATA_DSGL = 0x82,
1275 FW_RI_DATA_ISGL = 0x83
1276 };
1277
1278 enum fw_ri_sgl_depth {
1279 FW_RI_SGL_DEPTH_MAX_SQ = 16,
1280 FW_RI_SGL_DEPTH_MAX_RQ = 4
1281 };
1282
1283 enum fw_ri_cqe_err {
1284 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */
1285 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */
1286 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */
1287 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */
1288 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */
1289 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */
1290 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */
1291 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1292 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1293 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */
1294 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1295 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */
1296 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */
1297 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */
1298 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */
1299 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */
1300 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */
1301 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */
1302 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */
1303 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */
1304 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */
1305 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */
1306 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1307 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */
1308 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */
1309 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */
1310 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */
1311 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */
1312
1313 };
1314
1315 struct fw_ri_dsge_pair {
1316 __be32 len[2];
1317 __be64 addr[2];
1318 };
1319
1320 struct fw_ri_dsgl {
1321 __u8 op;
1322 __u8 r1;
1323 __be16 nsge;
1324 __be32 len0;
1325 __be64 addr0;
1326 #ifndef C99_NOT_SUPPORTED
1327 struct fw_ri_dsge_pair sge[0];
1328 #endif
1329 };
1330
1331 struct fw_ri_sge {
1332 __be32 stag;
1333 __be32 len;
1334 __be64 to;
1335 };
1336
1337 struct fw_ri_isgl {
1338 __u8 op;
1339 __u8 r1;
1340 __be16 nsge;
1341 __be32 r2;
1342 #ifndef C99_NOT_SUPPORTED
1343 struct fw_ri_sge sge[0];
1344 #endif
1345 };
1346
1347 struct fw_ri_immd {
1348 __u8 op;
1349 __u8 r1;
1350 __be16 r2;
1351 __be32 immdlen;
1352 #ifndef C99_NOT_SUPPORTED
1353 __u8 data[0];
1354 #endif
1355 };
1356
1357 struct fw_ri_tpte {
1358 __be32 valid_to_pdid;
1359 __be32 locread_to_qpid;
1360 __be32 nosnoop_pbladdr;
1361 __be32 len_lo;
1362 __be32 va_hi;
1363 __be32 va_lo_fbo;
1364 __be32 dca_mwbcnt_pstag;
1365 __be32 len_hi;
1366 };
1367
1368 #define S_FW_RI_TPTE_VALID 31
1369 #define M_FW_RI_TPTE_VALID 0x1
1370 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
1371 #define G_FW_RI_TPTE_VALID(x) \
1372 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1373 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
1374
1375 #define S_FW_RI_TPTE_STAGKEY 23
1376 #define M_FW_RI_TPTE_STAGKEY 0xff
1377 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
1378 #define G_FW_RI_TPTE_STAGKEY(x) \
1379 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1380
1381 #define S_FW_RI_TPTE_STAGSTATE 22
1382 #define M_FW_RI_TPTE_STAGSTATE 0x1
1383 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
1384 #define G_FW_RI_TPTE_STAGSTATE(x) \
1385 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1386 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
1387
1388 #define S_FW_RI_TPTE_STAGTYPE 20
1389 #define M_FW_RI_TPTE_STAGTYPE 0x3
1390 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
1391 #define G_FW_RI_TPTE_STAGTYPE(x) \
1392 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1393
1394 #define S_FW_RI_TPTE_PDID 0
1395 #define M_FW_RI_TPTE_PDID 0xfffff
1396 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
1397 #define G_FW_RI_TPTE_PDID(x) \
1398 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1399
1400 #define S_FW_RI_TPTE_PERM 28
1401 #define M_FW_RI_TPTE_PERM 0xf
1402 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
1403 #define G_FW_RI_TPTE_PERM(x) \
1404 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1405
1406 #define S_FW_RI_TPTE_REMINVDIS 27
1407 #define M_FW_RI_TPTE_REMINVDIS 0x1
1408 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
1409 #define G_FW_RI_TPTE_REMINVDIS(x) \
1410 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1411 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
1412
1413 #define S_FW_RI_TPTE_ADDRTYPE 26
1414 #define M_FW_RI_TPTE_ADDRTYPE 1
1415 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
1416 #define G_FW_RI_TPTE_ADDRTYPE(x) \
1417 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1418 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
1419
1420 #define S_FW_RI_TPTE_MWBINDEN 25
1421 #define M_FW_RI_TPTE_MWBINDEN 0x1
1422 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
1423 #define G_FW_RI_TPTE_MWBINDEN(x) \
1424 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1425 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
1426
1427 #define S_FW_RI_TPTE_PS 20
1428 #define M_FW_RI_TPTE_PS 0x1f
1429 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
1430 #define G_FW_RI_TPTE_PS(x) \
1431 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1432
1433 #define S_FW_RI_TPTE_QPID 0
1434 #define M_FW_RI_TPTE_QPID 0xfffff
1435 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
1436 #define G_FW_RI_TPTE_QPID(x) \
1437 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1438
1439 #define S_FW_RI_TPTE_NOSNOOP 31
1440 #define M_FW_RI_TPTE_NOSNOOP 0x1
1441 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
1442 #define G_FW_RI_TPTE_NOSNOOP(x) \
1443 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1444 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
1445
1446 #define S_FW_RI_TPTE_PBLADDR 0
1447 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff
1448 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
1449 #define G_FW_RI_TPTE_PBLADDR(x) \
1450 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1451
1452 #define S_FW_RI_TPTE_DCA 24
1453 #define M_FW_RI_TPTE_DCA 0x1f
1454 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
1455 #define G_FW_RI_TPTE_DCA(x) \
1456 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1457
1458 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0
1459 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
1460 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
1461 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1462 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
1463 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1464
1465 enum fw_ri_cqe_rxtx {
1466 FW_RI_CQE_RXTX_RX = 0x0,
1467 FW_RI_CQE_RXTX_TX = 0x1,
1468 };
1469
1470 struct fw_ri_cqe {
1471 union fw_ri_rxtx {
1472 struct fw_ri_scqe {
1473 __be32 qpid_n_stat_rxtx_type;
1474 __be32 plen;
1475 __be32 stag;
1476 __be32 wrid;
1477 } scqe;
1478 struct fw_ri_rcqe {
1479 __be32 qpid_n_stat_rxtx_type;
1480 __be32 plen;
1481 __be32 stag;
1482 __be32 msn;
1483 } rcqe;
1484 struct fw_ri_rcqe_imm {
1485 __be32 qpid_n_stat_rxtx_type;
1486 __be32 plen;
1487 __be32 mo;
1488 __be32 msn;
1489 __u64 imm_data;
1490 } imm_data_rcqe;
1491 } u;
1492 };
1493
1494 #define S_FW_RI_CQE_QPID 12
1495 #define M_FW_RI_CQE_QPID 0xfffff
1496 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID)
1497 #define G_FW_RI_CQE_QPID(x) \
1498 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
1499
1500 #define S_FW_RI_CQE_NOTIFY 10
1501 #define M_FW_RI_CQE_NOTIFY 0x1
1502 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1503 #define G_FW_RI_CQE_NOTIFY(x) \
1504 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
1505
1506 #define S_FW_RI_CQE_STATUS 5
1507 #define M_FW_RI_CQE_STATUS 0x1f
1508 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1509 #define G_FW_RI_CQE_STATUS(x) \
1510 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
1511
1512
1513 #define S_FW_RI_CQE_RXTX 4
1514 #define M_FW_RI_CQE_RXTX 0x1
1515 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX)
1516 #define G_FW_RI_CQE_RXTX(x) \
1517 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
1518
1519 #define S_FW_RI_CQE_TYPE 0
1520 #define M_FW_RI_CQE_TYPE 0xf
1521 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE)
1522 #define G_FW_RI_CQE_TYPE(x) \
1523 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
1524
1525 enum fw_ri_res_type {
1526 FW_RI_RES_TYPE_SQ,
1527 FW_RI_RES_TYPE_RQ,
1528 FW_RI_RES_TYPE_CQ,
1529 FW_RI_RES_TYPE_SRQ,
1530 };
1531
1532 enum fw_ri_res_op {
1533 FW_RI_RES_OP_WRITE,
1534 FW_RI_RES_OP_RESET,
1535 };
1536
1537 struct fw_ri_res {
1538 union fw_ri_restype {
1539 struct fw_ri_res_sqrq {
1540 __u8 restype;
1541 __u8 op;
1542 __be16 r3;
1543 __be32 eqid;
1544 __be32 r4[2];
1545 __be32 fetchszm_to_iqid;
1546 __be32 dcaen_to_eqsize;
1547 __be64 eqaddr;
1548 } sqrq;
1549 struct fw_ri_res_cq {
1550 __u8 restype;
1551 __u8 op;
1552 __be16 r3;
1553 __be32 iqid;
1554 __be32 r4[2];
1555 __be32 iqandst_to_iqandstindex;
1556 __be16 iqdroprss_to_iqesize;
1557 __be16 iqsize;
1558 __be64 iqaddr;
1559 __be32 iqns_iqro;
1560 __be32 r6_lo;
1561 __be64 r7;
1562 } cq;
1563 struct fw_ri_res_srq {
1564 __u8 restype;
1565 __u8 op;
1566 __be16 r3;
1567 __be32 eqid;
1568 __be32 r4[2];
1569 __be32 fetchszm_to_iqid;
1570 __be32 dcaen_to_eqsize;
1571 __be64 eqaddr;
1572 __be32 srqid;
1573 __be32 pdid;
1574 __be32 hwsrqsize;
1575 __be32 hwsrqaddr;
1576 } srq;
1577 } u;
1578 };
1579
1580 struct fw_ri_res_wr {
1581 __be32 op_nres;
1582 __be32 len16_pkd;
1583 __u64 cookie;
1584 #ifndef C99_NOT_SUPPORTED
1585 struct fw_ri_res res[0];
1586 #endif
1587 };
1588
1589 #define S_FW_RI_RES_WR_VFN 8
1590 #define M_FW_RI_RES_WR_VFN 0xff
1591 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN)
1592 #define G_FW_RI_RES_WR_VFN(x) \
1593 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1594
1595 #define S_FW_RI_RES_WR_NRES 0
1596 #define M_FW_RI_RES_WR_NRES 0xff
1597 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
1598 #define G_FW_RI_RES_WR_NRES(x) \
1599 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1600
1601 #define S_FW_RI_RES_WR_FETCHSZM 26
1602 #define M_FW_RI_RES_WR_FETCHSZM 0x1
1603 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
1604 #define G_FW_RI_RES_WR_FETCHSZM(x) \
1605 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1606 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
1607
1608 #define S_FW_RI_RES_WR_STATUSPGNS 25
1609 #define M_FW_RI_RES_WR_STATUSPGNS 0x1
1610 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
1611 #define G_FW_RI_RES_WR_STATUSPGNS(x) \
1612 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1613 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
1614
1615 #define S_FW_RI_RES_WR_STATUSPGRO 24
1616 #define M_FW_RI_RES_WR_STATUSPGRO 0x1
1617 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
1618 #define G_FW_RI_RES_WR_STATUSPGRO(x) \
1619 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1620 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
1621
1622 #define S_FW_RI_RES_WR_FETCHNS 23
1623 #define M_FW_RI_RES_WR_FETCHNS 0x1
1624 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
1625 #define G_FW_RI_RES_WR_FETCHNS(x) \
1626 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1627 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
1628
1629 #define S_FW_RI_RES_WR_FETCHRO 22
1630 #define M_FW_RI_RES_WR_FETCHRO 0x1
1631 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
1632 #define G_FW_RI_RES_WR_FETCHRO(x) \
1633 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1634 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
1635
1636 #define S_FW_RI_RES_WR_HOSTFCMODE 20
1637 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3
1638 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1639 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \
1640 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1641
1642 #define S_FW_RI_RES_WR_CPRIO 19
1643 #define M_FW_RI_RES_WR_CPRIO 0x1
1644 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
1645 #define G_FW_RI_RES_WR_CPRIO(x) \
1646 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1647 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
1648
1649 #define S_FW_RI_RES_WR_ONCHIP 18
1650 #define M_FW_RI_RES_WR_ONCHIP 0x1
1651 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
1652 #define G_FW_RI_RES_WR_ONCHIP(x) \
1653 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1654 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
1655
1656 #define S_FW_RI_RES_WR_PCIECHN 16
1657 #define M_FW_RI_RES_WR_PCIECHN 0x3
1658 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
1659 #define G_FW_RI_RES_WR_PCIECHN(x) \
1660 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1661
1662 #define S_FW_RI_RES_WR_IQID 0
1663 #define M_FW_RI_RES_WR_IQID 0xffff
1664 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
1665 #define G_FW_RI_RES_WR_IQID(x) \
1666 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1667
1668 #define S_FW_RI_RES_WR_DCAEN 31
1669 #define M_FW_RI_RES_WR_DCAEN 0x1
1670 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
1671 #define G_FW_RI_RES_WR_DCAEN(x) \
1672 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1673 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
1674
1675 #define S_FW_RI_RES_WR_DCACPU 26
1676 #define M_FW_RI_RES_WR_DCACPU 0x1f
1677 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
1678 #define G_FW_RI_RES_WR_DCACPU(x) \
1679 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1680
1681 #define S_FW_RI_RES_WR_FBMIN 23
1682 #define M_FW_RI_RES_WR_FBMIN 0x7
1683 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
1684 #define G_FW_RI_RES_WR_FBMIN(x) \
1685 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1686
1687 #define S_FW_RI_RES_WR_FBMAX 20
1688 #define M_FW_RI_RES_WR_FBMAX 0x7
1689 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
1690 #define G_FW_RI_RES_WR_FBMAX(x) \
1691 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1692
1693 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19
1694 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
1695 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1696 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
1697 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1698 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1699
1700 #define S_FW_RI_RES_WR_CIDXFTHRESH 16
1701 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
1702 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1703 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
1704 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1705
1706 #define S_FW_RI_RES_WR_EQSIZE 0
1707 #define M_FW_RI_RES_WR_EQSIZE 0xffff
1708 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
1709 #define G_FW_RI_RES_WR_EQSIZE(x) \
1710 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1711
1712 #define S_FW_RI_RES_WR_IQANDST 15
1713 #define M_FW_RI_RES_WR_IQANDST 0x1
1714 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
1715 #define G_FW_RI_RES_WR_IQANDST(x) \
1716 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1717 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
1718
1719 #define S_FW_RI_RES_WR_IQANUS 14
1720 #define M_FW_RI_RES_WR_IQANUS 0x1
1721 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
1722 #define G_FW_RI_RES_WR_IQANUS(x) \
1723 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1724 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
1725
1726 #define S_FW_RI_RES_WR_IQANUD 12
1727 #define M_FW_RI_RES_WR_IQANUD 0x3
1728 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
1729 #define G_FW_RI_RES_WR_IQANUD(x) \
1730 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1731
1732 #define S_FW_RI_RES_WR_IQANDSTINDEX 0
1733 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
1734 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1735 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
1736 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1737
1738 #define S_FW_RI_RES_WR_IQDROPRSS 15
1739 #define M_FW_RI_RES_WR_IQDROPRSS 0x1
1740 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
1741 #define G_FW_RI_RES_WR_IQDROPRSS(x) \
1742 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1743 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
1744
1745 #define S_FW_RI_RES_WR_IQGTSMODE 14
1746 #define M_FW_RI_RES_WR_IQGTSMODE 0x1
1747 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
1748 #define G_FW_RI_RES_WR_IQGTSMODE(x) \
1749 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1750 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
1751
1752 #define S_FW_RI_RES_WR_IQPCIECH 12
1753 #define M_FW_RI_RES_WR_IQPCIECH 0x3
1754 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
1755 #define G_FW_RI_RES_WR_IQPCIECH(x) \
1756 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1757
1758 #define S_FW_RI_RES_WR_IQDCAEN 11
1759 #define M_FW_RI_RES_WR_IQDCAEN 0x1
1760 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
1761 #define G_FW_RI_RES_WR_IQDCAEN(x) \
1762 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1763 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
1764
1765 #define S_FW_RI_RES_WR_IQDCACPU 6
1766 #define M_FW_RI_RES_WR_IQDCACPU 0x1f
1767 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
1768 #define G_FW_RI_RES_WR_IQDCACPU(x) \
1769 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1770
1771 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
1772 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
1773 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1774 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1775 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1776 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1777
1778 #define S_FW_RI_RES_WR_IQO 3
1779 #define M_FW_RI_RES_WR_IQO 0x1
1780 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
1781 #define G_FW_RI_RES_WR_IQO(x) \
1782 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1783 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
1784
1785 #define S_FW_RI_RES_WR_IQCPRIO 2
1786 #define M_FW_RI_RES_WR_IQCPRIO 0x1
1787 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
1788 #define G_FW_RI_RES_WR_IQCPRIO(x) \
1789 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1790 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
1791
1792 #define S_FW_RI_RES_WR_IQESIZE 0
1793 #define M_FW_RI_RES_WR_IQESIZE 0x3
1794 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
1795 #define G_FW_RI_RES_WR_IQESIZE(x) \
1796 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1797
1798 #define S_FW_RI_RES_WR_IQNS 31
1799 #define M_FW_RI_RES_WR_IQNS 0x1
1800 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
1801 #define G_FW_RI_RES_WR_IQNS(x) \
1802 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1803 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
1804
1805 #define S_FW_RI_RES_WR_IQRO 30
1806 #define M_FW_RI_RES_WR_IQRO 0x1
1807 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
1808 #define G_FW_RI_RES_WR_IQRO(x) \
1809 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1810 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
1811
1812 struct fw_ri_rdma_write_wr {
1813 __u8 opcode;
1814 __u8 flags;
1815 __u16 wrid;
1816 __u8 r1[3];
1817 __u8 len16;
1818 __u64 immd_data;
1819 __be32 plen;
1820 __be32 stag_sink;
1821 __be64 to_sink;
1822 #ifndef C99_NOT_SUPPORTED
1823 union {
1824 struct fw_ri_immd immd_src[0];
1825 struct fw_ri_isgl isgl_src[0];
1826 } u;
1827 #endif
1828 };
1829
1830 struct fw_ri_send_wr {
1831 __u8 opcode;
1832 __u8 flags;
1833 __u16 wrid;
1834 __u8 r1[3];
1835 __u8 len16;
1836 __be32 sendop_pkd;
1837 __be32 stag_inv;
1838 __be32 plen;
1839 __be32 r3;
1840 __be64 r4;
1841 #ifndef C99_NOT_SUPPORTED
1842 union {
1843 struct fw_ri_immd immd_src[0];
1844 struct fw_ri_isgl isgl_src[0];
1845 } u;
1846 #endif
1847 };
1848
1849 #define S_FW_RI_SEND_WR_SENDOP 0
1850 #define M_FW_RI_SEND_WR_SENDOP 0xf
1851 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
1852 #define G_FW_RI_SEND_WR_SENDOP(x) \
1853 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1854
1855 struct fw_ri_rdma_write_cmpl_wr {
1856 __u8 opcode;
1857 __u8 flags;
1858 __u16 wrid;
1859 __u8 r1[3];
1860 __u8 len16;
1861 __u8 r2;
1862 __u8 flags_send;
1863 __u16 wrid_send;
1864 __be32 stag_inv;
1865 __be32 plen;
1866 __be32 stag_sink;
1867 __be64 to_sink;
1868 union fw_ri_cmpl {
1869 struct fw_ri_immd_cmpl {
1870 __u8 op;
1871 __u8 r1[6];
1872 __u8 immdlen;
1873 __u8 data[16];
1874 } immd_src;
1875 struct fw_ri_isgl isgl_src;
1876 } u_cmpl;
1877 __be64 r3;
1878 #ifndef C99_NOT_SUPPORTED
1879 union fw_ri_write {
1880 struct fw_ri_immd immd_src[0];
1881 struct fw_ri_isgl isgl_src[0];
1882 } u;
1883 #endif
1884 };
1885
1886 struct fw_ri_rdma_read_wr {
1887 __u8 opcode;
1888 __u8 flags;
1889 __u16 wrid;
1890 __u8 r1[3];
1891 __u8 len16;
1892 __be64 r2;
1893 __be32 stag_sink;
1894 __be32 to_sink_hi;
1895 __be32 to_sink_lo;
1896 __be32 plen;
1897 __be32 stag_src;
1898 __be32 to_src_hi;
1899 __be32 to_src_lo;
1900 __be32 r5;
1901 };
1902
1903 struct fw_ri_recv_wr {
1904 __u8 opcode;
1905 __u8 r1;
1906 __u16 wrid;
1907 __u8 r2[3];
1908 __u8 len16;
1909 struct fw_ri_isgl isgl;
1910 };
1911
1912 struct fw_ri_bind_mw_wr {
1913 __u8 opcode;
1914 __u8 flags;
1915 __u16 wrid;
1916 __u8 r1[3];
1917 __u8 len16;
1918 __u8 qpbinde_to_dcacpu;
1919 __u8 pgsz_shift;
1920 __u8 addr_type;
1921 __u8 mem_perms;
1922 __be32 stag_mr;
1923 __be32 stag_mw;
1924 __be32 r3;
1925 __be64 len_mw;
1926 __be64 va_fbo;
1927 __be64 r4;
1928 };
1929
1930 #define S_FW_RI_BIND_MW_WR_QPBINDE 6
1931 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
1932 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1933 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
1934 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1935 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1936
1937 #define S_FW_RI_BIND_MW_WR_NS 5
1938 #define M_FW_RI_BIND_MW_WR_NS 0x1
1939 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
1940 #define G_FW_RI_BIND_MW_WR_NS(x) \
1941 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1942 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
1943
1944 #define S_FW_RI_BIND_MW_WR_DCACPU 0
1945 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
1946 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1947 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \
1948 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1949
1950 struct fw_ri_fr_nsmr_wr {
1951 __u8 opcode;
1952 __u8 flags;
1953 __u16 wrid;
1954 __u8 r1[3];
1955 __u8 len16;
1956 __u8 qpbinde_to_dcacpu;
1957 __u8 pgsz_shift;
1958 __u8 addr_type;
1959 __u8 mem_perms;
1960 __be32 stag;
1961 __be32 len_hi;
1962 __be32 len_lo;
1963 __be32 va_hi;
1964 __be32 va_lo_fbo;
1965 };
1966
1967 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6
1968 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
1969 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1970 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
1971 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1972 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1973
1974 #define S_FW_RI_FR_NSMR_WR_NS 5
1975 #define M_FW_RI_FR_NSMR_WR_NS 0x1
1976 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
1977 #define G_FW_RI_FR_NSMR_WR_NS(x) \
1978 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1979 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
1980
1981 #define S_FW_RI_FR_NSMR_WR_DCACPU 0
1982 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
1983 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1984 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
1985 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1986
1987 struct fw_ri_fr_nsmr_tpte_wr {
1988 __u8 opcode;
1989 __u8 flags;
1990 __u16 wrid;
1991 __u8 r1[3];
1992 __u8 len16;
1993 __be32 r2;
1994 __be32 stag;
1995 struct fw_ri_tpte tpte;
1996 __be64 pbl[2];
1997 };
1998
1999 struct fw_ri_inv_lstag_wr {
2000 __u8 opcode;
2001 __u8 flags;
2002 __u16 wrid;
2003 __u8 r1[3];
2004 __u8 len16;
2005 __be32 r2;
2006 __be32 stag_inv;
2007 };
2008
2009 struct fw_ri_send_immediate_wr {
2010 __u8 opcode;
2011 __u8 flags;
2012 __u16 wrid;
2013 __u8 r1[3];
2014 __u8 len16;
2015 __be32 sendimmop_pkd;
2016 __be32 r3;
2017 __be32 plen;
2018 __be32 r4;
2019 __be64 r5;
2020 #ifndef C99_NOT_SUPPORTED
2021 struct fw_ri_immd immd_src[0];
2022 #endif
2023 };
2024
2025 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
2026 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf
2027 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
2028 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2029 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
2030 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
2031 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2032
2033 enum fw_ri_atomic_op {
2034 FW_RI_ATOMIC_OP_FETCHADD,
2035 FW_RI_ATOMIC_OP_SWAP,
2036 FW_RI_ATOMIC_OP_CMDSWAP,
2037 };
2038
2039 struct fw_ri_atomic_wr {
2040 __u8 opcode;
2041 __u8 flags;
2042 __u16 wrid;
2043 __u8 r1[3];
2044 __u8 len16;
2045 __be32 atomicop_pkd;
2046 __be64 r3;
2047 __be32 aopcode_pkd;
2048 __be32 reqid;
2049 __be32 stag;
2050 __be32 to_hi;
2051 __be32 to_lo;
2052 __be32 addswap_data_hi;
2053 __be32 addswap_data_lo;
2054 __be32 addswap_mask_hi;
2055 __be32 addswap_mask_lo;
2056 __be32 compare_data_hi;
2057 __be32 compare_data_lo;
2058 __be32 compare_mask_hi;
2059 __be32 compare_mask_lo;
2060 __be32 r5;
2061 };
2062
2063 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0
2064 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf
2065 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
2066 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
2067 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
2068
2069 #define S_FW_RI_ATOMIC_WR_AOPCODE 0
2070 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf
2071 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
2072 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
2073 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
2074
2075 enum fw_ri_type {
2076 FW_RI_TYPE_INIT,
2077 FW_RI_TYPE_FINI,
2078 FW_RI_TYPE_TERMINATE
2079 };
2080
2081 enum fw_ri_init_p2ptype {
2082 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
2083 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
2084 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
2085 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
2086 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
2087 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
2088 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
2089 };
2090
2091 enum fw_ri_init_rqeqid_srq {
2092 FW_RI_INIT_RQEQID_SRQ = 1 << 31,
2093 };
2094
2095 struct fw_ri_wr {
2096 __be32 op_compl;
2097 __be32 flowid_len16;
2098 __u64 cookie;
2099 union fw_ri {
2100 struct fw_ri_init {
2101 __u8 type;
2102 __u8 mpareqbit_p2ptype;
2103 __u8 r4[2];
2104 __u8 mpa_attrs;
2105 __u8 qp_caps;
2106 __be16 nrqe;
2107 __be32 pdid;
2108 __be32 qpid;
2109 __be32 sq_eqid;
2110 __be32 rq_eqid;
2111 __be32 scqid;
2112 __be32 rcqid;
2113 __be32 ord_max;
2114 __be32 ird_max;
2115 __be32 iss;
2116 __be32 irs;
2117 __be32 hwrqsize;
2118 __be32 hwrqaddr;
2119 __be64 r5;
2120 union fw_ri_init_p2p {
2121 struct fw_ri_rdma_write_wr write;
2122 struct fw_ri_rdma_read_wr read;
2123 struct fw_ri_send_wr send;
2124 } u;
2125 } init;
2126 struct fw_ri_fini {
2127 __u8 type;
2128 __u8 r3[7];
2129 __be64 r4;
2130 } fini;
2131 struct fw_ri_terminate {
2132 __u8 type;
2133 __u8 r3[3];
2134 __be32 immdlen;
2135 __u8 termmsg[40];
2136 } terminate;
2137 } u;
2138 };
2139
2140 #define S_FW_RI_WR_MPAREQBIT 7
2141 #define M_FW_RI_WR_MPAREQBIT 0x1
2142 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
2143 #define G_FW_RI_WR_MPAREQBIT(x) \
2144 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2145 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
2146
2147 #define S_FW_RI_WR_0BRRBIT 6
2148 #define M_FW_RI_WR_0BRRBIT 0x1
2149 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT)
2150 #define G_FW_RI_WR_0BRRBIT(x) \
2151 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2152 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U)
2153
2154 #define S_FW_RI_WR_P2PTYPE 0
2155 #define M_FW_RI_WR_P2PTYPE 0xf
2156 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
2157 #define G_FW_RI_WR_P2PTYPE(x) \
2158 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2159
2160 /******************************************************************************
2161 * F O i S C S I W O R K R E Q U E S T s
2162 *********************************************/
2163
2164 #define FW_FOISCSI_NAME_MAX_LEN 224
2165 #define FW_FOISCSI_ALIAS_MAX_LEN 224
2166 #define FW_FOISCSI_KEY_MAX_LEN 64
2167 #define FW_FOISCSI_VAL_MAX_LEN 256
2168 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128
2169 #define FW_FOISCSI_INIT_NODE_MAX 8
2170
2171 enum fw_chnet_ifconf_wr_subop {
2172 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2173
2174 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2175 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2176
2177 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2178 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2179
2180 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2181 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2182
2183 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2184 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2185
2186 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2187 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2188
2189 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2190 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2191
2192 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2193 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2194
2195 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2196 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2197 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2198
2199 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4,
2200 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6,
2201
2202 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4,
2203 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6,
2204
2205 FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR,
2206
2207 FW_CHNET_IFCONF_WR_SUBOP_MAX,
2208 };
2209
2210 struct fw_chnet_ifconf_wr {
2211 __be32 op_compl;
2212 __be32 flowid_len16;
2213 __u64 cookie;
2214 __be32 if_flowid;
2215 __u8 idx;
2216 __u8 subop;
2217 __u8 retval;
2218 __u8 r2;
2219 union {
2220 __be64 r3;
2221 struct fw_chnet_ifconf_ping {
2222 __be16 ping_time;
2223 __u8 ping_rsptype;
2224 __u8 ping_param_rspcode_to_fin_bit;
2225 __u8 ping_pktsize;
2226 __u8 ping_ttl;
2227 __be16 ping_seq;
2228 } ping;
2229 struct fw_chnet_ifconf_mac {
2230 __u8 peer_mac[6];
2231 __u8 smac_idx;
2232 } mac;
2233 } u;
2234 struct fw_chnet_ifconf_params {
2235 __be16 ping_pldsize;
2236 __be16 r0;
2237 __be16 vlanid;
2238 __be16 mtu;
2239 union fw_chnet_ifconf_addr_type {
2240 struct fw_chnet_ifconf_ipv4 {
2241 __be32 addr;
2242 __be32 mask;
2243 __be32 router;
2244 __be32 r0;
2245 __be64 r1;
2246 } ipv4;
2247 struct fw_chnet_ifconf_ipv6 {
2248 __u8 prefix_len;
2249 __u8 r0;
2250 __be16 r1;
2251 __be32 r2;
2252 __be64 addr_hi;
2253 __be64 addr_lo;
2254 __be64 router_hi;
2255 __be64 router_lo;
2256 } ipv6;
2257 } in_attr;
2258 } param;
2259 };
2260
2261 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1
2262 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1
2263 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \
2264 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT)
2265 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \
2266 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \
2267 M_FW_CHNET_IFCONF_WR_PING_MACBIT)
2268 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \
2269 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U)
2270
2271 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0
2272 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1
2273 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT)
2274 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \
2275 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT)
2276 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U)
2277
2278 enum fw_foiscsi_node_type {
2279 FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2280 FW_FOISCSI_NODE_TYPE_TARGET,
2281 };
2282
2283 enum fw_foiscsi_session_type {
2284 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2285 FW_FOISCSI_SESSION_TYPE_NORMAL,
2286 };
2287
2288 enum fw_foiscsi_auth_policy {
2289 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2290 FW_FOISCSI_AUTH_POLICY_MUTUAL,
2291 };
2292
2293 enum fw_foiscsi_auth_method {
2294 FW_FOISCSI_AUTH_METHOD_NONE = 0,
2295 FW_FOISCSI_AUTH_METHOD_CHAP,
2296 FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2297 FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2298 };
2299
2300 enum fw_foiscsi_digest_type {
2301 FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2302 FW_FOISCSI_DIGEST_TYPE_CRC32,
2303 FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2304 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2305 };
2306
2307 enum fw_foiscsi_wr_subop {
2308 FW_FOISCSI_WR_SUBOP_ADD = 1,
2309 FW_FOISCSI_WR_SUBOP_DEL = 2,
2310 FW_FOISCSI_WR_SUBOP_MOD = 4,
2311 };
2312
2313 enum fw_coiscsi_stats_wr_subop {
2314 FW_COISCSI_WR_SUBOP_TOT = 1,
2315 FW_COISCSI_WR_SUBOP_MAX = 2,
2316 FW_COISCSI_WR_SUBOP_CUR = 3,
2317 FW_COISCSI_WR_SUBOP_CLR = 4,
2318 };
2319
2320 enum fw_foiscsi_ctrl_state {
2321 FW_FOISCSI_CTRL_STATE_FREE = 0,
2322 FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2323 FW_FOISCSI_CTRL_STATE_FAILED,
2324 FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2325 FW_FOISCSI_CTRL_STATE_REDIRECT,
2326 };
2327
2328 struct fw_rdev_wr {
2329 __be32 op_to_immdlen;
2330 __be32 alloc_to_len16;
2331 __be64 cookie;
2332 __u8 protocol;
2333 __u8 event_cause;
2334 __u8 cur_state;
2335 __u8 prev_state;
2336 __be32 flags_to_assoc_flowid;
2337 union rdev_entry {
2338 struct fcoe_rdev_entry {
2339 __be32 flowid;
2340 __u8 protocol;
2341 __u8 event_cause;
2342 __u8 flags;
2343 __u8 rjt_reason;
2344 __u8 cur_login_st;
2345 __u8 prev_login_st;
2346 __be16 rcv_fr_sz;
2347 __u8 rd_xfer_rdy_to_rport_type;
2348 __u8 vft_to_qos;
2349 __u8 org_proc_assoc_to_acc_rsp_code;
2350 __u8 enh_disc_to_tgt;
2351 __u8 wwnn[8];
2352 __u8 wwpn[8];
2353 __be16 iqid;
2354 __u8 fc_oui[3];
2355 __u8 r_id[3];
2356 } fcoe_rdev;
2357 struct iscsi_rdev_entry {
2358 __be32 flowid;
2359 __u8 protocol;
2360 __u8 event_cause;
2361 __u8 flags;
2362 __u8 r3;
2363 __be16 iscsi_opts;
2364 __be16 tcp_opts;
2365 __be16 ip_opts;
2366 __be16 max_rcv_len;
2367 __be16 max_snd_len;
2368 __be16 first_brst_len;
2369 __be16 max_brst_len;
2370 __be16 r4;
2371 __be16 def_time2wait;
2372 __be16 def_time2ret;
2373 __be16 nop_out_intrvl;
2374 __be16 non_scsi_to;
2375 __be16 isid;
2376 __be16 tsid;
2377 __be16 port;
2378 __be16 tpgt;
2379 __u8 r5[6];
2380 __be16 iqid;
2381 } iscsi_rdev;
2382 } u;
2383 };
2384
2385 #define S_FW_RDEV_WR_IMMDLEN 0
2386 #define M_FW_RDEV_WR_IMMDLEN 0xff
2387 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)
2388 #define G_FW_RDEV_WR_IMMDLEN(x) \
2389 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2390
2391 #define S_FW_RDEV_WR_ALLOC 31
2392 #define M_FW_RDEV_WR_ALLOC 0x1
2393 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC)
2394 #define G_FW_RDEV_WR_ALLOC(x) \
2395 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2396 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U)
2397
2398 #define S_FW_RDEV_WR_FREE 30
2399 #define M_FW_RDEV_WR_FREE 0x1
2400 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE)
2401 #define G_FW_RDEV_WR_FREE(x) \
2402 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2403 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U)
2404
2405 #define S_FW_RDEV_WR_MODIFY 29
2406 #define M_FW_RDEV_WR_MODIFY 0x1
2407 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY)
2408 #define G_FW_RDEV_WR_MODIFY(x) \
2409 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2410 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U)
2411
2412 #define S_FW_RDEV_WR_FLOWID 8
2413 #define M_FW_RDEV_WR_FLOWID 0xfffff
2414 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID)
2415 #define G_FW_RDEV_WR_FLOWID(x) \
2416 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2417
2418 #define S_FW_RDEV_WR_LEN16 0
2419 #define M_FW_RDEV_WR_LEN16 0xff
2420 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16)
2421 #define G_FW_RDEV_WR_LEN16(x) \
2422 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2423
2424 #define S_FW_RDEV_WR_FLAGS 24
2425 #define M_FW_RDEV_WR_FLAGS 0xff
2426 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS)
2427 #define G_FW_RDEV_WR_FLAGS(x) \
2428 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2429
2430 #define S_FW_RDEV_WR_GET_NEXT 20
2431 #define M_FW_RDEV_WR_GET_NEXT 0xf
2432 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT)
2433 #define G_FW_RDEV_WR_GET_NEXT(x) \
2434 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2435
2436 #define S_FW_RDEV_WR_ASSOC_FLOWID 0
2437 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff
2438 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2439 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
2440 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2441
2442 #define S_FW_RDEV_WR_RJT 7
2443 #define M_FW_RDEV_WR_RJT 0x1
2444 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT)
2445 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2446 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U)
2447
2448 #define S_FW_RDEV_WR_REASON 0
2449 #define M_FW_RDEV_WR_REASON 0x7f
2450 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON)
2451 #define G_FW_RDEV_WR_REASON(x) \
2452 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2453
2454 #define S_FW_RDEV_WR_RD_XFER_RDY 7
2455 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1
2456 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2457 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \
2458 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2459 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U)
2460
2461 #define S_FW_RDEV_WR_WR_XFER_RDY 6
2462 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1
2463 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2464 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \
2465 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2466 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U)
2467
2468 #define S_FW_RDEV_WR_FC_SP 5
2469 #define M_FW_RDEV_WR_FC_SP 0x1
2470 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP)
2471 #define G_FW_RDEV_WR_FC_SP(x) \
2472 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2473 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U)
2474
2475 #define S_FW_RDEV_WR_RPORT_TYPE 0
2476 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f
2477 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE)
2478 #define G_FW_RDEV_WR_RPORT_TYPE(x) \
2479 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2480
2481 #define S_FW_RDEV_WR_VFT 7
2482 #define M_FW_RDEV_WR_VFT 0x1
2483 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT)
2484 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2485 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U)
2486
2487 #define S_FW_RDEV_WR_NPIV 6
2488 #define M_FW_RDEV_WR_NPIV 0x1
2489 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV)
2490 #define G_FW_RDEV_WR_NPIV(x) \
2491 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2492 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U)
2493
2494 #define S_FW_RDEV_WR_CLASS 4
2495 #define M_FW_RDEV_WR_CLASS 0x3
2496 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS)
2497 #define G_FW_RDEV_WR_CLASS(x) \
2498 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2499
2500 #define S_FW_RDEV_WR_SEQ_DEL 3
2501 #define M_FW_RDEV_WR_SEQ_DEL 0x1
2502 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)
2503 #define G_FW_RDEV_WR_SEQ_DEL(x) \
2504 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2505 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U)
2506
2507 #define S_FW_RDEV_WR_PRIO_PREEMP 2
2508 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1
2509 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2510 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \
2511 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2512 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U)
2513
2514 #define S_FW_RDEV_WR_PREF 1
2515 #define M_FW_RDEV_WR_PREF 0x1
2516 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF)
2517 #define G_FW_RDEV_WR_PREF(x) \
2518 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2519 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U)
2520
2521 #define S_FW_RDEV_WR_QOS 0
2522 #define M_FW_RDEV_WR_QOS 0x1
2523 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS)
2524 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2525 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U)
2526
2527 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7
2528 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1
2529 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2530 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
2531 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2532 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2533
2534 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6
2535 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1
2536 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2537 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
2538 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2539 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2540
2541 #define S_FW_RDEV_WR_IMAGE_PAIR 5
2542 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1
2543 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2544 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \
2545 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2546 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)
2547
2548 #define S_FW_RDEV_WR_ACC_RSP_CODE 0
2549 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f
2550 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2551 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
2552 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2553
2554 #define S_FW_RDEV_WR_ENH_DISC 7
2555 #define M_FW_RDEV_WR_ENH_DISC 0x1
2556 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC)
2557 #define G_FW_RDEV_WR_ENH_DISC(x) \
2558 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2559 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U)
2560
2561 #define S_FW_RDEV_WR_REC 6
2562 #define M_FW_RDEV_WR_REC 0x1
2563 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC)
2564 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2565 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U)
2566
2567 #define S_FW_RDEV_WR_TASK_RETRY_ID 5
2568 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1
2569 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2570 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
2571 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2572 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2573
2574 #define S_FW_RDEV_WR_RETRY 4
2575 #define M_FW_RDEV_WR_RETRY 0x1
2576 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY)
2577 #define G_FW_RDEV_WR_RETRY(x) \
2578 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2579 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U)
2580
2581 #define S_FW_RDEV_WR_CONF_CMPL 3
2582 #define M_FW_RDEV_WR_CONF_CMPL 0x1
2583 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL)
2584 #define G_FW_RDEV_WR_CONF_CMPL(x) \
2585 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2586 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U)
2587
2588 #define S_FW_RDEV_WR_DATA_OVLY 2
2589 #define M_FW_RDEV_WR_DATA_OVLY 0x1
2590 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY)
2591 #define G_FW_RDEV_WR_DATA_OVLY(x) \
2592 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2593 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U)
2594
2595 #define S_FW_RDEV_WR_INI 1
2596 #define M_FW_RDEV_WR_INI 0x1
2597 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI)
2598 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2599 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U)
2600
2601 #define S_FW_RDEV_WR_TGT 0
2602 #define M_FW_RDEV_WR_TGT 0x1
2603 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT)
2604 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2605 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U)
2606
2607 struct fw_foiscsi_node_wr {
2608 __be32 op_to_immdlen;
2609 __be32 no_sess_recv_to_len16;
2610 __u64 cookie;
2611 __u8 subop;
2612 __u8 status;
2613 __u8 alias_len;
2614 __u8 iqn_len;
2615 __be32 node_flowid;
2616 __be16 nodeid;
2617 __be16 login_retry;
2618 __be16 retry_timeout;
2619 __be16 r3;
2620 __u8 iqn[224];
2621 __u8 alias[224];
2622 __be32 isid_tval_to_isid_cval;
2623 };
2624
2625 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
2626 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff
2627 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2628 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
2629 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2630
2631 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28
2632 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1
2633 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \
2634 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV)
2635 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \
2636 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \
2637 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV)
2638 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \
2639 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U)
2640
2641 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30
2642 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3
2643 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \
2644 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL)
2645 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \
2646 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL)
2647
2648 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24
2649 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f
2650 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \
2651 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL)
2652 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \
2653 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL)
2654
2655 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8
2656 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff
2657 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \
2658 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL)
2659 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \
2660 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL)
2661
2662 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0
2663 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff
2664 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \
2665 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL)
2666 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \
2667 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL)
2668
2669 struct fw_foiscsi_ctrl_wr {
2670 __be32 op_to_no_fin;
2671 __be32 flowid_len16;
2672 __u64 cookie;
2673 __u8 subop;
2674 __u8 status;
2675 __u8 ctrl_state;
2676 __u8 io_state;
2677 __be32 node_id;
2678 __be32 ctrl_id;
2679 __be32 io_id;
2680 struct fw_foiscsi_sess_attr {
2681 __be32 sess_type_to_erl;
2682 __be16 max_conn;
2683 __be16 max_r2t;
2684 __be16 time2wait;
2685 __be16 time2retain;
2686 __be32 max_burst;
2687 __be32 first_burst;
2688 __be32 r1;
2689 } sess_attr;
2690 struct fw_foiscsi_conn_attr {
2691 __be32 hdigest_to_tcp_ws_en;
2692 __be32 max_rcv_dsl;
2693 __be32 ping_tmo;
2694 __be16 dst_port;
2695 __be16 src_port;
2696 union fw_foiscsi_conn_attr_addr {
2697 struct fw_foiscsi_conn_attr_ipv6 {
2698 __be64 dst_addr[2];
2699 __be64 src_addr[2];
2700 } ipv6_addr;
2701 struct fw_foiscsi_conn_attr_ipv4 {
2702 __be32 dst_addr;
2703 __be32 src_addr;
2704 } ipv4_addr;
2705 } u;
2706 } conn_attr;
2707 __u8 tgt_name_len;
2708 __u8 r3[7];
2709 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2710 };
2711
2712 #define S_FW_FOISCSI_CTRL_WR_PORTID 1
2713 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7
2714 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID)
2715 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \
2716 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID)
2717
2718 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0
2719 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1
2720 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN)
2721 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \
2722 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN)
2723 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U)
2724
2725 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30
2726 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3
2727 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2728 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2729 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2730 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2731
2732 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29
2733 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1
2734 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2735 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2736 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2737 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2738 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2739 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
2740 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2741
2742 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28
2743 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1
2744 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2745 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2746 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2747 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2748 M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2749 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
2750 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2751
2752 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27
2753 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1
2754 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2755 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2756 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2757 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2758 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2759 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
2760 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2761
2762 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26
2763 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1
2764 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2765 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2766 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2767 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2768 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2769 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
2770 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2771
2772 #define S_FW_FOISCSI_CTRL_WR_ERL 24
2773 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3
2774 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2775 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \
2776 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2777
2778 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30
2779 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3
2780 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2781 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
2782 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2783
2784 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28
2785 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3
2786 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2787 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
2788 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2789
2790 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25
2791 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7
2792 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2793 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2794 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2795 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2796 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2797
2798 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23
2799 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3
2800 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2801 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2802 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2803 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2804 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2805
2806 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21
2807 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3
2808 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2809 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2810 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2811 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2812
2813 #define S_FW_FOISCSI_CTRL_WR_IPV6 20
2814 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1
2815 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2816 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \
2817 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2818 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2819
2820 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16
2821 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf
2822 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \
2823 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
2824 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \
2825 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
2826
2827 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12
2828 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf
2829 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS)
2830 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \
2831 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS)
2832
2833 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11
2834 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1
2835 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \
2836 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
2837 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \
2838 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
2839 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U)
2840
2841 struct fw_foiscsi_chap_wr {
2842 __be32 op_to_kv_flag;
2843 __be32 flowid_len16;
2844 __u64 cookie;
2845 __u8 status;
2846 union fw_foiscsi_len {
2847 struct fw_foiscsi_chap_lens {
2848 __u8 id_len;
2849 __u8 sec_len;
2850 } chapl;
2851 struct fw_foiscsi_vend_kv_lens {
2852 __u8 key_len;
2853 __u8 val_len;
2854 } vend_kvl;
2855 } lenu;
2856 __u8 node_type;
2857 __be16 node_id;
2858 __u8 r3[2];
2859 union fw_foiscsi_chap_vend {
2860 struct fw_foiscsi_chap {
2861 __u8 chap_id[224];
2862 __u8 chap_sec[128];
2863 } chap;
2864 struct fw_foiscsi_vend_kv {
2865 __u8 vend_key[64];
2866 __u8 vend_val[256];
2867 } vend_kv;
2868 } u;
2869 };
2870
2871 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20
2872 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1
2873 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG)
2874 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \
2875 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG)
2876 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U)
2877
2878 /******************************************************************************
2879 * C O i S C S I W O R K R E Q U E S T S
2880 ********************************************/
2881
2882 enum fw_chnet_addr_type {
2883 FW_CHNET_ADDD_TYPE_NONE = 0,
2884 FW_CHNET_ADDR_TYPE_IPV4,
2885 FW_CHNET_ADDR_TYPE_IPV6,
2886 };
2887
2888 enum fw_msg_wr_type {
2889 FW_MSG_WR_TYPE_RPL = 0,
2890 FW_MSG_WR_TYPE_ERR,
2891 FW_MSG_WR_TYPE_PLD,
2892 };
2893
2894 struct fw_coiscsi_tgt_wr {
2895 __be32 op_compl;
2896 __be32 flowid_len16;
2897 __u64 cookie;
2898 __u8 subop;
2899 __u8 status;
2900 __be16 r4;
2901 __be32 flags;
2902 struct fw_coiscsi_tgt_conn_attr {
2903 __be32 in_tid;
2904 __be16 in_port;
2905 __u8 in_type;
2906 __u8 r6;
2907 union fw_coiscsi_tgt_conn_attr_addr {
2908 struct fw_coiscsi_tgt_conn_attr_in_addr {
2909 __be32 addr;
2910 __be32 r7;
2911 __be32 r8[2];
2912 } in_addr;
2913 struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2914 __be64 addr[2];
2915 } in_addr6;
2916 } u;
2917 } conn_attr;
2918 };
2919
2920 #define S_FW_COISCSI_TGT_WR_PORTID 0
2921 #define M_FW_COISCSI_TGT_WR_PORTID 0x7
2922 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID)
2923 #define G_FW_COISCSI_TGT_WR_PORTID(x) \
2924 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID)
2925
2926 struct fw_coiscsi_tgt_conn_wr {
2927 __be32 op_compl;
2928 __be32 flowid_len16;
2929 __u64 cookie;
2930 __u8 subop;
2931 __u8 status;
2932 __be16 iq_id;
2933 __be32 in_stid;
2934 __be32 io_id;
2935 __be32 flags_fin;
2936 union {
2937 struct fw_coiscsi_tgt_conn_tcp {
2938 __be16 in_sport;
2939 __be16 in_dport;
2940 __u8 wscale_wsen;
2941 __u8 r4[3];
2942 union fw_coiscsi_tgt_conn_tcp_addr {
2943 struct fw_coiscsi_tgt_conn_tcp_in_addr {
2944 __be32 saddr;
2945 __be32 daddr;
2946 } in_addr;
2947 struct fw_coiscsi_tgt_conn_tcp_in_addr6 {
2948 __be64 saddr[2];
2949 __be64 daddr[2];
2950 } in_addr6;
2951 } u;
2952 } conn_tcp;
2953 struct fw_coiscsi_tgt_conn_stats {
2954 __be32 ddp_reqs;
2955 __be32 ddp_cmpls;
2956 __be16 ddp_aborts;
2957 __be16 ddp_bps;
2958 } stats;
2959 } u;
2960 struct fw_coiscsi_tgt_conn_iscsi {
2961 __be32 hdigest_to_ddp_pgsz;
2962 __be32 tgt_id;
2963 __be16 max_r2t;
2964 __be16 r5;
2965 __be32 max_burst;
2966 __be32 max_rdsl;
2967 __be32 max_tdsl;
2968 __be32 cur_sn;
2969 __be32 r6;
2970 } conn_iscsi;
2971 };
2972
2973 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0
2974 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7
2975 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
2976 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID)
2977 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \
2978 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \
2979 M_FW_COISCSI_TGT_CONN_WR_PORTID)
2980
2981 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0
2982 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1
2983 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN)
2984 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \
2985 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN)
2986 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U)
2987
2988 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1
2989 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf
2990 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \
2991 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE)
2992 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \
2993 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \
2994 M_FW_COISCSI_TGT_CONN_WR_WSCALE)
2995
2996 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0
2997 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1
2998 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \
2999 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN)
3000 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \
3001 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN)
3002 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U)
3003
3004 struct fw_coiscsi_tgt_xmit_wr {
3005 __be32 op_to_immdlen;
3006 union {
3007 struct cmpl_stat {
3008 __be32 cmpl_status_pkd;
3009 } cs;
3010 struct flowid_len {
3011 __be32 flowid_len16;
3012 } fllen;
3013 } u;
3014 __u64 cookie;
3015 __be16 iq_id;
3016 __be16 r3;
3017 __be32 pz_off;
3018 __be32 t_xfer_len;
3019 union {
3020 __be32 tag;
3021 __be32 datasn;
3022 __be32 ddp_status;
3023 } cu;
3024 };
3025
3026 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23
3027 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1
3028 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \
3029 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST)
3030 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \
3031 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST)
3032 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U)
3033
3034 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22
3035 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1
3036 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \
3037 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST)
3038 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \
3039 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST)
3040 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U)
3041
3042 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20
3043 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1
3044 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP)
3045 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \
3046 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP)
3047 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U)
3048
3049 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19
3050 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1
3051 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \
3052 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT)
3053 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \
3054 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT)
3055 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U)
3056
3057 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18
3058 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1
3059 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \
3060 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL)
3061 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \
3062 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL)
3063 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U)
3064
3065 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16
3066 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3
3067 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \
3068 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN)
3069 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \
3070 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \
3071 M_FW_COISCSI_TGT_XMIT_WR_PADLEN)
3072
3073 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15
3074 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1
3075 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \
3076 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)
3077 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \
3078 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \
3079 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)
3080 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \
3081 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U)
3082
3083 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0
3084 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff
3085 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \
3086 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)
3087 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \
3088 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \
3089 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)
3090
3091 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8
3092 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff
3093 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \
3094 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)
3095 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \
3096 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \
3097 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)
3098
3099 struct fw_coiscsi_stats_wr {
3100 __be32 op_compl;
3101 __be32 flowid_len16;
3102 __u64 cookie;
3103 __u8 subop;
3104 __u8 status;
3105 union fw_coiscsi_stats {
3106 struct fw_coiscsi_resource {
3107 __u8 num_ipv4_tgt;
3108 __u8 num_ipv6_tgt;
3109 __be16 num_l2t_entries;
3110 __be16 num_csocks;
3111 __be16 num_tasks;
3112 __be16 num_ppods_zone[11];
3113 __be32 num_bufll64;
3114 __u8 r2[12];
3115 } rsrc;
3116 } u;
3117 };
3118
3119 #define S_FW_COISCSI_STATS_WR_PORTID 0
3120 #define M_FW_COISCSI_STATS_WR_PORTID 0x7
3121 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID)
3122 #define G_FW_COISCSI_STATS_WR_PORTID(x) \
3123 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID)
3124
3125 struct fw_isns_wr {
3126 __be32 op_compl;
3127 __be32 flowid_len16;
3128 __u64 cookie;
3129 __u8 subop;
3130 __u8 status;
3131 __be16 iq_id;
3132 __be16 vlanid;
3133 __be16 r4;
3134 struct fw_tcp_conn_attr {
3135 __be32 in_tid;
3136 __be16 in_port;
3137 __u8 in_type;
3138 __u8 r6;
3139 union fw_tcp_conn_attr_addr {
3140 struct fw_tcp_conn_attr_in_addr {
3141 __be32 addr;
3142 __be32 r7;
3143 __be32 r8[2];
3144 } in_addr;
3145 struct fw_tcp_conn_attr_in_addr6 {
3146 __be64 addr[2];
3147 } in_addr6;
3148 } u;
3149 } conn_attr;
3150 };
3151
3152 #define S_FW_ISNS_WR_PORTID 0
3153 #define M_FW_ISNS_WR_PORTID 0x7
3154 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID)
3155 #define G_FW_ISNS_WR_PORTID(x) \
3156 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID)
3157
3158 struct fw_isns_xmit_wr {
3159 __be32 op_to_immdlen;
3160 __be32 flowid_len16;
3161 __u64 cookie;
3162 __be16 iq_id;
3163 __be16 r4;
3164 __be32 xfer_len;
3165 __be64 r5;
3166 };
3167
3168 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0
3169 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff
3170 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
3171 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \
3172 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
3173
3174 /******************************************************************************
3175 * F O F C O E W O R K R E Q U E S T s
3176 *******************************************/
3177
3178 struct fw_fcoe_els_ct_wr {
3179 __be32 op_immdlen;
3180 __be32 flowid_len16;
3181 __be64 cookie;
3182 __be16 iqid;
3183 __u8 tmo_val;
3184 __u8 els_ct_type;
3185 __u8 ctl_pri;
3186 __u8 cp_en_class;
3187 __be16 xfer_cnt;
3188 __u8 fl_to_sp;
3189 __u8 l_id[3];
3190 __u8 r5;
3191 __u8 r_id[3];
3192 __be64 rsp_dmaaddr;
3193 __be32 rsp_dmalen;
3194 __be32 r6;
3195 };
3196
3197 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24
3198 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff
3199 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
3200 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
3201 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
3202
3203 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
3204 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff
3205 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
3206 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
3207 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
3208
3209 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8
3210 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff
3211 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
3212 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
3213 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
3214
3215 #define S_FW_FCOE_ELS_CT_WR_LEN16 0
3216 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff
3217 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
3218 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
3219 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
3220
3221 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6
3222 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3
3223 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
3224 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
3225 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
3226
3227 #define S_FW_FCOE_ELS_CT_WR_CLASS 4
3228 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3
3229 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
3230 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
3231 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
3232
3233 #define S_FW_FCOE_ELS_CT_WR_FL 2
3234 #define M_FW_FCOE_ELS_CT_WR_FL 0x1
3235 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL)
3236 #define G_FW_FCOE_ELS_CT_WR_FL(x) \
3237 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
3238 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U)
3239
3240 #define S_FW_FCOE_ELS_CT_WR_NPIV 1
3241 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1
3242 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
3243 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
3244 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
3245 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U)
3246
3247 #define S_FW_FCOE_ELS_CT_WR_SP 0
3248 #define M_FW_FCOE_ELS_CT_WR_SP 0x1
3249 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP)
3250 #define G_FW_FCOE_ELS_CT_WR_SP(x) \
3251 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
3252 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U)
3253
3254 /******************************************************************************
3255 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path)
3256 *****************************************************************************/
3257
3258 struct fw_scsi_write_wr {
3259 __be32 op_immdlen;
3260 __be32 flowid_len16;
3261 __be64 cookie;
3262 __be16 iqid;
3263 __u8 tmo_val;
3264 __u8 use_xfer_cnt;
3265 union fw_scsi_write_priv {
3266 struct fcoe_write_priv {
3267 __u8 ctl_pri;
3268 __u8 cp_en_class;
3269 __u8 r3_lo[2];
3270 } fcoe;
3271 struct iscsi_write_priv {
3272 __u8 r3[4];
3273 } iscsi;
3274 } u;
3275 __be32 xfer_cnt;
3276 __be32 ini_xfer_cnt;
3277 __be64 rsp_dmaaddr;
3278 __be32 rsp_dmalen;
3279 __be32 r4;
3280 };
3281
3282 #define S_FW_SCSI_WRITE_WR_OPCODE 24
3283 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff
3284 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE)
3285 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \
3286 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
3287
3288 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0
3289 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff
3290 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
3291 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
3292 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
3293
3294 #define S_FW_SCSI_WRITE_WR_FLOWID 8
3295 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff
3296 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID)
3297 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \
3298 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
3299
3300 #define S_FW_SCSI_WRITE_WR_LEN16 0
3301 #define M_FW_SCSI_WRITE_WR_LEN16 0xff
3302 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16)
3303 #define G_FW_SCSI_WRITE_WR_LEN16(x) \
3304 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
3305
3306 #define S_FW_SCSI_WRITE_WR_CP_EN 6
3307 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3
3308 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN)
3309 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \
3310 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
3311
3312 #define S_FW_SCSI_WRITE_WR_CLASS 4
3313 #define M_FW_SCSI_WRITE_WR_CLASS 0x3
3314 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS)
3315 #define G_FW_SCSI_WRITE_WR_CLASS(x) \
3316 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
3317
3318 struct fw_scsi_read_wr {
3319 __be32 op_immdlen;
3320 __be32 flowid_len16;
3321 __be64 cookie;
3322 __be16 iqid;
3323 __u8 tmo_val;
3324 __u8 use_xfer_cnt;
3325 union fw_scsi_read_priv {
3326 struct fcoe_read_priv {
3327 __u8 ctl_pri;
3328 __u8 cp_en_class;
3329 __u8 r3_lo[2];
3330 } fcoe;
3331 struct iscsi_read_priv {
3332 __u8 r3[4];
3333 } iscsi;
3334 } u;
3335 __be32 xfer_cnt;
3336 __be32 ini_xfer_cnt;
3337 __be64 rsp_dmaaddr;
3338 __be32 rsp_dmalen;
3339 __be32 r4;
3340 };
3341
3342 #define S_FW_SCSI_READ_WR_OPCODE 24
3343 #define M_FW_SCSI_READ_WR_OPCODE 0xff
3344 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE)
3345 #define G_FW_SCSI_READ_WR_OPCODE(x) \
3346 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
3347
3348 #define S_FW_SCSI_READ_WR_IMMDLEN 0
3349 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff
3350 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN)
3351 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \
3352 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
3353
3354 #define S_FW_SCSI_READ_WR_FLOWID 8
3355 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff
3356 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID)
3357 #define G_FW_SCSI_READ_WR_FLOWID(x) \
3358 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
3359
3360 #define S_FW_SCSI_READ_WR_LEN16 0
3361 #define M_FW_SCSI_READ_WR_LEN16 0xff
3362 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16)
3363 #define G_FW_SCSI_READ_WR_LEN16(x) \
3364 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
3365
3366 #define S_FW_SCSI_READ_WR_CP_EN 6
3367 #define M_FW_SCSI_READ_WR_CP_EN 0x3
3368 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN)
3369 #define G_FW_SCSI_READ_WR_CP_EN(x) \
3370 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3371
3372 #define S_FW_SCSI_READ_WR_CLASS 4
3373 #define M_FW_SCSI_READ_WR_CLASS 0x3
3374 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS)
3375 #define G_FW_SCSI_READ_WR_CLASS(x) \
3376 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3377
3378 struct fw_scsi_cmd_wr {
3379 __be32 op_immdlen;
3380 __be32 flowid_len16;
3381 __be64 cookie;
3382 __be16 iqid;
3383 __u8 tmo_val;
3384 __u8 r3;
3385 union fw_scsi_cmd_priv {
3386 struct fcoe_cmd_priv {
3387 __u8 ctl_pri;
3388 __u8 cp_en_class;
3389 __u8 r4_lo[2];
3390 } fcoe;
3391 struct iscsi_cmd_priv {
3392 __u8 r4[4];
3393 } iscsi;
3394 } u;
3395 __u8 r5[8];
3396 __be64 rsp_dmaaddr;
3397 __be32 rsp_dmalen;
3398 __be32 r6;
3399 };
3400
3401 #define S_FW_SCSI_CMD_WR_OPCODE 24
3402 #define M_FW_SCSI_CMD_WR_OPCODE 0xff
3403 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE)
3404 #define G_FW_SCSI_CMD_WR_OPCODE(x) \
3405 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3406
3407 #define S_FW_SCSI_CMD_WR_IMMDLEN 0
3408 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff
3409 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3410 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
3411 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3412
3413 #define S_FW_SCSI_CMD_WR_FLOWID 8
3414 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff
3415 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID)
3416 #define G_FW_SCSI_CMD_WR_FLOWID(x) \
3417 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3418
3419 #define S_FW_SCSI_CMD_WR_LEN16 0
3420 #define M_FW_SCSI_CMD_WR_LEN16 0xff
3421 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16)
3422 #define G_FW_SCSI_CMD_WR_LEN16(x) \
3423 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3424
3425 #define S_FW_SCSI_CMD_WR_CP_EN 6
3426 #define M_FW_SCSI_CMD_WR_CP_EN 0x3
3427 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN)
3428 #define G_FW_SCSI_CMD_WR_CP_EN(x) \
3429 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3430
3431 #define S_FW_SCSI_CMD_WR_CLASS 4
3432 #define M_FW_SCSI_CMD_WR_CLASS 0x3
3433 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS)
3434 #define G_FW_SCSI_CMD_WR_CLASS(x) \
3435 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3436
3437 struct fw_scsi_abrt_cls_wr {
3438 __be32 op_immdlen;
3439 __be32 flowid_len16;
3440 __be64 cookie;
3441 __be16 iqid;
3442 __u8 tmo_val;
3443 __u8 sub_opcode_to_chk_all_io;
3444 __u8 r3[4];
3445 __be64 t_cookie;
3446 };
3447
3448 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24
3449 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff
3450 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3451 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
3452 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3453
3454 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
3455 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff
3456 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3457 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3458 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3459 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3460
3461 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8
3462 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff
3463 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3464 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
3465 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3466
3467 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
3468 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff
3469 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3470 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
3471 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3472
3473 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2
3474 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f
3475 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3476 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3477 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3478 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3479 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3480
3481 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1
3482 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1
3483 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3484 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
3485 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3486 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3487
3488 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
3489 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1
3490 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3491 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3492 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3493 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3494 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3495 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
3496 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3497
3498 struct fw_scsi_tgt_acc_wr {
3499 __be32 op_immdlen;
3500 __be32 flowid_len16;
3501 __be64 cookie;
3502 __be16 iqid;
3503 __u8 r3;
3504 __u8 use_burst_len;
3505 union fw_scsi_tgt_acc_priv {
3506 struct fcoe_tgt_acc_priv {
3507 __u8 ctl_pri;
3508 __u8 cp_en_class;
3509 __u8 r4_lo[2];
3510 } fcoe;
3511 struct iscsi_tgt_acc_priv {
3512 __u8 r4[4];
3513 } iscsi;
3514 } u;
3515 __be32 burst_len;
3516 __be32 rel_off;
3517 __be64 r5;
3518 __be32 r6;
3519 __be32 tot_xfer_len;
3520 };
3521
3522 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24
3523 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff
3524 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3525 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
3526 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3527
3528 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
3529 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff
3530 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3531 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
3532 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3533
3534 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8
3535 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff
3536 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3537 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
3538 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3539
3540 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0
3541 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff
3542 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3543 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
3544 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3545
3546 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6
3547 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3
3548 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3549 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
3550 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3551
3552 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4
3553 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3
3554 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3555 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
3556 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3557
3558 struct fw_scsi_tgt_xmit_wr {
3559 __be32 op_immdlen;
3560 __be32 flowid_len16;
3561 __be64 cookie;
3562 __be16 iqid;
3563 __u8 auto_rsp;
3564 __u8 use_xfer_cnt;
3565 union fw_scsi_tgt_xmit_priv {
3566 struct fcoe_tgt_xmit_priv {
3567 __u8 ctl_pri;
3568 __u8 cp_en_class;
3569 __u8 r3_lo[2];
3570 } fcoe;
3571 struct iscsi_tgt_xmit_priv {
3572 __u8 r3[4];
3573 } iscsi;
3574 } u;
3575 __be32 xfer_cnt;
3576 __be32 r4;
3577 __be64 r5;
3578 __be32 r6;
3579 __be32 tot_xfer_len;
3580 };
3581
3582 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24
3583 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff
3584 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3585 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
3586 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3587
3588 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
3589 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff
3590 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3591 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3592 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3593 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3594
3595 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8
3596 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff
3597 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3598 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
3599 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3600
3601 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
3602 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff
3603 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3604 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
3605 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3606
3607 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6
3608 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3
3609 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3610 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
3611 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3612
3613 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4
3614 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3
3615 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3616 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
3617 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3618
3619 struct fw_scsi_tgt_rsp_wr {
3620 __be32 op_immdlen;
3621 __be32 flowid_len16;
3622 __be64 cookie;
3623 __be16 iqid;
3624 __u8 r3[2];
3625 union fw_scsi_tgt_rsp_priv {
3626 struct fcoe_tgt_rsp_priv {
3627 __u8 ctl_pri;
3628 __u8 cp_en_class;
3629 __u8 r4_lo[2];
3630 } fcoe;
3631 struct iscsi_tgt_rsp_priv {
3632 __u8 r4[4];
3633 } iscsi;
3634 } u;
3635 __u8 r5[8];
3636 };
3637
3638 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24
3639 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff
3640 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3641 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
3642 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3643
3644 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
3645 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff
3646 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3647 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
3648 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3649
3650 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8
3651 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff
3652 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3653 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
3654 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3655
3656 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0
3657 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff
3658 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3659 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
3660 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3661
3662 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6
3663 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3
3664 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3665 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
3666 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3667
3668 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4
3669 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3
3670 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3671 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
3672 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3673
3674 struct fw_pofcoe_tcb_wr {
3675 __be32 op_compl;
3676 __be32 equiq_to_len16;
3677 __be32 r4;
3678 __be32 xfer_len;
3679 __be32 tid_to_port;
3680 __be16 x_id;
3681 __be16 vlan_id;
3682 __be64 cookie;
3683 __be32 s_id;
3684 __be32 d_id;
3685 __be32 tag;
3686 __be16 r6;
3687 __be16 iqid;
3688 };
3689
3690 #define S_FW_POFCOE_TCB_WR_TID 12
3691 #define M_FW_POFCOE_TCB_WR_TID 0xfffff
3692 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID)
3693 #define G_FW_POFCOE_TCB_WR_TID(x) \
3694 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3695
3696 #define S_FW_POFCOE_TCB_WR_ALLOC 4
3697 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1
3698 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3699 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \
3700 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3701 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U)
3702
3703 #define S_FW_POFCOE_TCB_WR_FREE 3
3704 #define M_FW_POFCOE_TCB_WR_FREE 0x1
3705 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE)
3706 #define G_FW_POFCOE_TCB_WR_FREE(x) \
3707 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3708 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)
3709
3710 #define S_FW_POFCOE_TCB_WR_PORT 0
3711 #define M_FW_POFCOE_TCB_WR_PORT 0x7
3712 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT)
3713 #define G_FW_POFCOE_TCB_WR_PORT(x) \
3714 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3715
3716 struct fw_pofcoe_ulptx_wr {
3717 __be32 op_pkd;
3718 __be32 equiq_to_len16;
3719 __u64 cookie;
3720 };
3721
3722 /*******************************************************************
3723 * T10 DIF related definition
3724 *******************************************************************/
3725 struct fw_tx_pi_header {
3726 __be16 op_to_inline;
3727 __u8 pi_interval_tag_type;
3728 __u8 num_pi;
3729 __be32 pi_start4_pi_end4;
3730 __u8 tag_gen_enabled_pkd;
3731 __u8 num_pi_dsg;
3732 __be16 app_tag;
3733 __be32 ref_tag;
3734 };
3735
3736 #define S_FW_TX_PI_HEADER_OP 8
3737 #define M_FW_TX_PI_HEADER_OP 0xff
3738 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP)
3739 #define G_FW_TX_PI_HEADER_OP(x) \
3740 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3741
3742 #define S_FW_TX_PI_HEADER_ULPTXMORE 7
3743 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1
3744 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3745 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \
3746 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3747 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3748
3749 #define S_FW_TX_PI_HEADER_PI_CONTROL 4
3750 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7
3751 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3752 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \
3753 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3754
3755 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2
3756 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1
3757 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3758 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \
3759 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3760 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3761
3762 #define S_FW_TX_PI_HEADER_VALIDATE 1
3763 #define M_FW_TX_PI_HEADER_VALIDATE 0x1
3764 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE)
3765 #define G_FW_TX_PI_HEADER_VALIDATE(x) \
3766 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3767 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U)
3768
3769 #define S_FW_TX_PI_HEADER_INLINE 0
3770 #define M_FW_TX_PI_HEADER_INLINE 0x1
3771 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE)
3772 #define G_FW_TX_PI_HEADER_INLINE(x) \
3773 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3774 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U)
3775
3776 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7
3777 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1
3778 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3779 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3780 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3781 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3782 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3783
3784 #define S_FW_TX_PI_HEADER_TAG_TYPE 5
3785 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3
3786 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3787 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \
3788 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3789
3790 #define S_FW_TX_PI_HEADER_PI_START4 22
3791 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff
3792 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4)
3793 #define G_FW_TX_PI_HEADER_PI_START4(x) \
3794 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3795
3796 #define S_FW_TX_PI_HEADER_PI_END4 0
3797 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff
3798 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4)
3799 #define G_FW_TX_PI_HEADER_PI_END4(x) \
3800 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3801
3802 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6
3803 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3
3804 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3805 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3806 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3807 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3808 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3809
3810 enum fw_pi_error_type {
3811 FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3812 };
3813
3814 struct fw_pi_error {
3815 __be32 err_type_pkd;
3816 __be32 flowid_len16;
3817 __be16 r2;
3818 __be16 app_tag;
3819 __be32 ref_tag;
3820 __be32 pisc[4];
3821 };
3822
3823 #define S_FW_PI_ERROR_ERR_TYPE 24
3824 #define M_FW_PI_ERROR_ERR_TYPE 0xff
3825 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE)
3826 #define G_FW_PI_ERROR_ERR_TYPE(x) \
3827 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3828
3829 struct fw_tlstx_data_wr {
3830 __be32 op_to_immdlen;
3831 __be32 flowid_len16;
3832 __be32 plen;
3833 __be32 lsodisable_to_flags;
3834 __be32 r5;
3835 __be32 ctxloc_to_exp;
3836 __be16 mfs;
3837 __be16 adjustedplen_pkd;
3838 __be16 expinplenmax_pkd;
3839 __u8 pdusinplenmax_pkd;
3840 __u8 r10;
3841 };
3842
3843 #define S_FW_TLSTX_DATA_WR_OPCODE 24
3844 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff
3845 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3846 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \
3847 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3848
3849 #define S_FW_TLSTX_DATA_WR_COMPL 21
3850 #define M_FW_TLSTX_DATA_WR_COMPL 0x1
3851 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3852 #define G_FW_TLSTX_DATA_WR_COMPL(x) \
3853 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3854 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U)
3855
3856 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0
3857 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff
3858 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3859 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \
3860 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3861
3862 #define S_FW_TLSTX_DATA_WR_FLOWID 8
3863 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff
3864 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3865 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \
3866 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3867
3868 #define S_FW_TLSTX_DATA_WR_LEN16 0
3869 #define M_FW_TLSTX_DATA_WR_LEN16 0xff
3870 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3871 #define G_FW_TLSTX_DATA_WR_LEN16(x) \
3872 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3873
3874 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31
3875 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1
3876 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3877 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3878 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3879 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3880 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3881
3882 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30
3883 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1
3884 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3885 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \
3886 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3887 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3888
3889 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3890 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3891 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3892 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3893 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3894 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3895 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3896 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3897
3898 #define S_FW_TLSTX_DATA_WR_FLAGS 0
3899 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff
3900 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3901 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \
3902 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3903
3904 #define S_FW_TLSTX_DATA_WR_CTXLOC 30
3905 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3
3906 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3907 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \
3908 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3909
3910 #define S_FW_TLSTX_DATA_WR_IVDSGL 29
3911 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1
3912 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3913 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \
3914 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3915 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3916
3917 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24
3918 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f
3919 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3920 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \
3921 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3922
3923 #define S_FW_TLSTX_DATA_WR_NUMIVS 14
3924 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff
3925 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3926 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \
3927 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3928
3929 #define S_FW_TLSTX_DATA_WR_EXP 0
3930 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff
3931 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP)
3932 #define G_FW_TLSTX_DATA_WR_EXP(x) \
3933 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3934
3935 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3936 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3937 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3938 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3939 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3940 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3941 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3942
3943 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3944 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3945 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3946 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3947 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3948 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3949 M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3950
3951 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3952 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3953 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3954 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3955 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3956 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3957 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3958
3959 struct fw_crypto_lookaside_wr {
3960 __be32 op_to_cctx_size;
3961 __be32 len16_pkd;
3962 __be32 session_id;
3963 __be32 rx_chid_to_rx_q_id;
3964 __be32 key_addr;
3965 __be32 pld_size_hash_size;
3966 __be64 cookie;
3967 };
3968
3969 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3970 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3971 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3972 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3973 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3974 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3975 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3976
3977 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3978 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
3979 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3980 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3981 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3982 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
3983 M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3984 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
3985
3986 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
3987 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
3988 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3989 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3990 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3991 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
3992 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3993
3994 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
3995 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
3996 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3997 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3998 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3999 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
4000 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4001
4002 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
4003 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
4004 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4005 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4006 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4007 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
4008 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4009
4010 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
4011 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
4012 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4013 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4014 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4015 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
4016 M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4017
4018 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
4019 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
4020 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4021 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4022 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4023 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
4024 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4025
4026 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27
4027 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3
4028 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4029 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
4030 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4031 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
4032
4033 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
4034 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
4035 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4036 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4037 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4038 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
4039 M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4040
4041 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23
4042 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3
4043 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4044 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
4045 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4046 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
4047
4048 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
4049 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
4050 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4051 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4052 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4053 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
4054 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4055
4056 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
4057 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
4058 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4059 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4060 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4061 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
4062 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4063
4064 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
4065 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
4066 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4067 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4068 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4069 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
4070 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4071
4072 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
4073 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
4074 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4075 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4076 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4077 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
4078 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4079
4080 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
4081 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
4082 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4083 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4084 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4085 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
4086 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4087
4088 struct fw_tls_tunnel_ofld_wr {
4089 __be32 op_compl;
4090 __be32 flowid_len16;
4091 __be32 plen;
4092 __be32 r4;
4093 };
4094
4095 /******************************************************************************
4096 * C O M M A N D s
4097 *********************/
4098
4099 /*
4100 * The maximum length of time, in miliseconds, that we expect any firmware
4101 * command to take to execute and return a reply to the host. The RESET
4102 * and INITIALIZE commands can take a fair amount of time to execute but
4103 * most execute in far less time than this maximum. This constant is used
4104 * by host software to determine how long to wait for a firmware command
4105 * reply before declaring the firmware as dead/unreachable ...
4106 */
4107 #define FW_CMD_MAX_TIMEOUT 10000
4108
4109 /*
4110 * If a host driver does a HELLO and discovers that there's already a MASTER
4111 * selected, we may have to wait for that MASTER to finish issuing RESET,
4112 * configuration and INITIALIZE commands. Also, there's a possibility that
4113 * our own HELLO may get lost if it happens right as the MASTER is issuign a
4114 * RESET command, so we need to be willing to make a few retries of our HELLO.
4115 */
4116 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
4117 #define FW_CMD_HELLO_RETRIES 3
4118
4119 enum fw_cmd_opcodes {
4120 FW_LDST_CMD = 0x01,
4121 FW_RESET_CMD = 0x03,
4122 FW_HELLO_CMD = 0x04,
4123 FW_BYE_CMD = 0x05,
4124 FW_INITIALIZE_CMD = 0x06,
4125 FW_CAPS_CONFIG_CMD = 0x07,
4126 FW_PARAMS_CMD = 0x08,
4127 FW_PFVF_CMD = 0x09,
4128 FW_IQ_CMD = 0x10,
4129 FW_EQ_MNGT_CMD = 0x11,
4130 FW_EQ_ETH_CMD = 0x12,
4131 FW_EQ_CTRL_CMD = 0x13,
4132 FW_EQ_OFLD_CMD = 0x21,
4133 FW_VI_CMD = 0x14,
4134 FW_VI_MAC_CMD = 0x15,
4135 FW_VI_RXMODE_CMD = 0x16,
4136 FW_VI_ENABLE_CMD = 0x17,
4137 FW_VI_STATS_CMD = 0x1a,
4138 FW_ACL_MAC_CMD = 0x18,
4139 FW_ACL_VLAN_CMD = 0x19,
4140 FW_PORT_CMD = 0x1b,
4141 FW_PORT_STATS_CMD = 0x1c,
4142 FW_PORT_LB_STATS_CMD = 0x1d,
4143 FW_PORT_TRACE_CMD = 0x1e,
4144 FW_PORT_TRACE_MMAP_CMD = 0x1f,
4145 FW_RSS_IND_TBL_CMD = 0x20,
4146 FW_RSS_GLB_CONFIG_CMD = 0x22,
4147 FW_RSS_VI_CONFIG_CMD = 0x23,
4148 FW_SCHED_CMD = 0x24,
4149 FW_DEVLOG_CMD = 0x25,
4150 FW_WATCHDOG_CMD = 0x27,
4151 FW_CLIP_CMD = 0x28,
4152 FW_CLIP2_CMD = 0x29,
4153 FW_CHNET_IFACE_CMD = 0x26,
4154 FW_FCOE_RES_INFO_CMD = 0x31,
4155 FW_FCOE_LINK_CMD = 0x32,
4156 FW_FCOE_VNP_CMD = 0x33,
4157 FW_FCOE_SPARAMS_CMD = 0x35,
4158 FW_FCOE_STATS_CMD = 0x37,
4159 FW_FCOE_FCF_CMD = 0x38,
4160 FW_DCB_IEEE_CMD = 0x3a,
4161 FW_DIAG_CMD = 0x3d,
4162 FW_PTP_CMD = 0x3e,
4163 FW_HMA_CMD = 0x3f,
4164 FW_LASTC2E_CMD = 0x40,
4165 FW_ERROR_CMD = 0x80,
4166 FW_DEBUG_CMD = 0x81,
4167 };
4168
4169 enum fw_cmd_cap {
4170 FW_CMD_CAP_PF = 0x01,
4171 FW_CMD_CAP_DMAQ = 0x02,
4172 FW_CMD_CAP_PORT = 0x04,
4173 FW_CMD_CAP_PORTPROMISC = 0x08,
4174 FW_CMD_CAP_PORTSTATS = 0x10,
4175 FW_CMD_CAP_VF = 0x80,
4176 };
4177
4178 /*
4179 * Generic command header flit0
4180 */
4181 struct fw_cmd_hdr {
4182 __be32 hi;
4183 __be32 lo;
4184 };
4185
4186 #define S_FW_CMD_OP 24
4187 #define M_FW_CMD_OP 0xff
4188 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
4189 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
4190
4191 #define S_FW_CMD_REQUEST 23
4192 #define M_FW_CMD_REQUEST 0x1
4193 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
4194 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
4195 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
4196
4197 #define S_FW_CMD_READ 22
4198 #define M_FW_CMD_READ 0x1
4199 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
4200 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
4201 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
4202
4203 #define S_FW_CMD_WRITE 21
4204 #define M_FW_CMD_WRITE 0x1
4205 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
4206 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
4207 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
4208
4209 #define S_FW_CMD_EXEC 20
4210 #define M_FW_CMD_EXEC 0x1
4211 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
4212 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
4213 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
4214
4215 #define S_FW_CMD_RAMASK 20
4216 #define M_FW_CMD_RAMASK 0xf
4217 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK)
4218 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
4219
4220 #define S_FW_CMD_RETVAL 8
4221 #define M_FW_CMD_RETVAL 0xff
4222 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
4223 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
4224
4225 #define S_FW_CMD_LEN16 0
4226 #define M_FW_CMD_LEN16 0xff
4227 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
4228 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
4229
4230 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
4231
4232 /*
4233 * address spaces
4234 */
4235 enum fw_ldst_addrspc {
4236 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
4237 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
4238 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
4239 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
4240 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
4241 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
4242 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
4243 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
4244 FW_LDST_ADDRSPC_MDIO = 0x0018,
4245 FW_LDST_ADDRSPC_MPS = 0x0020,
4246 FW_LDST_ADDRSPC_FUNC = 0x0028,
4247 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
4248 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */
4249 FW_LDST_ADDRSPC_LE = 0x0030,
4250 FW_LDST_ADDRSPC_I2C = 0x0038,
4251 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
4252 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041,
4253 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042,
4254 FW_LDST_ADDRSPC_CIM_Q = 0x0048,
4255 };
4256
4257 /*
4258 * MDIO VSC8634 register access control field
4259 */
4260 enum fw_ldst_mdio_vsc8634_aid {
4261 FW_LDST_MDIO_VS_STANDARD,
4262 FW_LDST_MDIO_VS_EXTENDED,
4263 FW_LDST_MDIO_VS_GPIO
4264 };
4265
4266 enum fw_ldst_mps_fid {
4267 FW_LDST_MPS_ATRB,
4268 FW_LDST_MPS_RPLC
4269 };
4270
4271 enum fw_ldst_func_access_ctl {
4272 FW_LDST_FUNC_ACC_CTL_VIID,
4273 FW_LDST_FUNC_ACC_CTL_FID
4274 };
4275
4276 enum fw_ldst_func_mod_index {
4277 FW_LDST_FUNC_MPS
4278 };
4279
4280 struct fw_ldst_cmd {
4281 __be32 op_to_addrspace;
4282 __be32 cycles_to_len16;
4283 union fw_ldst {
4284 struct fw_ldst_addrval {
4285 __be32 addr;
4286 __be32 val;
4287 } addrval;
4288 struct fw_ldst_idctxt {
4289 __be32 physid;
4290 __be32 msg_ctxtflush;
4291 __be32 ctxt_data7;
4292 __be32 ctxt_data6;
4293 __be32 ctxt_data5;
4294 __be32 ctxt_data4;
4295 __be32 ctxt_data3;
4296 __be32 ctxt_data2;
4297 __be32 ctxt_data1;
4298 __be32 ctxt_data0;
4299 } idctxt;
4300 struct fw_ldst_mdio {
4301 __be16 paddr_mmd;
4302 __be16 raddr;
4303 __be16 vctl;
4304 __be16 rval;
4305 } mdio;
4306 struct fw_ldst_cim_rq {
4307 __u8 req_first64[8];
4308 __u8 req_second64[8];
4309 __u8 resp_first64[8];
4310 __u8 resp_second64[8];
4311 __be32 r3[2];
4312 } cim_rq;
4313 union fw_ldst_mps {
4314 struct fw_ldst_mps_rplc {
4315 __be16 fid_idx;
4316 __be16 rplcpf_pkd;
4317 __be32 rplc255_224;
4318 __be32 rplc223_192;
4319 __be32 rplc191_160;
4320 __be32 rplc159_128;
4321 __be32 rplc127_96;
4322 __be32 rplc95_64;
4323 __be32 rplc63_32;
4324 __be32 rplc31_0;
4325 } rplc;
4326 struct fw_ldst_mps_atrb {
4327 __be16 fid_mpsid;
4328 __be16 r2[3];
4329 __be32 r3[2];
4330 __be32 r4;
4331 __be32 atrb;
4332 __be16 vlan[16];
4333 } atrb;
4334 } mps;
4335 struct fw_ldst_func {
4336 __u8 access_ctl;
4337 __u8 mod_index;
4338 __be16 ctl_id;
4339 __be32 offset;
4340 __be64 data0;
4341 __be64 data1;
4342 } func;
4343 struct fw_ldst_pcie {
4344 __u8 ctrl_to_fn;
4345 __u8 bnum;
4346 __u8 r;
4347 __u8 ext_r;
4348 __u8 select_naccess;
4349 __u8 pcie_fn;
4350 __be16 nset_pkd;
4351 __be32 data[12];
4352 } pcie;
4353 struct fw_ldst_i2c_deprecated {
4354 __u8 pid_pkd;
4355 __u8 base;
4356 __u8 boffset;
4357 __u8 data;
4358 __be32 r9;
4359 } i2c_deprecated;
4360 struct fw_ldst_i2c {
4361 __u8 pid;
4362 __u8 did;
4363 __u8 boffset;
4364 __u8 blen;
4365 __be32 r9;
4366 __u8 data[48];
4367 } i2c;
4368 struct fw_ldst_le {
4369 __be32 index;
4370 __be32 r9;
4371 __u8 val[33];
4372 __u8 r11[7];
4373 } le;
4374 } u;
4375 };
4376
4377 #define S_FW_LDST_CMD_ADDRSPACE 0
4378 #define M_FW_LDST_CMD_ADDRSPACE 0xff
4379 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
4380 #define G_FW_LDST_CMD_ADDRSPACE(x) \
4381 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4382
4383 #define S_FW_LDST_CMD_CYCLES 16
4384 #define M_FW_LDST_CMD_CYCLES 0xffff
4385 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES)
4386 #define G_FW_LDST_CMD_CYCLES(x) \
4387 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4388
4389 #define S_FW_LDST_CMD_MSG 31
4390 #define M_FW_LDST_CMD_MSG 0x1
4391 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG)
4392 #define G_FW_LDST_CMD_MSG(x) \
4393 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4394 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U)
4395
4396 #define S_FW_LDST_CMD_CTXTFLUSH 30
4397 #define M_FW_LDST_CMD_CTXTFLUSH 0x1
4398 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH)
4399 #define G_FW_LDST_CMD_CTXTFLUSH(x) \
4400 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4401 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U)
4402
4403 #define S_FW_LDST_CMD_PADDR 8
4404 #define M_FW_LDST_CMD_PADDR 0x1f
4405 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR)
4406 #define G_FW_LDST_CMD_PADDR(x) \
4407 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4408
4409 #define S_FW_LDST_CMD_MMD 0
4410 #define M_FW_LDST_CMD_MMD 0x1f
4411 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD)
4412 #define G_FW_LDST_CMD_MMD(x) \
4413 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4414
4415 #define S_FW_LDST_CMD_FID 15
4416 #define M_FW_LDST_CMD_FID 0x1
4417 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID)
4418 #define G_FW_LDST_CMD_FID(x) \
4419 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4420 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U)
4421
4422 #define S_FW_LDST_CMD_IDX 0
4423 #define M_FW_LDST_CMD_IDX 0x7fff
4424 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX)
4425 #define G_FW_LDST_CMD_IDX(x) \
4426 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4427
4428 #define S_FW_LDST_CMD_RPLCPF 0
4429 #define M_FW_LDST_CMD_RPLCPF 0xff
4430 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF)
4431 #define G_FW_LDST_CMD_RPLCPF(x) \
4432 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4433
4434 #define S_FW_LDST_CMD_MPSID 0
4435 #define M_FW_LDST_CMD_MPSID 0x7fff
4436 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID)
4437 #define G_FW_LDST_CMD_MPSID(x) \
4438 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4439
4440 #define S_FW_LDST_CMD_CTRL 7
4441 #define M_FW_LDST_CMD_CTRL 0x1
4442 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL)
4443 #define G_FW_LDST_CMD_CTRL(x) \
4444 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4445 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U)
4446
4447 #define S_FW_LDST_CMD_LC 4
4448 #define M_FW_LDST_CMD_LC 0x1
4449 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC)
4450 #define G_FW_LDST_CMD_LC(x) \
4451 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4452 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U)
4453
4454 #define S_FW_LDST_CMD_AI 3
4455 #define M_FW_LDST_CMD_AI 0x1
4456 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI)
4457 #define G_FW_LDST_CMD_AI(x) \
4458 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4459 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U)
4460
4461 #define S_FW_LDST_CMD_FN 0
4462 #define M_FW_LDST_CMD_FN 0x7
4463 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN)
4464 #define G_FW_LDST_CMD_FN(x) \
4465 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4466
4467 #define S_FW_LDST_CMD_SELECT 4
4468 #define M_FW_LDST_CMD_SELECT 0xf
4469 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT)
4470 #define G_FW_LDST_CMD_SELECT(x) \
4471 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4472
4473 #define S_FW_LDST_CMD_NACCESS 0
4474 #define M_FW_LDST_CMD_NACCESS 0xf
4475 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS)
4476 #define G_FW_LDST_CMD_NACCESS(x) \
4477 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4478
4479 #define S_FW_LDST_CMD_NSET 14
4480 #define M_FW_LDST_CMD_NSET 0x3
4481 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET)
4482 #define G_FW_LDST_CMD_NSET(x) \
4483 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4484
4485 #define S_FW_LDST_CMD_PID 6
4486 #define M_FW_LDST_CMD_PID 0x3
4487 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID)
4488 #define G_FW_LDST_CMD_PID(x) \
4489 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4490
4491 struct fw_reset_cmd {
4492 __be32 op_to_write;
4493 __be32 retval_len16;
4494 __be32 val;
4495 __be32 halt_pkd;
4496 };
4497
4498 #define S_FW_RESET_CMD_HALT 31
4499 #define M_FW_RESET_CMD_HALT 0x1
4500 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
4501 #define G_FW_RESET_CMD_HALT(x) \
4502 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4503 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
4504
4505 enum {
4506 FW_HELLO_CMD_STAGE_OS = 0,
4507 FW_HELLO_CMD_STAGE_PREOS0 = 1,
4508 FW_HELLO_CMD_STAGE_PREOS1 = 2,
4509 FW_HELLO_CMD_STAGE_POSTOS = 3,
4510 };
4511
4512 struct fw_hello_cmd {
4513 __be32 op_to_write;
4514 __be32 retval_len16;
4515 __be32 err_to_clearinit;
4516 __be32 fwrev;
4517 };
4518
4519 #define S_FW_HELLO_CMD_ERR 31
4520 #define M_FW_HELLO_CMD_ERR 0x1
4521 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
4522 #define G_FW_HELLO_CMD_ERR(x) \
4523 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4524 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
4525
4526 #define S_FW_HELLO_CMD_INIT 30
4527 #define M_FW_HELLO_CMD_INIT 0x1
4528 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
4529 #define G_FW_HELLO_CMD_INIT(x) \
4530 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4531 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
4532
4533 #define S_FW_HELLO_CMD_MASTERDIS 29
4534 #define M_FW_HELLO_CMD_MASTERDIS 0x1
4535 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
4536 #define G_FW_HELLO_CMD_MASTERDIS(x) \
4537 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4538 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
4539
4540 #define S_FW_HELLO_CMD_MASTERFORCE 28
4541 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
4542 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
4543 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
4544 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4545 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
4546
4547 #define S_FW_HELLO_CMD_MBMASTER 24
4548 #define M_FW_HELLO_CMD_MBMASTER 0xf
4549 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
4550 #define G_FW_HELLO_CMD_MBMASTER(x) \
4551 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4552
4553 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23
4554 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1
4555 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4556 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
4557 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4558 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4559
4560 #define S_FW_HELLO_CMD_MBASYNCNOT 20
4561 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
4562 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4563 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
4564 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4565
4566 #define S_FW_HELLO_CMD_STAGE 17
4567 #define M_FW_HELLO_CMD_STAGE 0x7
4568 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
4569 #define G_FW_HELLO_CMD_STAGE(x) \
4570 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4571
4572 #define S_FW_HELLO_CMD_CLEARINIT 16
4573 #define M_FW_HELLO_CMD_CLEARINIT 0x1
4574 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
4575 #define G_FW_HELLO_CMD_CLEARINIT(x) \
4576 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4577 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
4578
4579 struct fw_bye_cmd {
4580 __be32 op_to_write;
4581 __be32 retval_len16;
4582 __be64 r3;
4583 };
4584
4585 struct fw_initialize_cmd {
4586 __be32 op_to_write;
4587 __be32 retval_len16;
4588 __be64 r3;
4589 };
4590
4591 enum fw_caps_config_hm {
4592 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
4593 FW_CAPS_CONFIG_HM_PL = 0x00000002,
4594 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
4595 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
4596 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
4597 FW_CAPS_CONFIG_HM_TP = 0x00000020,
4598 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
4599 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
4600 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
4601 FW_CAPS_CONFIG_HM_MC = 0x00000200,
4602 FW_CAPS_CONFIG_HM_LE = 0x00000400,
4603 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
4604 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
4605 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
4606 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
4607 FW_CAPS_CONFIG_HM_MI = 0x00008000,
4608 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
4609 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
4610 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
4611 FW_CAPS_CONFIG_HM_MA = 0x00080000,
4612 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
4613 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
4614 FW_CAPS_CONFIG_HM_UART = 0x00400000,
4615 FW_CAPS_CONFIG_HM_SF = 0x00800000,
4616 };
4617
4618 /*
4619 * The VF Register Map.
4620 *
4621 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4622 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4623 * the Slice to Module Map Table (see below) in the Physical Function Register
4624 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4625 * and Offset registers in the PF Register Map. The MBDATA base address is
4626 * quite constrained as it determines the Mailbox Data addresses for both PFs
4627 * and VFs, and therefore must fit in both the VF and PF Register Maps without
4628 * overlapping other registers.
4629 */
4630 #define FW_T4VF_SGE_BASE_ADDR 0x0000
4631 #define FW_T4VF_MPS_BASE_ADDR 0x0100
4632 #define FW_T4VF_PL_BASE_ADDR 0x0200
4633 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
4634 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */
4635 #define FW_T4VF_CIM_BASE_ADDR 0x0300
4636
4637 #define FW_T4VF_REGMAP_START 0x0000
4638 #define FW_T4VF_REGMAP_SIZE 0x0400
4639
4640 enum fw_caps_config_nbm {
4641 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
4642 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
4643 };
4644
4645 enum fw_caps_config_link {
4646 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
4647 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
4648 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
4649 };
4650
4651 enum fw_caps_config_switch {
4652 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
4653 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
4654 };
4655
4656 enum fw_caps_config_nic {
4657 FW_CAPS_CONFIG_NIC = 0x00000001,
4658 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
4659 FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
4660 FW_CAPS_CONFIG_NIC_UM = 0x00000008,
4661 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
4662 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
4663 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
4664 };
4665
4666 enum fw_caps_config_toe {
4667 FW_CAPS_CONFIG_TOE = 0x00000001,
4668 };
4669
4670 enum fw_caps_config_rdma {
4671 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
4672 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
4673 };
4674
4675 enum fw_caps_config_iscsi {
4676 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4677 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4678 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4679 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4680 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4681 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4682 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4683 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4684 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4685 };
4686
4687 enum fw_caps_config_crypto {
4688 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4689 FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4690 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
4691 FW_CAPS_CONFIG_TLS_HW = 0x00000008,
4692 };
4693
4694 enum fw_caps_config_fcoe {
4695 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
4696 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
4697 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
4698 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4699 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
4700 };
4701
4702 enum fw_memtype_cf {
4703 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
4704 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
4705 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
4706 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
4707 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
4708 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
4709 };
4710
4711 struct fw_caps_config_cmd {
4712 __be32 op_to_write;
4713 __be32 cfvalid_to_len16;
4714 __be32 r2;
4715 __be32 hwmbitmap;
4716 __be16 nbmcaps;
4717 __be16 linkcaps;
4718 __be16 switchcaps;
4719 __be16 r3;
4720 __be16 niccaps;
4721 __be16 toecaps;
4722 __be16 rdmacaps;
4723 __be16 cryptocaps;
4724 __be16 iscsicaps;
4725 __be16 fcoecaps;
4726 __be32 cfcsum;
4727 __be32 finiver;
4728 __be32 finicsum;
4729 };
4730
4731 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
4732 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
4733 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4734 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
4735 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4736 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4737
4738 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
4739 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
4740 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4741 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4742 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4743 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4744 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4745
4746 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4747 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4748 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4749 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4750 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4751 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4752 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4753
4754 /*
4755 * params command mnemonics
4756 */
4757 enum fw_params_mnem {
4758 FW_PARAMS_MNEM_DEV = 1, /* device params */
4759 FW_PARAMS_MNEM_PFVF = 2, /* function params */
4760 FW_PARAMS_MNEM_REG = 3, /* limited register access */
4761 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
4762 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
4763 FW_PARAMS_MNEM_LAST
4764 };
4765
4766 /*
4767 * device parameters
4768 */
4769 #define S_FW_PARAMS_PARAM_FILTER_MODE 16
4770 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
4771 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
4772 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
4773 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
4774 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
4775 M_FW_PARAMS_PARAM_FILTER_MODE)
4776
4777 #define S_FW_PARAMS_PARAM_FILTER_MASK 0
4778 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
4779 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
4780 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
4781 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
4782 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
4783 M_FW_PARAMS_PARAM_FILTER_MASK)
4784
4785 enum fw_params_param_dev {
4786 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
4787 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
4788 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
4789 * allocated by the device's
4790 * Lookup Engine
4791 */
4792 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4793 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,
4794 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4795 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4796 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07,
4797 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4798 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4799 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4800 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
4801 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
4802 FW_PARAMS_PARAM_DEV_CF = 0x0D,
4803 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
4804 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
4805 FW_PARAMS_PARAM_DEV_LOAD = 0x10,
4806 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
4807 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
4808 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4809 */
4810 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4811 */
4812 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4813 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
4814 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4815 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
4816 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
4817 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
4818 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
4819 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
4820 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
4821
4822 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
4823 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
4824 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
4825 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
4826 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22,
4827 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
4828 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
4829 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,
4830 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
4831 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
4832 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
4833 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
4834 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
4835 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
4836 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,
4837 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,
4838 FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
4839 FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F,
4840 FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30,
4841 FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
4842 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32,
4843 };
4844
4845 /*
4846 * dev bypass parameters; actions and modes
4847 */
4848 enum fw_params_param_dev_bypass {
4849
4850 /* actions
4851 */
4852 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4853 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4854
4855 /* modes
4856 */
4857 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4858 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
4859 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4860 };
4861
4862 enum fw_params_param_dev_phyfw {
4863 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4864 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4865 };
4866
4867 enum fw_params_param_dev_diag {
4868 FW_PARAM_DEV_DIAG_TMP = 0x00,
4869 FW_PARAM_DEV_DIAG_VDD = 0x01,
4870 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
4871 FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03,
4872 };
4873
4874 enum fw_params_param_dev_filter{
4875 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
4876 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
4877 };
4878
4879 enum fw_filter_vnic_mode {
4880 FW_VNIC_MODE_PF_VF = 0,
4881 FW_VNIC_MODE_OUTER_VLAN = 1,
4882 FW_VNIC_MODE_ENCAP_EN = 2,
4883 };
4884
4885 enum fw_params_param_dev_ktls_hw {
4886 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00,
4887 FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01,
4888 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE = 0x00,
4889 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE = 0x01,
4890 };
4891
4892 enum fw_params_param_dev_fwcache {
4893 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
4894 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
4895 };
4896
4897 /*
4898 * physical and virtual function parameters
4899 */
4900 enum fw_params_param_pfvf {
4901 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
4902 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4903 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4904 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4905 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4906 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4907 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4908 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4909 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4910 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4911 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4912 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4913 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4914 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4915 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4916 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4917 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
4918 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4919 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
4920 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4921 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4922 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4923 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
4924 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
4925 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
4926 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
4927 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
4928 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4929 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
4930 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
4931 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
4932 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
4933 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
4934 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4935 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4936 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
4937 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
4938 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4939 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4940 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4941 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4942 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4943 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4944 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4945 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4946 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4947 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
4948 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
4949 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
4950 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
4951 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
4952 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
4953 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
4954 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
4955 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
4956 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
4957 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
4958 };
4959
4960 /*
4961 * virtual link state as seen by the specified VF
4962 */
4963 enum vf_link_states {
4964 VF_LINK_STATE_AUTO = 0x00,
4965 VF_LINK_STATE_ENABLE = 0x01,
4966 VF_LINK_STATE_DISABLE = 0x02,
4967 };
4968
4969 /*
4970 * dma queue parameters
4971 */
4972 enum fw_params_param_dmaq {
4973 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4974 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4975 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
4976 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03,
4977 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4978 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4979 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4980 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4981 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
4982 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
4983 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
4984 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
4985 };
4986
4987 /*
4988 * chnet parameters
4989 */
4990 enum fw_params_param_chnet {
4991 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00,
4992 };
4993
4994 enum fw_params_param_chnet_flags {
4995 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,
4996 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2,
4997 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
4998 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8,
4999 };
5000
5001 #define S_FW_PARAMS_MNEM 24
5002 #define M_FW_PARAMS_MNEM 0xff
5003 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
5004 #define G_FW_PARAMS_MNEM(x) \
5005 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
5006
5007 #define S_FW_PARAMS_PARAM_X 16
5008 #define M_FW_PARAMS_PARAM_X 0xff
5009 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
5010 #define G_FW_PARAMS_PARAM_X(x) \
5011 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
5012
5013 #define S_FW_PARAMS_PARAM_Y 8
5014 #define M_FW_PARAMS_PARAM_Y 0xff
5015 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
5016 #define G_FW_PARAMS_PARAM_Y(x) \
5017 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
5018
5019 #define S_FW_PARAMS_PARAM_Z 0
5020 #define M_FW_PARAMS_PARAM_Z 0xff
5021 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
5022 #define G_FW_PARAMS_PARAM_Z(x) \
5023 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
5024
5025 #define S_FW_PARAMS_PARAM_XYZ 0
5026 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
5027 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
5028 #define G_FW_PARAMS_PARAM_XYZ(x) \
5029 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
5030
5031 #define S_FW_PARAMS_PARAM_YZ 0
5032 #define M_FW_PARAMS_PARAM_YZ 0xffff
5033 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
5034 #define G_FW_PARAMS_PARAM_YZ(x) \
5035 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
5036
5037 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
5038 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
5039 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5040 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5041 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
5042 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
5043 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
5044
5045 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
5046 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
5047 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5048 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5049 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
5050 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
5051 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
5052
5053 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0
5054 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff
5055 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5056 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5057 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
5058 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
5059
5060 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29
5061 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7
5062 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
5063 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5064 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
5065 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
5066 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
5067
5068 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0
5069 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff
5070 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
5071 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5072 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
5073 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
5074 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
5075
5076 struct fw_params_cmd {
5077 __be32 op_to_vfn;
5078 __be32 retval_len16;
5079 struct fw_params_param {
5080 __be32 mnem;
5081 __be32 val;
5082 } param[7];
5083 };
5084
5085 #define S_FW_PARAMS_CMD_PFN 8
5086 #define M_FW_PARAMS_CMD_PFN 0x7
5087 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
5088 #define G_FW_PARAMS_CMD_PFN(x) \
5089 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
5090
5091 #define S_FW_PARAMS_CMD_VFN 0
5092 #define M_FW_PARAMS_CMD_VFN 0xff
5093 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
5094 #define G_FW_PARAMS_CMD_VFN(x) \
5095 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
5096
5097 struct fw_pfvf_cmd {
5098 __be32 op_to_vfn;
5099 __be32 retval_len16;
5100 __be32 niqflint_niq;
5101 __be32 type_to_neq;
5102 __be32 tc_to_nexactf;
5103 __be32 r_caps_to_nethctrl;
5104 __be16 nricq;
5105 __be16 nriqp;
5106 __be32 r4;
5107 };
5108
5109 #define S_FW_PFVF_CMD_PFN 8
5110 #define M_FW_PFVF_CMD_PFN 0x7
5111 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
5112 #define G_FW_PFVF_CMD_PFN(x) \
5113 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
5114
5115 #define S_FW_PFVF_CMD_VFN 0
5116 #define M_FW_PFVF_CMD_VFN 0xff
5117 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
5118 #define G_FW_PFVF_CMD_VFN(x) \
5119 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
5120
5121 #define S_FW_PFVF_CMD_NIQFLINT 20
5122 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
5123 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT)
5124 #define G_FW_PFVF_CMD_NIQFLINT(x) \
5125 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
5126
5127 #define S_FW_PFVF_CMD_NIQ 0
5128 #define M_FW_PFVF_CMD_NIQ 0xfffff
5129 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ)
5130 #define G_FW_PFVF_CMD_NIQ(x) \
5131 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
5132
5133 #define S_FW_PFVF_CMD_TYPE 31
5134 #define M_FW_PFVF_CMD_TYPE 0x1
5135 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE)
5136 #define G_FW_PFVF_CMD_TYPE(x) \
5137 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
5138 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U)
5139
5140 #define S_FW_PFVF_CMD_CMASK 24
5141 #define M_FW_PFVF_CMD_CMASK 0xf
5142 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK)
5143 #define G_FW_PFVF_CMD_CMASK(x) \
5144 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
5145
5146 #define S_FW_PFVF_CMD_PMASK 20
5147 #define M_FW_PFVF_CMD_PMASK 0xf
5148 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK)
5149 #define G_FW_PFVF_CMD_PMASK(x) \
5150 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
5151
5152 #define S_FW_PFVF_CMD_NEQ 0
5153 #define M_FW_PFVF_CMD_NEQ 0xfffff
5154 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ)
5155 #define G_FW_PFVF_CMD_NEQ(x) \
5156 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
5157
5158 #define S_FW_PFVF_CMD_TC 24
5159 #define M_FW_PFVF_CMD_TC 0xff
5160 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC)
5161 #define G_FW_PFVF_CMD_TC(x) \
5162 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
5163
5164 #define S_FW_PFVF_CMD_NVI 16
5165 #define M_FW_PFVF_CMD_NVI 0xff
5166 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI)
5167 #define G_FW_PFVF_CMD_NVI(x) \
5168 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
5169
5170 #define S_FW_PFVF_CMD_NEXACTF 0
5171 #define M_FW_PFVF_CMD_NEXACTF 0xffff
5172 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF)
5173 #define G_FW_PFVF_CMD_NEXACTF(x) \
5174 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
5175
5176 #define S_FW_PFVF_CMD_R_CAPS 24
5177 #define M_FW_PFVF_CMD_R_CAPS 0xff
5178 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS)
5179 #define G_FW_PFVF_CMD_R_CAPS(x) \
5180 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
5181
5182 #define S_FW_PFVF_CMD_WX_CAPS 16
5183 #define M_FW_PFVF_CMD_WX_CAPS 0xff
5184 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS)
5185 #define G_FW_PFVF_CMD_WX_CAPS(x) \
5186 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
5187
5188 #define S_FW_PFVF_CMD_NETHCTRL 0
5189 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
5190 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL)
5191 #define G_FW_PFVF_CMD_NETHCTRL(x) \
5192 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
5193
5194 /*
5195 * ingress queue type; the first 1K ingress queues can have associated 0,
5196 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
5197 * capabilities
5198 */
5199 enum fw_iq_type {
5200 FW_IQ_TYPE_FL_INT_CAP,
5201 FW_IQ_TYPE_NO_FL_INT_CAP,
5202 FW_IQ_TYPE_VF_CQ
5203 };
5204
5205 enum fw_iq_iqtype {
5206 FW_IQ_IQTYPE_OTHER,
5207 FW_IQ_IQTYPE_NIC,
5208 FW_IQ_IQTYPE_OFLD,
5209 };
5210
5211 struct fw_iq_cmd {
5212 __be32 op_to_vfn;
5213 __be32 alloc_to_len16;
5214 __be16 physiqid;
5215 __be16 iqid;
5216 __be16 fl0id;
5217 __be16 fl1id;
5218 __be32 type_to_iqandstindex;
5219 __be16 iqdroprss_to_iqesize;
5220 __be16 iqsize;
5221 __be64 iqaddr;
5222 __be32 iqns_to_fl0congen;
5223 __be16 fl0dcaen_to_fl0cidxfthresh;
5224 __be16 fl0size;
5225 __be64 fl0addr;
5226 __be32 fl1cngchmap_to_fl1congen;
5227 __be16 fl1dcaen_to_fl1cidxfthresh;
5228 __be16 fl1size;
5229 __be64 fl1addr;
5230 };
5231
5232 #define S_FW_IQ_CMD_PFN 8
5233 #define M_FW_IQ_CMD_PFN 0x7
5234 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
5235 #define G_FW_IQ_CMD_PFN(x) \
5236 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
5237
5238 #define S_FW_IQ_CMD_VFN 0
5239 #define M_FW_IQ_CMD_VFN 0xff
5240 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
5241 #define G_FW_IQ_CMD_VFN(x) \
5242 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
5243
5244 #define S_FW_IQ_CMD_ALLOC 31
5245 #define M_FW_IQ_CMD_ALLOC 0x1
5246 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
5247 #define G_FW_IQ_CMD_ALLOC(x) \
5248 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
5249 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
5250
5251 #define S_FW_IQ_CMD_FREE 30
5252 #define M_FW_IQ_CMD_FREE 0x1
5253 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
5254 #define G_FW_IQ_CMD_FREE(x) \
5255 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
5256 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
5257
5258 #define S_FW_IQ_CMD_MODIFY 29
5259 #define M_FW_IQ_CMD_MODIFY 0x1
5260 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY)
5261 #define G_FW_IQ_CMD_MODIFY(x) \
5262 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
5263 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U)
5264
5265 #define S_FW_IQ_CMD_IQSTART 28
5266 #define M_FW_IQ_CMD_IQSTART 0x1
5267 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
5268 #define G_FW_IQ_CMD_IQSTART(x) \
5269 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
5270 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
5271
5272 #define S_FW_IQ_CMD_IQSTOP 27
5273 #define M_FW_IQ_CMD_IQSTOP 0x1
5274 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
5275 #define G_FW_IQ_CMD_IQSTOP(x) \
5276 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
5277 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
5278
5279 #define S_FW_IQ_CMD_TYPE 29
5280 #define M_FW_IQ_CMD_TYPE 0x7
5281 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
5282 #define G_FW_IQ_CMD_TYPE(x) \
5283 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
5284
5285 #define S_FW_IQ_CMD_IQASYNCH 28
5286 #define M_FW_IQ_CMD_IQASYNCH 0x1
5287 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
5288 #define G_FW_IQ_CMD_IQASYNCH(x) \
5289 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
5290 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
5291
5292 #define S_FW_IQ_CMD_VIID 16
5293 #define M_FW_IQ_CMD_VIID 0xfff
5294 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
5295 #define G_FW_IQ_CMD_VIID(x) \
5296 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
5297
5298 #define S_FW_IQ_CMD_IQANDST 15
5299 #define M_FW_IQ_CMD_IQANDST 0x1
5300 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
5301 #define G_FW_IQ_CMD_IQANDST(x) \
5302 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
5303 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
5304
5305 #define S_FW_IQ_CMD_IQANUS 14
5306 #define M_FW_IQ_CMD_IQANUS 0x1
5307 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS)
5308 #define G_FW_IQ_CMD_IQANUS(x) \
5309 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
5310 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U)
5311
5312 #define S_FW_IQ_CMD_IQANUD 12
5313 #define M_FW_IQ_CMD_IQANUD 0x3
5314 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
5315 #define G_FW_IQ_CMD_IQANUD(x) \
5316 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
5317
5318 #define S_FW_IQ_CMD_IQANDSTINDEX 0
5319 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
5320 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
5321 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
5322 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
5323
5324 #define S_FW_IQ_CMD_IQDROPRSS 15
5325 #define M_FW_IQ_CMD_IQDROPRSS 0x1
5326 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS)
5327 #define G_FW_IQ_CMD_IQDROPRSS(x) \
5328 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
5329 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U)
5330
5331 #define S_FW_IQ_CMD_IQGTSMODE 14
5332 #define M_FW_IQ_CMD_IQGTSMODE 0x1
5333 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
5334 #define G_FW_IQ_CMD_IQGTSMODE(x) \
5335 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
5336 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
5337
5338 #define S_FW_IQ_CMD_IQPCIECH 12
5339 #define M_FW_IQ_CMD_IQPCIECH 0x3
5340 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
5341 #define G_FW_IQ_CMD_IQPCIECH(x) \
5342 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
5343
5344 #define S_FW_IQ_CMD_IQDCAEN 11
5345 #define M_FW_IQ_CMD_IQDCAEN 0x1
5346 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN)
5347 #define G_FW_IQ_CMD_IQDCAEN(x) \
5348 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
5349 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U)
5350
5351 #define S_FW_IQ_CMD_IQDCACPU 6
5352 #define M_FW_IQ_CMD_IQDCACPU 0x1f
5353 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU)
5354 #define G_FW_IQ_CMD_IQDCACPU(x) \
5355 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
5356
5357 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
5358 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
5359 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
5360 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
5361 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
5362
5363 #define S_FW_IQ_CMD_IQO 3
5364 #define M_FW_IQ_CMD_IQO 0x1
5365 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO)
5366 #define G_FW_IQ_CMD_IQO(x) \
5367 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
5368 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U)
5369
5370 #define S_FW_IQ_CMD_IQCPRIO 2
5371 #define M_FW_IQ_CMD_IQCPRIO 0x1
5372 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO)
5373 #define G_FW_IQ_CMD_IQCPRIO(x) \
5374 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
5375 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U)
5376
5377 #define S_FW_IQ_CMD_IQESIZE 0
5378 #define M_FW_IQ_CMD_IQESIZE 0x3
5379 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
5380 #define G_FW_IQ_CMD_IQESIZE(x) \
5381 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
5382
5383 #define S_FW_IQ_CMD_IQNS 31
5384 #define M_FW_IQ_CMD_IQNS 0x1
5385 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS)
5386 #define G_FW_IQ_CMD_IQNS(x) \
5387 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
5388 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U)
5389
5390 #define S_FW_IQ_CMD_IQRO 30
5391 #define M_FW_IQ_CMD_IQRO 0x1
5392 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
5393 #define G_FW_IQ_CMD_IQRO(x) \
5394 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
5395 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
5396
5397 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28
5398 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3
5399 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
5400 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
5401 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5402
5403 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
5404 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
5405 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5406 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
5407 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5408 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5409
5410 #define S_FW_IQ_CMD_IQFLINTISCSIC 26
5411 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1
5412 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5413 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
5414 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5415 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5416
5417 #define S_FW_IQ_CMD_IQTYPE 24
5418 #define M_FW_IQ_CMD_IQTYPE 0x3
5419 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
5420 #define G_FW_IQ_CMD_IQTYPE(x) \
5421 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
5422
5423 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
5424 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
5425 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5426 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
5427 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5428
5429 #define S_FW_IQ_CMD_FL0CONGDROP 16
5430 #define M_FW_IQ_CMD_FL0CONGDROP 0x1
5431 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP)
5432 #define G_FW_IQ_CMD_FL0CONGDROP(x) \
5433 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5434 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U)
5435
5436 #define S_FW_IQ_CMD_FL0CACHELOCK 15
5437 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1
5438 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5439 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \
5440 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5441 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U)
5442
5443 #define S_FW_IQ_CMD_FL0DBP 14
5444 #define M_FW_IQ_CMD_FL0DBP 0x1
5445 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP)
5446 #define G_FW_IQ_CMD_FL0DBP(x) \
5447 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5448 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U)
5449
5450 #define S_FW_IQ_CMD_FL0DATANS 13
5451 #define M_FW_IQ_CMD_FL0DATANS 0x1
5452 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS)
5453 #define G_FW_IQ_CMD_FL0DATANS(x) \
5454 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5455 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U)
5456
5457 #define S_FW_IQ_CMD_FL0DATARO 12
5458 #define M_FW_IQ_CMD_FL0DATARO 0x1
5459 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
5460 #define G_FW_IQ_CMD_FL0DATARO(x) \
5461 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5462 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
5463
5464 #define S_FW_IQ_CMD_FL0CONGCIF 11
5465 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
5466 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
5467 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
5468 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5469 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
5470
5471 #define S_FW_IQ_CMD_FL0ONCHIP 10
5472 #define M_FW_IQ_CMD_FL0ONCHIP 0x1
5473 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP)
5474 #define G_FW_IQ_CMD_FL0ONCHIP(x) \
5475 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5476 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U)
5477
5478 #define S_FW_IQ_CMD_FL0STATUSPGNS 9
5479 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1
5480 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5481 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
5482 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5483 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5484
5485 #define S_FW_IQ_CMD_FL0STATUSPGRO 8
5486 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1
5487 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5488 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
5489 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5490 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5491
5492 #define S_FW_IQ_CMD_FL0FETCHNS 7
5493 #define M_FW_IQ_CMD_FL0FETCHNS 0x1
5494 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS)
5495 #define G_FW_IQ_CMD_FL0FETCHNS(x) \
5496 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5497 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U)
5498
5499 #define S_FW_IQ_CMD_FL0FETCHRO 6
5500 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
5501 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
5502 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
5503 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5504 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
5505
5506 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
5507 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
5508 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5509 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
5510 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5511
5512 #define S_FW_IQ_CMD_FL0CPRIO 3
5513 #define M_FW_IQ_CMD_FL0CPRIO 0x1
5514 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO)
5515 #define G_FW_IQ_CMD_FL0CPRIO(x) \
5516 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5517 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U)
5518
5519 #define S_FW_IQ_CMD_FL0PADEN 2
5520 #define M_FW_IQ_CMD_FL0PADEN 0x1
5521 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
5522 #define G_FW_IQ_CMD_FL0PADEN(x) \
5523 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5524 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
5525
5526 #define S_FW_IQ_CMD_FL0PACKEN 1
5527 #define M_FW_IQ_CMD_FL0PACKEN 0x1
5528 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
5529 #define G_FW_IQ_CMD_FL0PACKEN(x) \
5530 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5531 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
5532
5533 #define S_FW_IQ_CMD_FL0CONGEN 0
5534 #define M_FW_IQ_CMD_FL0CONGEN 0x1
5535 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
5536 #define G_FW_IQ_CMD_FL0CONGEN(x) \
5537 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5538 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
5539
5540 #define S_FW_IQ_CMD_FL0DCAEN 15
5541 #define M_FW_IQ_CMD_FL0DCAEN 0x1
5542 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN)
5543 #define G_FW_IQ_CMD_FL0DCAEN(x) \
5544 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5545 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U)
5546
5547 #define S_FW_IQ_CMD_FL0DCACPU 10
5548 #define M_FW_IQ_CMD_FL0DCACPU 0x1f
5549 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU)
5550 #define G_FW_IQ_CMD_FL0DCACPU(x) \
5551 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5552
5553 #define S_FW_IQ_CMD_FL0FBMIN 7
5554 #define M_FW_IQ_CMD_FL0FBMIN 0x7
5555 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
5556 #define G_FW_IQ_CMD_FL0FBMIN(x) \
5557 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5558
5559 #define S_FW_IQ_CMD_FL0FBMAX 4
5560 #define M_FW_IQ_CMD_FL0FBMAX 0x7
5561 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
5562 #define G_FW_IQ_CMD_FL0FBMAX(x) \
5563 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5564
5565 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3
5566 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1
5567 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5568 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
5569 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5570 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5571
5572 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
5573 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7
5574 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5575 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
5576 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5577
5578 #define S_FW_IQ_CMD_FL1CNGCHMAP 20
5579 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf
5580 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5581 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
5582 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5583
5584 #define S_FW_IQ_CMD_FL1CONGDROP 16
5585 #define M_FW_IQ_CMD_FL1CONGDROP 0x1
5586 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP)
5587 #define G_FW_IQ_CMD_FL1CONGDROP(x) \
5588 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5589 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U)
5590
5591 #define S_FW_IQ_CMD_FL1CACHELOCK 15
5592 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1
5593 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5594 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \
5595 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5596 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U)
5597
5598 #define S_FW_IQ_CMD_FL1DBP 14
5599 #define M_FW_IQ_CMD_FL1DBP 0x1
5600 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP)
5601 #define G_FW_IQ_CMD_FL1DBP(x) \
5602 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5603 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U)
5604
5605 #define S_FW_IQ_CMD_FL1DATANS 13
5606 #define M_FW_IQ_CMD_FL1DATANS 0x1
5607 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS)
5608 #define G_FW_IQ_CMD_FL1DATANS(x) \
5609 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5610 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U)
5611
5612 #define S_FW_IQ_CMD_FL1DATARO 12
5613 #define M_FW_IQ_CMD_FL1DATARO 0x1
5614 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO)
5615 #define G_FW_IQ_CMD_FL1DATARO(x) \
5616 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5617 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U)
5618
5619 #define S_FW_IQ_CMD_FL1CONGCIF 11
5620 #define M_FW_IQ_CMD_FL1CONGCIF 0x1
5621 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF)
5622 #define G_FW_IQ_CMD_FL1CONGCIF(x) \
5623 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5624 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U)
5625
5626 #define S_FW_IQ_CMD_FL1ONCHIP 10
5627 #define M_FW_IQ_CMD_FL1ONCHIP 0x1
5628 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP)
5629 #define G_FW_IQ_CMD_FL1ONCHIP(x) \
5630 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5631 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U)
5632
5633 #define S_FW_IQ_CMD_FL1STATUSPGNS 9
5634 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1
5635 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5636 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
5637 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5638 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5639
5640 #define S_FW_IQ_CMD_FL1STATUSPGRO 8
5641 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1
5642 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5643 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
5644 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5645 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5646
5647 #define S_FW_IQ_CMD_FL1FETCHNS 7
5648 #define M_FW_IQ_CMD_FL1FETCHNS 0x1
5649 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS)
5650 #define G_FW_IQ_CMD_FL1FETCHNS(x) \
5651 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5652 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U)
5653
5654 #define S_FW_IQ_CMD_FL1FETCHRO 6
5655 #define M_FW_IQ_CMD_FL1FETCHRO 0x1
5656 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO)
5657 #define G_FW_IQ_CMD_FL1FETCHRO(x) \
5658 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5659 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U)
5660
5661 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4
5662 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3
5663 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5664 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
5665 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5666
5667 #define S_FW_IQ_CMD_FL1CPRIO 3
5668 #define M_FW_IQ_CMD_FL1CPRIO 0x1
5669 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO)
5670 #define G_FW_IQ_CMD_FL1CPRIO(x) \
5671 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5672 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U)
5673
5674 #define S_FW_IQ_CMD_FL1PADEN 2
5675 #define M_FW_IQ_CMD_FL1PADEN 0x1
5676 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN)
5677 #define G_FW_IQ_CMD_FL1PADEN(x) \
5678 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5679 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U)
5680
5681 #define S_FW_IQ_CMD_FL1PACKEN 1
5682 #define M_FW_IQ_CMD_FL1PACKEN 0x1
5683 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN)
5684 #define G_FW_IQ_CMD_FL1PACKEN(x) \
5685 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5686 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U)
5687
5688 #define S_FW_IQ_CMD_FL1CONGEN 0
5689 #define M_FW_IQ_CMD_FL1CONGEN 0x1
5690 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN)
5691 #define G_FW_IQ_CMD_FL1CONGEN(x) \
5692 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5693 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U)
5694
5695 #define S_FW_IQ_CMD_FL1DCAEN 15
5696 #define M_FW_IQ_CMD_FL1DCAEN 0x1
5697 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN)
5698 #define G_FW_IQ_CMD_FL1DCAEN(x) \
5699 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5700 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U)
5701
5702 #define S_FW_IQ_CMD_FL1DCACPU 10
5703 #define M_FW_IQ_CMD_FL1DCACPU 0x1f
5704 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU)
5705 #define G_FW_IQ_CMD_FL1DCACPU(x) \
5706 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5707
5708 #define S_FW_IQ_CMD_FL1FBMIN 7
5709 #define M_FW_IQ_CMD_FL1FBMIN 0x7
5710 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN)
5711 #define G_FW_IQ_CMD_FL1FBMIN(x) \
5712 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5713
5714 #define S_FW_IQ_CMD_FL1FBMAX 4
5715 #define M_FW_IQ_CMD_FL1FBMAX 0x7
5716 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX)
5717 #define G_FW_IQ_CMD_FL1FBMAX(x) \
5718 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5719
5720 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3
5721 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1
5722 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5723 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
5724 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5725 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5726
5727 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
5728 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7
5729 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5730 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
5731 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5732
5733 struct fw_eq_mngt_cmd {
5734 __be32 op_to_vfn;
5735 __be32 alloc_to_len16;
5736 __be32 cmpliqid_eqid;
5737 __be32 physeqid_pkd;
5738 __be32 fetchszm_to_iqid;
5739 __be32 dcaen_to_eqsize;
5740 __be64 eqaddr;
5741 };
5742
5743 #define S_FW_EQ_MNGT_CMD_PFN 8
5744 #define M_FW_EQ_MNGT_CMD_PFN 0x7
5745 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN)
5746 #define G_FW_EQ_MNGT_CMD_PFN(x) \
5747 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5748
5749 #define S_FW_EQ_MNGT_CMD_VFN 0
5750 #define M_FW_EQ_MNGT_CMD_VFN 0xff
5751 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN)
5752 #define G_FW_EQ_MNGT_CMD_VFN(x) \
5753 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5754
5755 #define S_FW_EQ_MNGT_CMD_ALLOC 31
5756 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1
5757 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5758 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \
5759 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5760 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U)
5761
5762 #define S_FW_EQ_MNGT_CMD_FREE 30
5763 #define M_FW_EQ_MNGT_CMD_FREE 0x1
5764 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE)
5765 #define G_FW_EQ_MNGT_CMD_FREE(x) \
5766 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5767 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U)
5768
5769 #define S_FW_EQ_MNGT_CMD_MODIFY 29
5770 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1
5771 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5772 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \
5773 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5774 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U)
5775
5776 #define S_FW_EQ_MNGT_CMD_EQSTART 28
5777 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1
5778 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5779 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \
5780 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5781 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U)
5782
5783 #define S_FW_EQ_MNGT_CMD_EQSTOP 27
5784 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1
5785 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5786 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
5787 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5788 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5789
5790 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20
5791 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff
5792 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5793 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
5794 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5795
5796 #define S_FW_EQ_MNGT_CMD_EQID 0
5797 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff
5798 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID)
5799 #define G_FW_EQ_MNGT_CMD_EQID(x) \
5800 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5801
5802 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0
5803 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff
5804 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5805 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
5806 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5807
5808 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26
5809 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1
5810 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5811 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
5812 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5813 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5814
5815 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25
5816 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1
5817 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5818 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
5819 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5820 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5821
5822 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24
5823 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1
5824 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5825 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
5826 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5827 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5828
5829 #define S_FW_EQ_MNGT_CMD_FETCHNS 23
5830 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1
5831 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5832 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
5833 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5834 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5835
5836 #define S_FW_EQ_MNGT_CMD_FETCHRO 22
5837 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1
5838 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5839 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
5840 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5841 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5842
5843 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20
5844 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3
5845 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5846 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
5847 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5848
5849 #define S_FW_EQ_MNGT_CMD_CPRIO 19
5850 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1
5851 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5852 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \
5853 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5854 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U)
5855
5856 #define S_FW_EQ_MNGT_CMD_ONCHIP 18
5857 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1
5858 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5859 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
5860 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5861 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5862
5863 #define S_FW_EQ_MNGT_CMD_PCIECHN 16
5864 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3
5865 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5866 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
5867 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5868
5869 #define S_FW_EQ_MNGT_CMD_IQID 0
5870 #define M_FW_EQ_MNGT_CMD_IQID 0xffff
5871 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID)
5872 #define G_FW_EQ_MNGT_CMD_IQID(x) \
5873 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5874
5875 #define S_FW_EQ_MNGT_CMD_DCAEN 31
5876 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1
5877 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5878 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \
5879 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5880 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U)
5881
5882 #define S_FW_EQ_MNGT_CMD_DCACPU 26
5883 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f
5884 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5885 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \
5886 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5887
5888 #define S_FW_EQ_MNGT_CMD_FBMIN 23
5889 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7
5890 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5891 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \
5892 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5893
5894 #define S_FW_EQ_MNGT_CMD_FBMAX 20
5895 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7
5896 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5897 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \
5898 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5899
5900 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19
5901 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1
5902 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5903 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5904 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5905 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5906 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5907
5908 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16
5909 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7
5910 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5911 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
5912 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5913
5914 #define S_FW_EQ_MNGT_CMD_EQSIZE 0
5915 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff
5916 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5917 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
5918 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5919
5920 struct fw_eq_eth_cmd {
5921 __be32 op_to_vfn;
5922 __be32 alloc_to_len16;
5923 __be32 eqid_pkd;
5924 __be32 physeqid_pkd;
5925 __be32 fetchszm_to_iqid;
5926 __be32 dcaen_to_eqsize;
5927 __be64 eqaddr;
5928 __be32 autoequiqe_to_viid;
5929 __be32 timeren_timerix;
5930 __be64 r9;
5931 };
5932
5933 #define S_FW_EQ_ETH_CMD_PFN 8
5934 #define M_FW_EQ_ETH_CMD_PFN 0x7
5935 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
5936 #define G_FW_EQ_ETH_CMD_PFN(x) \
5937 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5938
5939 #define S_FW_EQ_ETH_CMD_VFN 0
5940 #define M_FW_EQ_ETH_CMD_VFN 0xff
5941 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
5942 #define G_FW_EQ_ETH_CMD_VFN(x) \
5943 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5944
5945 #define S_FW_EQ_ETH_CMD_ALLOC 31
5946 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
5947 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
5948 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
5949 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5950 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
5951
5952 #define S_FW_EQ_ETH_CMD_FREE 30
5953 #define M_FW_EQ_ETH_CMD_FREE 0x1
5954 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
5955 #define G_FW_EQ_ETH_CMD_FREE(x) \
5956 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5957 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
5958
5959 #define S_FW_EQ_ETH_CMD_MODIFY 29
5960 #define M_FW_EQ_ETH_CMD_MODIFY 0x1
5961 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY)
5962 #define G_FW_EQ_ETH_CMD_MODIFY(x) \
5963 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5964 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U)
5965
5966 #define S_FW_EQ_ETH_CMD_EQSTART 28
5967 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
5968 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
5969 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
5970 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5971 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
5972
5973 #define S_FW_EQ_ETH_CMD_EQSTOP 27
5974 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1
5975 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5976 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \
5977 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5978 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U)
5979
5980 #define S_FW_EQ_ETH_CMD_EQID 0
5981 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
5982 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
5983 #define G_FW_EQ_ETH_CMD_EQID(x) \
5984 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5985
5986 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
5987 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
5988 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5989 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
5990 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5991
5992 #define S_FW_EQ_ETH_CMD_FETCHSZM 26
5993 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1
5994 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5995 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
5996 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5997 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U)
5998
5999 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25
6000 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1
6001 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
6002 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
6003 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
6004 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
6005
6006 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24
6007 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1
6008 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
6009 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
6010 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
6011 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
6012
6013 #define S_FW_EQ_ETH_CMD_FETCHNS 23
6014 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1
6015 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS)
6016 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \
6017 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
6018 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U)
6019
6020 #define S_FW_EQ_ETH_CMD_FETCHRO 22
6021 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
6022 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
6023 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
6024 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
6025 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
6026
6027 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
6028 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
6029 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
6030 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
6031 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
6032
6033 #define S_FW_EQ_ETH_CMD_CPRIO 19
6034 #define M_FW_EQ_ETH_CMD_CPRIO 0x1
6035 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO)
6036 #define G_FW_EQ_ETH_CMD_CPRIO(x) \
6037 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
6038 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U)
6039
6040 #define S_FW_EQ_ETH_CMD_ONCHIP 18
6041 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1
6042 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP)
6043 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \
6044 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
6045 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U)
6046
6047 #define S_FW_EQ_ETH_CMD_PCIECHN 16
6048 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
6049 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
6050 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
6051 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
6052
6053 #define S_FW_EQ_ETH_CMD_IQID 0
6054 #define M_FW_EQ_ETH_CMD_IQID 0xffff
6055 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
6056 #define G_FW_EQ_ETH_CMD_IQID(x) \
6057 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
6058
6059 #define S_FW_EQ_ETH_CMD_DCAEN 31
6060 #define M_FW_EQ_ETH_CMD_DCAEN 0x1
6061 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN)
6062 #define G_FW_EQ_ETH_CMD_DCAEN(x) \
6063 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
6064 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U)
6065
6066 #define S_FW_EQ_ETH_CMD_DCACPU 26
6067 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f
6068 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU)
6069 #define G_FW_EQ_ETH_CMD_DCACPU(x) \
6070 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
6071
6072 #define S_FW_EQ_ETH_CMD_FBMIN 23
6073 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
6074 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
6075 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
6076 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
6077
6078 #define S_FW_EQ_ETH_CMD_FBMAX 20
6079 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
6080 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
6081 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
6082 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
6083
6084 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19
6085 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1
6086 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6087 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
6088 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
6089 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
6090
6091 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
6092 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
6093 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
6094 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
6095 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
6096
6097 #define S_FW_EQ_ETH_CMD_EQSIZE 0
6098 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
6099 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
6100 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
6101 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
6102
6103 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
6104 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
6105 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
6106 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
6107 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
6108 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
6109
6110 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
6111 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
6112 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
6113 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
6114 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
6115 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
6116
6117 #define S_FW_EQ_ETH_CMD_VIID 16
6118 #define M_FW_EQ_ETH_CMD_VIID 0xfff
6119 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
6120 #define G_FW_EQ_ETH_CMD_VIID(x) \
6121 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
6122
6123 #define S_FW_EQ_ETH_CMD_TIMEREN 3
6124 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1
6125 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN)
6126 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \
6127 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
6128 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U)
6129
6130 #define S_FW_EQ_ETH_CMD_TIMERIX 0
6131 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7
6132 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX)
6133 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \
6134 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
6135
6136 struct fw_eq_ctrl_cmd {
6137 __be32 op_to_vfn;
6138 __be32 alloc_to_len16;
6139 __be32 cmpliqid_eqid;
6140 __be32 physeqid_pkd;
6141 __be32 fetchszm_to_iqid;
6142 __be32 dcaen_to_eqsize;
6143 __be64 eqaddr;
6144 };
6145
6146 #define S_FW_EQ_CTRL_CMD_PFN 8
6147 #define M_FW_EQ_CTRL_CMD_PFN 0x7
6148 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
6149 #define G_FW_EQ_CTRL_CMD_PFN(x) \
6150 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
6151
6152 #define S_FW_EQ_CTRL_CMD_VFN 0
6153 #define M_FW_EQ_CTRL_CMD_VFN 0xff
6154 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
6155 #define G_FW_EQ_CTRL_CMD_VFN(x) \
6156 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
6157
6158 #define S_FW_EQ_CTRL_CMD_ALLOC 31
6159 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1
6160 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
6161 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \
6162 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
6163 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
6164
6165 #define S_FW_EQ_CTRL_CMD_FREE 30
6166 #define M_FW_EQ_CTRL_CMD_FREE 0x1
6167 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
6168 #define G_FW_EQ_CTRL_CMD_FREE(x) \
6169 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
6170 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
6171
6172 #define S_FW_EQ_CTRL_CMD_MODIFY 29
6173 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1
6174 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY)
6175 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \
6176 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
6177 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U)
6178
6179 #define S_FW_EQ_CTRL_CMD_EQSTART 28
6180 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1
6181 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
6182 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \
6183 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
6184 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
6185
6186 #define S_FW_EQ_CTRL_CMD_EQSTOP 27
6187 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1
6188 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
6189 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
6190 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
6191 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U)
6192
6193 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
6194 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff
6195 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
6196 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
6197 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
6198
6199 #define S_FW_EQ_CTRL_CMD_EQID 0
6200 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
6201 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
6202 #define G_FW_EQ_CTRL_CMD_EQID(x) \
6203 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
6204
6205 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
6206 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
6207 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
6208 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
6209 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
6210
6211 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26
6212 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1
6213 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
6214 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
6215 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
6216 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
6217
6218 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25
6219 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1
6220 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
6221 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
6222 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
6223 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
6224
6225 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24
6226 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1
6227 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
6228 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
6229 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
6230 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
6231
6232 #define S_FW_EQ_CTRL_CMD_FETCHNS 23
6233 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1
6234 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
6235 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
6236 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
6237 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U)
6238
6239 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
6240 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1
6241 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
6242 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
6243 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
6244 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
6245
6246 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
6247 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
6248 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
6249 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
6250 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
6251
6252 #define S_FW_EQ_CTRL_CMD_CPRIO 19
6253 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1
6254 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO)
6255 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \
6256 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
6257 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U)
6258
6259 #define S_FW_EQ_CTRL_CMD_ONCHIP 18
6260 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1
6261 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
6262 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
6263 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
6264 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U)
6265
6266 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
6267 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3
6268 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
6269 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
6270 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
6271
6272 #define S_FW_EQ_CTRL_CMD_IQID 0
6273 #define M_FW_EQ_CTRL_CMD_IQID 0xffff
6274 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
6275 #define G_FW_EQ_CTRL_CMD_IQID(x) \
6276 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
6277
6278 #define S_FW_EQ_CTRL_CMD_DCAEN 31
6279 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1
6280 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN)
6281 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \
6282 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
6283 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U)
6284
6285 #define S_FW_EQ_CTRL_CMD_DCACPU 26
6286 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f
6287 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU)
6288 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \
6289 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
6290
6291 #define S_FW_EQ_CTRL_CMD_FBMIN 23
6292 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7
6293 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
6294 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \
6295 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
6296
6297 #define S_FW_EQ_CTRL_CMD_FBMAX 20
6298 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7
6299 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
6300 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \
6301 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
6302
6303 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19
6304 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1
6305 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6306 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6307 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6308 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6309 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
6310
6311 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
6312 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7
6313 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6314 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
6315 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6316
6317 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
6318 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff
6319 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
6320 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
6321 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
6322
6323 struct fw_eq_ofld_cmd {
6324 __be32 op_to_vfn;
6325 __be32 alloc_to_len16;
6326 __be32 eqid_pkd;
6327 __be32 physeqid_pkd;
6328 __be32 fetchszm_to_iqid;
6329 __be32 dcaen_to_eqsize;
6330 __be64 eqaddr;
6331 };
6332
6333 #define S_FW_EQ_OFLD_CMD_PFN 8
6334 #define M_FW_EQ_OFLD_CMD_PFN 0x7
6335 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN)
6336 #define G_FW_EQ_OFLD_CMD_PFN(x) \
6337 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
6338
6339 #define S_FW_EQ_OFLD_CMD_VFN 0
6340 #define M_FW_EQ_OFLD_CMD_VFN 0xff
6341 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN)
6342 #define G_FW_EQ_OFLD_CMD_VFN(x) \
6343 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
6344
6345 #define S_FW_EQ_OFLD_CMD_ALLOC 31
6346 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1
6347 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC)
6348 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \
6349 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
6350 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U)
6351
6352 #define S_FW_EQ_OFLD_CMD_FREE 30
6353 #define M_FW_EQ_OFLD_CMD_FREE 0x1
6354 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE)
6355 #define G_FW_EQ_OFLD_CMD_FREE(x) \
6356 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
6357 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U)
6358
6359 #define S_FW_EQ_OFLD_CMD_MODIFY 29
6360 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1
6361 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY)
6362 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \
6363 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
6364 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U)
6365
6366 #define S_FW_EQ_OFLD_CMD_EQSTART 28
6367 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1
6368 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART)
6369 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \
6370 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
6371 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U)
6372
6373 #define S_FW_EQ_OFLD_CMD_EQSTOP 27
6374 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1
6375 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
6376 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
6377 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
6378 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U)
6379
6380 #define S_FW_EQ_OFLD_CMD_EQID 0
6381 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff
6382 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID)
6383 #define G_FW_EQ_OFLD_CMD_EQID(x) \
6384 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
6385
6386 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0
6387 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff
6388 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
6389 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
6390 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
6391
6392 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26
6393 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1
6394 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
6395 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
6396 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
6397 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
6398
6399 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25
6400 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1
6401 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
6402 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
6403 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
6404 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
6405
6406 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24
6407 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1
6408 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
6409 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
6410 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
6411 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
6412
6413 #define S_FW_EQ_OFLD_CMD_FETCHNS 23
6414 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1
6415 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
6416 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
6417 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
6418 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U)
6419
6420 #define S_FW_EQ_OFLD_CMD_FETCHRO 22
6421 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1
6422 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6423 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
6424 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6425 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6426
6427 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20
6428 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3
6429 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6430 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
6431 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6432
6433 #define S_FW_EQ_OFLD_CMD_CPRIO 19
6434 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1
6435 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6436 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \
6437 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6438 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U)
6439
6440 #define S_FW_EQ_OFLD_CMD_ONCHIP 18
6441 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1
6442 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6443 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
6444 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6445 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6446
6447 #define S_FW_EQ_OFLD_CMD_PCIECHN 16
6448 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3
6449 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6450 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
6451 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6452
6453 #define S_FW_EQ_OFLD_CMD_IQID 0
6454 #define M_FW_EQ_OFLD_CMD_IQID 0xffff
6455 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID)
6456 #define G_FW_EQ_OFLD_CMD_IQID(x) \
6457 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6458
6459 #define S_FW_EQ_OFLD_CMD_DCAEN 31
6460 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1
6461 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6462 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \
6463 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6464 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U)
6465
6466 #define S_FW_EQ_OFLD_CMD_DCACPU 26
6467 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f
6468 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6469 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \
6470 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6471
6472 #define S_FW_EQ_OFLD_CMD_FBMIN 23
6473 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7
6474 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6475 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \
6476 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6477
6478 #define S_FW_EQ_OFLD_CMD_FBMAX 20
6479 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7
6480 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6481 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \
6482 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6483
6484 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19
6485 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1
6486 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6487 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6488 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6489 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6490 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6491
6492 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16
6493 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7
6494 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6495 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
6496 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6497
6498 #define S_FW_EQ_OFLD_CMD_EQSIZE 0
6499 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff
6500 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6501 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
6502 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6503
6504 /* Following macros present here only to maintain backward
6505 * compatibiity. Driver must not use these anymore */
6506 /* Macros for VIID parsing:
6507 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6508 #define S_FW_VIID_PFN 8
6509 #define M_FW_VIID_PFN 0x7
6510 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN)
6511 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6512
6513 #define S_FW_VIID_VIVLD 7
6514 #define M_FW_VIID_VIVLD 0x1
6515 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD)
6516 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6517
6518 #define S_FW_VIID_VIN 0
6519 #define M_FW_VIID_VIN 0x7F
6520 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
6521 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6522
6523 /* Macros for VIID parsing:
6524 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */
6525 #define S_FW_256VIID_PFN 9
6526 #define M_FW_256VIID_PFN 0x7
6527 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN)
6528 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
6529
6530 #define S_FW_256VIID_VIVLD 8
6531 #define M_FW_256VIID_VIVLD 0x1
6532 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD)
6533 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
6534
6535 #define S_FW_256VIID_VIN 0
6536 #define M_FW_256VIID_VIN 0xFF
6537 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN)
6538 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
6539
6540 enum fw_vi_func {
6541 FW_VI_FUNC_ETH,
6542 FW_VI_FUNC_OFLD,
6543 FW_VI_FUNC_IWARP,
6544 FW_VI_FUNC_OPENISCSI,
6545 FW_VI_FUNC_OPENFCOE,
6546 FW_VI_FUNC_FOISCSI,
6547 FW_VI_FUNC_FOFCOE,
6548 FW_VI_FUNC_FW,
6549 };
6550
6551 struct fw_vi_cmd {
6552 __be32 op_to_vfn;
6553 __be32 alloc_to_len16;
6554 __be16 type_to_viid;
6555 __u8 mac[6];
6556 __u8 portid_pkd;
6557 __u8 nmac;
6558 __u8 nmac0[6];
6559 __be16 norss_rsssize;
6560 __u8 nmac1[6];
6561 __be16 idsiiq_pkd;
6562 __u8 nmac2[6];
6563 __be16 idseiq_pkd;
6564 __u8 nmac3[6];
6565 __be64 r9;
6566 __be64 r10;
6567 };
6568
6569 #define S_FW_VI_CMD_PFN 8
6570 #define M_FW_VI_CMD_PFN 0x7
6571 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
6572 #define G_FW_VI_CMD_PFN(x) \
6573 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6574
6575 #define S_FW_VI_CMD_VFN 0
6576 #define M_FW_VI_CMD_VFN 0xff
6577 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
6578 #define G_FW_VI_CMD_VFN(x) \
6579 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6580
6581 #define S_FW_VI_CMD_ALLOC 31
6582 #define M_FW_VI_CMD_ALLOC 0x1
6583 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
6584 #define G_FW_VI_CMD_ALLOC(x) \
6585 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6586 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
6587
6588 #define S_FW_VI_CMD_FREE 30
6589 #define M_FW_VI_CMD_FREE 0x1
6590 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
6591 #define G_FW_VI_CMD_FREE(x) \
6592 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6593 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
6594
6595 #define S_FW_VI_CMD_VFVLD 24
6596 #define M_FW_VI_CMD_VFVLD 0x1
6597 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD)
6598 #define G_FW_VI_CMD_VFVLD(x) \
6599 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
6600 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U)
6601
6602 #define S_FW_VI_CMD_VIN 16
6603 #define M_FW_VI_CMD_VIN 0xff
6604 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN)
6605 #define G_FW_VI_CMD_VIN(x) \
6606 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
6607
6608 #define S_FW_VI_CMD_TYPE 15
6609 #define M_FW_VI_CMD_TYPE 0x1
6610 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
6611 #define G_FW_VI_CMD_TYPE(x) \
6612 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6613 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
6614
6615 #define S_FW_VI_CMD_FUNC 12
6616 #define M_FW_VI_CMD_FUNC 0x7
6617 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
6618 #define G_FW_VI_CMD_FUNC(x) \
6619 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6620
6621 #define S_FW_VI_CMD_VIID 0
6622 #define M_FW_VI_CMD_VIID 0xfff
6623 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
6624 #define G_FW_VI_CMD_VIID(x) \
6625 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6626
6627 #define S_FW_VI_CMD_PORTID 4
6628 #define M_FW_VI_CMD_PORTID 0xf
6629 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
6630 #define G_FW_VI_CMD_PORTID(x) \
6631 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6632
6633 #define S_FW_VI_CMD_NORSS 11
6634 #define M_FW_VI_CMD_NORSS 0x1
6635 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS)
6636 #define G_FW_VI_CMD_NORSS(x) \
6637 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6638 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U)
6639
6640 #define S_FW_VI_CMD_RSSSIZE 0
6641 #define M_FW_VI_CMD_RSSSIZE 0x7ff
6642 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
6643 #define G_FW_VI_CMD_RSSSIZE(x) \
6644 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6645
6646 #define S_FW_VI_CMD_IDSIIQ 0
6647 #define M_FW_VI_CMD_IDSIIQ 0x3ff
6648 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ)
6649 #define G_FW_VI_CMD_IDSIIQ(x) \
6650 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6651
6652 #define S_FW_VI_CMD_IDSEIQ 0
6653 #define M_FW_VI_CMD_IDSEIQ 0x3ff
6654 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ)
6655 #define G_FW_VI_CMD_IDSEIQ(x) \
6656 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6657
6658 /* Special VI_MAC command index ids */
6659 #define FW_VI_MAC_ADD_MAC 0x3FF
6660 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
6661 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
6662 #define FW_VI_MAC_ID_BASED_FREE 0x3FC
6663
6664 enum fw_vi_mac_smac {
6665 FW_VI_MAC_MPS_TCAM_ENTRY,
6666 FW_VI_MAC_MPS_TCAM_ONLY,
6667 FW_VI_MAC_SMT_ONLY,
6668 FW_VI_MAC_SMT_AND_MPSTCAM
6669 };
6670
6671 enum fw_vi_mac_result {
6672 FW_VI_MAC_R_SUCCESS,
6673 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6674 FW_VI_MAC_R_SMAC_FAIL,
6675 FW_VI_MAC_R_F_ACL_CHECK
6676 };
6677
6678 enum fw_vi_mac_entry_types {
6679 FW_VI_MAC_TYPE_EXACTMAC,
6680 FW_VI_MAC_TYPE_HASHVEC,
6681 FW_VI_MAC_TYPE_RAW,
6682 FW_VI_MAC_TYPE_EXACTMAC_VNI,
6683 };
6684
6685 struct fw_vi_mac_cmd {
6686 __be32 op_to_viid;
6687 __be32 freemacs_to_len16;
6688 union fw_vi_mac {
6689 struct fw_vi_mac_exact {
6690 __be16 valid_to_idx;
6691 __u8 macaddr[6];
6692 } exact[7];
6693 struct fw_vi_mac_hash {
6694 __be64 hashvec;
6695 } hash;
6696 struct fw_vi_mac_raw {
6697 __be32 raw_idx_pkd;
6698 __be32 data0_pkd;
6699 __be32 data1[2];
6700 __be64 data0m_pkd;
6701 __be32 data1m[2];
6702 } raw;
6703 struct fw_vi_mac_vni {
6704 __be16 valid_to_idx;
6705 __u8 macaddr[6];
6706 __be16 r7;
6707 __u8 macaddr_mask[6];
6708 __be32 lookup_type_to_vni;
6709 __be32 vni_mask_pkd;
6710 } exact_vni[2];
6711 } u;
6712 };
6713
6714 #define S_FW_VI_MAC_CMD_SMTID 12
6715 #define M_FW_VI_MAC_CMD_SMTID 0xff
6716 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID)
6717 #define G_FW_VI_MAC_CMD_SMTID(x) \
6718 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)
6719
6720 #define S_FW_VI_MAC_CMD_VIID 0
6721 #define M_FW_VI_MAC_CMD_VIID 0xfff
6722 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
6723 #define G_FW_VI_MAC_CMD_VIID(x) \
6724 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6725
6726 #define S_FW_VI_MAC_CMD_FREEMACS 31
6727 #define M_FW_VI_MAC_CMD_FREEMACS 0x1
6728 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
6729 #define G_FW_VI_MAC_CMD_FREEMACS(x) \
6730 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6731 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
6732
6733 #define S_FW_VI_MAC_CMD_IS_SMAC 30
6734 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1
6735 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC)
6736 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \
6737 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)
6738 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U)
6739
6740 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
6741 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
6742 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6743 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \
6744 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6745
6746 #define S_FW_VI_MAC_CMD_HASHUNIEN 22
6747 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
6748 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6749 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
6750 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6751 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6752
6753 #define S_FW_VI_MAC_CMD_VALID 15
6754 #define M_FW_VI_MAC_CMD_VALID 0x1
6755 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
6756 #define G_FW_VI_MAC_CMD_VALID(x) \
6757 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6758 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
6759
6760 #define S_FW_VI_MAC_CMD_PRIO 12
6761 #define M_FW_VI_MAC_CMD_PRIO 0x7
6762 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO)
6763 #define G_FW_VI_MAC_CMD_PRIO(x) \
6764 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6765
6766 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
6767 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
6768 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6769 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
6770 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6771
6772 #define S_FW_VI_MAC_CMD_IDX 0
6773 #define M_FW_VI_MAC_CMD_IDX 0x3ff
6774 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
6775 #define G_FW_VI_MAC_CMD_IDX(x) \
6776 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6777
6778 #define S_FW_VI_MAC_CMD_RAW_IDX 16
6779 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
6780 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6781 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
6782 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6783
6784 #define S_FW_VI_MAC_CMD_DATA0 0
6785 #define M_FW_VI_MAC_CMD_DATA0 0xffff
6786 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0)
6787 #define G_FW_VI_MAC_CMD_DATA0(x) \
6788 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6789
6790 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31
6791 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1
6792 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
6793 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \
6794 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
6795 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
6796
6797 #define S_FW_VI_MAC_CMD_DIP_HIT 30
6798 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1
6799 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT)
6800 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \
6801 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
6802 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U)
6803
6804 #define S_FW_VI_MAC_CMD_VNI 0
6805 #define M_FW_VI_MAC_CMD_VNI 0xffffff
6806 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI)
6807 #define G_FW_VI_MAC_CMD_VNI(x) \
6808 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
6809
6810 /* Extracting loopback port number passed from driver.
6811 * as a part of fw_vi_mac_vni For non loopback entries
6812 * ignore the field and update port number from flowc.
6813 * Fw will ignore if physical port number received.
6814 * expected range (4-7).
6815 */
6816
6817 #define S_FW_VI_MAC_CMD_PORT 24
6818 #define M_FW_VI_MAC_CMD_PORT 0x7
6819 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT)
6820 #define G_FW_VI_MAC_CMD_PORT(x) \
6821 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)
6822
6823 #define S_FW_VI_MAC_CMD_VNI_MASK 0
6824 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff
6825 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK)
6826 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \
6827 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
6828
6829 /* T4 max MTU supported */
6830 #define T4_MAX_MTU_SUPPORTED 9600
6831 #define FW_RXMODE_MTU_NO_CHG 65535
6832
6833 struct fw_vi_rxmode_cmd {
6834 __be32 op_to_viid;
6835 __be32 retval_len16;
6836 __be32 mtu_to_vlanexen;
6837 __be32 r4_lo;
6838 };
6839
6840 #define S_FW_VI_RXMODE_CMD_VIID 0
6841 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
6842 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
6843 #define G_FW_VI_RXMODE_CMD_VIID(x) \
6844 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6845
6846 #define S_FW_VI_RXMODE_CMD_MTU 16
6847 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
6848 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
6849 #define G_FW_VI_RXMODE_CMD_MTU(x) \
6850 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6851
6852 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
6853 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
6854 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6855 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
6856 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6857
6858 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
6859 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
6860 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6861 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6862 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6863 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6864
6865 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
6866 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
6867 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6868 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6869 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6870 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6871
6872 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
6873 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
6874 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6875 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
6876 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6877
6878 struct fw_vi_enable_cmd {
6879 __be32 op_to_viid;
6880 __be32 ien_to_len16;
6881 __be16 blinkdur;
6882 __be16 r3;
6883 __be32 r4;
6884 };
6885
6886 #define S_FW_VI_ENABLE_CMD_VIID 0
6887 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
6888 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
6889 #define G_FW_VI_ENABLE_CMD_VIID(x) \
6890 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6891
6892 #define S_FW_VI_ENABLE_CMD_IEN 31
6893 #define M_FW_VI_ENABLE_CMD_IEN 0x1
6894 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
6895 #define G_FW_VI_ENABLE_CMD_IEN(x) \
6896 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6897 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
6898
6899 #define S_FW_VI_ENABLE_CMD_EEN 30
6900 #define M_FW_VI_ENABLE_CMD_EEN 0x1
6901 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
6902 #define G_FW_VI_ENABLE_CMD_EEN(x) \
6903 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6904 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
6905
6906 #define S_FW_VI_ENABLE_CMD_LED 29
6907 #define M_FW_VI_ENABLE_CMD_LED 0x1
6908 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED)
6909 #define G_FW_VI_ENABLE_CMD_LED(x) \
6910 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6911 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U)
6912
6913 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
6914 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
6915 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6916 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
6917 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6918 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6919
6920 /* VI VF stats offset definitions */
6921 #define VI_VF_NUM_STATS 16
6922 enum fw_vi_stats_vf_index {
6923 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6924 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6925 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6926 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6927 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6928 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6929 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6930 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6931 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6932 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6933 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6934 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6935 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6936 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6937 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6938 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6939 };
6940
6941 /* VI PF stats offset definitions */
6942 #define VI_PF_NUM_STATS 17
6943 enum fw_vi_stats_pf_index {
6944 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6945 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6946 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6947 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6948 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6949 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6950 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6951 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6952 FW_VI_PF_STAT_RX_BYTES_IX,
6953 FW_VI_PF_STAT_RX_FRAMES_IX,
6954 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6955 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6956 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6957 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6958 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6959 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6960 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6961 };
6962
6963 struct fw_vi_stats_cmd {
6964 __be32 op_to_viid;
6965 __be32 retval_len16;
6966 union fw_vi_stats {
6967 struct fw_vi_stats_ctl {
6968 __be16 nstats_ix;
6969 __be16 r6;
6970 __be32 r7;
6971 __be64 stat0;
6972 __be64 stat1;
6973 __be64 stat2;
6974 __be64 stat3;
6975 __be64 stat4;
6976 __be64 stat5;
6977 } ctl;
6978 struct fw_vi_stats_pf {
6979 __be64 tx_bcast_bytes;
6980 __be64 tx_bcast_frames;
6981 __be64 tx_mcast_bytes;
6982 __be64 tx_mcast_frames;
6983 __be64 tx_ucast_bytes;
6984 __be64 tx_ucast_frames;
6985 __be64 tx_offload_bytes;
6986 __be64 tx_offload_frames;
6987 __be64 rx_pf_bytes;
6988 __be64 rx_pf_frames;
6989 __be64 rx_bcast_bytes;
6990 __be64 rx_bcast_frames;
6991 __be64 rx_mcast_bytes;
6992 __be64 rx_mcast_frames;
6993 __be64 rx_ucast_bytes;
6994 __be64 rx_ucast_frames;
6995 __be64 rx_err_frames;
6996 } pf;
6997 struct fw_vi_stats_vf {
6998 __be64 tx_bcast_bytes;
6999 __be64 tx_bcast_frames;
7000 __be64 tx_mcast_bytes;
7001 __be64 tx_mcast_frames;
7002 __be64 tx_ucast_bytes;
7003 __be64 tx_ucast_frames;
7004 __be64 tx_drop_frames;
7005 __be64 tx_offload_bytes;
7006 __be64 tx_offload_frames;
7007 __be64 rx_bcast_bytes;
7008 __be64 rx_bcast_frames;
7009 __be64 rx_mcast_bytes;
7010 __be64 rx_mcast_frames;
7011 __be64 rx_ucast_bytes;
7012 __be64 rx_ucast_frames;
7013 __be64 rx_err_frames;
7014 } vf;
7015 } u;
7016 };
7017
7018 #define S_FW_VI_STATS_CMD_VIID 0
7019 #define M_FW_VI_STATS_CMD_VIID 0xfff
7020 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
7021 #define G_FW_VI_STATS_CMD_VIID(x) \
7022 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
7023
7024 #define S_FW_VI_STATS_CMD_NSTATS 12
7025 #define M_FW_VI_STATS_CMD_NSTATS 0x7
7026 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
7027 #define G_FW_VI_STATS_CMD_NSTATS(x) \
7028 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
7029
7030 #define S_FW_VI_STATS_CMD_IX 0
7031 #define M_FW_VI_STATS_CMD_IX 0x1f
7032 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
7033 #define G_FW_VI_STATS_CMD_IX(x) \
7034 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
7035
7036 struct fw_acl_mac_cmd {
7037 __be32 op_to_vfn;
7038 __be32 en_to_len16;
7039 __u8 nmac;
7040 __u8 r3[7];
7041 __be16 r4;
7042 __u8 macaddr0[6];
7043 __be16 r5;
7044 __u8 macaddr1[6];
7045 __be16 r6;
7046 __u8 macaddr2[6];
7047 __be16 r7;
7048 __u8 macaddr3[6];
7049 };
7050
7051 #define S_FW_ACL_MAC_CMD_PFN 8
7052 #define M_FW_ACL_MAC_CMD_PFN 0x7
7053 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN)
7054 #define G_FW_ACL_MAC_CMD_PFN(x) \
7055 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
7056
7057 #define S_FW_ACL_MAC_CMD_VFN 0
7058 #define M_FW_ACL_MAC_CMD_VFN 0xff
7059 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN)
7060 #define G_FW_ACL_MAC_CMD_VFN(x) \
7061 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
7062
7063 #define S_FW_ACL_MAC_CMD_EN 31
7064 #define M_FW_ACL_MAC_CMD_EN 0x1
7065 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN)
7066 #define G_FW_ACL_MAC_CMD_EN(x) \
7067 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
7068 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U)
7069
7070 struct fw_acl_vlan_cmd {
7071 __be32 op_to_vfn;
7072 __be32 en_to_len16;
7073 __u8 nvlan;
7074 __u8 dropnovlan_fm;
7075 __u8 r3_lo[6];
7076 __be16 vlanid[16];
7077 };
7078
7079 #define S_FW_ACL_VLAN_CMD_PFN 8
7080 #define M_FW_ACL_VLAN_CMD_PFN 0x7
7081 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN)
7082 #define G_FW_ACL_VLAN_CMD_PFN(x) \
7083 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
7084
7085 #define S_FW_ACL_VLAN_CMD_VFN 0
7086 #define M_FW_ACL_VLAN_CMD_VFN 0xff
7087 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN)
7088 #define G_FW_ACL_VLAN_CMD_VFN(x) \
7089 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
7090
7091 #define S_FW_ACL_VLAN_CMD_EN 31
7092 #define M_FW_ACL_VLAN_CMD_EN 0x1
7093 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN)
7094 #define G_FW_ACL_VLAN_CMD_EN(x) \
7095 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
7096 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
7097
7098 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30
7099 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1
7100 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7101 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)
7102 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
7103 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)
7104 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)
7105
7106 #define S_FW_ACL_VLAN_CMD_PMASK 16
7107 #define M_FW_ACL_VLAN_CMD_PMASK 0xf
7108 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK)
7109 #define G_FW_ACL_VLAN_CMD_PMASK(x) \
7110 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)
7111
7112 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
7113 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
7114 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
7115 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
7116 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
7117 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
7118
7119 #define S_FW_ACL_VLAN_CMD_FM 6
7120 #define M_FW_ACL_VLAN_CMD_FM 0x1
7121 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM)
7122 #define G_FW_ACL_VLAN_CMD_FM(x) \
7123 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
7124 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
7125
7126 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
7127 enum fw_port_cap {
7128 FW_PORT_CAP_SPEED_100M = 0x0001,
7129 FW_PORT_CAP_SPEED_1G = 0x0002,
7130 FW_PORT_CAP_SPEED_25G = 0x0004,
7131 FW_PORT_CAP_SPEED_10G = 0x0008,
7132 FW_PORT_CAP_SPEED_40G = 0x0010,
7133 FW_PORT_CAP_SPEED_100G = 0x0020,
7134 FW_PORT_CAP_FC_RX = 0x0040,
7135 FW_PORT_CAP_FC_TX = 0x0080,
7136 FW_PORT_CAP_ANEG = 0x0100,
7137 FW_PORT_CAP_MDIAUTO = 0x0200,
7138 FW_PORT_CAP_MDISTRAIGHT = 0x0400,
7139 FW_PORT_CAP_FEC_RS = 0x0800,
7140 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
7141 FW_PORT_CAP_FORCE_PAUSE = 0x2000,
7142 FW_PORT_CAP_802_3_PAUSE = 0x4000,
7143 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
7144 };
7145
7146 #define S_FW_PORT_CAP_SPEED 0
7147 #define M_FW_PORT_CAP_SPEED 0x3f
7148 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
7149 #define G_FW_PORT_CAP_SPEED(x) \
7150 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
7151
7152 #define S_FW_PORT_CAP_FC 6
7153 #define M_FW_PORT_CAP_FC 0x3
7154 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC)
7155 #define G_FW_PORT_CAP_FC(x) \
7156 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
7157
7158 #define S_FW_PORT_CAP_ANEG 8
7159 #define M_FW_PORT_CAP_ANEG 0x1
7160 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG)
7161 #define G_FW_PORT_CAP_ANEG(x) \
7162 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
7163
7164 #define S_FW_PORT_CAP_FEC 11
7165 #define M_FW_PORT_CAP_FEC 0x3
7166 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
7167 #define G_FW_PORT_CAP_FEC(x) \
7168 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
7169
7170 #define S_FW_PORT_CAP_FORCE_PAUSE 13
7171 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1
7172 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE)
7173 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \
7174 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
7175
7176 #define S_FW_PORT_CAP_802_3 14
7177 #define M_FW_PORT_CAP_802_3 0x3
7178 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
7179 #define G_FW_PORT_CAP_802_3(x) \
7180 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
7181
7182 enum fw_port_mdi {
7183 FW_PORT_CAP_MDI_UNCHANGED,
7184 FW_PORT_CAP_MDI_AUTO,
7185 FW_PORT_CAP_MDI_F_STRAIGHT,
7186 FW_PORT_CAP_MDI_F_CROSSOVER
7187 };
7188
7189 #define S_FW_PORT_CAP_MDI 9
7190 #define M_FW_PORT_CAP_MDI 3
7191 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
7192 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
7193
7194 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
7195 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL
7196 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL
7197 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL
7198 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL
7199 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL
7200 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL
7201 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL
7202 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL
7203 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL
7204 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
7205 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
7206 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
7207 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL
7208 #define FW_PORT_CAP32_FC_RX 0x00010000UL
7209 #define FW_PORT_CAP32_FC_TX 0x00020000UL
7210 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
7211 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
7212 #define FW_PORT_CAP32_ANEG 0x00100000UL
7213 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL
7214 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
7215 #define FW_PORT_CAP32_FEC_RS 0x00800000UL
7216 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
7217 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL
7218 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
7219 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
7220 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
7221 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL
7222 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL
7223
7224 #define S_FW_PORT_CAP32_SPEED 0
7225 #define M_FW_PORT_CAP32_SPEED 0xfff
7226 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
7227 #define G_FW_PORT_CAP32_SPEED(x) \
7228 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
7229
7230 #define S_FW_PORT_CAP32_FC 16
7231 #define M_FW_PORT_CAP32_FC 0x3
7232 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC)
7233 #define G_FW_PORT_CAP32_FC(x) \
7234 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
7235
7236 #define S_FW_PORT_CAP32_802_3 18
7237 #define M_FW_PORT_CAP32_802_3 0x3
7238 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3)
7239 #define G_FW_PORT_CAP32_802_3(x) \
7240 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
7241
7242 #define S_FW_PORT_CAP32_ANEG 20
7243 #define M_FW_PORT_CAP32_ANEG 0x1
7244 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG)
7245 #define G_FW_PORT_CAP32_ANEG(x) \
7246 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
7247
7248 #define S_FW_PORT_CAP32_FORCE_PAUSE 28
7249 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1
7250 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
7251 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
7252 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
7253
7254 enum fw_port_mdi32 {
7255 FW_PORT_CAP32_MDI_UNCHANGED,
7256 FW_PORT_CAP32_MDI_AUTO,
7257 FW_PORT_CAP32_MDI_F_STRAIGHT,
7258 FW_PORT_CAP32_MDI_F_CROSSOVER
7259 };
7260
7261 #define S_FW_PORT_CAP32_MDI 21
7262 #define M_FW_PORT_CAP32_MDI 3
7263 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
7264 #define G_FW_PORT_CAP32_MDI(x) \
7265 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
7266
7267 #define S_FW_PORT_CAP32_FEC 23
7268 #define M_FW_PORT_CAP32_FEC 0x1f
7269 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)
7270 #define G_FW_PORT_CAP32_FEC(x) \
7271 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
7272
7273 /* macros to isolate various 32-bit Port Capabilities sub-fields */
7274 #define CAP32_SPEED(__cap32) \
7275 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)
7276
7277 #define CAP32_FEC(__cap32) \
7278 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
7279
7280 #define CAP32_FC(__cap32) \
7281 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
7282
7283 static inline bool
fec_supported(uint32_t caps)7284 fec_supported(uint32_t caps)
7285 {
7286
7287 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G |
7288 FW_PORT_CAP32_SPEED_100G)) != 0);
7289 }
7290
7291 enum fw_port_action {
7292 FW_PORT_ACTION_L1_CFG = 0x0001,
7293 FW_PORT_ACTION_L2_CFG = 0x0002,
7294 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
7295 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
7296 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
7297 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
7298 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
7299 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
7300 FW_PORT_ACTION_L1_CFG32 = 0x0009,
7301 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
7302 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
7303 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
7304 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
7305 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
7306 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
7307 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
7308 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
7309 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
7310 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
7311 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
7312 FW_PORT_ACTION_PHY_RESET = 0x0040,
7313 FW_PORT_ACTION_PMA_RESET = 0x0041,
7314 FW_PORT_ACTION_PCS_RESET = 0x0042,
7315 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
7316 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
7317 FW_PORT_ACTION_AN_RESET = 0x0045,
7318 };
7319
7320 enum fw_port_l2cfg_ctlbf {
7321 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
7322 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
7323 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
7324 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
7325 FW_PORT_L2_CTLBF_IVLAN = 0x10,
7326 FW_PORT_L2_CTLBF_TXIPG = 0x20,
7327 FW_PORT_L2_CTLBF_MTU = 0x40,
7328 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80,
7329 };
7330
7331 enum fw_dcb_app_tlv_sf {
7332 FW_DCB_APP_SF_ETHERTYPE,
7333 FW_DCB_APP_SF_SOCKET_TCP,
7334 FW_DCB_APP_SF_SOCKET_UDP,
7335 FW_DCB_APP_SF_SOCKET_ALL,
7336 };
7337
7338 enum fw_port_dcb_versions {
7339 FW_PORT_DCB_VER_UNKNOWN,
7340 FW_PORT_DCB_VER_CEE1D0,
7341 FW_PORT_DCB_VER_CEE1D01,
7342 FW_PORT_DCB_VER_IEEE,
7343 FW_PORT_DCB_VER_AUTO=7
7344 };
7345
7346 enum fw_port_dcb_cfg {
7347 FW_PORT_DCB_CFG_PG = 0x01,
7348 FW_PORT_DCB_CFG_PFC = 0x02,
7349 FW_PORT_DCB_CFG_APPL = 0x04
7350 };
7351
7352 enum fw_port_dcb_cfg_rc {
7353 FW_PORT_DCB_CFG_SUCCESS = 0x0,
7354 FW_PORT_DCB_CFG_ERROR = 0x1
7355 };
7356
7357 enum fw_port_dcb_type {
7358 FW_PORT_DCB_TYPE_PGID = 0x00,
7359 FW_PORT_DCB_TYPE_PGRATE = 0x01,
7360 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
7361 FW_PORT_DCB_TYPE_PFC = 0x03,
7362 FW_PORT_DCB_TYPE_APP_ID = 0x04,
7363 FW_PORT_DCB_TYPE_CONTROL = 0x05,
7364 };
7365
7366 enum fw_port_dcb_feature_state {
7367 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
7368 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
7369 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
7370 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
7371 };
7372
7373 enum fw_port_diag_ops {
7374 FW_PORT_DIAGS_TEMP = 0x00,
7375 FW_PORT_DIAGS_TX_POWER = 0x01,
7376 FW_PORT_DIAGS_RX_POWER = 0x02,
7377 FW_PORT_DIAGS_TX_DIS = 0x03,
7378 };
7379
7380 struct fw_port_cmd {
7381 __be32 op_to_portid;
7382 __be32 action_to_len16;
7383 union fw_port {
7384 struct fw_port_l1cfg {
7385 __be32 rcap;
7386 __be32 r;
7387 } l1cfg;
7388 struct fw_port_l2cfg {
7389 __u8 ctlbf;
7390 __u8 ovlan3_to_ivlan0;
7391 __be16 ivlantype;
7392 __be16 txipg_force_pinfo;
7393 __be16 mtu;
7394 __be16 ovlan0mask;
7395 __be16 ovlan0type;
7396 __be16 ovlan1mask;
7397 __be16 ovlan1type;
7398 __be16 ovlan2mask;
7399 __be16 ovlan2type;
7400 __be16 ovlan3mask;
7401 __be16 ovlan3type;
7402 } l2cfg;
7403 struct fw_port_info {
7404 __be32 lstatus_to_modtype;
7405 __be16 pcap;
7406 __be16 acap;
7407 __be16 mtu;
7408 __u8 cbllen;
7409 __u8 auxlinfo;
7410 __u8 dcbxdis_pkd;
7411 __u8 r8_lo;
7412 __be16 lpacap;
7413 __be64 r9;
7414 } info;
7415 struct fw_port_diags {
7416 __u8 diagop;
7417 __u8 r[3];
7418 __be32 diagval;
7419 } diags;
7420 union fw_port_dcb {
7421 struct fw_port_dcb_pgid {
7422 __u8 type;
7423 __u8 apply_pkd;
7424 __u8 r10_lo[2];
7425 __be32 pgid;
7426 __be64 r11;
7427 } pgid;
7428 struct fw_port_dcb_pgrate {
7429 __u8 type;
7430 __u8 apply_pkd;
7431 __u8 r10_lo[5];
7432 __u8 num_tcs_supported;
7433 __u8 pgrate[8];
7434 __u8 tsa[8];
7435 } pgrate;
7436 struct fw_port_dcb_priorate {
7437 __u8 type;
7438 __u8 apply_pkd;
7439 __u8 r10_lo[6];
7440 __u8 strict_priorate[8];
7441 } priorate;
7442 struct fw_port_dcb_pfc {
7443 __u8 type;
7444 __u8 pfcen;
7445 __u8 apply_pkd;
7446 __u8 r10_lo[4];
7447 __u8 max_pfc_tcs;
7448 __be64 r11;
7449 } pfc;
7450 struct fw_port_app_priority {
7451 __u8 type;
7452 __u8 apply_pkd;
7453 __u8 r10_lo;
7454 __u8 idx;
7455 __u8 user_prio_map;
7456 __u8 sel_field;
7457 __be16 protocolid;
7458 __be64 r12;
7459 } app_priority;
7460 struct fw_port_dcb_control {
7461 __u8 type;
7462 __u8 all_syncd_pkd;
7463 __be16 dcb_version_to_app_state;
7464 __be32 r11;
7465 __be64 r12;
7466 } control;
7467 } dcb;
7468 struct fw_port_l1cfg32 {
7469 __be32 rcap32;
7470 __be32 r;
7471 } l1cfg32;
7472 struct fw_port_info32 {
7473 __be32 lstatus32_to_cbllen32;
7474 __be32 auxlinfo32_mtu32;
7475 __be32 linkattr32;
7476 __be32 pcaps32;
7477 __be32 acaps32;
7478 __be32 lpacaps32;
7479 } info32;
7480 } u;
7481 };
7482
7483 #define S_FW_PORT_CMD_READ 22
7484 #define M_FW_PORT_CMD_READ 0x1
7485 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)
7486 #define G_FW_PORT_CMD_READ(x) \
7487 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
7488 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U)
7489
7490 #define S_FW_PORT_CMD_PORTID 0
7491 #define M_FW_PORT_CMD_PORTID 0xf
7492 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
7493 #define G_FW_PORT_CMD_PORTID(x) \
7494 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
7495
7496 #define S_FW_PORT_CMD_ACTION 16
7497 #define M_FW_PORT_CMD_ACTION 0xffff
7498 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
7499 #define G_FW_PORT_CMD_ACTION(x) \
7500 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
7501
7502 #define S_FW_PORT_CMD_OVLAN3 7
7503 #define M_FW_PORT_CMD_OVLAN3 0x1
7504 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3)
7505 #define G_FW_PORT_CMD_OVLAN3(x) \
7506 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
7507 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U)
7508
7509 #define S_FW_PORT_CMD_OVLAN2 6
7510 #define M_FW_PORT_CMD_OVLAN2 0x1
7511 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2)
7512 #define G_FW_PORT_CMD_OVLAN2(x) \
7513 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
7514 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U)
7515
7516 #define S_FW_PORT_CMD_OVLAN1 5
7517 #define M_FW_PORT_CMD_OVLAN1 0x1
7518 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1)
7519 #define G_FW_PORT_CMD_OVLAN1(x) \
7520 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
7521 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U)
7522
7523 #define S_FW_PORT_CMD_OVLAN0 4
7524 #define M_FW_PORT_CMD_OVLAN0 0x1
7525 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0)
7526 #define G_FW_PORT_CMD_OVLAN0(x) \
7527 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7528 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U)
7529
7530 #define S_FW_PORT_CMD_IVLAN0 3
7531 #define M_FW_PORT_CMD_IVLAN0 0x1
7532 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0)
7533 #define G_FW_PORT_CMD_IVLAN0(x) \
7534 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7535 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
7536
7537 #define S_FW_PORT_CMD_OVLAN_FILT 2
7538 #define M_FW_PORT_CMD_OVLAN_FILT 0x1
7539 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT)
7540 #define G_FW_PORT_CMD_OVLAN_FILT(x) \
7541 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
7542 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U)
7543
7544 #define S_FW_PORT_CMD_TXIPG 3
7545 #define M_FW_PORT_CMD_TXIPG 0x1fff
7546 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
7547 #define G_FW_PORT_CMD_TXIPG(x) \
7548 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7549
7550 #define S_FW_PORT_CMD_FORCE_PINFO 0
7551 #define M_FW_PORT_CMD_FORCE_PINFO 0x1
7552 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO)
7553 #define G_FW_PORT_CMD_FORCE_PINFO(x) \
7554 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7555 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U)
7556
7557 #define S_FW_PORT_CMD_LSTATUS 31
7558 #define M_FW_PORT_CMD_LSTATUS 0x1
7559 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
7560 #define G_FW_PORT_CMD_LSTATUS(x) \
7561 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7562 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
7563
7564 #define S_FW_PORT_CMD_LSPEED 24
7565 #define M_FW_PORT_CMD_LSPEED 0x3f
7566 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
7567 #define G_FW_PORT_CMD_LSPEED(x) \
7568 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7569
7570 #define S_FW_PORT_CMD_TXPAUSE 23
7571 #define M_FW_PORT_CMD_TXPAUSE 0x1
7572 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
7573 #define G_FW_PORT_CMD_TXPAUSE(x) \
7574 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7575 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
7576
7577 #define S_FW_PORT_CMD_RXPAUSE 22
7578 #define M_FW_PORT_CMD_RXPAUSE 0x1
7579 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
7580 #define G_FW_PORT_CMD_RXPAUSE(x) \
7581 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7582 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
7583
7584 #define S_FW_PORT_CMD_MDIOCAP 21
7585 #define M_FW_PORT_CMD_MDIOCAP 0x1
7586 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
7587 #define G_FW_PORT_CMD_MDIOCAP(x) \
7588 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7589 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
7590
7591 #define S_FW_PORT_CMD_MDIOADDR 16
7592 #define M_FW_PORT_CMD_MDIOADDR 0x1f
7593 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
7594 #define G_FW_PORT_CMD_MDIOADDR(x) \
7595 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7596
7597 #define S_FW_PORT_CMD_LPTXPAUSE 15
7598 #define M_FW_PORT_CMD_LPTXPAUSE 0x1
7599 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE)
7600 #define G_FW_PORT_CMD_LPTXPAUSE(x) \
7601 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7602 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U)
7603
7604 #define S_FW_PORT_CMD_LPRXPAUSE 14
7605 #define M_FW_PORT_CMD_LPRXPAUSE 0x1
7606 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE)
7607 #define G_FW_PORT_CMD_LPRXPAUSE(x) \
7608 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7609 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U)
7610
7611 #define S_FW_PORT_CMD_PTYPE 8
7612 #define M_FW_PORT_CMD_PTYPE 0x1f
7613 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
7614 #define G_FW_PORT_CMD_PTYPE(x) \
7615 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7616
7617 #define S_FW_PORT_CMD_LINKDNRC 5
7618 #define M_FW_PORT_CMD_LINKDNRC 0x7
7619 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
7620 #define G_FW_PORT_CMD_LINKDNRC(x) \
7621 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7622
7623 #define S_FW_PORT_CMD_MODTYPE 0
7624 #define M_FW_PORT_CMD_MODTYPE 0x1f
7625 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
7626 #define G_FW_PORT_CMD_MODTYPE(x) \
7627 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7628
7629 #define S_FW_PORT_AUXLINFO_KX4 2
7630 #define M_FW_PORT_AUXLINFO_KX4 0x1
7631 #define V_FW_PORT_AUXLINFO_KX4(x) \
7632 ((x) << S_FW_PORT_AUXLINFO_KX4)
7633 #define G_FW_PORT_AUXLINFO_KX4(x) \
7634 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
7635 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
7636
7637 #define S_FW_PORT_AUXLINFO_KR 1
7638 #define M_FW_PORT_AUXLINFO_KR 0x1
7639 #define V_FW_PORT_AUXLINFO_KR(x) \
7640 ((x) << S_FW_PORT_AUXLINFO_KR)
7641 #define G_FW_PORT_AUXLINFO_KR(x) \
7642 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
7643 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
7644
7645 #define S_FW_PORT_CMD_DCBXDIS 7
7646 #define M_FW_PORT_CMD_DCBXDIS 0x1
7647 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
7648 #define G_FW_PORT_CMD_DCBXDIS(x) \
7649 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7650 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
7651
7652 #define S_FW_PORT_CMD_APPLY 7
7653 #define M_FW_PORT_CMD_APPLY 0x1
7654 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
7655 #define G_FW_PORT_CMD_APPLY(x) \
7656 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7657 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
7658
7659 #define S_FW_PORT_CMD_ALL_SYNCD 7
7660 #define M_FW_PORT_CMD_ALL_SYNCD 0x1
7661 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
7662 #define G_FW_PORT_CMD_ALL_SYNCD(x) \
7663 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7664 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
7665
7666 #define S_FW_PORT_CMD_DCB_VERSION 12
7667 #define M_FW_PORT_CMD_DCB_VERSION 0x7
7668 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION)
7669 #define G_FW_PORT_CMD_DCB_VERSION(x) \
7670 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7671
7672 #define S_FW_PORT_CMD_PFC_STATE 8
7673 #define M_FW_PORT_CMD_PFC_STATE 0xf
7674 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
7675 #define G_FW_PORT_CMD_PFC_STATE(x) \
7676 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7677
7678 #define S_FW_PORT_CMD_ETS_STATE 4
7679 #define M_FW_PORT_CMD_ETS_STATE 0xf
7680 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
7681 #define G_FW_PORT_CMD_ETS_STATE(x) \
7682 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7683
7684 #define S_FW_PORT_CMD_APP_STATE 0
7685 #define M_FW_PORT_CMD_APP_STATE 0xf
7686 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
7687 #define G_FW_PORT_CMD_APP_STATE(x) \
7688 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7689
7690 #define S_FW_PORT_CMD_LSTATUS32 31
7691 #define M_FW_PORT_CMD_LSTATUS32 0x1
7692 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
7693 #define G_FW_PORT_CMD_LSTATUS32(x) \
7694 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
7695 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
7696
7697 #define S_FW_PORT_CMD_LINKDNRC32 28
7698 #define M_FW_PORT_CMD_LINKDNRC32 0x7
7699 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32)
7700 #define G_FW_PORT_CMD_LINKDNRC32(x) \
7701 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
7702
7703 #define S_FW_PORT_CMD_DCBXDIS32 27
7704 #define M_FW_PORT_CMD_DCBXDIS32 0x1
7705 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32)
7706 #define G_FW_PORT_CMD_DCBXDIS32(x) \
7707 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
7708 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U)
7709
7710 #define S_FW_PORT_CMD_MDIOCAP32 26
7711 #define M_FW_PORT_CMD_MDIOCAP32 0x1
7712 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
7713 #define G_FW_PORT_CMD_MDIOCAP32(x) \
7714 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
7715 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
7716
7717 #define S_FW_PORT_CMD_MDIOADDR32 21
7718 #define M_FW_PORT_CMD_MDIOADDR32 0x1f
7719 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32)
7720 #define G_FW_PORT_CMD_MDIOADDR32(x) \
7721 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
7722
7723 #define S_FW_PORT_CMD_PORTTYPE32 13
7724 #define M_FW_PORT_CMD_PORTTYPE32 0xff
7725 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32)
7726 #define G_FW_PORT_CMD_PORTTYPE32(x) \
7727 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
7728
7729 #define S_FW_PORT_CMD_MODTYPE32 8
7730 #define M_FW_PORT_CMD_MODTYPE32 0x1f
7731 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32)
7732 #define G_FW_PORT_CMD_MODTYPE32(x) \
7733 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
7734
7735 #define S_FW_PORT_CMD_CBLLEN32 0
7736 #define M_FW_PORT_CMD_CBLLEN32 0xff
7737 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32)
7738 #define G_FW_PORT_CMD_CBLLEN32(x) \
7739 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
7740
7741 #define S_FW_PORT_CMD_AUXLINFO32 24
7742 #define M_FW_PORT_CMD_AUXLINFO32 0xff
7743 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32)
7744 #define G_FW_PORT_CMD_AUXLINFO32(x) \
7745 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
7746
7747 #define S_FW_PORT_AUXLINFO32_KX4 2
7748 #define M_FW_PORT_AUXLINFO32_KX4 0x1
7749 #define V_FW_PORT_AUXLINFO32_KX4(x) \
7750 ((x) << S_FW_PORT_AUXLINFO32_KX4)
7751 #define G_FW_PORT_AUXLINFO32_KX4(x) \
7752 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
7753 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U)
7754
7755 #define S_FW_PORT_AUXLINFO32_KR 1
7756 #define M_FW_PORT_AUXLINFO32_KR 0x1
7757 #define V_FW_PORT_AUXLINFO32_KR(x) \
7758 ((x) << S_FW_PORT_AUXLINFO32_KR)
7759 #define G_FW_PORT_AUXLINFO32_KR(x) \
7760 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
7761 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U)
7762
7763 #define S_FW_PORT_CMD_MTU32 0
7764 #define M_FW_PORT_CMD_MTU32 0xffff
7765 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32)
7766 #define G_FW_PORT_CMD_MTU32(x) \
7767 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
7768
7769 /*
7770 * These are configured into the VPD and hence tools that generate
7771 * VPD may use this enumeration.
7772 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
7773 *
7774 * REMEMBER:
7775 * Update the Common Code t4_hw.c:t4_get_port_type_description()
7776 * with any new Firmware Port Technology Types!
7777 */
7778 enum fw_port_type {
7779 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
7780 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
7781 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
7782 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */
7783 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */
7784 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
7785 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
7786 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
7787 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
7788 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
7789 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7790 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7791 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
7792 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
7793 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
7794 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7795 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
7796 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
7797 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
7798 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
7799 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
7800 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
7801 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/
7802 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7803 };
7804
7805 static inline bool
is_bt(enum fw_port_type port_type)7806 is_bt(enum fw_port_type port_type)
7807 {
7808 return (port_type == FW_PORT_TYPE_BT_SGMII ||
7809 port_type == FW_PORT_TYPE_BT_XFI ||
7810 port_type == FW_PORT_TYPE_BT_XAUI);
7811 }
7812
7813 /* These are read from module's EEPROM and determined once the
7814 module is inserted. */
7815 enum fw_port_module_type {
7816 FW_PORT_MOD_TYPE_NA = 0x0,
7817 FW_PORT_MOD_TYPE_LR = 0x1,
7818 FW_PORT_MOD_TYPE_SR = 0x2,
7819 FW_PORT_MOD_TYPE_ER = 0x3,
7820 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
7821 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
7822 FW_PORT_MOD_TYPE_LRM = 0x6,
7823 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
7824 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
7825 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
7826 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
7827 };
7828
7829 /* used by FW and tools may use this to generate VPD */
7830 enum fw_port_mod_sub_type {
7831 FW_PORT_MOD_SUB_TYPE_NA,
7832 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7833 FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7834 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7835 FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7836 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7837 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7838 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7839 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7840
7841 /*
7842 * The following will never been in the VPD. They are TWINAX cable
7843 * lengths decoded from SFP+ module i2c PROMs. These should almost
7844 * certainly go somewhere else ...
7845 */
7846 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7847 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7848 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7849 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7850 };
7851
7852 /* link down reason codes (3b) */
7853 enum fw_port_link_dn_rc {
7854 FW_PORT_LINK_DN_RC_NONE,
7855 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
7856 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
7857 FW_PORT_LINK_DN_RESERVED3,
7858 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
7859 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
7860 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
7861 FW_PORT_LINK_DN_RESERVED7
7862 };
7863 enum fw_port_stats_tx_index {
7864 FW_STAT_TX_PORT_BYTES_IX = 0,
7865 FW_STAT_TX_PORT_FRAMES_IX,
7866 FW_STAT_TX_PORT_BCAST_IX,
7867 FW_STAT_TX_PORT_MCAST_IX,
7868 FW_STAT_TX_PORT_UCAST_IX,
7869 FW_STAT_TX_PORT_ERROR_IX,
7870 FW_STAT_TX_PORT_64B_IX,
7871 FW_STAT_TX_PORT_65B_127B_IX,
7872 FW_STAT_TX_PORT_128B_255B_IX,
7873 FW_STAT_TX_PORT_256B_511B_IX,
7874 FW_STAT_TX_PORT_512B_1023B_IX,
7875 FW_STAT_TX_PORT_1024B_1518B_IX,
7876 FW_STAT_TX_PORT_1519B_MAX_IX,
7877 FW_STAT_TX_PORT_DROP_IX,
7878 FW_STAT_TX_PORT_PAUSE_IX,
7879 FW_STAT_TX_PORT_PPP0_IX,
7880 FW_STAT_TX_PORT_PPP1_IX,
7881 FW_STAT_TX_PORT_PPP2_IX,
7882 FW_STAT_TX_PORT_PPP3_IX,
7883 FW_STAT_TX_PORT_PPP4_IX,
7884 FW_STAT_TX_PORT_PPP5_IX,
7885 FW_STAT_TX_PORT_PPP6_IX,
7886 FW_STAT_TX_PORT_PPP7_IX,
7887 FW_NUM_PORT_TX_STATS
7888 };
7889
7890 enum fw_port_stat_rx_index {
7891 FW_STAT_RX_PORT_BYTES_IX = 0,
7892 FW_STAT_RX_PORT_FRAMES_IX,
7893 FW_STAT_RX_PORT_BCAST_IX,
7894 FW_STAT_RX_PORT_MCAST_IX,
7895 FW_STAT_RX_PORT_UCAST_IX,
7896 FW_STAT_RX_PORT_MTU_ERROR_IX,
7897 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7898 FW_STAT_RX_PORT_CRC_ERROR_IX,
7899 FW_STAT_RX_PORT_LEN_ERROR_IX,
7900 FW_STAT_RX_PORT_SYM_ERROR_IX,
7901 FW_STAT_RX_PORT_64B_IX,
7902 FW_STAT_RX_PORT_65B_127B_IX,
7903 FW_STAT_RX_PORT_128B_255B_IX,
7904 FW_STAT_RX_PORT_256B_511B_IX,
7905 FW_STAT_RX_PORT_512B_1023B_IX,
7906 FW_STAT_RX_PORT_1024B_1518B_IX,
7907 FW_STAT_RX_PORT_1519B_MAX_IX,
7908 FW_STAT_RX_PORT_PAUSE_IX,
7909 FW_STAT_RX_PORT_PPP0_IX,
7910 FW_STAT_RX_PORT_PPP1_IX,
7911 FW_STAT_RX_PORT_PPP2_IX,
7912 FW_STAT_RX_PORT_PPP3_IX,
7913 FW_STAT_RX_PORT_PPP4_IX,
7914 FW_STAT_RX_PORT_PPP5_IX,
7915 FW_STAT_RX_PORT_PPP6_IX,
7916 FW_STAT_RX_PORT_PPP7_IX,
7917 FW_STAT_RX_PORT_LESS_64B_IX,
7918 FW_STAT_RX_PORT_MAC_ERROR_IX,
7919 FW_NUM_PORT_RX_STATS
7920 };
7921 /* port stats */
7922 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7923 FW_NUM_PORT_RX_STATS)
7924
7925
7926 struct fw_port_stats_cmd {
7927 __be32 op_to_portid;
7928 __be32 retval_len16;
7929 union fw_port_stats {
7930 struct fw_port_stats_ctl {
7931 __u8 nstats_bg_bm;
7932 __u8 tx_ix;
7933 __be16 r6;
7934 __be32 r7;
7935 __be64 stat0;
7936 __be64 stat1;
7937 __be64 stat2;
7938 __be64 stat3;
7939 __be64 stat4;
7940 __be64 stat5;
7941 } ctl;
7942 struct fw_port_stats_all {
7943 __be64 tx_bytes;
7944 __be64 tx_frames;
7945 __be64 tx_bcast;
7946 __be64 tx_mcast;
7947 __be64 tx_ucast;
7948 __be64 tx_error;
7949 __be64 tx_64b;
7950 __be64 tx_65b_127b;
7951 __be64 tx_128b_255b;
7952 __be64 tx_256b_511b;
7953 __be64 tx_512b_1023b;
7954 __be64 tx_1024b_1518b;
7955 __be64 tx_1519b_max;
7956 __be64 tx_drop;
7957 __be64 tx_pause;
7958 __be64 tx_ppp0;
7959 __be64 tx_ppp1;
7960 __be64 tx_ppp2;
7961 __be64 tx_ppp3;
7962 __be64 tx_ppp4;
7963 __be64 tx_ppp5;
7964 __be64 tx_ppp6;
7965 __be64 tx_ppp7;
7966 __be64 rx_bytes;
7967 __be64 rx_frames;
7968 __be64 rx_bcast;
7969 __be64 rx_mcast;
7970 __be64 rx_ucast;
7971 __be64 rx_mtu_error;
7972 __be64 rx_mtu_crc_error;
7973 __be64 rx_crc_error;
7974 __be64 rx_len_error;
7975 __be64 rx_sym_error;
7976 __be64 rx_64b;
7977 __be64 rx_65b_127b;
7978 __be64 rx_128b_255b;
7979 __be64 rx_256b_511b;
7980 __be64 rx_512b_1023b;
7981 __be64 rx_1024b_1518b;
7982 __be64 rx_1519b_max;
7983 __be64 rx_pause;
7984 __be64 rx_ppp0;
7985 __be64 rx_ppp1;
7986 __be64 rx_ppp2;
7987 __be64 rx_ppp3;
7988 __be64 rx_ppp4;
7989 __be64 rx_ppp5;
7990 __be64 rx_ppp6;
7991 __be64 rx_ppp7;
7992 __be64 rx_less_64b;
7993 __be64 rx_bg_drop;
7994 __be64 rx_bg_trunc;
7995 } all;
7996 } u;
7997 };
7998
7999 #define S_FW_PORT_STATS_CMD_NSTATS 4
8000 #define M_FW_PORT_STATS_CMD_NSTATS 0x7
8001 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS)
8002 #define G_FW_PORT_STATS_CMD_NSTATS(x) \
8003 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
8004
8005 #define S_FW_PORT_STATS_CMD_BG_BM 0
8006 #define M_FW_PORT_STATS_CMD_BG_BM 0x3
8007 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM)
8008 #define G_FW_PORT_STATS_CMD_BG_BM(x) \
8009 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
8010
8011 #define S_FW_PORT_STATS_CMD_TX 7
8012 #define M_FW_PORT_STATS_CMD_TX 0x1
8013 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX)
8014 #define G_FW_PORT_STATS_CMD_TX(x) \
8015 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
8016 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U)
8017
8018 #define S_FW_PORT_STATS_CMD_IX 0
8019 #define M_FW_PORT_STATS_CMD_IX 0x3f
8020 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX)
8021 #define G_FW_PORT_STATS_CMD_IX(x) \
8022 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
8023
8024 /* port loopback stats */
8025 #define FW_NUM_LB_STATS 14
8026 enum fw_port_lb_stats_index {
8027 FW_STAT_LB_PORT_BYTES_IX,
8028 FW_STAT_LB_PORT_FRAMES_IX,
8029 FW_STAT_LB_PORT_BCAST_IX,
8030 FW_STAT_LB_PORT_MCAST_IX,
8031 FW_STAT_LB_PORT_UCAST_IX,
8032 FW_STAT_LB_PORT_ERROR_IX,
8033 FW_STAT_LB_PORT_64B_IX,
8034 FW_STAT_LB_PORT_65B_127B_IX,
8035 FW_STAT_LB_PORT_128B_255B_IX,
8036 FW_STAT_LB_PORT_256B_511B_IX,
8037 FW_STAT_LB_PORT_512B_1023B_IX,
8038 FW_STAT_LB_PORT_1024B_1518B_IX,
8039 FW_STAT_LB_PORT_1519B_MAX_IX,
8040 FW_STAT_LB_PORT_DROP_FRAMES_IX
8041 };
8042
8043 struct fw_port_lb_stats_cmd {
8044 __be32 op_to_lbport;
8045 __be32 retval_len16;
8046 union fw_port_lb_stats {
8047 struct fw_port_lb_stats_ctl {
8048 __u8 nstats_bg_bm;
8049 __u8 ix_pkd;
8050 __be16 r6;
8051 __be32 r7;
8052 __be64 stat0;
8053 __be64 stat1;
8054 __be64 stat2;
8055 __be64 stat3;
8056 __be64 stat4;
8057 __be64 stat5;
8058 } ctl;
8059 struct fw_port_lb_stats_all {
8060 __be64 tx_bytes;
8061 __be64 tx_frames;
8062 __be64 tx_bcast;
8063 __be64 tx_mcast;
8064 __be64 tx_ucast;
8065 __be64 tx_error;
8066 __be64 tx_64b;
8067 __be64 tx_65b_127b;
8068 __be64 tx_128b_255b;
8069 __be64 tx_256b_511b;
8070 __be64 tx_512b_1023b;
8071 __be64 tx_1024b_1518b;
8072 __be64 tx_1519b_max;
8073 __be64 rx_lb_drop;
8074 __be64 rx_lb_trunc;
8075 } all;
8076 } u;
8077 };
8078
8079 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0
8080 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf
8081 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8082 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
8083 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
8084 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
8085
8086 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4
8087 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7
8088 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8089 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
8090 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
8091 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
8092
8093 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0
8094 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3
8095 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
8096 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
8097 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
8098
8099 #define S_FW_PORT_LB_STATS_CMD_IX 0
8100 #define M_FW_PORT_LB_STATS_CMD_IX 0xf
8101 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX)
8102 #define G_FW_PORT_LB_STATS_CMD_IX(x) \
8103 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
8104
8105 /* Trace related defines */
8106 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
8107 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560
8108
8109 struct fw_port_trace_cmd {
8110 __be32 op_to_portid;
8111 __be32 retval_len16;
8112 __be16 traceen_to_pciech;
8113 __be16 qnum;
8114 __be32 r5;
8115 };
8116
8117 #define S_FW_PORT_TRACE_CMD_PORTID 0
8118 #define M_FW_PORT_TRACE_CMD_PORTID 0xf
8119 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID)
8120 #define G_FW_PORT_TRACE_CMD_PORTID(x) \
8121 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
8122
8123 #define S_FW_PORT_TRACE_CMD_TRACEEN 15
8124 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1
8125 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
8126 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
8127 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
8128 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U)
8129
8130 #define S_FW_PORT_TRACE_CMD_FLTMODE 14
8131 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1
8132 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
8133 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
8134 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
8135 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U)
8136
8137 #define S_FW_PORT_TRACE_CMD_DUPLEN 13
8138 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1
8139 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
8140 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
8141 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
8142 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U)
8143
8144 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8
8145 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f
8146 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8147 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8148 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
8149 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
8150 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
8151
8152 #define S_FW_PORT_TRACE_CMD_PCIECH 6
8153 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3
8154 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH)
8155 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \
8156 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
8157
8158 struct fw_port_trace_mmap_cmd {
8159 __be32 op_to_portid;
8160 __be32 retval_len16;
8161 __be32 fid_to_skipoffset;
8162 __be32 minpktsize_capturemax;
8163 __u8 map[224];
8164 };
8165
8166 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
8167 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf
8168 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8169 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
8170 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
8171 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
8172 M_FW_PORT_TRACE_MMAP_CMD_PORTID)
8173
8174 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30
8175 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3
8176 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
8177 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
8178 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
8179
8180 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29
8181 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1
8182 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8183 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8184 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
8185 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
8186 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
8187 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
8188
8189 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
8190 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
8191 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8192 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8193 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
8194 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
8195 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
8196 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
8197
8198 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
8199 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
8200 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8201 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8202 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
8203 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
8204 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
8205
8206 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
8207 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
8208 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8209 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8210 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
8211 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
8212 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
8213
8214 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
8215 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
8216 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8217 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8218 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
8219 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
8220 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
8221
8222 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
8223 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
8224 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8225 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8226 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
8227 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
8228 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
8229
8230 enum fw_ptp_subop {
8231
8232 /* none */
8233 FW_PTP_SC_INIT_TIMER = 0x00,
8234 FW_PTP_SC_TX_TYPE = 0x01,
8235
8236 /* init */
8237 FW_PTP_SC_RXTIME_STAMP = 0x08,
8238 FW_PTP_SC_RDRX_TYPE = 0x09,
8239
8240 /* ts */
8241 FW_PTP_SC_ADJ_FREQ = 0x10,
8242 FW_PTP_SC_ADJ_TIME = 0x11,
8243 FW_PTP_SC_ADJ_FTIME = 0x12,
8244 FW_PTP_SC_WALL_CLOCK = 0x13,
8245 FW_PTP_SC_GET_TIME = 0x14,
8246 FW_PTP_SC_SET_TIME = 0x15,
8247 };
8248
8249 struct fw_ptp_cmd {
8250 __be32 op_to_portid;
8251 __be32 retval_len16;
8252 union fw_ptp {
8253 struct fw_ptp_sc {
8254 __u8 sc;
8255 __u8 r3[7];
8256 } scmd;
8257 struct fw_ptp_init {
8258 __u8 sc;
8259 __u8 txchan;
8260 __be16 absid;
8261 __be16 mode;
8262 __be16 ptp_rx_ctrl_pkd;
8263 } init;
8264 struct fw_ptp_ts {
8265 __u8 sc;
8266 __u8 sign;
8267 __be16 r3;
8268 __be32 ppb;
8269 __be64 tm;
8270 } ts;
8271 } u;
8272 __be64 r3;
8273 };
8274
8275 #define S_FW_PTP_CMD_PORTID 0
8276 #define M_FW_PTP_CMD_PORTID 0xf
8277 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID)
8278 #define G_FW_PTP_CMD_PORTID(x) \
8279 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
8280
8281 #define S_FW_PTP_CMD_PTP_RX_CTRL 15
8282 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1
8283 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
8284 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \
8285 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
8286 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U)
8287
8288
8289 struct fw_rss_ind_tbl_cmd {
8290 __be32 op_to_viid;
8291 __be32 retval_len16;
8292 __be16 niqid;
8293 __be16 startidx;
8294 __be32 r3;
8295 __be32 iq0_to_iq2;
8296 __be32 iq3_to_iq5;
8297 __be32 iq6_to_iq8;
8298 __be32 iq9_to_iq11;
8299 __be32 iq12_to_iq14;
8300 __be32 iq15_to_iq17;
8301 __be32 iq18_to_iq20;
8302 __be32 iq21_to_iq23;
8303 __be32 iq24_to_iq26;
8304 __be32 iq27_to_iq29;
8305 __be32 iq30_iq31;
8306 __be32 r15_lo;
8307 };
8308
8309 #define S_FW_RSS_IND_TBL_CMD_VIID 0
8310 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
8311 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
8312 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
8313 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
8314
8315 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
8316 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
8317 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
8318 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
8319 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
8320
8321 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
8322 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
8323 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
8324 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
8325 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
8326
8327 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
8328 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
8329 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
8330 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
8331 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
8332
8333 #define S_FW_RSS_IND_TBL_CMD_IQ3 20
8334 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff
8335 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
8336 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
8337 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
8338
8339 #define S_FW_RSS_IND_TBL_CMD_IQ4 10
8340 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff
8341 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
8342 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
8343 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
8344
8345 #define S_FW_RSS_IND_TBL_CMD_IQ5 0
8346 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff
8347 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
8348 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
8349 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
8350
8351 #define S_FW_RSS_IND_TBL_CMD_IQ6 20
8352 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff
8353 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
8354 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
8355 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
8356
8357 #define S_FW_RSS_IND_TBL_CMD_IQ7 10
8358 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff
8359 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
8360 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
8361 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
8362
8363 #define S_FW_RSS_IND_TBL_CMD_IQ8 0
8364 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff
8365 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
8366 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
8367 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
8368
8369 #define S_FW_RSS_IND_TBL_CMD_IQ9 20
8370 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff
8371 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
8372 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
8373 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
8374
8375 #define S_FW_RSS_IND_TBL_CMD_IQ10 10
8376 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff
8377 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
8378 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
8379 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
8380
8381 #define S_FW_RSS_IND_TBL_CMD_IQ11 0
8382 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff
8383 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
8384 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
8385 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
8386
8387 #define S_FW_RSS_IND_TBL_CMD_IQ12 20
8388 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff
8389 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
8390 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
8391 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
8392
8393 #define S_FW_RSS_IND_TBL_CMD_IQ13 10
8394 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff
8395 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
8396 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
8397 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
8398
8399 #define S_FW_RSS_IND_TBL_CMD_IQ14 0
8400 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff
8401 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
8402 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
8403 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
8404
8405 #define S_FW_RSS_IND_TBL_CMD_IQ15 20
8406 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff
8407 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
8408 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
8409 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
8410
8411 #define S_FW_RSS_IND_TBL_CMD_IQ16 10
8412 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff
8413 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
8414 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
8415 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
8416
8417 #define S_FW_RSS_IND_TBL_CMD_IQ17 0
8418 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff
8419 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
8420 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
8421 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
8422
8423 #define S_FW_RSS_IND_TBL_CMD_IQ18 20
8424 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff
8425 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
8426 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
8427 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
8428
8429 #define S_FW_RSS_IND_TBL_CMD_IQ19 10
8430 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff
8431 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
8432 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
8433 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
8434
8435 #define S_FW_RSS_IND_TBL_CMD_IQ20 0
8436 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff
8437 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
8438 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
8439 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
8440
8441 #define S_FW_RSS_IND_TBL_CMD_IQ21 20
8442 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff
8443 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
8444 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
8445 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
8446
8447 #define S_FW_RSS_IND_TBL_CMD_IQ22 10
8448 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff
8449 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
8450 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
8451 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
8452
8453 #define S_FW_RSS_IND_TBL_CMD_IQ23 0
8454 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff
8455 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
8456 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
8457 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
8458
8459 #define S_FW_RSS_IND_TBL_CMD_IQ24 20
8460 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff
8461 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
8462 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
8463 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
8464
8465 #define S_FW_RSS_IND_TBL_CMD_IQ25 10
8466 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff
8467 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
8468 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
8469 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
8470
8471 #define S_FW_RSS_IND_TBL_CMD_IQ26 0
8472 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff
8473 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
8474 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
8475 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
8476
8477 #define S_FW_RSS_IND_TBL_CMD_IQ27 20
8478 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff
8479 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
8480 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
8481 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
8482
8483 #define S_FW_RSS_IND_TBL_CMD_IQ28 10
8484 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff
8485 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
8486 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
8487 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
8488
8489 #define S_FW_RSS_IND_TBL_CMD_IQ29 0
8490 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff
8491 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
8492 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
8493 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
8494
8495 #define S_FW_RSS_IND_TBL_CMD_IQ30 20
8496 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff
8497 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
8498 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
8499 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
8500
8501 #define S_FW_RSS_IND_TBL_CMD_IQ31 10
8502 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff
8503 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
8504 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
8505 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
8506
8507 struct fw_rss_glb_config_cmd {
8508 __be32 op_to_write;
8509 __be32 retval_len16;
8510 union fw_rss_glb_config {
8511 struct fw_rss_glb_config_manual {
8512 __be32 mode_pkd;
8513 __be32 r3;
8514 __be64 r4;
8515 __be64 r5;
8516 } manual;
8517 struct fw_rss_glb_config_basicvirtual {
8518 __be32 mode_keymode;
8519 __be32 synmapen_to_hashtoeplitz;
8520 __be64 r8;
8521 __be64 r9;
8522 } basicvirtual;
8523 } u;
8524 };
8525
8526 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
8527 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
8528 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
8529 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
8530 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
8531
8532 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
8533 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
8534 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
8535
8536 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
8537 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
8538 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8539 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8540 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8541 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
8542 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8543
8544 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
8545 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
8546 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
8547 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
8548
8549 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
8550 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
8551 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8552 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8553 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8554 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
8555 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8556 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
8557
8558 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
8559 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
8560 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8561 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8562 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8563 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8564 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8565 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8566 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8567
8568 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8569 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8570 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8571 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8572 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8573 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8574 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8575 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8576 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8577
8578 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8579 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8580 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8581 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8582 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8583 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8584 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8585 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8586 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8587
8588 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8589 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8590 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8591 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8592 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8593 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8594 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8595 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8596 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8597
8598 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8599 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8600 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8601 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8602 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8603 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8604 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8605 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8606
8607 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8608 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8609 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8610 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8611 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8612 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8613 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8614 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8615
8616 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8617 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8618 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8619 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8620 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8621 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8622 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8623 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8624 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8625
8626 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8627 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8628 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8629 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8630 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8631 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8632 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8633 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8634 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8635
8636 struct fw_rss_vi_config_cmd {
8637 __be32 op_to_viid;
8638 __be32 retval_len16;
8639 union fw_rss_vi_config {
8640 struct fw_rss_vi_config_manual {
8641 __be64 r3;
8642 __be64 r4;
8643 __be64 r5;
8644 } manual;
8645 struct fw_rss_vi_config_basicvirtual {
8646 __be32 r6;
8647 __be32 defaultq_to_udpen;
8648 __be32 secretkeyidx_pkd;
8649 __be32 secretkeyxor;
8650 __be64 r10;
8651 } basicvirtual;
8652 } u;
8653 };
8654
8655 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
8656 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
8657 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8658 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
8659 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8660
8661 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
8662 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
8663 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8664 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8665 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8666 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8667 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8668
8669 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8670 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8671 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8672 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8673 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8674 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8675 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8676 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8677 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8678
8679 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8680 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8681 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8682 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8683 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8684 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8685 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8686 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8687 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8688
8689 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8690 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8691 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8692 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8693 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8694 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8695 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8696 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8697 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8698
8699 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8700 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8701 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8702 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8703 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8704 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8705 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8706 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8707 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8708
8709 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
8710 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
8711 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8712 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
8713 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8714 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8715
8716 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8717 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8718 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8719 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8720 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8721 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8722 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8723
8724 enum fw_sched_sc {
8725 FW_SCHED_SC_CONFIG = 0,
8726 FW_SCHED_SC_PARAMS = 1,
8727 };
8728
8729 enum fw_sched_type {
8730 FW_SCHED_TYPE_PKTSCHED = 0,
8731 FW_SCHED_TYPE_STREAMSCHED = 1,
8732 };
8733
8734 enum fw_sched_params_level {
8735 FW_SCHED_PARAMS_LEVEL_CL_RL = 0,
8736 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1,
8737 FW_SCHED_PARAMS_LEVEL_CH_RL = 2,
8738 };
8739
8740 enum fw_sched_params_mode {
8741 FW_SCHED_PARAMS_MODE_CLASS = 0,
8742 FW_SCHED_PARAMS_MODE_FLOW = 1,
8743 };
8744
8745 enum fw_sched_params_unit {
8746 FW_SCHED_PARAMS_UNIT_BITRATE = 0,
8747 FW_SCHED_PARAMS_UNIT_PKTRATE = 1,
8748 };
8749
8750 enum fw_sched_params_rate {
8751 FW_SCHED_PARAMS_RATE_REL = 0,
8752 FW_SCHED_PARAMS_RATE_ABS = 1,
8753 };
8754
8755 struct fw_sched_cmd {
8756 __be32 op_to_write;
8757 __be32 retval_len16;
8758 union fw_sched {
8759 struct fw_sched_config {
8760 __u8 sc;
8761 __u8 type;
8762 __u8 minmaxen;
8763 __u8 r3[5];
8764 __u8 nclasses[4];
8765 __be32 r4;
8766 } config;
8767 struct fw_sched_params {
8768 __u8 sc;
8769 __u8 type;
8770 __u8 level;
8771 __u8 mode;
8772 __u8 unit;
8773 __u8 rate;
8774 __u8 ch;
8775 __u8 cl;
8776 __be32 min;
8777 __be32 max;
8778 __be16 weight;
8779 __be16 pktsize;
8780 __be16 burstsize;
8781 __be16 r4;
8782 } params;
8783 } u;
8784 };
8785
8786 /*
8787 * length of the formatting string
8788 */
8789 #define FW_DEVLOG_FMT_LEN 192
8790
8791 /*
8792 * maximum number of the formatting string parameters
8793 */
8794 #define FW_DEVLOG_FMT_PARAMS_NUM 8
8795
8796 /*
8797 * priority levels
8798 */
8799 enum fw_devlog_level {
8800 FW_DEVLOG_LEVEL_EMERG = 0x0,
8801 FW_DEVLOG_LEVEL_CRIT = 0x1,
8802 FW_DEVLOG_LEVEL_ERR = 0x2,
8803 FW_DEVLOG_LEVEL_NOTICE = 0x3,
8804 FW_DEVLOG_LEVEL_INFO = 0x4,
8805 FW_DEVLOG_LEVEL_DEBUG = 0x5,
8806 FW_DEVLOG_LEVEL_MAX = 0x5,
8807 };
8808
8809 /*
8810 * facilities that may send a log message
8811 */
8812 enum fw_devlog_facility {
8813 FW_DEVLOG_FACILITY_CORE = 0x00,
8814 FW_DEVLOG_FACILITY_CF = 0x01,
8815 FW_DEVLOG_FACILITY_SCHED = 0x02,
8816 FW_DEVLOG_FACILITY_TIMER = 0x04,
8817 FW_DEVLOG_FACILITY_RES = 0x06,
8818 FW_DEVLOG_FACILITY_HW = 0x08,
8819 FW_DEVLOG_FACILITY_FLR = 0x10,
8820 FW_DEVLOG_FACILITY_DMAQ = 0x12,
8821 FW_DEVLOG_FACILITY_PHY = 0x14,
8822 FW_DEVLOG_FACILITY_MAC = 0x16,
8823 FW_DEVLOG_FACILITY_PORT = 0x18,
8824 FW_DEVLOG_FACILITY_VI = 0x1A,
8825 FW_DEVLOG_FACILITY_FILTER = 0x1C,
8826 FW_DEVLOG_FACILITY_ACL = 0x1E,
8827 FW_DEVLOG_FACILITY_TM = 0x20,
8828 FW_DEVLOG_FACILITY_QFC = 0x22,
8829 FW_DEVLOG_FACILITY_DCB = 0x24,
8830 FW_DEVLOG_FACILITY_ETH = 0x26,
8831 FW_DEVLOG_FACILITY_OFLD = 0x28,
8832 FW_DEVLOG_FACILITY_RI = 0x2A,
8833 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
8834 FW_DEVLOG_FACILITY_FCOE = 0x2E,
8835 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
8836 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
8837 FW_DEVLOG_FACILITY_CHNET = 0x34,
8838 FW_DEVLOG_FACILITY_COISCSI = 0x36,
8839 FW_DEVLOG_FACILITY_MAX = 0x38,
8840 };
8841
8842 /*
8843 * log message format
8844 */
8845 struct fw_devlog_e {
8846 __be64 timestamp;
8847 __be32 seqno;
8848 __be16 reserved1;
8849 __u8 level;
8850 __u8 facility;
8851 __u8 fmt[FW_DEVLOG_FMT_LEN];
8852 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
8853 __be32 reserved3[4];
8854 };
8855
8856 struct fw_devlog_cmd {
8857 __be32 op_to_write;
8858 __be32 retval_len16;
8859 __u8 level;
8860 __u8 r2[7];
8861 __be32 memtype_devlog_memaddr16_devlog;
8862 __be32 memsize_devlog;
8863 __be32 r3[2];
8864 };
8865
8866 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28
8867 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf
8868 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8869 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8870 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8871 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8872
8873 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8874 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8875 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8876 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8877 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8878 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8879 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8880
8881 enum fw_watchdog_actions {
8882 FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8883 FW_WATCHDOG_ACTION_FLR = 1,
8884 FW_WATCHDOG_ACTION_BYPASS = 2,
8885 FW_WATCHDOG_ACTION_TMPCHK = 3,
8886 FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8887
8888 FW_WATCHDOG_ACTION_MAX = 5,
8889 };
8890
8891 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60
8892
8893 struct fw_watchdog_cmd {
8894 __be32 op_to_vfn;
8895 __be32 retval_len16;
8896 __be32 timeout;
8897 __be32 action;
8898 };
8899
8900 #define S_FW_WATCHDOG_CMD_PFN 8
8901 #define M_FW_WATCHDOG_CMD_PFN 0x7
8902 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN)
8903 #define G_FW_WATCHDOG_CMD_PFN(x) \
8904 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8905
8906 #define S_FW_WATCHDOG_CMD_VFN 0
8907 #define M_FW_WATCHDOG_CMD_VFN 0xff
8908 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN)
8909 #define G_FW_WATCHDOG_CMD_VFN(x) \
8910 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8911
8912 struct fw_clip_cmd {
8913 __be32 op_to_write;
8914 __be32 alloc_to_len16;
8915 __be64 ip_hi;
8916 __be64 ip_lo;
8917 __be32 r4[2];
8918 };
8919
8920 #define S_FW_CLIP_CMD_ALLOC 31
8921 #define M_FW_CLIP_CMD_ALLOC 0x1
8922 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
8923 #define G_FW_CLIP_CMD_ALLOC(x) \
8924 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8925 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
8926
8927 #define S_FW_CLIP_CMD_FREE 30
8928 #define M_FW_CLIP_CMD_FREE 0x1
8929 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
8930 #define G_FW_CLIP_CMD_FREE(x) \
8931 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8932 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
8933
8934 #define S_FW_CLIP_CMD_INDEX 16
8935 #define M_FW_CLIP_CMD_INDEX 0x1fff
8936 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX)
8937 #define G_FW_CLIP_CMD_INDEX(x) \
8938 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
8939
8940 struct fw_clip2_cmd {
8941 __be32 op_to_write;
8942 __be32 alloc_to_len16;
8943 __be64 ip_hi;
8944 __be64 ip_lo;
8945 __be64 ipm_hi;
8946 __be64 ipm_lo;
8947 __be32 r4[2];
8948 };
8949
8950 /******************************************************************************
8951 * F O i S C S I C O M M A N D s
8952 **************************************/
8953
8954 #define FW_CHNET_IFACE_ADDR_MAX 3
8955
8956 enum fw_chnet_iface_cmd_subop {
8957 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8958
8959 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8960 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8961
8962 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8963 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8964
8965 FW_CHNET_IFACE_CMD_SUBOP_MAX,
8966 };
8967
8968 struct fw_chnet_iface_cmd {
8969 __be32 op_to_portid;
8970 __be32 retval_len16;
8971 __u8 subop;
8972 __u8 r2[2];
8973 __u8 flags;
8974 __be32 ifid_ifstate;
8975 __be16 mtu;
8976 __be16 vlanid;
8977 __be32 r3;
8978 __be16 r4;
8979 __u8 mac[6];
8980 };
8981
8982 #define S_FW_CHNET_IFACE_CMD_PORTID 0
8983 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf
8984 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8985 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \
8986 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8987
8988 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16
8989 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff
8990 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
8991 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID)
8992 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \
8993 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID)
8994
8995 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0
8996 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1
8997 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
8998 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F)
8999 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \
9000 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \
9001 M_FW_CHNET_IFACE_CMD_RSS_IQID_F)
9002 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U)
9003
9004 #define S_FW_CHNET_IFACE_CMD_IFID 8
9005 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
9006 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
9007 #define G_FW_CHNET_IFACE_CMD_IFID(x) \
9008 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
9009
9010 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0
9011 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff
9012 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
9013 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
9014 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
9015
9016 struct fw_fcoe_res_info_cmd {
9017 __be32 op_to_read;
9018 __be32 retval_len16;
9019 __be16 e_d_tov;
9020 __be16 r_a_tov_seq;
9021 __be16 r_a_tov_els;
9022 __be16 r_r_tov;
9023 __be32 max_xchgs;
9024 __be32 max_ssns;
9025 __be32 used_xchgs;
9026 __be32 used_ssns;
9027 __be32 max_fcfs;
9028 __be32 max_vnps;
9029 __be32 used_fcfs;
9030 __be32 used_vnps;
9031 };
9032
9033 struct fw_fcoe_link_cmd {
9034 __be32 op_to_portid;
9035 __be32 retval_len16;
9036 __be32 sub_opcode_fcfi;
9037 __u8 r3;
9038 __u8 lstatus;
9039 __be16 flags;
9040 __u8 r4;
9041 __u8 set_vlan;
9042 __be16 vlan_id;
9043 __be32 vnpi_pkd;
9044 __be16 r6;
9045 __u8 phy_mac[6];
9046 __u8 vnport_wwnn[8];
9047 __u8 vnport_wwpn[8];
9048 };
9049
9050 #define S_FW_FCOE_LINK_CMD_PORTID 0
9051 #define M_FW_FCOE_LINK_CMD_PORTID 0xf
9052 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID)
9053 #define G_FW_FCOE_LINK_CMD_PORTID(x) \
9054 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
9055
9056 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24
9057 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff
9058 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9059 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
9060 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
9061 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
9062
9063 #define S_FW_FCOE_LINK_CMD_FCFI 0
9064 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff
9065 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI)
9066 #define G_FW_FCOE_LINK_CMD_FCFI(x) \
9067 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
9068
9069 #define S_FW_FCOE_LINK_CMD_VNPI 0
9070 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff
9071 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI)
9072 #define G_FW_FCOE_LINK_CMD_VNPI(x) \
9073 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
9074
9075 struct fw_fcoe_vnp_cmd {
9076 __be32 op_to_fcfi;
9077 __be32 alloc_to_len16;
9078 __be32 gen_wwn_to_vnpi;
9079 __be32 vf_id;
9080 __be16 iqid;
9081 __u8 vnport_mac[6];
9082 __u8 vnport_wwnn[8];
9083 __u8 vnport_wwpn[8];
9084 __u8 cmn_srv_parms[16];
9085 __u8 clsp_word_0_1[8];
9086 };
9087
9088 #define S_FW_FCOE_VNP_CMD_FCFI 0
9089 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff
9090 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI)
9091 #define G_FW_FCOE_VNP_CMD_FCFI(x) \
9092 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
9093
9094 #define S_FW_FCOE_VNP_CMD_ALLOC 31
9095 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1
9096 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC)
9097 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \
9098 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
9099 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U)
9100
9101 #define S_FW_FCOE_VNP_CMD_FREE 30
9102 #define M_FW_FCOE_VNP_CMD_FREE 0x1
9103 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE)
9104 #define G_FW_FCOE_VNP_CMD_FREE(x) \
9105 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
9106 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U)
9107
9108 #define S_FW_FCOE_VNP_CMD_MODIFY 29
9109 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1
9110 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY)
9111 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \
9112 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
9113 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U)
9114
9115 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22
9116 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1
9117 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
9118 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
9119 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
9120 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
9121
9122 #define S_FW_FCOE_VNP_CMD_PERSIST 21
9123 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1
9124 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST)
9125 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \
9126 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
9127 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U)
9128
9129 #define S_FW_FCOE_VNP_CMD_VFID_EN 20
9130 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1
9131 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
9132 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
9133 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
9134 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U)
9135
9136 #define S_FW_FCOE_VNP_CMD_VNPI 0
9137 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff
9138 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI)
9139 #define G_FW_FCOE_VNP_CMD_VNPI(x) \
9140 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
9141
9142 struct fw_fcoe_sparams_cmd {
9143 __be32 op_to_portid;
9144 __be32 retval_len16;
9145 __u8 r3[7];
9146 __u8 cos;
9147 __u8 lport_wwnn[8];
9148 __u8 lport_wwpn[8];
9149 __u8 cmn_srv_parms[16];
9150 __u8 cls_srv_parms[16];
9151 };
9152
9153 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0
9154 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf
9155 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
9156 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
9157 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
9158
9159 struct fw_fcoe_stats_cmd {
9160 __be32 op_to_flowid;
9161 __be32 free_to_len16;
9162 union fw_fcoe_stats {
9163 struct fw_fcoe_stats_ctl {
9164 __u8 nstats_port;
9165 __u8 port_valid_ix;
9166 __be16 r6;
9167 __be32 r7;
9168 __be64 stat0;
9169 __be64 stat1;
9170 __be64 stat2;
9171 __be64 stat3;
9172 __be64 stat4;
9173 __be64 stat5;
9174 } ctl;
9175 struct fw_fcoe_port_stats {
9176 __be64 tx_bcast_bytes;
9177 __be64 tx_bcast_frames;
9178 __be64 tx_mcast_bytes;
9179 __be64 tx_mcast_frames;
9180 __be64 tx_ucast_bytes;
9181 __be64 tx_ucast_frames;
9182 __be64 tx_drop_frames;
9183 __be64 tx_offload_bytes;
9184 __be64 tx_offload_frames;
9185 __be64 rx_bcast_bytes;
9186 __be64 rx_bcast_frames;
9187 __be64 rx_mcast_bytes;
9188 __be64 rx_mcast_frames;
9189 __be64 rx_ucast_bytes;
9190 __be64 rx_ucast_frames;
9191 __be64 rx_err_frames;
9192 } port_stats;
9193 struct fw_fcoe_fcf_stats {
9194 __be32 fip_tx_bytes;
9195 __be32 fip_tx_fr;
9196 __be64 fcf_ka;
9197 __be64 mcast_adv_rcvd;
9198 __be16 ucast_adv_rcvd;
9199 __be16 sol_sent;
9200 __be16 vlan_req;
9201 __be16 vlan_rpl;
9202 __be16 clr_vlink;
9203 __be16 link_down;
9204 __be16 link_up;
9205 __be16 logo;
9206 __be16 flogi_req;
9207 __be16 flogi_rpl;
9208 __be16 fdisc_req;
9209 __be16 fdisc_rpl;
9210 __be16 fka_prd_chg;
9211 __be16 fc_map_chg;
9212 __be16 vfid_chg;
9213 __u8 no_fka_req;
9214 __u8 no_vnp;
9215 } fcf_stats;
9216 struct fw_fcoe_pcb_stats {
9217 __be64 tx_bytes;
9218 __be64 tx_frames;
9219 __be64 rx_bytes;
9220 __be64 rx_frames;
9221 __be32 vnp_ka;
9222 __be32 unsol_els_rcvd;
9223 __be64 unsol_cmd_rcvd;
9224 __be16 implicit_logo;
9225 __be16 flogi_inv_sparm;
9226 __be16 fdisc_inv_sparm;
9227 __be16 flogi_rjt;
9228 __be16 fdisc_rjt;
9229 __be16 no_ssn;
9230 __be16 mac_flt_fail;
9231 __be16 inv_fr_rcvd;
9232 } pcb_stats;
9233 struct fw_fcoe_scb_stats {
9234 __be64 tx_bytes;
9235 __be64 tx_frames;
9236 __be64 rx_bytes;
9237 __be64 rx_frames;
9238 __be32 host_abrt_req;
9239 __be32 adap_auto_abrt;
9240 __be32 adap_abrt_rsp;
9241 __be32 host_ios_req;
9242 __be16 ssn_offl_ios;
9243 __be16 ssn_not_rdy_ios;
9244 __u8 rx_data_ddp_err;
9245 __u8 ddp_flt_set_err;
9246 __be16 rx_data_fr_err;
9247 __u8 bad_st_abrt_req;
9248 __u8 no_io_abrt_req;
9249 __u8 abort_tmo;
9250 __u8 abort_tmo_2;
9251 __be32 abort_req;
9252 __u8 no_ppod_res_tmo;
9253 __u8 bp_tmo;
9254 __u8 adap_auto_cls;
9255 __u8 no_io_cls_req;
9256 __be32 host_cls_req;
9257 __be64 unsol_cmd_rcvd;
9258 __be32 plogi_req_rcvd;
9259 __be32 prli_req_rcvd;
9260 __be16 logo_req_rcvd;
9261 __be16 prlo_req_rcvd;
9262 __be16 plogi_rjt_rcvd;
9263 __be16 prli_rjt_rcvd;
9264 __be32 adisc_req_rcvd;
9265 __be32 rscn_rcvd;
9266 __be32 rrq_req_rcvd;
9267 __be32 unsol_els_rcvd;
9268 __u8 adisc_rjt_rcvd;
9269 __u8 scr_rjt;
9270 __u8 ct_rjt;
9271 __u8 inval_bls_rcvd;
9272 __be32 ba_rjt_rcvd;
9273 } scb_stats;
9274 } u;
9275 };
9276
9277 #define S_FW_FCOE_STATS_CMD_FLOWID 0
9278 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff
9279 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID)
9280 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \
9281 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
9282
9283 #define S_FW_FCOE_STATS_CMD_FREE 30
9284 #define M_FW_FCOE_STATS_CMD_FREE 0x1
9285 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE)
9286 #define G_FW_FCOE_STATS_CMD_FREE(x) \
9287 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
9288 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U)
9289
9290 #define S_FW_FCOE_STATS_CMD_NSTATS 4
9291 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7
9292 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS)
9293 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \
9294 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
9295
9296 #define S_FW_FCOE_STATS_CMD_PORT 0
9297 #define M_FW_FCOE_STATS_CMD_PORT 0x3
9298 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT)
9299 #define G_FW_FCOE_STATS_CMD_PORT(x) \
9300 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
9301
9302 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7
9303 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1
9304 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9305 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
9306 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
9307 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
9308 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
9309
9310 #define S_FW_FCOE_STATS_CMD_IX 0
9311 #define M_FW_FCOE_STATS_CMD_IX 0x3f
9312 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX)
9313 #define G_FW_FCOE_STATS_CMD_IX(x) \
9314 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
9315
9316 struct fw_fcoe_fcf_cmd {
9317 __be32 op_to_fcfi;
9318 __be32 retval_len16;
9319 __be16 priority_pkd;
9320 __u8 mac[6];
9321 __u8 name_id[8];
9322 __u8 fabric[8];
9323 __be16 vf_id;
9324 __be16 max_fcoe_size;
9325 __u8 vlan_id;
9326 __u8 fc_map[3];
9327 __be32 fka_adv;
9328 __be32 r6;
9329 __u8 r7_hi;
9330 __u8 fpma_to_portid;
9331 __u8 spma_mac[6];
9332 __be64 r8;
9333 };
9334
9335 #define S_FW_FCOE_FCF_CMD_FCFI 0
9336 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff
9337 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI)
9338 #define G_FW_FCOE_FCF_CMD_FCFI(x) \
9339 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
9340
9341 #define S_FW_FCOE_FCF_CMD_PRIORITY 0
9342 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff
9343 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
9344 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
9345 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
9346
9347 #define S_FW_FCOE_FCF_CMD_FPMA 6
9348 #define M_FW_FCOE_FCF_CMD_FPMA 0x1
9349 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA)
9350 #define G_FW_FCOE_FCF_CMD_FPMA(x) \
9351 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
9352 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U)
9353
9354 #define S_FW_FCOE_FCF_CMD_SPMA 5
9355 #define M_FW_FCOE_FCF_CMD_SPMA 0x1
9356 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA)
9357 #define G_FW_FCOE_FCF_CMD_SPMA(x) \
9358 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
9359 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U)
9360
9361 #define S_FW_FCOE_FCF_CMD_LOGIN 4
9362 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1
9363 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN)
9364 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \
9365 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
9366 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U)
9367
9368 #define S_FW_FCOE_FCF_CMD_PORTID 0
9369 #define M_FW_FCOE_FCF_CMD_PORTID 0xf
9370 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID)
9371 #define G_FW_FCOE_FCF_CMD_PORTID(x) \
9372 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
9373
9374 /******************************************************************************
9375 * E R R O R a n d D E B U G C O M M A N D s
9376 ******************************************************/
9377
9378 enum fw_error_type {
9379 FW_ERROR_TYPE_EXCEPTION = 0x0,
9380 FW_ERROR_TYPE_HWMODULE = 0x1,
9381 FW_ERROR_TYPE_WR = 0x2,
9382 FW_ERROR_TYPE_ACL = 0x3,
9383 };
9384
9385 enum fw_dcb_ieee_locations {
9386 FW_IEEE_LOC_LOCAL,
9387 FW_IEEE_LOC_PEER,
9388 FW_IEEE_LOC_OPERATIONAL,
9389 };
9390
9391 struct fw_dcb_ieee_cmd {
9392 __be32 op_to_location;
9393 __be32 changed_to_len16;
9394 union fw_dcbx_stats {
9395 struct fw_dcbx_pfc_stats_ieee {
9396 __be32 pfc_mbc_pkd;
9397 __be32 pfc_willing_to_pfc_en;
9398 } dcbx_pfc_stats;
9399 struct fw_dcbx_ets_stats_ieee {
9400 __be32 cbs_to_ets_max_tc;
9401 __be32 pg_table;
9402 __u8 pg_percent[8];
9403 __u8 tsa[8];
9404 } dcbx_ets_stats;
9405 struct fw_dcbx_app_stats_ieee {
9406 __be32 num_apps_pkd;
9407 __be32 r6;
9408 __be32 app[4];
9409 } dcbx_app_stats;
9410 struct fw_dcbx_control {
9411 __be32 multi_peer_invalidated;
9412 __u8 version;
9413 __u8 r6[3];
9414 } dcbx_control;
9415 } u;
9416 };
9417
9418 #define S_FW_DCB_IEEE_CMD_PORT 8
9419 #define M_FW_DCB_IEEE_CMD_PORT 0x7
9420 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT)
9421 #define G_FW_DCB_IEEE_CMD_PORT(x) \
9422 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
9423
9424 #define S_FW_DCB_IEEE_CMD_FEATURE 2
9425 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7
9426 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE)
9427 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \
9428 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
9429
9430 #define S_FW_DCB_IEEE_CMD_LOCATION 0
9431 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3
9432 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION)
9433 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \
9434 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
9435
9436 #define S_FW_DCB_IEEE_CMD_CHANGED 20
9437 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1
9438 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED)
9439 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \
9440 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
9441 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U)
9442
9443 #define S_FW_DCB_IEEE_CMD_RECEIVED 19
9444 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1
9445 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
9446 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \
9447 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
9448 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U)
9449
9450 #define S_FW_DCB_IEEE_CMD_APPLY 18
9451 #define M_FW_DCB_IEEE_CMD_APPLY 0x1
9452 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY)
9453 #define G_FW_DCB_IEEE_CMD_APPLY(x) \
9454 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
9455 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)
9456
9457 #define S_FW_DCB_IEEE_CMD_DISABLED 17
9458 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1
9459 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED)
9460 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \
9461 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
9462 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U)
9463
9464 #define S_FW_DCB_IEEE_CMD_MORE 16
9465 #define M_FW_DCB_IEEE_CMD_MORE 0x1
9466 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE)
9467 #define G_FW_DCB_IEEE_CMD_MORE(x) \
9468 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
9469 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U)
9470
9471 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0
9472 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1
9473 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
9474 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \
9475 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
9476 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
9477
9478 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16
9479 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1
9480 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
9481 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
9482 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
9483 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
9484 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
9485
9486 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8
9487 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff
9488 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9489 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \
9490 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
9491
9492 #define S_FW_DCB_IEEE_CMD_PFC_EN 0
9493 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff
9494 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
9495 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \
9496 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
9497
9498 #define S_FW_DCB_IEEE_CMD_CBS 16
9499 #define M_FW_DCB_IEEE_CMD_CBS 0x1
9500 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS)
9501 #define G_FW_DCB_IEEE_CMD_CBS(x) \
9502 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
9503 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U)
9504
9505 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8
9506 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1
9507 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
9508 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
9509 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
9510 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
9511 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
9512
9513 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0
9514 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff
9515 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9516 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \
9517 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9518
9519 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0
9520 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7
9521 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
9522 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \
9523 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
9524
9525 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31
9526 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1
9527 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
9528 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \
9529 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
9530 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
9531
9532 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30
9533 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1
9534 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9535 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
9536 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9537 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
9538 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
9539
9540 /* Hand-written */
9541 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16
9542 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff
9543 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9544 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \
9545 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9546
9547 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3
9548 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7
9549 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
9550 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \
9551 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
9552
9553 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0
9554 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7
9555 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
9556 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \
9557 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
9558
9559
9560 struct fw_error_cmd {
9561 __be32 op_to_type;
9562 __be32 len16_pkd;
9563 union fw_error {
9564 struct fw_error_exception {
9565 __be32 info[6];
9566 } exception;
9567 struct fw_error_hwmodule {
9568 __be32 regaddr;
9569 __be32 regval;
9570 } hwmodule;
9571 struct fw_error_wr {
9572 __be16 cidx;
9573 __be16 pfn_vfn;
9574 __be32 eqid;
9575 __u8 wrhdr[16];
9576 } wr;
9577 struct fw_error_acl {
9578 __be16 cidx;
9579 __be16 pfn_vfn;
9580 __be32 eqid;
9581 __be16 mv_pkd;
9582 __u8 val[6];
9583 __be64 r4;
9584 } acl;
9585 } u;
9586 };
9587
9588 #define S_FW_ERROR_CMD_FATAL 4
9589 #define M_FW_ERROR_CMD_FATAL 0x1
9590 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL)
9591 #define G_FW_ERROR_CMD_FATAL(x) \
9592 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
9593 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U)
9594
9595 #define S_FW_ERROR_CMD_TYPE 0
9596 #define M_FW_ERROR_CMD_TYPE 0xf
9597 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE)
9598 #define G_FW_ERROR_CMD_TYPE(x) \
9599 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9600
9601 #define S_FW_ERROR_CMD_PFN 8
9602 #define M_FW_ERROR_CMD_PFN 0x7
9603 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9604 #define G_FW_ERROR_CMD_PFN(x) \
9605 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9606
9607 #define S_FW_ERROR_CMD_VFN 0
9608 #define M_FW_ERROR_CMD_VFN 0xff
9609 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9610 #define G_FW_ERROR_CMD_VFN(x) \
9611 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9612
9613 #define S_FW_ERROR_CMD_PFN 8
9614 #define M_FW_ERROR_CMD_PFN 0x7
9615 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9616 #define G_FW_ERROR_CMD_PFN(x) \
9617 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9618
9619 #define S_FW_ERROR_CMD_VFN 0
9620 #define M_FW_ERROR_CMD_VFN 0xff
9621 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9622 #define G_FW_ERROR_CMD_VFN(x) \
9623 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9624
9625 #define S_FW_ERROR_CMD_MV 15
9626 #define M_FW_ERROR_CMD_MV 0x1
9627 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV)
9628 #define G_FW_ERROR_CMD_MV(x) \
9629 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9630 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U)
9631
9632 struct fw_debug_cmd {
9633 __be32 op_type;
9634 __be32 len16_pkd;
9635 union fw_debug {
9636 struct fw_debug_assert {
9637 __be32 fcid;
9638 __be32 line;
9639 __be32 x;
9640 __be32 y;
9641 __u8 filename_0_7[8];
9642 __u8 filename_8_15[8];
9643 __be64 r3;
9644 } assert;
9645 struct fw_debug_prt {
9646 __be16 dprtstridx;
9647 __be16 r3[3];
9648 __be32 dprtstrparam0;
9649 __be32 dprtstrparam1;
9650 __be32 dprtstrparam2;
9651 __be32 dprtstrparam3;
9652 } prt;
9653 } u;
9654 };
9655
9656 #define S_FW_DEBUG_CMD_TYPE 0
9657 #define M_FW_DEBUG_CMD_TYPE 0xff
9658 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
9659 #define G_FW_DEBUG_CMD_TYPE(x) \
9660 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9661
9662 enum fw_diag_cmd_type {
9663 FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9664 FW_DIAG_CMD_TYPE_MEM_TEST_DIAG,
9665 };
9666
9667 enum fw_diag_cmd_ofldiag_op {
9668 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9669 FW_DIAG_CMD_OFLDIAG_TEST_START,
9670 FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9671 FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9672 };
9673
9674 enum fw_diag_cmd_ofldiag_status {
9675 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9676 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9677 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9678 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9679 };
9680
9681 enum fw_diag_cmd_memdiag_op {
9682 FW_DIAG_CMD_MEMDIAG_TEST_START=1,
9683 FW_DIAG_CMD_MEMDIAG_TEST_STOP,
9684 FW_DIAG_CMD_MEMDIAG_TEST_STATUS,
9685 FW_DIAG_CMD_MEMDIAG_TEST_INIT,
9686 };
9687
9688
9689 enum fw_diag_cmd_memdiag_status {
9690 FW_DIAG_CMD_MEMDIAG_STATUS_NONE,
9691 FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING,
9692 FW_DIAG_CMD_MEMDIAG_STATUS_FAILED,
9693 FW_DIAG_CMD_MEMDIAG_STATUS_PASSED
9694 };
9695
9696
9697 struct fw_diag_cmd {
9698 __be32 op_type;
9699 __be32 len16_pkd;
9700 union fw_diag_test {
9701 struct fw_diag_test_ofldiag {
9702 __u8 test_op;
9703 __u8 r3;
9704 __be16 test_status;
9705 __be32 duration;
9706 } ofldiag;
9707 struct fw_diag_test_memtest_diag {
9708 __u8 test_op;
9709 __u8 test_status;
9710 __be16 size; /* in KB */
9711 __be32 duration; /* in seconds */
9712 } memdiag;
9713 } u;
9714 };
9715
9716 #define S_FW_DIAG_CMD_OPCODE 24
9717 #define M_FW_DIAG_CMD_OPCODE 0xff
9718 #define V_FW_DIAG_CMD_OPCODE(x) ((x) << S_FW_DIAG_CMD_OPCODE)
9719 #define G_FW_DIAG_CMD_OPCODE(x) \
9720 (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE)
9721
9722 #define S_FW_DIAG_CMD_TYPE 0
9723 #define M_FW_DIAG_CMD_TYPE 0xff
9724 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
9725 #define G_FW_DIAG_CMD_TYPE(x) \
9726 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9727
9728 #define S_FW_DIAG_CMD_LEN16 0
9729 #define M_FW_DIAG_CMD_LEN16 0xff
9730 #define V_FW_DIAG_CMD_LEN16(x) ((x) << S_FW_DIAG_CMD_LEN16)
9731 #define G_FW_DIAG_CMD_LEN16(x) \
9732 (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16)
9733
9734 struct fw_hma_cmd {
9735 __be32 op_pkd;
9736 __be32 retval_len16;
9737 __be32 mode_to_pcie_params;
9738 __be32 naddr_size;
9739 __be32 addr_size_pkd;
9740 __be32 r6;
9741 __be64 phy_address[5];
9742 };
9743
9744 #define S_FW_HMA_CMD_MODE 31
9745 #define M_FW_HMA_CMD_MODE 0x1
9746 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE)
9747 #define G_FW_HMA_CMD_MODE(x) \
9748 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
9749 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U)
9750
9751 #define S_FW_HMA_CMD_SOC 30
9752 #define M_FW_HMA_CMD_SOC 0x1
9753 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC)
9754 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
9755 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U)
9756
9757 #define S_FW_HMA_CMD_EOC 29
9758 #define M_FW_HMA_CMD_EOC 0x1
9759 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC)
9760 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
9761 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U)
9762
9763 #define S_FW_HMA_CMD_PCIE_PARAMS 0
9764 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff
9765 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS)
9766 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \
9767 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
9768
9769 #define S_FW_HMA_CMD_NADDR 12
9770 #define M_FW_HMA_CMD_NADDR 0x3f
9771 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR)
9772 #define G_FW_HMA_CMD_NADDR(x) \
9773 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
9774
9775 #define S_FW_HMA_CMD_SIZE 0
9776 #define M_FW_HMA_CMD_SIZE 0xfff
9777 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE)
9778 #define G_FW_HMA_CMD_SIZE(x) \
9779 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
9780
9781 #define S_FW_HMA_CMD_ADDR_SIZE 11
9782 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff
9783 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE)
9784 #define G_FW_HMA_CMD_ADDR_SIZE(x) \
9785 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
9786
9787 /******************************************************************************
9788 * P C I E F W R E G I S T E R
9789 **************************************/
9790
9791 enum pcie_fw_eval {
9792 PCIE_FW_EVAL_CRASH = 0,
9793 PCIE_FW_EVAL_PREP = 1,
9794 PCIE_FW_EVAL_CONF = 2,
9795 PCIE_FW_EVAL_INIT = 3,
9796 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4,
9797 PCIE_FW_EVAL_OVERHEAT = 5,
9798 PCIE_FW_EVAL_DEVICESHUTDOWN = 6,
9799 };
9800
9801 /**
9802 * Register definitions for the PCIE_FW register which the firmware uses
9803 * to retain status across RESETs. This register should be considered
9804 * as a READ-ONLY register for Host Software and only to be used to
9805 * track firmware initialization/error state, etc.
9806 */
9807 #define S_PCIE_FW_ERR 31
9808 #define M_PCIE_FW_ERR 0x1
9809 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
9810 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9811 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
9812
9813 #define S_PCIE_FW_INIT 30
9814 #define M_PCIE_FW_INIT 0x1
9815 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
9816 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9817 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
9818
9819 #define S_PCIE_FW_HALT 29
9820 #define M_PCIE_FW_HALT 0x1
9821 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
9822 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9823 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
9824
9825 #define S_PCIE_FW_EVAL 24
9826 #define M_PCIE_FW_EVAL 0x7
9827 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
9828 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9829
9830 #define S_PCIE_FW_STAGE 21
9831 #define M_PCIE_FW_STAGE 0x7
9832 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE)
9833 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9834
9835 #define S_PCIE_FW_ASYNCNOT_VLD 20
9836 #define M_PCIE_FW_ASYNCNOT_VLD 0x1
9837 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
9838 ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9839 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
9840 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9841 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U)
9842
9843 #define S_PCIE_FW_ASYNCNOTINT 19
9844 #define M_PCIE_FW_ASYNCNOTINT 0x1
9845 #define V_PCIE_FW_ASYNCNOTINT(x) \
9846 ((x) << S_PCIE_FW_ASYNCNOTINT)
9847 #define G_PCIE_FW_ASYNCNOTINT(x) \
9848 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9849 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U)
9850
9851 #define S_PCIE_FW_ASYNCNOT 16
9852 #define M_PCIE_FW_ASYNCNOT 0x7
9853 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT)
9854 #define G_PCIE_FW_ASYNCNOT(x) \
9855 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9856
9857 #define S_PCIE_FW_MASTER_VLD 15
9858 #define M_PCIE_FW_MASTER_VLD 0x1
9859 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
9860 #define G_PCIE_FW_MASTER_VLD(x) \
9861 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9862 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
9863
9864 #define S_PCIE_FW_MASTER 12
9865 #define M_PCIE_FW_MASTER 0x7
9866 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
9867 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9868
9869 #define S_PCIE_FW_RESET_VLD 11
9870 #define M_PCIE_FW_RESET_VLD 0x1
9871 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD)
9872 #define G_PCIE_FW_RESET_VLD(x) \
9873 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9874 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U)
9875
9876 #define S_PCIE_FW_RESET 8
9877 #define M_PCIE_FW_RESET 0x7
9878 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET)
9879 #define G_PCIE_FW_RESET(x) \
9880 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9881
9882 #define S_PCIE_FW_REGISTERED 0
9883 #define M_PCIE_FW_REGISTERED 0xff
9884 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
9885 #define G_PCIE_FW_REGISTERED(x) \
9886 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9887
9888
9889 /******************************************************************************
9890 * P C I E F W P F 0 R E G I S T E R
9891 **********************************************/
9892
9893 /*
9894 * this register is available as 32-bit of persistent storage (across
9895 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9896 * will not write it)
9897 */
9898
9899
9900 /******************************************************************************
9901 * P C I E F W P F 7 R E G I S T E R
9902 **********************************************/
9903
9904 /*
9905 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9906 * access the "devlog" which needing to contact firmware. The encoding is
9907 * mostly the same as that returned by the DEVLOG command except for the size
9908 * which is encoded as the number of entries in multiples-1 of 128 here rather
9909 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
9910 * and 15 means 2048. This of course in turn constrains the allowed values
9911 * for the devlog size ...
9912 */
9913 #define PCIE_FW_PF_DEVLOG 7
9914
9915 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28
9916 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf
9917 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9918 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9919 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9920 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9921 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9922
9923 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4
9924 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff
9925 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9926 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9927 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9928
9929 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0
9930 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf
9931 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9932 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9933 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9934
9935
9936 /******************************************************************************
9937 * B I N A R Y H E A D E R F O R M A T
9938 **********************************************/
9939
9940 /*
9941 * firmware binary header format
9942 */
9943 struct fw_hdr {
9944 __u8 ver;
9945 __u8 chip; /* terminator chip family */
9946 __be16 len512; /* bin length in units of 512-bytes */
9947 __be32 fw_ver; /* firmware version */
9948 __be32 tp_microcode_ver; /* tcp processor microcode version */
9949 __u8 intfver_nic;
9950 __u8 intfver_vnic;
9951 __u8 intfver_ofld;
9952 __u8 intfver_ri;
9953 __u8 intfver_iscsipdu;
9954 __u8 intfver_iscsi;
9955 __u8 intfver_fcoepdu;
9956 __u8 intfver_fcoe;
9957 __u32 reserved2;
9958 __u32 reserved3;
9959 __be32 magic; /* runtime or bootstrap fw */
9960 __be32 flags;
9961 __be32 reserved6[4];
9962 __u8 reserved7[3];
9963 __u8 dsign_len;
9964 __u8 dsign[72]; /* fw binary digital signature */
9965 };
9966
9967 enum fw_hdr_chip {
9968 FW_HDR_CHIP_T4,
9969 FW_HDR_CHIP_T5,
9970 FW_HDR_CHIP_T6
9971 };
9972
9973 #define S_FW_HDR_FW_VER_MAJOR 24
9974 #define M_FW_HDR_FW_VER_MAJOR 0xff
9975 #define V_FW_HDR_FW_VER_MAJOR(x) \
9976 ((x) << S_FW_HDR_FW_VER_MAJOR)
9977 #define G_FW_HDR_FW_VER_MAJOR(x) \
9978 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9979
9980 #define S_FW_HDR_FW_VER_MINOR 16
9981 #define M_FW_HDR_FW_VER_MINOR 0xff
9982 #define V_FW_HDR_FW_VER_MINOR(x) \
9983 ((x) << S_FW_HDR_FW_VER_MINOR)
9984 #define G_FW_HDR_FW_VER_MINOR(x) \
9985 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9986
9987 #define S_FW_HDR_FW_VER_MICRO 8
9988 #define M_FW_HDR_FW_VER_MICRO 0xff
9989 #define V_FW_HDR_FW_VER_MICRO(x) \
9990 ((x) << S_FW_HDR_FW_VER_MICRO)
9991 #define G_FW_HDR_FW_VER_MICRO(x) \
9992 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9993
9994 #define S_FW_HDR_FW_VER_BUILD 0
9995 #define M_FW_HDR_FW_VER_BUILD 0xff
9996 #define V_FW_HDR_FW_VER_BUILD(x) \
9997 ((x) << S_FW_HDR_FW_VER_BUILD)
9998 #define G_FW_HDR_FW_VER_BUILD(x) \
9999 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
10000
10001 enum {
10002 T4FW_VERSION_MAJOR = 1,
10003 T4FW_VERSION_MINOR = 27,
10004 T4FW_VERSION_MICRO = 5,
10005 T4FW_VERSION_BUILD = 0,
10006
10007 T5FW_VERSION_MAJOR = 1,
10008 T5FW_VERSION_MINOR = 27,
10009 T5FW_VERSION_MICRO = 5,
10010 T5FW_VERSION_BUILD = 0,
10011
10012 T6FW_VERSION_MAJOR = 1,
10013 T6FW_VERSION_MINOR = 27,
10014 T6FW_VERSION_MICRO = 5,
10015 T6FW_VERSION_BUILD = 0,
10016 };
10017
10018 enum {
10019 /* T4
10020 */
10021 T4FW_HDR_INTFVER_NIC = 0x00,
10022 T4FW_HDR_INTFVER_VNIC = 0x00,
10023 T4FW_HDR_INTFVER_OFLD = 0x00,
10024 T4FW_HDR_INTFVER_RI = 0x00,
10025 T4FW_HDR_INTFVER_ISCSIPDU= 0x00,
10026 T4FW_HDR_INTFVER_ISCSI = 0x00,
10027 T4FW_HDR_INTFVER_FCOEPDU = 0x00,
10028 T4FW_HDR_INTFVER_FCOE = 0x00,
10029
10030 /* T5
10031 */
10032 T5FW_HDR_INTFVER_NIC = 0x00,
10033 T5FW_HDR_INTFVER_VNIC = 0x00,
10034 T5FW_HDR_INTFVER_OFLD = 0x00,
10035 T5FW_HDR_INTFVER_RI = 0x00,
10036 T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
10037 T5FW_HDR_INTFVER_ISCSI = 0x00,
10038 T5FW_HDR_INTFVER_FCOEPDU= 0x00,
10039 T5FW_HDR_INTFVER_FCOE = 0x00,
10040
10041 /* T6
10042 */
10043 T6FW_HDR_INTFVER_NIC = 0x00,
10044 T6FW_HDR_INTFVER_VNIC = 0x00,
10045 T6FW_HDR_INTFVER_OFLD = 0x00,
10046 T6FW_HDR_INTFVER_RI = 0x00,
10047 T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
10048 T6FW_HDR_INTFVER_ISCSI = 0x00,
10049 T6FW_HDR_INTFVER_FCOEPDU= 0x00,
10050 T6FW_HDR_INTFVER_FCOE = 0x00,
10051 };
10052
10053 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \
10054 V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \
10055 V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD))
10056
10057 enum {
10058 FW_HDR_MAGIC_RUNTIME = 0x00000000,
10059 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
10060 };
10061
10062 enum fw_hdr_flags {
10063 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
10064 FW_HDR_FLAGS_SIGNED_FW = 0x00000002,
10065 };
10066
10067 /*
10068 * External PHY firmware binary header format
10069 */
10070 struct fw_ephy_hdr {
10071 __u8 ver;
10072 __u8 reserved;
10073 __be16 len512; /* bin length in units of 512-bytes */
10074 __be32 magic;
10075
10076 __be16 vendor_id;
10077 __be16 device_id;
10078 __be32 version;
10079
10080 __be32 reserved1[4];
10081 };
10082
10083 enum {
10084 FW_EPHY_HDR_MAGIC = 0x65706879,
10085 };
10086
10087 struct fw_ifconf_dhcp_info {
10088 __be32 addr;
10089 __be32 mask;
10090 __be16 vlanid;
10091 __be16 mtu;
10092 __be32 gw;
10093 __u8 op;
10094 __u8 len;
10095 __u8 data[270];
10096 };
10097
10098 struct fw_ifconf_ping_info {
10099 __be16 ping_pldsize;
10100 };
10101
10102 #endif /* _T4FW_INTERFACE_H_ */
10103