xref: /netbsd/sys/dev/pci/cxgb/cxgb_regs.h (revision 86bb752c)
1 /**************************************************************************
2 
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11 
12  2. Neither the name of the Chelsio Corporation nor the names of its
13     contributors may be used to endorse or promote products derived from
14     this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27 
28 ***************************************************************************/
29 /* This file is automatically generated --- do not edit */
30 
31 /* registers for module SGE3 */
32 #define SGE3_BASE_ADDR 0x0
33 
34 #define A_SG_CONTROL 0x0
35 
36 #define S_EGRENUPBP    21
37 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP)
38 #define F_EGRENUPBP    V_EGRENUPBP(1U)
39 
40 #define S_DROPPKT    20
41 #define V_DROPPKT(x) ((x) << S_DROPPKT)
42 #define F_DROPPKT    V_DROPPKT(1U)
43 
44 #define S_EGRGENCTRL    19
45 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
46 #define F_EGRGENCTRL    V_EGRGENCTRL(1U)
47 
48 #define S_USERSPACESIZE    14
49 #define M_USERSPACESIZE    0x1f
50 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
51 #define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE)
52 
53 #define S_HOSTPAGESIZE    11
54 #define M_HOSTPAGESIZE    0x7
55 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
56 #define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE)
57 
58 #define S_PCIRELAX    10
59 #define V_PCIRELAX(x) ((x) << S_PCIRELAX)
60 #define F_PCIRELAX    V_PCIRELAX(1U)
61 
62 #define S_FLMODE    9
63 #define V_FLMODE(x) ((x) << S_FLMODE)
64 #define F_FLMODE    V_FLMODE(1U)
65 
66 #define S_PKTSHIFT    6
67 #define M_PKTSHIFT    0x7
68 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
69 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
70 
71 #define S_ONEINTMULTQ    5
72 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
73 #define F_ONEINTMULTQ    V_ONEINTMULTQ(1U)
74 
75 #define S_FLPICKAVAIL    4
76 #define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL)
77 #define F_FLPICKAVAIL    V_FLPICKAVAIL(1U)
78 
79 #define S_BIGENDIANEGRESS    3
80 #define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS)
81 #define F_BIGENDIANEGRESS    V_BIGENDIANEGRESS(1U)
82 
83 #define S_BIGENDIANINGRESS    2
84 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
85 #define F_BIGENDIANINGRESS    V_BIGENDIANINGRESS(1U)
86 
87 #define S_ISCSICOALESCING    1
88 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
89 #define F_ISCSICOALESCING    V_ISCSICOALESCING(1U)
90 
91 #define S_GLOBALENABLE    0
92 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
93 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
94 
95 #define S_URGTNL    26
96 #define V_URGTNL(x) ((x) << S_URGTNL)
97 #define F_URGTNL    V_URGTNL(1U)
98 
99 #define S_NEWNOTIFY    25
100 #define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY)
101 #define F_NEWNOTIFY    V_NEWNOTIFY(1U)
102 
103 #define S_AVOIDCQOVFL    24
104 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
105 #define F_AVOIDCQOVFL    V_AVOIDCQOVFL(1U)
106 
107 #define S_OPTONEINTMULTQ    23
108 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
109 #define F_OPTONEINTMULTQ    V_OPTONEINTMULTQ(1U)
110 
111 #define S_CQCRDTCTRL    22
112 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
113 #define F_CQCRDTCTRL    V_CQCRDTCTRL(1U)
114 
115 #define A_SG_KDOORBELL 0x4
116 
117 #define S_SELEGRCNTX    31
118 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
119 #define F_SELEGRCNTX    V_SELEGRCNTX(1U)
120 
121 #define S_EGRCNTX    0
122 #define M_EGRCNTX    0xffff
123 #define V_EGRCNTX(x) ((x) << S_EGRCNTX)
124 #define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX)
125 
126 #define A_SG_GTS 0x8
127 
128 #define S_RSPQ    29
129 #define M_RSPQ    0x7
130 #define V_RSPQ(x) ((x) << S_RSPQ)
131 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
132 
133 #define S_NEWTIMER    16
134 #define M_NEWTIMER    0x1fff
135 #define V_NEWTIMER(x) ((x) << S_NEWTIMER)
136 #define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER)
137 
138 #define S_NEWINDEX    0
139 #define M_NEWINDEX    0xffff
140 #define V_NEWINDEX(x) ((x) << S_NEWINDEX)
141 #define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX)
142 
143 #define A_SG_CONTEXT_CMD 0xc
144 
145 #define S_CONTEXT_CMD_OPCODE    28
146 #define M_CONTEXT_CMD_OPCODE    0xf
147 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
148 #define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE)
149 
150 #define S_CONTEXT_CMD_BUSY    27
151 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
152 #define F_CONTEXT_CMD_BUSY    V_CONTEXT_CMD_BUSY(1U)
153 
154 #define S_CQ_CREDIT    20
155 #define M_CQ_CREDIT    0x7f
156 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
157 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
158 
159 #define S_CQ    19
160 #define V_CQ(x) ((x) << S_CQ)
161 #define F_CQ    V_CQ(1U)
162 
163 #define S_RESPONSEQ    18
164 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
165 #define F_RESPONSEQ    V_RESPONSEQ(1U)
166 
167 #define S_EGRESS    17
168 #define V_EGRESS(x) ((x) << S_EGRESS)
169 #define F_EGRESS    V_EGRESS(1U)
170 
171 #define S_FREELIST    16
172 #define V_FREELIST(x) ((x) << S_FREELIST)
173 #define F_FREELIST    V_FREELIST(1U)
174 
175 #define S_CONTEXT    0
176 #define M_CONTEXT    0xffff
177 #define V_CONTEXT(x) ((x) << S_CONTEXT)
178 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
179 
180 #define A_SG_CONTEXT_DATA0 0x10
181 #define A_SG_CONTEXT_DATA1 0x14
182 #define A_SG_CONTEXT_DATA2 0x18
183 #define A_SG_CONTEXT_DATA3 0x1c
184 #define A_SG_CONTEXT_MASK0 0x20
185 #define A_SG_CONTEXT_MASK1 0x24
186 #define A_SG_CONTEXT_MASK2 0x28
187 #define A_SG_CONTEXT_MASK3 0x2c
188 #define A_SG_RSPQ_CREDIT_RETURN 0x30
189 
190 #define S_CREDITS    0
191 #define M_CREDITS    0xffff
192 #define V_CREDITS(x) ((x) << S_CREDITS)
193 #define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS)
194 
195 #define A_SG_DATA_INTR 0x34
196 
197 #define S_ERRINTR    31
198 #define V_ERRINTR(x) ((x) << S_ERRINTR)
199 #define F_ERRINTR    V_ERRINTR(1U)
200 
201 #define S_DATAINTR    0
202 #define M_DATAINTR    0xff
203 #define V_DATAINTR(x) ((x) << S_DATAINTR)
204 #define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR)
205 
206 #define A_SG_HI_DRB_HI_THRSH 0x38
207 
208 #define S_HIDRBHITHRSH    0
209 #define M_HIDRBHITHRSH    0x3ff
210 #define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH)
211 #define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH)
212 
213 #define A_SG_HI_DRB_LO_THRSH 0x3c
214 
215 #define S_HIDRBLOTHRSH    0
216 #define M_HIDRBLOTHRSH    0x3ff
217 #define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH)
218 #define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH)
219 
220 #define A_SG_LO_DRB_HI_THRSH 0x40
221 
222 #define S_LODRBHITHRSH    0
223 #define M_LODRBHITHRSH    0x3ff
224 #define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH)
225 #define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH)
226 
227 #define A_SG_LO_DRB_LO_THRSH 0x44
228 
229 #define S_LODRBLOTHRSH    0
230 #define M_LODRBLOTHRSH    0x3ff
231 #define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH)
232 #define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH)
233 
234 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48
235 #define A_SG_RSPQ_FL_STATUS 0x4c
236 
237 #define S_RSPQ0STARVED    0
238 #define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED)
239 #define F_RSPQ0STARVED    V_RSPQ0STARVED(1U)
240 
241 #define S_RSPQ1STARVED    1
242 #define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED)
243 #define F_RSPQ1STARVED    V_RSPQ1STARVED(1U)
244 
245 #define S_RSPQ2STARVED    2
246 #define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED)
247 #define F_RSPQ2STARVED    V_RSPQ2STARVED(1U)
248 
249 #define S_RSPQ3STARVED    3
250 #define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED)
251 #define F_RSPQ3STARVED    V_RSPQ3STARVED(1U)
252 
253 #define S_RSPQ4STARVED    4
254 #define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED)
255 #define F_RSPQ4STARVED    V_RSPQ4STARVED(1U)
256 
257 #define S_RSPQ5STARVED    5
258 #define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED)
259 #define F_RSPQ5STARVED    V_RSPQ5STARVED(1U)
260 
261 #define S_RSPQ6STARVED    6
262 #define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED)
263 #define F_RSPQ6STARVED    V_RSPQ6STARVED(1U)
264 
265 #define S_RSPQ7STARVED    7
266 #define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED)
267 #define F_RSPQ7STARVED    V_RSPQ7STARVED(1U)
268 
269 #define S_RSPQ0DISABLED    8
270 #define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED)
271 #define F_RSPQ0DISABLED    V_RSPQ0DISABLED(1U)
272 
273 #define S_RSPQ1DISABLED    9
274 #define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED)
275 #define F_RSPQ1DISABLED    V_RSPQ1DISABLED(1U)
276 
277 #define S_RSPQ2DISABLED    10
278 #define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED)
279 #define F_RSPQ2DISABLED    V_RSPQ2DISABLED(1U)
280 
281 #define S_RSPQ3DISABLED    11
282 #define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED)
283 #define F_RSPQ3DISABLED    V_RSPQ3DISABLED(1U)
284 
285 #define S_RSPQ4DISABLED    12
286 #define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED)
287 #define F_RSPQ4DISABLED    V_RSPQ4DISABLED(1U)
288 
289 #define S_RSPQ5DISABLED    13
290 #define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED)
291 #define F_RSPQ5DISABLED    V_RSPQ5DISABLED(1U)
292 
293 #define S_RSPQ6DISABLED    14
294 #define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED)
295 #define F_RSPQ6DISABLED    V_RSPQ6DISABLED(1U)
296 
297 #define S_RSPQ7DISABLED    15
298 #define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED)
299 #define F_RSPQ7DISABLED    V_RSPQ7DISABLED(1U)
300 
301 #define S_FL0EMPTY    16
302 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
303 #define F_FL0EMPTY    V_FL0EMPTY(1U)
304 
305 #define S_FL1EMPTY    17
306 #define V_FL1EMPTY(x) ((x) << S_FL1EMPTY)
307 #define F_FL1EMPTY    V_FL1EMPTY(1U)
308 
309 #define S_FL2EMPTY    18
310 #define V_FL2EMPTY(x) ((x) << S_FL2EMPTY)
311 #define F_FL2EMPTY    V_FL2EMPTY(1U)
312 
313 #define S_FL3EMPTY    19
314 #define V_FL3EMPTY(x) ((x) << S_FL3EMPTY)
315 #define F_FL3EMPTY    V_FL3EMPTY(1U)
316 
317 #define S_FL4EMPTY    20
318 #define V_FL4EMPTY(x) ((x) << S_FL4EMPTY)
319 #define F_FL4EMPTY    V_FL4EMPTY(1U)
320 
321 #define S_FL5EMPTY    21
322 #define V_FL5EMPTY(x) ((x) << S_FL5EMPTY)
323 #define F_FL5EMPTY    V_FL5EMPTY(1U)
324 
325 #define S_FL6EMPTY    22
326 #define V_FL6EMPTY(x) ((x) << S_FL6EMPTY)
327 #define F_FL6EMPTY    V_FL6EMPTY(1U)
328 
329 #define S_FL7EMPTY    23
330 #define V_FL7EMPTY(x) ((x) << S_FL7EMPTY)
331 #define F_FL7EMPTY    V_FL7EMPTY(1U)
332 
333 #define S_FL8EMPTY    24
334 #define V_FL8EMPTY(x) ((x) << S_FL8EMPTY)
335 #define F_FL8EMPTY    V_FL8EMPTY(1U)
336 
337 #define S_FL9EMPTY    25
338 #define V_FL9EMPTY(x) ((x) << S_FL9EMPTY)
339 #define F_FL9EMPTY    V_FL9EMPTY(1U)
340 
341 #define S_FL10EMPTY    26
342 #define V_FL10EMPTY(x) ((x) << S_FL10EMPTY)
343 #define F_FL10EMPTY    V_FL10EMPTY(1U)
344 
345 #define S_FL11EMPTY    27
346 #define V_FL11EMPTY(x) ((x) << S_FL11EMPTY)
347 #define F_FL11EMPTY    V_FL11EMPTY(1U)
348 
349 #define S_FL12EMPTY    28
350 #define V_FL12EMPTY(x) ((x) << S_FL12EMPTY)
351 #define F_FL12EMPTY    V_FL12EMPTY(1U)
352 
353 #define S_FL13EMPTY    29
354 #define V_FL13EMPTY(x) ((x) << S_FL13EMPTY)
355 #define F_FL13EMPTY    V_FL13EMPTY(1U)
356 
357 #define S_FL14EMPTY    30
358 #define V_FL14EMPTY(x) ((x) << S_FL14EMPTY)
359 #define F_FL14EMPTY    V_FL14EMPTY(1U)
360 
361 #define S_FL15EMPTY    31
362 #define V_FL15EMPTY(x) ((x) << S_FL15EMPTY)
363 #define F_FL15EMPTY    V_FL15EMPTY(1U)
364 
365 #define A_SG_EGR_PRI_CNT 0x50
366 
367 #define S_EGRPRICNT    0
368 #define M_EGRPRICNT    0x1f
369 #define V_EGRPRICNT(x) ((x) << S_EGRPRICNT)
370 #define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT)
371 
372 #define S_EGRERROPCODE    24
373 #define M_EGRERROPCODE    0xff
374 #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE)
375 #define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE)
376 
377 #define S_EGRHIOPCODE    16
378 #define M_EGRHIOPCODE    0xff
379 #define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE)
380 #define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE)
381 
382 #define S_EGRLOOPCODE    8
383 #define M_EGRLOOPCODE    0xff
384 #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE)
385 #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE)
386 
387 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
388 
389 #define S_HIRCQDRBTHRSH    16
390 #define M_HIRCQDRBTHRSH    0x7ff
391 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
392 #define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH)
393 
394 #define S_LORCQDRBTHRSH    0
395 #define M_LORCQDRBTHRSH    0x7ff
396 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
397 #define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH)
398 
399 #define A_SG_EGR_CNTX_BADDR 0x58
400 
401 #define S_EGRCNTXBADDR    5
402 #define M_EGRCNTXBADDR    0x7ffffff
403 #define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR)
404 #define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR)
405 
406 #define A_SG_INT_CAUSE 0x5c
407 
408 #define S_HICTLDRBDROPERR    13
409 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
410 #define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)
411 
412 #define S_LOCTLDRBDROPERR    12
413 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
414 #define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)
415 
416 #define S_HIPIODRBDROPERR    11
417 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
418 #define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
419 
420 #define S_LOPIODRBDROPERR    10
421 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
422 #define F_LOPIODRBDROPERR    V_LOPIODRBDROPERR(1U)
423 
424 #define S_HICRDTUNDFLOWERR    9
425 #define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR)
426 #define F_HICRDTUNDFLOWERR    V_HICRDTUNDFLOWERR(1U)
427 
428 #define S_LOCRDTUNDFLOWERR    8
429 #define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR)
430 #define F_LOCRDTUNDFLOWERR    V_LOCRDTUNDFLOWERR(1U)
431 
432 #define S_HIPRIORITYDBFULL    7
433 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
434 #define F_HIPRIORITYDBFULL    V_HIPRIORITYDBFULL(1U)
435 
436 #define S_HIPRIORITYDBEMPTY    6
437 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
438 #define F_HIPRIORITYDBEMPTY    V_HIPRIORITYDBEMPTY(1U)
439 
440 #define S_LOPRIORITYDBFULL    5
441 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
442 #define F_LOPRIORITYDBFULL    V_LOPRIORITYDBFULL(1U)
443 
444 #define S_LOPRIORITYDBEMPTY    4
445 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
446 #define F_LOPRIORITYDBEMPTY    V_LOPRIORITYDBEMPTY(1U)
447 
448 #define S_RSPQDISABLED    3
449 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
450 #define F_RSPQDISABLED    V_RSPQDISABLED(1U)
451 
452 #define S_RSPQCREDITOVERFOW    2
453 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
454 #define F_RSPQCREDITOVERFOW    V_RSPQCREDITOVERFOW(1U)
455 
456 #define S_FLEMPTY    1
457 #define V_FLEMPTY(x) ((x) << S_FLEMPTY)
458 #define F_FLEMPTY    V_FLEMPTY(1U)
459 
460 #define S_RSPQSTARVE    0
461 #define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE)
462 #define F_RSPQSTARVE    V_RSPQSTARVE(1U)
463 
464 #define A_SG_INT_ENABLE 0x60
465 #define A_SG_CMDQ_CREDIT_TH 0x64
466 
467 #define S_TIMEOUT    8
468 #define M_TIMEOUT    0xffffff
469 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
470 #define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT)
471 
472 #define S_THRESHOLD    0
473 #define M_THRESHOLD    0xff
474 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
475 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
476 
477 #define A_SG_TIMER_TICK 0x68
478 #define A_SG_CQ_CONTEXT_BADDR 0x6c
479 
480 #define S_BASEADDR    5
481 #define M_BASEADDR    0x7ffffff
482 #define V_BASEADDR(x) ((x) << S_BASEADDR)
483 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
484 
485 #define A_SG_OCO_BASE 0x70
486 
487 #define S_BASE1    16
488 #define M_BASE1    0xffff
489 #define V_BASE1(x) ((x) << S_BASE1)
490 #define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1)
491 
492 #define S_BASE0    0
493 #define M_BASE0    0xffff
494 #define V_BASE0(x) ((x) << S_BASE0)
495 #define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0)
496 
497 #define A_SG_DRB_PRI_THRESH 0x74
498 
499 #define S_DRBPRITHRSH    0
500 #define M_DRBPRITHRSH    0xffff
501 #define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH)
502 #define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH)
503 
504 #define A_SG_DEBUG_INDEX 0x78
505 #define A_SG_DEBUG_DATA 0x7c
506 
507 /* registers for module PCIX1 */
508 #define PCIX1_BASE_ADDR 0x80
509 
510 #define A_PCIX_INT_ENABLE 0x80
511 
512 #define S_MSIXPARERR    22
513 #define M_MSIXPARERR    0x7
514 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
515 #define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR)
516 
517 #define S_CFPARERR    18
518 #define M_CFPARERR    0xf
519 #define V_CFPARERR(x) ((x) << S_CFPARERR)
520 #define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR)
521 
522 #define S_RFPARERR    14
523 #define M_RFPARERR    0xf
524 #define V_RFPARERR(x) ((x) << S_RFPARERR)
525 #define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR)
526 
527 #define S_WFPARERR    12
528 #define M_WFPARERR    0x3
529 #define V_WFPARERR(x) ((x) << S_WFPARERR)
530 #define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR)
531 
532 #define S_PIOPARERR    11
533 #define V_PIOPARERR(x) ((x) << S_PIOPARERR)
534 #define F_PIOPARERR    V_PIOPARERR(1U)
535 
536 #define S_DETUNCECCERR    10
537 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
538 #define F_DETUNCECCERR    V_DETUNCECCERR(1U)
539 
540 #define S_DETCORECCERR    9
541 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
542 #define F_DETCORECCERR    V_DETCORECCERR(1U)
543 
544 #define S_RCVSPLCMPERR    8
545 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
546 #define F_RCVSPLCMPERR    V_RCVSPLCMPERR(1U)
547 
548 #define S_UNXSPLCMP    7
549 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
550 #define F_UNXSPLCMP    V_UNXSPLCMP(1U)
551 
552 #define S_SPLCMPDIS    6
553 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
554 #define F_SPLCMPDIS    V_SPLCMPDIS(1U)
555 
556 #define S_DETPARERR    5
557 #define V_DETPARERR(x) ((x) << S_DETPARERR)
558 #define F_DETPARERR    V_DETPARERR(1U)
559 
560 #define S_SIGSYSERR    4
561 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
562 #define F_SIGSYSERR    V_SIGSYSERR(1U)
563 
564 #define S_RCVMSTABT    3
565 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
566 #define F_RCVMSTABT    V_RCVMSTABT(1U)
567 
568 #define S_RCVTARABT    2
569 #define V_RCVTARABT(x) ((x) << S_RCVTARABT)
570 #define F_RCVTARABT    V_RCVTARABT(1U)
571 
572 #define S_SIGTARABT    1
573 #define V_SIGTARABT(x) ((x) << S_SIGTARABT)
574 #define F_SIGTARABT    V_SIGTARABT(1U)
575 
576 #define S_MSTDETPARERR    0
577 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
578 #define F_MSTDETPARERR    V_MSTDETPARERR(1U)
579 
580 #define A_PCIX_INT_CAUSE 0x84
581 #define A_PCIX_CFG 0x88
582 
583 #define S_CLIDECEN    18
584 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
585 #define F_CLIDECEN    V_CLIDECEN(1U)
586 
587 #define S_LATTMRDIS    17
588 #define V_LATTMRDIS(x) ((x) << S_LATTMRDIS)
589 #define F_LATTMRDIS    V_LATTMRDIS(1U)
590 
591 #define S_LOWPWREN    16
592 #define V_LOWPWREN(x) ((x) << S_LOWPWREN)
593 #define F_LOWPWREN    V_LOWPWREN(1U)
594 
595 #define S_ASYNCINTVEC    11
596 #define M_ASYNCINTVEC    0x1f
597 #define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC)
598 #define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC)
599 
600 #define S_MAXSPLTRNC    8
601 #define M_MAXSPLTRNC    0x7
602 #define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC)
603 #define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC)
604 
605 #define S_MAXSPLTRNR    5
606 #define M_MAXSPLTRNR    0x7
607 #define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR)
608 #define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR)
609 
610 #define S_MAXWRBYTECNT    3
611 #define M_MAXWRBYTECNT    0x3
612 #define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT)
613 #define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT)
614 
615 #define S_WRREQATOMICEN    2
616 #define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN)
617 #define F_WRREQATOMICEN    V_WRREQATOMICEN(1U)
618 
619 #define S_RSTWRMMODE    1
620 #define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE)
621 #define F_RSTWRMMODE    V_RSTWRMMODE(1U)
622 
623 #define S_PIOACK64EN    0
624 #define V_PIOACK64EN(x) ((x) << S_PIOACK64EN)
625 #define F_PIOACK64EN    V_PIOACK64EN(1U)
626 
627 #define A_PCIX_MODE 0x8c
628 
629 #define S_PCLKRANGE    6
630 #define M_PCLKRANGE    0x3
631 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
632 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
633 
634 #define S_PCIXINITPAT    2
635 #define M_PCIXINITPAT    0xf
636 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
637 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
638 
639 #define S_66MHZ    1
640 #define V_66MHZ(x) ((x) << S_66MHZ)
641 #define F_66MHZ    V_66MHZ(1U)
642 
643 #define S_64BIT    0
644 #define V_64BIT(x) ((x) << S_64BIT)
645 #define F_64BIT    V_64BIT(1U)
646 
647 #define A_PCIX_CAL 0x90
648 
649 #define S_BUSY    31
650 #define V_BUSY(x) ((x) << S_BUSY)
651 #define F_BUSY    V_BUSY(1U)
652 
653 #define S_PERCALDIV    22
654 #define M_PERCALDIV    0xff
655 #define V_PERCALDIV(x) ((x) << S_PERCALDIV)
656 #define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV)
657 
658 #define S_PERCALEN    21
659 #define V_PERCALEN(x) ((x) << S_PERCALEN)
660 #define F_PERCALEN    V_PERCALEN(1U)
661 
662 #define S_SGLCALEN    20
663 #define V_SGLCALEN(x) ((x) << S_SGLCALEN)
664 #define F_SGLCALEN    V_SGLCALEN(1U)
665 
666 #define S_ZINUPDMODE    19
667 #define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE)
668 #define F_ZINUPDMODE    V_ZINUPDMODE(1U)
669 
670 #define S_ZINSEL    18
671 #define V_ZINSEL(x) ((x) << S_ZINSEL)
672 #define F_ZINSEL    V_ZINSEL(1U)
673 
674 #define S_ZPDMAN    15
675 #define M_ZPDMAN    0x7
676 #define V_ZPDMAN(x) ((x) << S_ZPDMAN)
677 #define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN)
678 
679 #define S_ZPUMAN    12
680 #define M_ZPUMAN    0x7
681 #define V_ZPUMAN(x) ((x) << S_ZPUMAN)
682 #define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN)
683 
684 #define S_ZPDOUT    9
685 #define M_ZPDOUT    0x7
686 #define V_ZPDOUT(x) ((x) << S_ZPDOUT)
687 #define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT)
688 
689 #define S_ZPUOUT    6
690 #define M_ZPUOUT    0x7
691 #define V_ZPUOUT(x) ((x) << S_ZPUOUT)
692 #define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT)
693 
694 #define S_ZPDIN    3
695 #define M_ZPDIN    0x7
696 #define V_ZPDIN(x) ((x) << S_ZPDIN)
697 #define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN)
698 
699 #define S_ZPUIN    0
700 #define M_ZPUIN    0x7
701 #define V_ZPUIN(x) ((x) << S_ZPUIN)
702 #define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN)
703 
704 #define A_PCIX_WOL 0x94
705 
706 #define S_WAKEUP1    3
707 #define V_WAKEUP1(x) ((x) << S_WAKEUP1)
708 #define F_WAKEUP1    V_WAKEUP1(1U)
709 
710 #define S_WAKEUP0    2
711 #define V_WAKEUP0(x) ((x) << S_WAKEUP0)
712 #define F_WAKEUP0    V_WAKEUP0(1U)
713 
714 #define S_SLEEPMODE1    1
715 #define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1)
716 #define F_SLEEPMODE1    V_SLEEPMODE1(1U)
717 
718 #define S_SLEEPMODE0    0
719 #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0)
720 #define F_SLEEPMODE0    V_SLEEPMODE0(1U)
721 
722 /* registers for module PCIE0 */
723 #define PCIE0_BASE_ADDR 0x80
724 
725 #define A_PCIE_INT_ENABLE 0x80
726 
727 #define S_BISTERR    15
728 #define M_BISTERR    0xff
729 #define V_BISTERR(x) ((x) << S_BISTERR)
730 #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR)
731 
732 #define S_PCIE_MSIXPARERR    12
733 #define M_PCIE_MSIXPARERR    0x7
734 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
735 #define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR)
736 
737 #define S_PCIE_CFPARERR    11
738 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
739 #define F_PCIE_CFPARERR    V_PCIE_CFPARERR(1U)
740 
741 #define S_PCIE_RFPARERR    10
742 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
743 #define F_PCIE_RFPARERR    V_PCIE_RFPARERR(1U)
744 
745 #define S_PCIE_WFPARERR    9
746 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
747 #define F_PCIE_WFPARERR    V_PCIE_WFPARERR(1U)
748 
749 #define S_PCIE_PIOPARERR    8
750 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
751 #define F_PCIE_PIOPARERR    V_PCIE_PIOPARERR(1U)
752 
753 #define S_UNXSPLCPLERRC    7
754 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
755 #define F_UNXSPLCPLERRC    V_UNXSPLCPLERRC(1U)
756 
757 #define S_UNXSPLCPLERRR    6
758 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
759 #define F_UNXSPLCPLERRR    V_UNXSPLCPLERRR(1U)
760 
761 #define S_VPDADDRCHNG    5
762 #define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG)
763 #define F_VPDADDRCHNG    V_VPDADDRCHNG(1U)
764 
765 #define S_BUSMSTREN    4
766 #define V_BUSMSTREN(x) ((x) << S_BUSMSTREN)
767 #define F_BUSMSTREN    V_BUSMSTREN(1U)
768 
769 #define S_PMSTCHNG    3
770 #define V_PMSTCHNG(x) ((x) << S_PMSTCHNG)
771 #define F_PMSTCHNG    V_PMSTCHNG(1U)
772 
773 #define S_PEXMSG    2
774 #define V_PEXMSG(x) ((x) << S_PEXMSG)
775 #define F_PEXMSG    V_PEXMSG(1U)
776 
777 #define S_ZEROLENRD    1
778 #define V_ZEROLENRD(x) ((x) << S_ZEROLENRD)
779 #define F_ZEROLENRD    V_ZEROLENRD(1U)
780 
781 #define S_PEXERR    0
782 #define V_PEXERR(x) ((x) << S_PEXERR)
783 #define F_PEXERR    V_PEXERR(1U)
784 
785 #define A_PCIE_INT_CAUSE 0x84
786 #define A_PCIE_CFG 0x88
787 
788 #define S_ENABLELINKDWNDRST    21
789 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
790 #define F_ENABLELINKDWNDRST    V_ENABLELINKDWNDRST(1U)
791 
792 #define S_ENABLELINKDOWNRST    20
793 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
794 #define F_ENABLELINKDOWNRST    V_ENABLELINKDOWNRST(1U)
795 
796 #define S_ENABLEHOTRST    19
797 #define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST)
798 #define F_ENABLEHOTRST    V_ENABLEHOTRST(1U)
799 
800 #define S_INIWAITFORGNT    18
801 #define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT)
802 #define F_INIWAITFORGNT    V_INIWAITFORGNT(1U)
803 
804 #define S_INIBEDIS    17
805 #define V_INIBEDIS(x) ((x) << S_INIBEDIS)
806 #define F_INIBEDIS    V_INIBEDIS(1U)
807 
808 #define S_PCIE_CLIDECEN    16
809 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
810 #define F_PCIE_CLIDECEN    V_PCIE_CLIDECEN(1U)
811 
812 #define S_PCIE_MAXSPLTRNC    7
813 #define M_PCIE_MAXSPLTRNC    0xf
814 #define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC)
815 #define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC)
816 
817 #define S_PCIE_MAXSPLTRNR    1
818 #define M_PCIE_MAXSPLTRNR    0x3f
819 #define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR)
820 #define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR)
821 
822 #define S_CRSTWRMMODE    0
823 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
824 #define F_CRSTWRMMODE    V_CRSTWRMMODE(1U)
825 
826 #define S_PRIORITYINTA    23
827 #define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA)
828 #define F_PRIORITYINTA    V_PRIORITYINTA(1U)
829 
830 #define S_INIFULLPKT    22
831 #define V_INIFULLPKT(x) ((x) << S_INIFULLPKT)
832 #define F_INIFULLPKT    V_INIFULLPKT(1U)
833 
834 #define A_PCIE_MODE 0x8c
835 
836 #define S_LNKCNTLSTATE    2
837 #define M_LNKCNTLSTATE    0xff
838 #define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE)
839 #define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE)
840 
841 #define S_VC0UP    1
842 #define V_VC0UP(x) ((x) << S_VC0UP)
843 #define F_VC0UP    V_VC0UP(1U)
844 
845 #define S_LNKINITIAL    0
846 #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL)
847 #define F_LNKINITIAL    V_LNKINITIAL(1U)
848 
849 #define S_NUMFSTTRNSEQRX    10
850 #define M_NUMFSTTRNSEQRX    0xff
851 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
852 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
853 
854 #define A_PCIE_CAL 0x90
855 
856 #define S_CALBUSY    31
857 #define V_CALBUSY(x) ((x) << S_CALBUSY)
858 #define F_CALBUSY    V_CALBUSY(1U)
859 
860 #define S_CALFAULT    30
861 #define V_CALFAULT(x) ((x) << S_CALFAULT)
862 #define F_CALFAULT    V_CALFAULT(1U)
863 
864 #define S_PCIE_ZINSEL    11
865 #define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL)
866 #define F_PCIE_ZINSEL    V_PCIE_ZINSEL(1U)
867 
868 #define S_ZMAN    8
869 #define M_ZMAN    0x7
870 #define V_ZMAN(x) ((x) << S_ZMAN)
871 #define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN)
872 
873 #define S_ZOUT    3
874 #define M_ZOUT    0x1f
875 #define V_ZOUT(x) ((x) << S_ZOUT)
876 #define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT)
877 
878 #define S_ZIN    0
879 #define M_ZIN    0x7
880 #define V_ZIN(x) ((x) << S_ZIN)
881 #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN)
882 
883 #define A_PCIE_WOL 0x94
884 #define A_PCIE_PEX_CTRL0 0x98
885 
886 #define S_NUMFSTTRNSEQ    22
887 #define M_NUMFSTTRNSEQ    0xff
888 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
889 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
890 
891 #define S_REPLAYLMT    2
892 #define M_REPLAYLMT    0xfffff
893 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
894 #define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT)
895 
896 #define S_TXPNDCHKEN    1
897 #define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN)
898 #define F_TXPNDCHKEN    V_TXPNDCHKEN(1U)
899 
900 #define S_CPLPNDCHKEN    0
901 #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN)
902 #define F_CPLPNDCHKEN    V_CPLPNDCHKEN(1U)
903 
904 #define S_CPLTIMEOUTRETRY    31
905 #define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY)
906 #define F_CPLTIMEOUTRETRY    V_CPLTIMEOUTRETRY(1U)
907 
908 #define S_STRICTTSMN    30
909 #define V_STRICTTSMN(x) ((x) << S_STRICTTSMN)
910 #define F_STRICTTSMN    V_STRICTTSMN(1U)
911 
912 #define A_PCIE_PEX_CTRL1 0x9c
913 
914 #define S_T3A_DLLPTIMEOUTLMT    11
915 #define M_T3A_DLLPTIMEOUTLMT    0xfffff
916 #define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT)
917 #define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT)
918 
919 #define S_T3A_ACKLAT    0
920 #define M_T3A_ACKLAT    0x7ff
921 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
922 #define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT)
923 
924 #define S_RXPHYERREN    31
925 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN)
926 #define F_RXPHYERREN    V_RXPHYERREN(1U)
927 
928 #define S_DLLPTIMEOUTLMT    13
929 #define M_DLLPTIMEOUTLMT    0x3ffff
930 #define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT)
931 #define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT)
932 
933 #define S_ACKLAT    0
934 #define M_ACKLAT    0x1fff
935 #define V_ACKLAT(x) ((x) << S_ACKLAT)
936 #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT)
937 
938 #define A_PCIE_PEX_CTRL2 0xa0
939 
940 #define S_PMEXITL1REQ    29
941 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ)
942 #define F_PMEXITL1REQ    V_PMEXITL1REQ(1U)
943 
944 #define S_PMTXIDLE    28
945 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE)
946 #define F_PMTXIDLE    V_PMTXIDLE(1U)
947 
948 #define S_PCIMODELOOP    27
949 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP)
950 #define F_PCIMODELOOP    V_PCIMODELOOP(1U)
951 
952 #define S_L1ASPMTXRXL0STIME    15
953 #define M_L1ASPMTXRXL0STIME    0xfff
954 #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME)
955 #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME)
956 
957 #define S_L0SIDLETIME    4
958 #define M_L0SIDLETIME    0x7ff
959 #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME)
960 #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME)
961 
962 #define S_ENTERL23    3
963 #define V_ENTERL23(x) ((x) << S_ENTERL23)
964 #define F_ENTERL23    V_ENTERL23(1U)
965 
966 #define S_ENTERL1ASPMEN    2
967 #define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN)
968 #define F_ENTERL1ASPMEN    V_ENTERL1ASPMEN(1U)
969 
970 #define S_ENTERL1EN    1
971 #define V_ENTERL1EN(x) ((x) << S_ENTERL1EN)
972 #define F_ENTERL1EN    V_ENTERL1EN(1U)
973 
974 #define S_ENTERL0SEN    0
975 #define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN)
976 #define F_ENTERL0SEN    V_ENTERL0SEN(1U)
977 
978 #define S_LNKCNTLDETDIR    30
979 #define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR)
980 #define F_LNKCNTLDETDIR    V_LNKCNTLDETDIR(1U)
981 
982 #define S_ENTERL1REN    29
983 #define V_ENTERL1REN(x) ((x) << S_ENTERL1REN)
984 #define F_ENTERL1REN    V_ENTERL1REN(1U)
985 
986 #define A_PCIE_PEX_ERR 0xa4
987 
988 #define S_FLOWCTLOFLOWERR    17
989 #define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR)
990 #define F_FLOWCTLOFLOWERR    V_FLOWCTLOFLOWERR(1U)
991 
992 #define S_REPLAYTIMEOUT    16
993 #define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT)
994 #define F_REPLAYTIMEOUT    V_REPLAYTIMEOUT(1U)
995 
996 #define S_REPLAYROLLOVER    15
997 #define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER)
998 #define F_REPLAYROLLOVER    V_REPLAYROLLOVER(1U)
999 
1000 #define S_BADDLLP    14
1001 #define V_BADDLLP(x) ((x) << S_BADDLLP)
1002 #define F_BADDLLP    V_BADDLLP(1U)
1003 
1004 #define S_DLLPERR    13
1005 #define V_DLLPERR(x) ((x) << S_DLLPERR)
1006 #define F_DLLPERR    V_DLLPERR(1U)
1007 
1008 #define S_FLOWCTLPROTERR    12
1009 #define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR)
1010 #define F_FLOWCTLPROTERR    V_FLOWCTLPROTERR(1U)
1011 
1012 #define S_CPLTIMEOUT    11
1013 #define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT)
1014 #define F_CPLTIMEOUT    V_CPLTIMEOUT(1U)
1015 
1016 #define S_PHYRCVERR    10
1017 #define V_PHYRCVERR(x) ((x) << S_PHYRCVERR)
1018 #define F_PHYRCVERR    V_PHYRCVERR(1U)
1019 
1020 #define S_DISTLP    9
1021 #define V_DISTLP(x) ((x) << S_DISTLP)
1022 #define F_DISTLP    V_DISTLP(1U)
1023 
1024 #define S_BADECRC    8
1025 #define V_BADECRC(x) ((x) << S_BADECRC)
1026 #define F_BADECRC    V_BADECRC(1U)
1027 
1028 #define S_BADTLP    7
1029 #define V_BADTLP(x) ((x) << S_BADTLP)
1030 #define F_BADTLP    V_BADTLP(1U)
1031 
1032 #define S_MALTLP    6
1033 #define V_MALTLP(x) ((x) << S_MALTLP)
1034 #define F_MALTLP    V_MALTLP(1U)
1035 
1036 #define S_UNXCPL    5
1037 #define V_UNXCPL(x) ((x) << S_UNXCPL)
1038 #define F_UNXCPL    V_UNXCPL(1U)
1039 
1040 #define S_UNSREQ    4
1041 #define V_UNSREQ(x) ((x) << S_UNSREQ)
1042 #define F_UNSREQ    V_UNSREQ(1U)
1043 
1044 #define S_PSNREQ    3
1045 #define V_PSNREQ(x) ((x) << S_PSNREQ)
1046 #define F_PSNREQ    V_PSNREQ(1U)
1047 
1048 #define S_UNSCPL    2
1049 #define V_UNSCPL(x) ((x) << S_UNSCPL)
1050 #define F_UNSCPL    V_UNSCPL(1U)
1051 
1052 #define S_CPLABT    1
1053 #define V_CPLABT(x) ((x) << S_CPLABT)
1054 #define F_CPLABT    V_CPLABT(1U)
1055 
1056 #define S_PSNCPL    0
1057 #define V_PSNCPL(x) ((x) << S_PSNCPL)
1058 #define F_PSNCPL    V_PSNCPL(1U)
1059 
1060 #define S_CPLTIMEOUTID    18
1061 #define M_CPLTIMEOUTID    0x7f
1062 #define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID)
1063 #define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID)
1064 
1065 #define A_PCIE_PIPE_CTRL 0xa8
1066 
1067 #define S_RECDETUSEC    19
1068 #define M_RECDETUSEC    0x7
1069 #define V_RECDETUSEC(x) ((x) << S_RECDETUSEC)
1070 #define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC)
1071 
1072 #define S_PLLLCKCYC    6
1073 #define M_PLLLCKCYC    0x1fff
1074 #define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC)
1075 #define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC)
1076 
1077 #define S_ELECIDLEDETCYC    3
1078 #define M_ELECIDLEDETCYC    0x7
1079 #define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC)
1080 #define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC)
1081 
1082 #define S_USECDRLOS    2
1083 #define V_USECDRLOS(x) ((x) << S_USECDRLOS)
1084 #define F_USECDRLOS    V_USECDRLOS(1U)
1085 
1086 #define S_PCLKREQINP1    1
1087 #define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1)
1088 #define F_PCLKREQINP1    V_PCLKREQINP1(1U)
1089 
1090 #define S_PCLKOFFINP1    0
1091 #define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1)
1092 #define F_PCLKOFFINP1    V_PCLKOFFINP1(1U)
1093 
1094 #define S_PMASEL    3
1095 #define V_PMASEL(x) ((x) << S_PMASEL)
1096 #define F_PMASEL    V_PMASEL(1U)
1097 
1098 #define S_LANE    0
1099 #define M_LANE    0x7
1100 #define V_LANE(x) ((x) << S_LANE)
1101 #define G_LANE(x) (((x) >> S_LANE) & M_LANE)
1102 
1103 #define A_PCIE_SERDES_CTRL 0xac
1104 
1105 #define S_MANMODE    31
1106 #define V_MANMODE(x) ((x) << S_MANMODE)
1107 #define F_MANMODE    V_MANMODE(1U)
1108 
1109 #define S_MANLPBKEN    29
1110 #define M_MANLPBKEN    0x3
1111 #define V_MANLPBKEN(x) ((x) << S_MANLPBKEN)
1112 #define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN)
1113 
1114 #define S_MANTXRECDETEN    28
1115 #define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN)
1116 #define F_MANTXRECDETEN    V_MANTXRECDETEN(1U)
1117 
1118 #define S_MANTXBEACON    27
1119 #define V_MANTXBEACON(x) ((x) << S_MANTXBEACON)
1120 #define F_MANTXBEACON    V_MANTXBEACON(1U)
1121 
1122 #define S_MANTXEI    26
1123 #define V_MANTXEI(x) ((x) << S_MANTXEI)
1124 #define F_MANTXEI    V_MANTXEI(1U)
1125 
1126 #define S_MANRXPOLARITY    25
1127 #define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY)
1128 #define F_MANRXPOLARITY    V_MANRXPOLARITY(1U)
1129 
1130 #define S_MANTXRST    24
1131 #define V_MANTXRST(x) ((x) << S_MANTXRST)
1132 #define F_MANTXRST    V_MANTXRST(1U)
1133 
1134 #define S_MANRXRST    23
1135 #define V_MANRXRST(x) ((x) << S_MANRXRST)
1136 #define F_MANRXRST    V_MANRXRST(1U)
1137 
1138 #define S_MANTXEN    22
1139 #define V_MANTXEN(x) ((x) << S_MANTXEN)
1140 #define F_MANTXEN    V_MANTXEN(1U)
1141 
1142 #define S_MANRXEN    21
1143 #define V_MANRXEN(x) ((x) << S_MANRXEN)
1144 #define F_MANRXEN    V_MANRXEN(1U)
1145 
1146 #define S_MANEN    20
1147 #define V_MANEN(x) ((x) << S_MANEN)
1148 #define F_MANEN    V_MANEN(1U)
1149 
1150 #define S_PCIE_CMURANGE    17
1151 #define M_PCIE_CMURANGE    0x7
1152 #define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE)
1153 #define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE)
1154 
1155 #define S_PCIE_BGENB    16
1156 #define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB)
1157 #define F_PCIE_BGENB    V_PCIE_BGENB(1U)
1158 
1159 #define S_PCIE_ENSKPDROP    15
1160 #define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP)
1161 #define F_PCIE_ENSKPDROP    V_PCIE_ENSKPDROP(1U)
1162 
1163 #define S_PCIE_ENCOMMA    14
1164 #define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA)
1165 #define F_PCIE_ENCOMMA    V_PCIE_ENCOMMA(1U)
1166 
1167 #define S_PCIE_EN8B10B    13
1168 #define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B)
1169 #define F_PCIE_EN8B10B    V_PCIE_EN8B10B(1U)
1170 
1171 #define S_PCIE_ENELBUF    12
1172 #define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF)
1173 #define F_PCIE_ENELBUF    V_PCIE_ENELBUF(1U)
1174 
1175 #define S_PCIE_GAIN    7
1176 #define M_PCIE_GAIN    0x1f
1177 #define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN)
1178 #define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN)
1179 
1180 #define S_PCIE_BANDGAP    3
1181 #define M_PCIE_BANDGAP    0xf
1182 #define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP)
1183 #define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP)
1184 
1185 #define S_RXCOMADJ    2
1186 #define V_RXCOMADJ(x) ((x) << S_RXCOMADJ)
1187 #define F_RXCOMADJ    V_RXCOMADJ(1U)
1188 
1189 #define S_PREEMPH    0
1190 #define M_PREEMPH    0x3
1191 #define V_PREEMPH(x) ((x) << S_PREEMPH)
1192 #define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH)
1193 
1194 #define A_PCIE_SERDES_QUAD_CTRL0 0xac
1195 
1196 #define S_TESTSIG    10
1197 #define M_TESTSIG    0x7ffff
1198 #define V_TESTSIG(x) ((x) << S_TESTSIG)
1199 #define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG)
1200 
1201 #define S_OFFSET    2
1202 #define M_OFFSET    0xff
1203 #define V_OFFSET(x) ((x) << S_OFFSET)
1204 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
1205 
1206 #define S_OFFSETEN    1
1207 #define V_OFFSETEN(x) ((x) << S_OFFSETEN)
1208 #define F_OFFSETEN    V_OFFSETEN(1U)
1209 
1210 #define S_IDDQB    0
1211 #define V_IDDQB(x) ((x) << S_IDDQB)
1212 #define F_IDDQB    V_IDDQB(1U)
1213 
1214 #define A_PCIE_SERDES_STATUS0 0xb0
1215 
1216 #define S_RXERRLANE7    21
1217 #define M_RXERRLANE7    0x7
1218 #define V_RXERRLANE7(x) ((x) << S_RXERRLANE7)
1219 #define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7)
1220 
1221 #define S_RXERRLANE6    18
1222 #define M_RXERRLANE6    0x7
1223 #define V_RXERRLANE6(x) ((x) << S_RXERRLANE6)
1224 #define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6)
1225 
1226 #define S_RXERRLANE5    15
1227 #define M_RXERRLANE5    0x7
1228 #define V_RXERRLANE5(x) ((x) << S_RXERRLANE5)
1229 #define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5)
1230 
1231 #define S_RXERRLANE4    12
1232 #define M_RXERRLANE4    0x7
1233 #define V_RXERRLANE4(x) ((x) << S_RXERRLANE4)
1234 #define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4)
1235 
1236 #define S_PCIE_RXERRLANE3    9
1237 #define M_PCIE_RXERRLANE3    0x7
1238 #define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3)
1239 #define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3)
1240 
1241 #define S_PCIE_RXERRLANE2    6
1242 #define M_PCIE_RXERRLANE2    0x7
1243 #define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2)
1244 #define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2)
1245 
1246 #define S_PCIE_RXERRLANE1    3
1247 #define M_PCIE_RXERRLANE1    0x7
1248 #define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1)
1249 #define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1)
1250 
1251 #define S_PCIE_RXERRLANE0    0
1252 #define M_PCIE_RXERRLANE0    0x7
1253 #define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0)
1254 #define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0)
1255 
1256 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0
1257 
1258 #define S_FASTINIT    28
1259 #define V_FASTINIT(x) ((x) << S_FASTINIT)
1260 #define F_FASTINIT    V_FASTINIT(1U)
1261 
1262 #define S_CTCDISABLE    27
1263 #define V_CTCDISABLE(x) ((x) << S_CTCDISABLE)
1264 #define F_CTCDISABLE    V_CTCDISABLE(1U)
1265 
1266 #define S_MANRESETPLL    26
1267 #define V_MANRESETPLL(x) ((x) << S_MANRESETPLL)
1268 #define F_MANRESETPLL    V_MANRESETPLL(1U)
1269 
1270 #define S_MANL2PWRDN    25
1271 #define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN)
1272 #define F_MANL2PWRDN    V_MANL2PWRDN(1U)
1273 
1274 #define S_MANQUADEN    24
1275 #define V_MANQUADEN(x) ((x) << S_MANQUADEN)
1276 #define F_MANQUADEN    V_MANQUADEN(1U)
1277 
1278 #define S_RXEQCTL    22
1279 #define M_RXEQCTL    0x3
1280 #define V_RXEQCTL(x) ((x) << S_RXEQCTL)
1281 #define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL)
1282 
1283 #define S_HIVMODE    21
1284 #define V_HIVMODE(x) ((x) << S_HIVMODE)
1285 #define F_HIVMODE    V_HIVMODE(1U)
1286 
1287 #define S_REFSEL    19
1288 #define M_REFSEL    0x3
1289 #define V_REFSEL(x) ((x) << S_REFSEL)
1290 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
1291 
1292 #define S_RXTERMADJ    17
1293 #define M_RXTERMADJ    0x3
1294 #define V_RXTERMADJ(x) ((x) << S_RXTERMADJ)
1295 #define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ)
1296 
1297 #define S_TXTERMADJ    15
1298 #define M_TXTERMADJ    0x3
1299 #define V_TXTERMADJ(x) ((x) << S_TXTERMADJ)
1300 #define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ)
1301 
1302 #define S_DEQ    11
1303 #define M_DEQ    0xf
1304 #define V_DEQ(x) ((x) << S_DEQ)
1305 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
1306 
1307 #define S_DTX    7
1308 #define M_DTX    0xf
1309 #define V_DTX(x) ((x) << S_DTX)
1310 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
1311 
1312 #define S_LODRV    6
1313 #define V_LODRV(x) ((x) << S_LODRV)
1314 #define F_LODRV    V_LODRV(1U)
1315 
1316 #define S_HIDRV    5
1317 #define V_HIDRV(x) ((x) << S_HIDRV)
1318 #define F_HIDRV    V_HIDRV(1U)
1319 
1320 #define S_INTPARRESET    4
1321 #define V_INTPARRESET(x) ((x) << S_INTPARRESET)
1322 #define F_INTPARRESET    V_INTPARRESET(1U)
1323 
1324 #define S_INTPARLPBK    3
1325 #define V_INTPARLPBK(x) ((x) << S_INTPARLPBK)
1326 #define F_INTPARLPBK    V_INTPARLPBK(1U)
1327 
1328 #define S_INTSERLPBKWDRV    2
1329 #define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV)
1330 #define F_INTSERLPBKWDRV    V_INTSERLPBKWDRV(1U)
1331 
1332 #define S_PW    1
1333 #define V_PW(x) ((x) << S_PW)
1334 #define F_PW    V_PW(1U)
1335 
1336 #define S_PCLKDETECT    0
1337 #define V_PCLKDETECT(x) ((x) << S_PCLKDETECT)
1338 #define F_PCLKDETECT    V_PCLKDETECT(1U)
1339 
1340 #define A_PCIE_SERDES_STATUS1 0xb4
1341 
1342 #define S_CMULOCK    31
1343 #define V_CMULOCK(x) ((x) << S_CMULOCK)
1344 #define F_CMULOCK    V_CMULOCK(1U)
1345 
1346 #define S_RXKLOCKLANE7    23
1347 #define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7)
1348 #define F_RXKLOCKLANE7    V_RXKLOCKLANE7(1U)
1349 
1350 #define S_RXKLOCKLANE6    22
1351 #define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6)
1352 #define F_RXKLOCKLANE6    V_RXKLOCKLANE6(1U)
1353 
1354 #define S_RXKLOCKLANE5    21
1355 #define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5)
1356 #define F_RXKLOCKLANE5    V_RXKLOCKLANE5(1U)
1357 
1358 #define S_RXKLOCKLANE4    20
1359 #define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4)
1360 #define F_RXKLOCKLANE4    V_RXKLOCKLANE4(1U)
1361 
1362 #define S_PCIE_RXKLOCKLANE3    19
1363 #define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3)
1364 #define F_PCIE_RXKLOCKLANE3    V_PCIE_RXKLOCKLANE3(1U)
1365 
1366 #define S_PCIE_RXKLOCKLANE2    18
1367 #define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2)
1368 #define F_PCIE_RXKLOCKLANE2    V_PCIE_RXKLOCKLANE2(1U)
1369 
1370 #define S_PCIE_RXKLOCKLANE1    17
1371 #define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1)
1372 #define F_PCIE_RXKLOCKLANE1    V_PCIE_RXKLOCKLANE1(1U)
1373 
1374 #define S_PCIE_RXKLOCKLANE0    16
1375 #define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0)
1376 #define F_PCIE_RXKLOCKLANE0    V_PCIE_RXKLOCKLANE0(1U)
1377 
1378 #define S_RXUFLOWLANE7    15
1379 #define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7)
1380 #define F_RXUFLOWLANE7    V_RXUFLOWLANE7(1U)
1381 
1382 #define S_RXUFLOWLANE6    14
1383 #define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6)
1384 #define F_RXUFLOWLANE6    V_RXUFLOWLANE6(1U)
1385 
1386 #define S_RXUFLOWLANE5    13
1387 #define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5)
1388 #define F_RXUFLOWLANE5    V_RXUFLOWLANE5(1U)
1389 
1390 #define S_RXUFLOWLANE4    12
1391 #define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4)
1392 #define F_RXUFLOWLANE4    V_RXUFLOWLANE4(1U)
1393 
1394 #define S_PCIE_RXUFLOWLANE3    11
1395 #define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3)
1396 #define F_PCIE_RXUFLOWLANE3    V_PCIE_RXUFLOWLANE3(1U)
1397 
1398 #define S_PCIE_RXUFLOWLANE2    10
1399 #define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2)
1400 #define F_PCIE_RXUFLOWLANE2    V_PCIE_RXUFLOWLANE2(1U)
1401 
1402 #define S_PCIE_RXUFLOWLANE1    9
1403 #define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1)
1404 #define F_PCIE_RXUFLOWLANE1    V_PCIE_RXUFLOWLANE1(1U)
1405 
1406 #define S_PCIE_RXUFLOWLANE0    8
1407 #define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0)
1408 #define F_PCIE_RXUFLOWLANE0    V_PCIE_RXUFLOWLANE0(1U)
1409 
1410 #define S_RXOFLOWLANE7    7
1411 #define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7)
1412 #define F_RXOFLOWLANE7    V_RXOFLOWLANE7(1U)
1413 
1414 #define S_RXOFLOWLANE6    6
1415 #define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6)
1416 #define F_RXOFLOWLANE6    V_RXOFLOWLANE6(1U)
1417 
1418 #define S_RXOFLOWLANE5    5
1419 #define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5)
1420 #define F_RXOFLOWLANE5    V_RXOFLOWLANE5(1U)
1421 
1422 #define S_RXOFLOWLANE4    4
1423 #define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4)
1424 #define F_RXOFLOWLANE4    V_RXOFLOWLANE4(1U)
1425 
1426 #define S_PCIE_RXOFLOWLANE3    3
1427 #define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3)
1428 #define F_PCIE_RXOFLOWLANE3    V_PCIE_RXOFLOWLANE3(1U)
1429 
1430 #define S_PCIE_RXOFLOWLANE2    2
1431 #define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2)
1432 #define F_PCIE_RXOFLOWLANE2    V_PCIE_RXOFLOWLANE2(1U)
1433 
1434 #define S_PCIE_RXOFLOWLANE1    1
1435 #define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1)
1436 #define F_PCIE_RXOFLOWLANE1    V_PCIE_RXOFLOWLANE1(1U)
1437 
1438 #define S_PCIE_RXOFLOWLANE0    0
1439 #define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0)
1440 #define F_PCIE_RXOFLOWLANE0    V_PCIE_RXOFLOWLANE0(1U)
1441 
1442 #define A_PCIE_SERDES_LANE_CTRL 0xb4
1443 
1444 #define S_EXTBISTCHKERRCLR    22
1445 #define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR)
1446 #define F_EXTBISTCHKERRCLR    V_EXTBISTCHKERRCLR(1U)
1447 
1448 #define S_EXTBISTCHKEN    21
1449 #define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN)
1450 #define F_EXTBISTCHKEN    V_EXTBISTCHKEN(1U)
1451 
1452 #define S_EXTBISTGENEN    20
1453 #define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN)
1454 #define F_EXTBISTGENEN    V_EXTBISTGENEN(1U)
1455 
1456 #define S_EXTBISTPAT    17
1457 #define M_EXTBISTPAT    0x7
1458 #define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT)
1459 #define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT)
1460 
1461 #define S_EXTPARRESET    16
1462 #define V_EXTPARRESET(x) ((x) << S_EXTPARRESET)
1463 #define F_EXTPARRESET    V_EXTPARRESET(1U)
1464 
1465 #define S_EXTPARLPBK    15
1466 #define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK)
1467 #define F_EXTPARLPBK    V_EXTPARLPBK(1U)
1468 
1469 #define S_MANRXTERMEN    14
1470 #define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN)
1471 #define F_MANRXTERMEN    V_MANRXTERMEN(1U)
1472 
1473 #define S_MANBEACONTXEN    13
1474 #define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN)
1475 #define F_MANBEACONTXEN    V_MANBEACONTXEN(1U)
1476 
1477 #define S_MANRXDETECTEN    12
1478 #define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN)
1479 #define F_MANRXDETECTEN    V_MANRXDETECTEN(1U)
1480 
1481 #define S_MANTXIDLEEN    11
1482 #define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN)
1483 #define F_MANTXIDLEEN    V_MANTXIDLEEN(1U)
1484 
1485 #define S_MANRXIDLEEN    10
1486 #define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN)
1487 #define F_MANRXIDLEEN    V_MANRXIDLEEN(1U)
1488 
1489 #define S_MANL1PWRDN    9
1490 #define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN)
1491 #define F_MANL1PWRDN    V_MANL1PWRDN(1U)
1492 
1493 #define S_MANRESET    8
1494 #define V_MANRESET(x) ((x) << S_MANRESET)
1495 #define F_MANRESET    V_MANRESET(1U)
1496 
1497 #define S_MANFMOFFSET    3
1498 #define M_MANFMOFFSET    0x1f
1499 #define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET)
1500 #define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET)
1501 
1502 #define S_MANFMOFFSETEN    2
1503 #define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN)
1504 #define F_MANFMOFFSETEN    V_MANFMOFFSETEN(1U)
1505 
1506 #define S_MANLANEEN    1
1507 #define V_MANLANEEN(x) ((x) << S_MANLANEEN)
1508 #define F_MANLANEEN    V_MANLANEEN(1U)
1509 
1510 #define S_INTSERLPBK    0
1511 #define V_INTSERLPBK(x) ((x) << S_INTSERLPBK)
1512 #define F_INTSERLPBK    V_INTSERLPBK(1U)
1513 
1514 #define A_PCIE_SERDES_STATUS2 0xb8
1515 
1516 #define S_TXRECDETLANE7    31
1517 #define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7)
1518 #define F_TXRECDETLANE7    V_TXRECDETLANE7(1U)
1519 
1520 #define S_TXRECDETLANE6    30
1521 #define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6)
1522 #define F_TXRECDETLANE6    V_TXRECDETLANE6(1U)
1523 
1524 #define S_TXRECDETLANE5    29
1525 #define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5)
1526 #define F_TXRECDETLANE5    V_TXRECDETLANE5(1U)
1527 
1528 #define S_TXRECDETLANE4    28
1529 #define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4)
1530 #define F_TXRECDETLANE4    V_TXRECDETLANE4(1U)
1531 
1532 #define S_TXRECDETLANE3    27
1533 #define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3)
1534 #define F_TXRECDETLANE3    V_TXRECDETLANE3(1U)
1535 
1536 #define S_TXRECDETLANE2    26
1537 #define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2)
1538 #define F_TXRECDETLANE2    V_TXRECDETLANE2(1U)
1539 
1540 #define S_TXRECDETLANE1    25
1541 #define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1)
1542 #define F_TXRECDETLANE1    V_TXRECDETLANE1(1U)
1543 
1544 #define S_TXRECDETLANE0    24
1545 #define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0)
1546 #define F_TXRECDETLANE0    V_TXRECDETLANE0(1U)
1547 
1548 #define S_RXEIDLANE7    23
1549 #define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7)
1550 #define F_RXEIDLANE7    V_RXEIDLANE7(1U)
1551 
1552 #define S_RXEIDLANE6    22
1553 #define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6)
1554 #define F_RXEIDLANE6    V_RXEIDLANE6(1U)
1555 
1556 #define S_RXEIDLANE5    21
1557 #define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5)
1558 #define F_RXEIDLANE5    V_RXEIDLANE5(1U)
1559 
1560 #define S_RXEIDLANE4    20
1561 #define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4)
1562 #define F_RXEIDLANE4    V_RXEIDLANE4(1U)
1563 
1564 #define S_RXEIDLANE3    19
1565 #define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3)
1566 #define F_RXEIDLANE3    V_RXEIDLANE3(1U)
1567 
1568 #define S_RXEIDLANE2    18
1569 #define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2)
1570 #define F_RXEIDLANE2    V_RXEIDLANE2(1U)
1571 
1572 #define S_RXEIDLANE1    17
1573 #define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1)
1574 #define F_RXEIDLANE1    V_RXEIDLANE1(1U)
1575 
1576 #define S_RXEIDLANE0    16
1577 #define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0)
1578 #define F_RXEIDLANE0    V_RXEIDLANE0(1U)
1579 
1580 #define S_RXREMSKIPLANE7    15
1581 #define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7)
1582 #define F_RXREMSKIPLANE7    V_RXREMSKIPLANE7(1U)
1583 
1584 #define S_RXREMSKIPLANE6    14
1585 #define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6)
1586 #define F_RXREMSKIPLANE6    V_RXREMSKIPLANE6(1U)
1587 
1588 #define S_RXREMSKIPLANE5    13
1589 #define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5)
1590 #define F_RXREMSKIPLANE5    V_RXREMSKIPLANE5(1U)
1591 
1592 #define S_RXREMSKIPLANE4    12
1593 #define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4)
1594 #define F_RXREMSKIPLANE4    V_RXREMSKIPLANE4(1U)
1595 
1596 #define S_PCIE_RXREMSKIPLANE3    11
1597 #define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3)
1598 #define F_PCIE_RXREMSKIPLANE3    V_PCIE_RXREMSKIPLANE3(1U)
1599 
1600 #define S_PCIE_RXREMSKIPLANE2    10
1601 #define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2)
1602 #define F_PCIE_RXREMSKIPLANE2    V_PCIE_RXREMSKIPLANE2(1U)
1603 
1604 #define S_PCIE_RXREMSKIPLANE1    9
1605 #define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1)
1606 #define F_PCIE_RXREMSKIPLANE1    V_PCIE_RXREMSKIPLANE1(1U)
1607 
1608 #define S_PCIE_RXREMSKIPLANE0    8
1609 #define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0)
1610 #define F_PCIE_RXREMSKIPLANE0    V_PCIE_RXREMSKIPLANE0(1U)
1611 
1612 #define S_RXADDSKIPLANE7    7
1613 #define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7)
1614 #define F_RXADDSKIPLANE7    V_RXADDSKIPLANE7(1U)
1615 
1616 #define S_RXADDSKIPLANE6    6
1617 #define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6)
1618 #define F_RXADDSKIPLANE6    V_RXADDSKIPLANE6(1U)
1619 
1620 #define S_RXADDSKIPLANE5    5
1621 #define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5)
1622 #define F_RXADDSKIPLANE5    V_RXADDSKIPLANE5(1U)
1623 
1624 #define S_RXADDSKIPLANE4    4
1625 #define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4)
1626 #define F_RXADDSKIPLANE4    V_RXADDSKIPLANE4(1U)
1627 
1628 #define S_PCIE_RXADDSKIPLANE3    3
1629 #define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3)
1630 #define F_PCIE_RXADDSKIPLANE3    V_PCIE_RXADDSKIPLANE3(1U)
1631 
1632 #define S_PCIE_RXADDSKIPLANE2    2
1633 #define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2)
1634 #define F_PCIE_RXADDSKIPLANE2    V_PCIE_RXADDSKIPLANE2(1U)
1635 
1636 #define S_PCIE_RXADDSKIPLANE1    1
1637 #define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1)
1638 #define F_PCIE_RXADDSKIPLANE1    V_PCIE_RXADDSKIPLANE1(1U)
1639 
1640 #define S_PCIE_RXADDSKIPLANE0    0
1641 #define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0)
1642 #define F_PCIE_RXADDSKIPLANE0    V_PCIE_RXADDSKIPLANE0(1U)
1643 
1644 #define A_PCIE_SERDES_LANE_STAT 0xb8
1645 
1646 #define S_EXTBISTCHKERRCNT    8
1647 #define M_EXTBISTCHKERRCNT    0xffffff
1648 #define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT)
1649 #define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT)
1650 
1651 #define S_EXTBISTCHKFMD    7
1652 #define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD)
1653 #define F_EXTBISTCHKFMD    V_EXTBISTCHKFMD(1U)
1654 
1655 #define S_BEACONDETECTCHG    6
1656 #define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG)
1657 #define F_BEACONDETECTCHG    V_BEACONDETECTCHG(1U)
1658 
1659 #define S_RXDETECTCHG    5
1660 #define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG)
1661 #define F_RXDETECTCHG    V_RXDETECTCHG(1U)
1662 
1663 #define S_TXIDLEDETECTCHG    4
1664 #define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG)
1665 #define F_TXIDLEDETECTCHG    V_TXIDLEDETECTCHG(1U)
1666 
1667 #define S_BEACONDETECT    2
1668 #define V_BEACONDETECT(x) ((x) << S_BEACONDETECT)
1669 #define F_BEACONDETECT    V_BEACONDETECT(1U)
1670 
1671 #define S_RXDETECT    1
1672 #define V_RXDETECT(x) ((x) << S_RXDETECT)
1673 #define F_RXDETECT    V_RXDETECT(1U)
1674 
1675 #define S_TXIDLEDETECT    0
1676 #define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT)
1677 #define F_TXIDLEDETECT    V_TXIDLEDETECT(1U)
1678 
1679 #define A_PCIE_SERDES_BIST 0xbc
1680 
1681 #define S_PCIE_BISTDONE    24
1682 #define M_PCIE_BISTDONE    0xff
1683 #define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE)
1684 #define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE)
1685 
1686 #define S_PCIE_BISTCYCLETHRESH    3
1687 #define M_PCIE_BISTCYCLETHRESH    0xffff
1688 #define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH)
1689 #define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH)
1690 
1691 #define S_BISTMODE    0
1692 #define M_BISTMODE    0x7
1693 #define V_BISTMODE(x) ((x) << S_BISTMODE)
1694 #define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE)
1695 
1696 /* registers for module T3DBG */
1697 #define T3DBG_BASE_ADDR 0xc0
1698 
1699 #define A_T3DBG_DBG0_CFG 0xc0
1700 
1701 #define S_REGSELECT    9
1702 #define M_REGSELECT    0xff
1703 #define V_REGSELECT(x) ((x) << S_REGSELECT)
1704 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
1705 
1706 #define S_MODULESELECT    4
1707 #define M_MODULESELECT    0x1f
1708 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
1709 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
1710 
1711 #define S_CLKSELECT    0
1712 #define M_CLKSELECT    0xf
1713 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
1714 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
1715 
1716 #define A_T3DBG_DBG0_EN 0xc4
1717 
1718 #define S_SDRBYTE0    8
1719 #define V_SDRBYTE0(x) ((x) << S_SDRBYTE0)
1720 #define F_SDRBYTE0    V_SDRBYTE0(1U)
1721 
1722 #define S_DDREN    4
1723 #define V_DDREN(x) ((x) << S_DDREN)
1724 #define F_DDREN    V_DDREN(1U)
1725 
1726 #define S_PORTEN    0
1727 #define V_PORTEN(x) ((x) << S_PORTEN)
1728 #define F_PORTEN    V_PORTEN(1U)
1729 
1730 #define A_T3DBG_DBG1_CFG 0xc8
1731 #define A_T3DBG_DBG1_EN 0xcc
1732 #define A_T3DBG_GPIO_EN 0xd0
1733 
1734 #define S_GPIO11_OEN    27
1735 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
1736 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
1737 
1738 #define S_GPIO10_OEN    26
1739 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
1740 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
1741 
1742 #define S_GPIO9_OEN    25
1743 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
1744 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
1745 
1746 #define S_GPIO8_OEN    24
1747 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
1748 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
1749 
1750 #define S_GPIO7_OEN    23
1751 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
1752 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
1753 
1754 #define S_GPIO6_OEN    22
1755 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
1756 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
1757 
1758 #define S_GPIO5_OEN    21
1759 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
1760 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
1761 
1762 #define S_GPIO4_OEN    20
1763 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
1764 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
1765 
1766 #define S_GPIO3_OEN    19
1767 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
1768 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
1769 
1770 #define S_GPIO2_OEN    18
1771 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
1772 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
1773 
1774 #define S_GPIO1_OEN    17
1775 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
1776 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
1777 
1778 #define S_GPIO0_OEN    16
1779 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
1780 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
1781 
1782 #define S_GPIO11_OUT_VAL    11
1783 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
1784 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
1785 
1786 #define S_GPIO10_OUT_VAL    10
1787 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
1788 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
1789 
1790 #define S_GPIO9_OUT_VAL    9
1791 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
1792 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
1793 
1794 #define S_GPIO8_OUT_VAL    8
1795 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
1796 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
1797 
1798 #define S_GPIO7_OUT_VAL    7
1799 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
1800 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
1801 
1802 #define S_GPIO6_OUT_VAL    6
1803 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
1804 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
1805 
1806 #define S_GPIO5_OUT_VAL    5
1807 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
1808 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
1809 
1810 #define S_GPIO4_OUT_VAL    4
1811 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
1812 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
1813 
1814 #define S_GPIO3_OUT_VAL    3
1815 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
1816 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
1817 
1818 #define S_GPIO2_OUT_VAL    2
1819 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
1820 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
1821 
1822 #define S_GPIO1_OUT_VAL    1
1823 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
1824 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
1825 
1826 #define S_GPIO0_OUT_VAL    0
1827 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
1828 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
1829 
1830 #define A_T3DBG_GPIO_IN 0xd4
1831 
1832 #define S_GPIO11_IN    11
1833 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
1834 #define F_GPIO11_IN    V_GPIO11_IN(1U)
1835 
1836 #define S_GPIO10_IN    10
1837 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
1838 #define F_GPIO10_IN    V_GPIO10_IN(1U)
1839 
1840 #define S_GPIO9_IN    9
1841 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
1842 #define F_GPIO9_IN    V_GPIO9_IN(1U)
1843 
1844 #define S_GPIO8_IN    8
1845 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
1846 #define F_GPIO8_IN    V_GPIO8_IN(1U)
1847 
1848 #define S_GPIO7_IN    7
1849 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
1850 #define F_GPIO7_IN    V_GPIO7_IN(1U)
1851 
1852 #define S_GPIO6_IN    6
1853 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
1854 #define F_GPIO6_IN    V_GPIO6_IN(1U)
1855 
1856 #define S_GPIO5_IN    5
1857 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
1858 #define F_GPIO5_IN    V_GPIO5_IN(1U)
1859 
1860 #define S_GPIO4_IN    4
1861 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
1862 #define F_GPIO4_IN    V_GPIO4_IN(1U)
1863 
1864 #define S_GPIO3_IN    3
1865 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
1866 #define F_GPIO3_IN    V_GPIO3_IN(1U)
1867 
1868 #define S_GPIO2_IN    2
1869 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
1870 #define F_GPIO2_IN    V_GPIO2_IN(1U)
1871 
1872 #define S_GPIO1_IN    1
1873 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
1874 #define F_GPIO1_IN    V_GPIO1_IN(1U)
1875 
1876 #define S_GPIO0_IN    0
1877 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
1878 #define F_GPIO0_IN    V_GPIO0_IN(1U)
1879 
1880 #define S_GPIO11_CHG_DET    27
1881 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
1882 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
1883 
1884 #define S_GPIO10_CHG_DET    26
1885 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
1886 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
1887 
1888 #define S_GPIO9_CHG_DET    25
1889 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
1890 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
1891 
1892 #define S_GPIO8_CHG_DET    24
1893 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
1894 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
1895 
1896 #define S_GPIO7_CHG_DET    23
1897 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
1898 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
1899 
1900 #define S_GPIO6_CHG_DET    22
1901 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
1902 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
1903 
1904 #define S_GPIO5_CHG_DET    21
1905 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
1906 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
1907 
1908 #define S_GPIO4_CHG_DET    20
1909 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
1910 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
1911 
1912 #define S_GPIO3_CHG_DET    19
1913 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
1914 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
1915 
1916 #define S_GPIO2_CHG_DET    18
1917 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
1918 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
1919 
1920 #define S_GPIO1_CHG_DET    17
1921 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
1922 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
1923 
1924 #define S_GPIO0_CHG_DET    16
1925 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
1926 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
1927 
1928 #define A_T3DBG_INT_ENABLE 0xd8
1929 
1930 #define S_C_LOCK    21
1931 #define V_C_LOCK(x) ((x) << S_C_LOCK)
1932 #define F_C_LOCK    V_C_LOCK(1U)
1933 
1934 #define S_M_LOCK    20
1935 #define V_M_LOCK(x) ((x) << S_M_LOCK)
1936 #define F_M_LOCK    V_M_LOCK(1U)
1937 
1938 #define S_U_LOCK    19
1939 #define V_U_LOCK(x) ((x) << S_U_LOCK)
1940 #define F_U_LOCK    V_U_LOCK(1U)
1941 
1942 #define S_R_LOCK    18
1943 #define V_R_LOCK(x) ((x) << S_R_LOCK)
1944 #define F_R_LOCK    V_R_LOCK(1U)
1945 
1946 #define S_PX_LOCK    17
1947 #define V_PX_LOCK(x) ((x) << S_PX_LOCK)
1948 #define F_PX_LOCK    V_PX_LOCK(1U)
1949 
1950 #define S_PE_LOCK    16
1951 #define V_PE_LOCK(x) ((x) << S_PE_LOCK)
1952 #define F_PE_LOCK    V_PE_LOCK(1U)
1953 
1954 #define S_GPIO11    11
1955 #define V_GPIO11(x) ((x) << S_GPIO11)
1956 #define F_GPIO11    V_GPIO11(1U)
1957 
1958 #define S_GPIO10    10
1959 #define V_GPIO10(x) ((x) << S_GPIO10)
1960 #define F_GPIO10    V_GPIO10(1U)
1961 
1962 #define S_GPIO9    9
1963 #define V_GPIO9(x) ((x) << S_GPIO9)
1964 #define F_GPIO9    V_GPIO9(1U)
1965 
1966 #define S_GPIO8    8
1967 #define V_GPIO8(x) ((x) << S_GPIO8)
1968 #define F_GPIO8    V_GPIO8(1U)
1969 
1970 #define S_GPIO7    7
1971 #define V_GPIO7(x) ((x) << S_GPIO7)
1972 #define F_GPIO7    V_GPIO7(1U)
1973 
1974 #define S_GPIO6    6
1975 #define V_GPIO6(x) ((x) << S_GPIO6)
1976 #define F_GPIO6    V_GPIO6(1U)
1977 
1978 #define S_GPIO5    5
1979 #define V_GPIO5(x) ((x) << S_GPIO5)
1980 #define F_GPIO5    V_GPIO5(1U)
1981 
1982 #define S_GPIO4    4
1983 #define V_GPIO4(x) ((x) << S_GPIO4)
1984 #define F_GPIO4    V_GPIO4(1U)
1985 
1986 #define S_GPIO3    3
1987 #define V_GPIO3(x) ((x) << S_GPIO3)
1988 #define F_GPIO3    V_GPIO3(1U)
1989 
1990 #define S_GPIO2    2
1991 #define V_GPIO2(x) ((x) << S_GPIO2)
1992 #define F_GPIO2    V_GPIO2(1U)
1993 
1994 #define S_GPIO1    1
1995 #define V_GPIO1(x) ((x) << S_GPIO1)
1996 #define F_GPIO1    V_GPIO1(1U)
1997 
1998 #define S_GPIO0    0
1999 #define V_GPIO0(x) ((x) << S_GPIO0)
2000 #define F_GPIO0    V_GPIO0(1U)
2001 
2002 #define A_T3DBG_INT_CAUSE 0xdc
2003 #define A_T3DBG_DBG0_RST_VALUE 0xe0
2004 
2005 #define S_DEBUGDATA    0
2006 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
2007 #define F_DEBUGDATA    V_DEBUGDATA(1U)
2008 
2009 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4
2010 
2011 #define S_PCIE_OCLK_EN    20
2012 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
2013 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
2014 
2015 #define S_PCIX_OCLK_EN    16
2016 #define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN)
2017 #define F_PCIX_OCLK_EN    V_PCIX_OCLK_EN(1U)
2018 
2019 #define S_U_OCLK_EN    12
2020 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
2021 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
2022 
2023 #define S_R_OCLK_EN    8
2024 #define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN)
2025 #define F_R_OCLK_EN    V_R_OCLK_EN(1U)
2026 
2027 #define S_M_OCLK_EN    4
2028 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
2029 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
2030 
2031 #define S_C_OCLK_EN    0
2032 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
2033 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
2034 
2035 #define S_PCLKTREE_DBG_EN    17
2036 #define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN)
2037 #define F_PCLKTREE_DBG_EN    V_PCLKTREE_DBG_EN(1U)
2038 
2039 #define A_T3DBG_PLL_LOCK 0xe8
2040 
2041 #define S_PCIE_LOCK    20
2042 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
2043 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
2044 
2045 #define S_PCIX_LOCK    16
2046 #define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK)
2047 #define F_PCIX_LOCK    V_PCIX_LOCK(1U)
2048 
2049 #define S_PLL_U_LOCK    12
2050 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
2051 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
2052 
2053 #define S_PLL_R_LOCK    8
2054 #define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK)
2055 #define F_PLL_R_LOCK    V_PLL_R_LOCK(1U)
2056 
2057 #define S_PLL_M_LOCK    4
2058 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
2059 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
2060 
2061 #define S_PLL_C_LOCK    0
2062 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
2063 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
2064 
2065 #define A_T3DBG_SERDES_RBC_CFG 0xec
2066 
2067 #define S_X_RBC_LANE_SEL    16
2068 #define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL)
2069 #define F_X_RBC_LANE_SEL    V_X_RBC_LANE_SEL(1U)
2070 
2071 #define S_X_RBC_DBG_EN    12
2072 #define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN)
2073 #define F_X_RBC_DBG_EN    V_X_RBC_DBG_EN(1U)
2074 
2075 #define S_X_SERDES_SEL    8
2076 #define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL)
2077 #define F_X_SERDES_SEL    V_X_SERDES_SEL(1U)
2078 
2079 #define S_PE_RBC_LANE_SEL    4
2080 #define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL)
2081 #define F_PE_RBC_LANE_SEL    V_PE_RBC_LANE_SEL(1U)
2082 
2083 #define S_PE_RBC_DBG_EN    0
2084 #define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN)
2085 #define F_PE_RBC_DBG_EN    V_PE_RBC_DBG_EN(1U)
2086 
2087 #define A_T3DBG_GPIO_ACT_LOW 0xf0
2088 
2089 #define S_C_LOCK_ACT_LOW    21
2090 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
2091 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
2092 
2093 #define S_M_LOCK_ACT_LOW    20
2094 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
2095 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
2096 
2097 #define S_U_LOCK_ACT_LOW    19
2098 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
2099 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
2100 
2101 #define S_R_LOCK_ACT_LOW    18
2102 #define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW)
2103 #define F_R_LOCK_ACT_LOW    V_R_LOCK_ACT_LOW(1U)
2104 
2105 #define S_PX_LOCK_ACT_LOW    17
2106 #define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW)
2107 #define F_PX_LOCK_ACT_LOW    V_PX_LOCK_ACT_LOW(1U)
2108 
2109 #define S_PE_LOCK_ACT_LOW    16
2110 #define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW)
2111 #define F_PE_LOCK_ACT_LOW    V_PE_LOCK_ACT_LOW(1U)
2112 
2113 #define S_GPIO11_ACT_LOW    11
2114 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
2115 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
2116 
2117 #define S_GPIO10_ACT_LOW    10
2118 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
2119 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
2120 
2121 #define S_GPIO9_ACT_LOW    9
2122 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
2123 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
2124 
2125 #define S_GPIO8_ACT_LOW    8
2126 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
2127 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
2128 
2129 #define S_GPIO7_ACT_LOW    7
2130 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
2131 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
2132 
2133 #define S_GPIO6_ACT_LOW    6
2134 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
2135 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
2136 
2137 #define S_GPIO5_ACT_LOW    5
2138 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
2139 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
2140 
2141 #define S_GPIO4_ACT_LOW    4
2142 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
2143 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
2144 
2145 #define S_GPIO3_ACT_LOW    3
2146 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
2147 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
2148 
2149 #define S_GPIO2_ACT_LOW    2
2150 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
2151 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
2152 
2153 #define S_GPIO1_ACT_LOW    1
2154 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
2155 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
2156 
2157 #define S_GPIO0_ACT_LOW    0
2158 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
2159 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
2160 
2161 #define A_T3DBG_PMON_CFG 0xf4
2162 
2163 #define S_PMON_DONE    29
2164 #define V_PMON_DONE(x) ((x) << S_PMON_DONE)
2165 #define F_PMON_DONE    V_PMON_DONE(1U)
2166 
2167 #define S_PMON_FAIL    28
2168 #define V_PMON_FAIL(x) ((x) << S_PMON_FAIL)
2169 #define F_PMON_FAIL    V_PMON_FAIL(1U)
2170 
2171 #define S_PMON_FDEL_AUTO    22
2172 #define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO)
2173 #define F_PMON_FDEL_AUTO    V_PMON_FDEL_AUTO(1U)
2174 
2175 #define S_PMON_CDEL_AUTO    16
2176 #define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO)
2177 #define F_PMON_CDEL_AUTO    V_PMON_CDEL_AUTO(1U)
2178 
2179 #define S_PMON_FDEL_MANUAL    10
2180 #define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL)
2181 #define F_PMON_FDEL_MANUAL    V_PMON_FDEL_MANUAL(1U)
2182 
2183 #define S_PMON_CDEL_MANUAL    4
2184 #define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL)
2185 #define F_PMON_CDEL_MANUAL    V_PMON_CDEL_MANUAL(1U)
2186 
2187 #define S_PMON_MANUAL    1
2188 #define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL)
2189 #define F_PMON_MANUAL    V_PMON_MANUAL(1U)
2190 
2191 #define S_PMON_AUTO    0
2192 #define V_PMON_AUTO(x) ((x) << S_PMON_AUTO)
2193 #define F_PMON_AUTO    V_PMON_AUTO(1U)
2194 
2195 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8
2196 
2197 #define S_PE_REFCLK_DBG_EN    12
2198 #define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN)
2199 #define F_PE_REFCLK_DBG_EN    V_PE_REFCLK_DBG_EN(1U)
2200 
2201 #define S_X_REFCLK_DBG_EN    8
2202 #define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN)
2203 #define F_X_REFCLK_DBG_EN    V_X_REFCLK_DBG_EN(1U)
2204 
2205 #define S_PE_REFCLK_TERMADJ    5
2206 #define M_PE_REFCLK_TERMADJ    0x3
2207 #define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ)
2208 #define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ)
2209 
2210 #define S_PE_REFCLK_PD    4
2211 #define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD)
2212 #define F_PE_REFCLK_PD    V_PE_REFCLK_PD(1U)
2213 
2214 #define S_X_REFCLK_TERMADJ    1
2215 #define M_X_REFCLK_TERMADJ    0x3
2216 #define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ)
2217 #define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ)
2218 
2219 #define S_X_REFCLK_PD    0
2220 #define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD)
2221 #define F_X_REFCLK_PD    V_X_REFCLK_PD(1U)
2222 
2223 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc
2224 
2225 #define S_BSMODEQUAD1    31
2226 #define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1)
2227 #define F_BSMODEQUAD1    V_BSMODEQUAD1(1U)
2228 
2229 #define S_BSINSELLANE7    29
2230 #define M_BSINSELLANE7    0x3
2231 #define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7)
2232 #define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7)
2233 
2234 #define S_BSENLANE7    28
2235 #define V_BSENLANE7(x) ((x) << S_BSENLANE7)
2236 #define F_BSENLANE7    V_BSENLANE7(1U)
2237 
2238 #define S_BSINSELLANE6    25
2239 #define M_BSINSELLANE6    0x3
2240 #define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6)
2241 #define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6)
2242 
2243 #define S_BSENLANE6    24
2244 #define V_BSENLANE6(x) ((x) << S_BSENLANE6)
2245 #define F_BSENLANE6    V_BSENLANE6(1U)
2246 
2247 #define S_BSINSELLANE5    21
2248 #define M_BSINSELLANE5    0x3
2249 #define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5)
2250 #define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5)
2251 
2252 #define S_BSENLANE5    20
2253 #define V_BSENLANE5(x) ((x) << S_BSENLANE5)
2254 #define F_BSENLANE5    V_BSENLANE5(1U)
2255 
2256 #define S_BSINSELLANE4    17
2257 #define M_BSINSELLANE4    0x3
2258 #define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4)
2259 #define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4)
2260 
2261 #define S_BSENLANE4    16
2262 #define V_BSENLANE4(x) ((x) << S_BSENLANE4)
2263 #define F_BSENLANE4    V_BSENLANE4(1U)
2264 
2265 #define S_BSMODEQUAD0    15
2266 #define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0)
2267 #define F_BSMODEQUAD0    V_BSMODEQUAD0(1U)
2268 
2269 #define S_BSINSELLANE3    13
2270 #define M_BSINSELLANE3    0x3
2271 #define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3)
2272 #define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3)
2273 
2274 #define S_BSENLANE3    12
2275 #define V_BSENLANE3(x) ((x) << S_BSENLANE3)
2276 #define F_BSENLANE3    V_BSENLANE3(1U)
2277 
2278 #define S_BSINSELLANE2    9
2279 #define M_BSINSELLANE2    0x3
2280 #define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2)
2281 #define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2)
2282 
2283 #define S_BSENLANE2    8
2284 #define V_BSENLANE2(x) ((x) << S_BSENLANE2)
2285 #define F_BSENLANE2    V_BSENLANE2(1U)
2286 
2287 #define S_BSINSELLANE1    5
2288 #define M_BSINSELLANE1    0x3
2289 #define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1)
2290 #define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1)
2291 
2292 #define S_BSENLANE1    4
2293 #define V_BSENLANE1(x) ((x) << S_BSENLANE1)
2294 #define F_BSENLANE1    V_BSENLANE1(1U)
2295 
2296 #define S_BSINSELLANE0    1
2297 #define M_BSINSELLANE0    0x3
2298 #define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0)
2299 #define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0)
2300 
2301 #define S_BSENLANE0    0
2302 #define V_BSENLANE0(x) ((x) << S_BSENLANE0)
2303 #define F_BSENLANE0    V_BSENLANE0(1U)
2304 
2305 /* registers for module MC7_PMRX */
2306 #define MC7_PMRX_BASE_ADDR 0x100
2307 
2308 #define A_MC7_CFG 0x100
2309 
2310 #define S_IMPSETUPDATE    14
2311 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
2312 #define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
2313 
2314 #define S_IFEN    13
2315 #define V_IFEN(x) ((x) << S_IFEN)
2316 #define F_IFEN    V_IFEN(1U)
2317 
2318 #define S_TERM300    12
2319 #define V_TERM300(x) ((x) << S_TERM300)
2320 #define F_TERM300    V_TERM300(1U)
2321 
2322 #define S_TERM150    11
2323 #define V_TERM150(x) ((x) << S_TERM150)
2324 #define F_TERM150    V_TERM150(1U)
2325 
2326 #define S_SLOW    10
2327 #define V_SLOW(x) ((x) << S_SLOW)
2328 #define F_SLOW    V_SLOW(1U)
2329 
2330 #define S_WIDTH    8
2331 #define M_WIDTH    0x3
2332 #define V_WIDTH(x) ((x) << S_WIDTH)
2333 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
2334 
2335 #define S_ODTEN    7
2336 #define V_ODTEN(x) ((x) << S_ODTEN)
2337 #define F_ODTEN    V_ODTEN(1U)
2338 
2339 #define S_BKS    6
2340 #define V_BKS(x) ((x) << S_BKS)
2341 #define F_BKS    V_BKS(1U)
2342 
2343 #define S_ORG    5
2344 #define V_ORG(x) ((x) << S_ORG)
2345 #define F_ORG    V_ORG(1U)
2346 
2347 #define S_DEN    2
2348 #define M_DEN    0x7
2349 #define V_DEN(x) ((x) << S_DEN)
2350 #define G_DEN(x) (((x) >> S_DEN) & M_DEN)
2351 
2352 #define S_RDY    1
2353 #define V_RDY(x) ((x) << S_RDY)
2354 #define F_RDY    V_RDY(1U)
2355 
2356 #define S_CLKEN    0
2357 #define V_CLKEN(x) ((x) << S_CLKEN)
2358 #define F_CLKEN    V_CLKEN(1U)
2359 
2360 #define A_MC7_MODE 0x104
2361 
2362 #define S_MODE    0
2363 #define M_MODE    0xffff
2364 #define V_MODE(x) ((x) << S_MODE)
2365 #define G_MODE(x) (((x) >> S_MODE) & M_MODE)
2366 
2367 #define A_MC7_EXT_MODE1 0x108
2368 
2369 #define S_OCDADJUSTMODE    20
2370 #define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE)
2371 #define F_OCDADJUSTMODE    V_OCDADJUSTMODE(1U)
2372 
2373 #define S_OCDCODE    16
2374 #define M_OCDCODE    0xf
2375 #define V_OCDCODE(x) ((x) << S_OCDCODE)
2376 #define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE)
2377 
2378 #define S_EXTMODE1    0
2379 #define M_EXTMODE1    0xffff
2380 #define V_EXTMODE1(x) ((x) << S_EXTMODE1)
2381 #define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1)
2382 
2383 #define A_MC7_EXT_MODE2 0x10c
2384 
2385 #define S_EXTMODE2    0
2386 #define M_EXTMODE2    0xffff
2387 #define V_EXTMODE2(x) ((x) << S_EXTMODE2)
2388 #define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2)
2389 
2390 #define A_MC7_EXT_MODE3 0x110
2391 
2392 #define S_EXTMODE3    0
2393 #define M_EXTMODE3    0xffff
2394 #define V_EXTMODE3(x) ((x) << S_EXTMODE3)
2395 #define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3)
2396 
2397 #define A_MC7_PRE 0x114
2398 #define A_MC7_REF 0x118
2399 
2400 #define S_PREREFDIV    1
2401 #define M_PREREFDIV    0x3fff
2402 #define V_PREREFDIV(x) ((x) << S_PREREFDIV)
2403 #define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV)
2404 
2405 #define S_PERREFEN    0
2406 #define V_PERREFEN(x) ((x) << S_PERREFEN)
2407 #define F_PERREFEN    V_PERREFEN(1U)
2408 
2409 #define A_MC7_DLL 0x11c
2410 
2411 #define S_DLLLOCK    31
2412 #define V_DLLLOCK(x) ((x) << S_DLLLOCK)
2413 #define F_DLLLOCK    V_DLLLOCK(1U)
2414 
2415 #define S_DLLDELTA    24
2416 #define M_DLLDELTA    0x7f
2417 #define V_DLLDELTA(x) ((x) << S_DLLDELTA)
2418 #define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA)
2419 
2420 #define S_MANDELTA    3
2421 #define M_MANDELTA    0x7f
2422 #define V_MANDELTA(x) ((x) << S_MANDELTA)
2423 #define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA)
2424 
2425 #define S_DLLDELTASEL    2
2426 #define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL)
2427 #define F_DLLDELTASEL    V_DLLDELTASEL(1U)
2428 
2429 #define S_DLLENB    1
2430 #define V_DLLENB(x) ((x) << S_DLLENB)
2431 #define F_DLLENB    V_DLLENB(1U)
2432 
2433 #define S_DLLRST    0
2434 #define V_DLLRST(x) ((x) << S_DLLRST)
2435 #define F_DLLRST    V_DLLRST(1U)
2436 
2437 #define A_MC7_PARM 0x120
2438 
2439 #define S_ACTTOPREDLY    26
2440 #define M_ACTTOPREDLY    0xf
2441 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
2442 #define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY)
2443 
2444 #define S_ACTTORDWRDLY    23
2445 #define M_ACTTORDWRDLY    0x7
2446 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
2447 #define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY)
2448 
2449 #define S_PRECYC    20
2450 #define M_PRECYC    0x7
2451 #define V_PRECYC(x) ((x) << S_PRECYC)
2452 #define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC)
2453 
2454 #define S_REFCYC    13
2455 #define M_REFCYC    0x7f
2456 #define V_REFCYC(x) ((x) << S_REFCYC)
2457 #define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC)
2458 
2459 #define S_BKCYC    8
2460 #define M_BKCYC    0x1f
2461 #define V_BKCYC(x) ((x) << S_BKCYC)
2462 #define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC)
2463 
2464 #define S_WRTORDDLY    4
2465 #define M_WRTORDDLY    0xf
2466 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
2467 #define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY)
2468 
2469 #define S_RDTOWRDLY    0
2470 #define M_RDTOWRDLY    0xf
2471 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
2472 #define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY)
2473 
2474 #define A_MC7_HWM_WRR 0x124
2475 
2476 #define S_MEM_HWM    26
2477 #define M_MEM_HWM    0x3f
2478 #define V_MEM_HWM(x) ((x) << S_MEM_HWM)
2479 #define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM)
2480 
2481 #define S_ULP_HWM    22
2482 #define M_ULP_HWM    0xf
2483 #define V_ULP_HWM(x) ((x) << S_ULP_HWM)
2484 #define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM)
2485 
2486 #define S_TOT_RLD_WT    14
2487 #define M_TOT_RLD_WT    0xff
2488 #define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT)
2489 #define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT)
2490 
2491 #define S_MEM_RLD_WT    7
2492 #define M_MEM_RLD_WT    0x7f
2493 #define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT)
2494 #define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT)
2495 
2496 #define S_ULP_RLD_WT    0
2497 #define M_ULP_RLD_WT    0x7f
2498 #define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT)
2499 #define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT)
2500 
2501 #define A_MC7_CAL 0x128
2502 
2503 #define S_BUSY    31
2504 #define V_BUSY(x) ((x) << S_BUSY)
2505 #define F_BUSY    V_BUSY(1U)
2506 
2507 #define S_CAL_FAULT    30
2508 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
2509 #define F_CAL_FAULT    V_CAL_FAULT(1U)
2510 
2511 #define S_PER_CAL_DIV    22
2512 #define M_PER_CAL_DIV    0xff
2513 #define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV)
2514 #define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV)
2515 
2516 #define S_PER_CAL_EN    21
2517 #define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN)
2518 #define F_PER_CAL_EN    V_PER_CAL_EN(1U)
2519 
2520 #define S_SGL_CAL_EN    20
2521 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
2522 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
2523 
2524 #define S_IMP_UPD_MODE    19
2525 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
2526 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
2527 
2528 #define S_IMP_SEL    18
2529 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
2530 #define F_IMP_SEL    V_IMP_SEL(1U)
2531 
2532 #define S_IMP_MAN_PD    15
2533 #define M_IMP_MAN_PD    0x7
2534 #define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD)
2535 #define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD)
2536 
2537 #define S_IMP_MAN_PU    12
2538 #define M_IMP_MAN_PU    0x7
2539 #define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU)
2540 #define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU)
2541 
2542 #define S_IMP_CAL_PD    9
2543 #define M_IMP_CAL_PD    0x7
2544 #define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD)
2545 #define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD)
2546 
2547 #define S_IMP_CAL_PU    6
2548 #define M_IMP_CAL_PU    0x7
2549 #define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU)
2550 #define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU)
2551 
2552 #define S_IMP_SET_PD    3
2553 #define M_IMP_SET_PD    0x7
2554 #define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD)
2555 #define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD)
2556 
2557 #define S_IMP_SET_PU    0
2558 #define M_IMP_SET_PU    0x7
2559 #define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU)
2560 #define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU)
2561 
2562 #define A_MC7_ERR_ADDR 0x12c
2563 
2564 #define S_ERRADDRESS    3
2565 #define M_ERRADDRESS    0x1fffffff
2566 #define V_ERRADDRESS(x) ((x) << S_ERRADDRESS)
2567 #define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS)
2568 
2569 #define S_ERRAGENT    1
2570 #define M_ERRAGENT    0x3
2571 #define V_ERRAGENT(x) ((x) << S_ERRAGENT)
2572 #define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT)
2573 
2574 #define S_ERROP    0
2575 #define V_ERROP(x) ((x) << S_ERROP)
2576 #define F_ERROP    V_ERROP(1U)
2577 
2578 #define A_MC7_ECC 0x130
2579 
2580 #define S_UECNT    10
2581 #define M_UECNT    0xff
2582 #define V_UECNT(x) ((x) << S_UECNT)
2583 #define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT)
2584 
2585 #define S_CECNT    2
2586 #define M_CECNT    0xff
2587 #define V_CECNT(x) ((x) << S_CECNT)
2588 #define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT)
2589 
2590 #define S_ECCCHKEN    1
2591 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
2592 #define F_ECCCHKEN    V_ECCCHKEN(1U)
2593 
2594 #define S_ECCGENEN    0
2595 #define V_ECCGENEN(x) ((x) << S_ECCGENEN)
2596 #define F_ECCGENEN    V_ECCGENEN(1U)
2597 
2598 #define A_MC7_CE_ADDR 0x134
2599 #define A_MC7_CE_DATA0 0x138
2600 #define A_MC7_CE_DATA1 0x13c
2601 #define A_MC7_CE_DATA2 0x140
2602 
2603 #define S_DATA    0
2604 #define M_DATA    0xff
2605 #define V_DATA(x) ((x) << S_DATA)
2606 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
2607 
2608 #define A_MC7_UE_ADDR 0x144
2609 #define A_MC7_UE_DATA0 0x148
2610 #define A_MC7_UE_DATA1 0x14c
2611 #define A_MC7_UE_DATA2 0x150
2612 #define A_MC7_BD_ADDR 0x154
2613 
2614 #define S_ADDR    3
2615 #define M_ADDR    0x1fffffff
2616 #define V_ADDR(x) ((x) << S_ADDR)
2617 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
2618 
2619 #define A_MC7_BD_DATA0 0x158
2620 #define A_MC7_BD_DATA1 0x15c
2621 #define A_MC7_BD_DATA2 0x160
2622 #define A_MC7_BD_OP 0x164
2623 
2624 #define S_OP    0
2625 #define V_OP(x) ((x) << S_OP)
2626 #define F_OP    V_OP(1U)
2627 
2628 #define A_MC7_BIST_ADDR_BEG 0x168
2629 
2630 #define S_ADDRBEG    5
2631 #define M_ADDRBEG    0x7ffffff
2632 #define V_ADDRBEG(x) ((x) << S_ADDRBEG)
2633 #define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG)
2634 
2635 #define A_MC7_BIST_ADDR_END 0x16c
2636 
2637 #define S_ADDREND    5
2638 #define M_ADDREND    0x7ffffff
2639 #define V_ADDREND(x) ((x) << S_ADDREND)
2640 #define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND)
2641 
2642 #define A_MC7_BIST_DATA 0x170
2643 #define A_MC7_BIST_OP 0x174
2644 
2645 #define S_GAP    4
2646 #define M_GAP    0x1f
2647 #define V_GAP(x) ((x) << S_GAP)
2648 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
2649 
2650 #define S_CONT    3
2651 #define V_CONT(x) ((x) << S_CONT)
2652 #define F_CONT    V_CONT(1U)
2653 
2654 #define S_DATAPAT    1
2655 #define M_DATAPAT    0x3
2656 #define V_DATAPAT(x) ((x) << S_DATAPAT)
2657 #define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT)
2658 
2659 #define A_MC7_INT_ENABLE 0x178
2660 
2661 #define S_AE    17
2662 #define V_AE(x) ((x) << S_AE)
2663 #define F_AE    V_AE(1U)
2664 
2665 #define S_PE    2
2666 #define M_PE    0x7fff
2667 #define V_PE(x) ((x) << S_PE)
2668 #define G_PE(x) (((x) >> S_PE) & M_PE)
2669 
2670 #define S_UE    1
2671 #define V_UE(x) ((x) << S_UE)
2672 #define F_UE    V_UE(1U)
2673 
2674 #define S_CE    0
2675 #define V_CE(x) ((x) << S_CE)
2676 #define F_CE    V_CE(1U)
2677 
2678 #define A_MC7_INT_CAUSE 0x17c
2679 
2680 /* registers for module MC7_PMTX */
2681 #define MC7_PMTX_BASE_ADDR 0x180
2682 
2683 /* registers for module MC7_CM */
2684 #define MC7_CM_BASE_ADDR 0x200
2685 
2686 /* registers for module CIM */
2687 #define CIM_BASE_ADDR 0x280
2688 
2689 #define A_CIM_BOOT_CFG 0x280
2690 
2691 #define S_BOOTADDR    2
2692 #define M_BOOTADDR    0x3fffffff
2693 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
2694 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
2695 
2696 #define S_BOOTSDRAM    1
2697 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
2698 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
2699 
2700 #define S_UPCRST    0
2701 #define V_UPCRST(x) ((x) << S_UPCRST)
2702 #define F_UPCRST    V_UPCRST(1U)
2703 
2704 #define A_CIM_FLASH_BASE_ADDR 0x284
2705 
2706 #define S_FLASHBASEADDR    2
2707 #define M_FLASHBASEADDR    0x3fffff
2708 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
2709 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
2710 
2711 #define A_CIM_FLASH_ADDR_SIZE 0x288
2712 
2713 #define S_FLASHADDRSIZE    2
2714 #define M_FLASHADDRSIZE    0x3fffff
2715 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
2716 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
2717 
2718 #define A_CIM_SDRAM_BASE_ADDR 0x28c
2719 
2720 #define S_SDRAMBASEADDR    2
2721 #define M_SDRAMBASEADDR    0x3fffffff
2722 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
2723 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
2724 
2725 #define A_CIM_SDRAM_ADDR_SIZE 0x290
2726 
2727 #define S_SDRAMADDRSIZE    2
2728 #define M_SDRAMADDRSIZE    0x3fffffff
2729 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
2730 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
2731 
2732 #define A_CIM_UP_SPARE_INT 0x294
2733 
2734 #define S_UPSPAREINT    0
2735 #define M_UPSPAREINT    0x7
2736 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
2737 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
2738 
2739 #define A_CIM_HOST_INT_ENABLE 0x298
2740 
2741 #define S_TIMER1INTEN    15
2742 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
2743 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
2744 
2745 #define S_TIMER0INTEN    14
2746 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
2747 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
2748 
2749 #define S_PREFDROPINTEN    13
2750 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
2751 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
2752 
2753 #define S_BLKWRPLINTEN    12
2754 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
2755 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
2756 
2757 #define S_BLKRDPLINTEN    11
2758 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
2759 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
2760 
2761 #define S_BLKWRCTLINTEN    10
2762 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
2763 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
2764 
2765 #define S_BLKRDCTLINTEN    9
2766 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
2767 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
2768 
2769 #define S_BLKWRFLASHINTEN    8
2770 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
2771 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
2772 
2773 #define S_BLKRDFLASHINTEN    7
2774 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
2775 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
2776 
2777 #define S_SGLWRFLASHINTEN    6
2778 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
2779 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
2780 
2781 #define S_WRBLKFLASHINTEN    5
2782 #define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN)
2783 #define F_WRBLKFLASHINTEN    V_WRBLKFLASHINTEN(1U)
2784 
2785 #define S_BLKWRBOOTINTEN    4
2786 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
2787 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
2788 
2789 #define S_BLKRDBOOTINTEN    3
2790 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
2791 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
2792 
2793 #define S_FLASHRANGEINTEN    2
2794 #define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN)
2795 #define F_FLASHRANGEINTEN    V_FLASHRANGEINTEN(1U)
2796 
2797 #define S_SDRAMRANGEINTEN    1
2798 #define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN)
2799 #define F_SDRAMRANGEINTEN    V_SDRAMRANGEINTEN(1U)
2800 
2801 #define S_RSVDSPACEINTEN    0
2802 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
2803 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
2804 
2805 #define A_CIM_HOST_INT_CAUSE 0x29c
2806 
2807 #define S_TIMER1INT    15
2808 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
2809 #define F_TIMER1INT    V_TIMER1INT(1U)
2810 
2811 #define S_TIMER0INT    14
2812 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
2813 #define F_TIMER0INT    V_TIMER0INT(1U)
2814 
2815 #define S_PREFDROPINT    13
2816 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
2817 #define F_PREFDROPINT    V_PREFDROPINT(1U)
2818 
2819 #define S_BLKWRPLINT    12
2820 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
2821 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
2822 
2823 #define S_BLKRDPLINT    11
2824 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
2825 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
2826 
2827 #define S_BLKWRCTLINT    10
2828 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
2829 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
2830 
2831 #define S_BLKRDCTLINT    9
2832 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
2833 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
2834 
2835 #define S_BLKWRFLASHINT    8
2836 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
2837 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
2838 
2839 #define S_BLKRDFLASHINT    7
2840 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
2841 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
2842 
2843 #define S_SGLWRFLASHINT    6
2844 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
2845 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
2846 
2847 #define S_WRBLKFLASHINT    5
2848 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
2849 #define F_WRBLKFLASHINT    V_WRBLKFLASHINT(1U)
2850 
2851 #define S_BLKWRBOOTINT    4
2852 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
2853 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
2854 
2855 #define S_BLKRDBOOTINT    3
2856 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
2857 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
2858 
2859 #define S_FLASHRANGEINT    2
2860 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
2861 #define F_FLASHRANGEINT    V_FLASHRANGEINT(1U)
2862 
2863 #define S_SDRAMRANGEINT    1
2864 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
2865 #define F_SDRAMRANGEINT    V_SDRAMRANGEINT(1U)
2866 
2867 #define S_RSVDSPACEINT    0
2868 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
2869 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
2870 
2871 #define A_CIM_UP_INT_ENABLE 0x2a0
2872 
2873 #define S_MSTPLINTEN    16
2874 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
2875 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
2876 
2877 #define A_CIM_UP_INT_CAUSE 0x2a4
2878 
2879 #define S_MSTPLINT    16
2880 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
2881 #define F_MSTPLINT    V_MSTPLINT(1U)
2882 
2883 #define A_CIM_IBQ_FULLA_THRSH 0x2a8
2884 
2885 #define S_IBQ0FULLTHRSH    0
2886 #define M_IBQ0FULLTHRSH    0x1ff
2887 #define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH)
2888 #define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH)
2889 
2890 #define S_IBQ1FULLTHRSH    16
2891 #define M_IBQ1FULLTHRSH    0x1ff
2892 #define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH)
2893 #define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH)
2894 
2895 #define A_CIM_IBQ_FULLB_THRSH 0x2ac
2896 
2897 #define S_IBQ2FULLTHRSH    0
2898 #define M_IBQ2FULLTHRSH    0x1ff
2899 #define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH)
2900 #define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH)
2901 
2902 #define S_IBQ3FULLTHRSH    16
2903 #define M_IBQ3FULLTHRSH    0x1ff
2904 #define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH)
2905 #define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH)
2906 
2907 #define A_CIM_HOST_ACC_CTRL 0x2b0
2908 
2909 #define S_HOSTBUSY    17
2910 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
2911 #define F_HOSTBUSY    V_HOSTBUSY(1U)
2912 
2913 #define S_HOSTWRITE    16
2914 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
2915 #define F_HOSTWRITE    V_HOSTWRITE(1U)
2916 
2917 #define S_HOSTADDR    0
2918 #define M_HOSTADDR    0xffff
2919 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
2920 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
2921 
2922 #define A_CIM_HOST_ACC_DATA 0x2b4
2923 #define A_CIM_IBQ_DBG_CFG 0x2c0
2924 
2925 #define S_IBQDBGADDR    16
2926 #define M_IBQDBGADDR    0x1ff
2927 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
2928 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
2929 
2930 #define S_IBQDBGQID    3
2931 #define M_IBQDBGQID    0x3
2932 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
2933 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
2934 
2935 #define S_IBQDBGWR    2
2936 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
2937 #define F_IBQDBGWR    V_IBQDBGWR(1U)
2938 
2939 #define S_IBQDBGBUSY    1
2940 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
2941 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
2942 
2943 #define S_IBQDBGEN    0
2944 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
2945 #define F_IBQDBGEN    V_IBQDBGEN(1U)
2946 
2947 #define A_CIM_OBQ_DBG_CFG 0x2c4
2948 
2949 #define S_OBQDBGADDR    16
2950 #define M_OBQDBGADDR    0x1ff
2951 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
2952 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
2953 
2954 #define S_OBQDBGQID    3
2955 #define M_OBQDBGQID    0x3
2956 #define V_OBQDBGQID(x) ((x) << S_OBQDBGQID)
2957 #define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID)
2958 
2959 #define S_OBQDBGWR    2
2960 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
2961 #define F_OBQDBGWR    V_OBQDBGWR(1U)
2962 
2963 #define S_OBQDBGBUSY    1
2964 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
2965 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
2966 
2967 #define S_OBQDBGEN    0
2968 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
2969 #define F_OBQDBGEN    V_OBQDBGEN(1U)
2970 
2971 #define A_CIM_IBQ_DBG_DATA 0x2c8
2972 #define A_CIM_OBQ_DBG_DATA 0x2cc
2973 #define A_CIM_CDEBUGDATA 0x2d0
2974 
2975 #define S_CDEBUGDATAH    16
2976 #define M_CDEBUGDATAH    0xffff
2977 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
2978 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
2979 
2980 #define S_CDEBUGDATAL    0
2981 #define M_CDEBUGDATAL    0xffff
2982 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
2983 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
2984 
2985 #define A_CIM_DEBUGCFG 0x2e0
2986 
2987 #define S_POLADBGRDPTR    23
2988 #define M_POLADBGRDPTR    0x1ff
2989 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
2990 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
2991 
2992 #define S_PILADBGRDPTR    14
2993 #define M_PILADBGRDPTR    0x1ff
2994 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
2995 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
2996 
2997 #define S_CIM_LADBGEN    12
2998 #define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN)
2999 #define F_CIM_LADBGEN    V_CIM_LADBGEN(1U)
3000 
3001 #define S_DEBUGSELHI    5
3002 #define M_DEBUGSELHI    0x1f
3003 #define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI)
3004 #define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI)
3005 
3006 #define S_DEBUGSELLO    0
3007 #define M_DEBUGSELLO    0x1f
3008 #define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO)
3009 #define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO)
3010 
3011 #define A_CIM_DEBUGSTS 0x2e4
3012 
3013 #define S_POLADBGWRPTR    16
3014 #define M_POLADBGWRPTR    0x1ff
3015 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
3016 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
3017 
3018 #define S_PILADBGWRPTR    0
3019 #define M_PILADBGWRPTR    0x1ff
3020 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
3021 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
3022 
3023 #define A_CIM_PO_LA_DEBUGDATA 0x2e8
3024 #define A_CIM_PI_LA_DEBUGDATA 0x2ec
3025 
3026 /* registers for module TP1 */
3027 #define TP1_BASE_ADDR 0x300
3028 
3029 #define A_TP_IN_CONFIG 0x300
3030 
3031 #define S_RXFBARBPRIO    25
3032 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
3033 #define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)
3034 
3035 #define S_TXFBARBPRIO    24
3036 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
3037 #define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)
3038 
3039 #define S_DBMAXOPCNT    16
3040 #define M_DBMAXOPCNT    0xff
3041 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
3042 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
3043 
3044 #define S_NICMODE    14
3045 #define V_NICMODE(x) ((x) << S_NICMODE)
3046 #define F_NICMODE    V_NICMODE(1U)
3047 
3048 #define S_ECHECKSUMCHECKTCP    13
3049 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
3050 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
3051 
3052 #define S_ECHECKSUMCHECKIP    12
3053 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
3054 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
3055 
3056 #define S_ECPL    10
3057 #define V_ECPL(x) ((x) << S_ECPL)
3058 #define F_ECPL    V_ECPL(1U)
3059 
3060 #define S_EETHERNET    8
3061 #define V_EETHERNET(x) ((x) << S_EETHERNET)
3062 #define F_EETHERNET    V_EETHERNET(1U)
3063 
3064 #define S_ETUNNEL    7
3065 #define V_ETUNNEL(x) ((x) << S_ETUNNEL)
3066 #define F_ETUNNEL    V_ETUNNEL(1U)
3067 
3068 #define S_CCHECKSUMCHECKTCP    6
3069 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
3070 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
3071 
3072 #define S_CCHECKSUMCHECKIP    5
3073 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
3074 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
3075 
3076 #define S_CCPL    3
3077 #define V_CCPL(x) ((x) << S_CCPL)
3078 #define F_CCPL    V_CCPL(1U)
3079 
3080 #define S_CETHERNET    1
3081 #define V_CETHERNET(x) ((x) << S_CETHERNET)
3082 #define F_CETHERNET    V_CETHERNET(1U)
3083 
3084 #define S_CTUNNEL    0
3085 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
3086 #define F_CTUNNEL    V_CTUNNEL(1U)
3087 
3088 #define S_IPV6ENABLE    15
3089 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
3090 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
3091 
3092 #define A_TP_OUT_CONFIG 0x304
3093 
3094 #define S_VLANEXTRACTIONENABLE    12
3095 #define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE)
3096 #define F_VLANEXTRACTIONENABLE    V_VLANEXTRACTIONENABLE(1U)
3097 
3098 #define S_ECHECKSUMGENERATETCP    11
3099 #define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP)
3100 #define F_ECHECKSUMGENERATETCP    V_ECHECKSUMGENERATETCP(1U)
3101 
3102 #define S_ECHECKSUMGENERATEIP    10
3103 #define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP)
3104 #define F_ECHECKSUMGENERATEIP    V_ECHECKSUMGENERATEIP(1U)
3105 
3106 #define S_OUT_ECPL    8
3107 #define V_OUT_ECPL(x) ((x) << S_OUT_ECPL)
3108 #define F_OUT_ECPL    V_OUT_ECPL(1U)
3109 
3110 #define S_OUT_EETHERNET    6
3111 #define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET)
3112 #define F_OUT_EETHERNET    V_OUT_EETHERNET(1U)
3113 
3114 #define S_CCHECKSUMGENERATETCP    5
3115 #define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP)
3116 #define F_CCHECKSUMGENERATETCP    V_CCHECKSUMGENERATETCP(1U)
3117 
3118 #define S_CCHECKSUMGENERATEIP    4
3119 #define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP)
3120 #define F_CCHECKSUMGENERATEIP    V_CCHECKSUMGENERATEIP(1U)
3121 
3122 #define S_OUT_CCPL    2
3123 #define V_OUT_CCPL(x) ((x) << S_OUT_CCPL)
3124 #define F_OUT_CCPL    V_OUT_CCPL(1U)
3125 
3126 #define S_OUT_CETHERNET    0
3127 #define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET)
3128 #define F_OUT_CETHERNET    V_OUT_CETHERNET(1U)
3129 
3130 #define S_IPIDSPLITMODE    16
3131 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
3132 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
3133 
3134 #define S_VLANEXTRACTIONENABLE2NDPORT    13
3135 #define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT)
3136 #define F_VLANEXTRACTIONENABLE2NDPORT    V_VLANEXTRACTIONENABLE2NDPORT(1U)
3137 
3138 #define A_TP_GLOBAL_CONFIG 0x308
3139 
3140 #define S_RXFLOWCONTROLDISABLE    25
3141 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
3142 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
3143 
3144 #define S_TXPACINGENABLE    24
3145 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
3146 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
3147 
3148 #define S_ATTACKFILTERENABLE    23
3149 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
3150 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
3151 
3152 #define S_SYNCOOKIENOOPTIONS    22
3153 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
3154 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
3155 
3156 #define S_PROTECTEDMODE    21
3157 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
3158 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
3159 
3160 #define S_PINGDROP    20
3161 #define V_PINGDROP(x) ((x) << S_PINGDROP)
3162 #define F_PINGDROP    V_PINGDROP(1U)
3163 
3164 #define S_FRAGMENTDROP    19
3165 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
3166 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
3167 
3168 #define S_FIVETUPLELOOKUP    17
3169 #define M_FIVETUPLELOOKUP    0x3
3170 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
3171 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
3172 
3173 #define S_PATHMTU    15
3174 #define V_PATHMTU(x) ((x) << S_PATHMTU)
3175 #define F_PATHMTU    V_PATHMTU(1U)
3176 
3177 #define S_IPIDENTSPLIT    14
3178 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
3179 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
3180 
3181 #define S_IPCHECKSUMOFFLOAD    13
3182 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
3183 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
3184 
3185 #define S_UDPCHECKSUMOFFLOAD    12
3186 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
3187 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
3188 
3189 #define S_TCPCHECKSUMOFFLOAD    11
3190 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
3191 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
3192 
3193 #define S_QOSMAPPING    10
3194 #define V_QOSMAPPING(x) ((x) << S_QOSMAPPING)
3195 #define F_QOSMAPPING    V_QOSMAPPING(1U)
3196 
3197 #define S_TCAMSERVERUSE    8
3198 #define M_TCAMSERVERUSE    0x3
3199 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
3200 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
3201 
3202 #define S_IPTTL    0
3203 #define M_IPTTL    0xff
3204 #define V_IPTTL(x) ((x) << S_IPTTL)
3205 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
3206 
3207 #define S_SYNCOOKIEPARAMS    26
3208 #define M_SYNCOOKIEPARAMS    0x3f
3209 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
3210 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
3211 
3212 #define A_TP_GLOBAL_RX_CREDIT 0x30c
3213 #define A_TP_CMM_SIZE 0x310
3214 
3215 #define S_CMMEMMGRSIZE    0
3216 #define M_CMMEMMGRSIZE    0xfffffff
3217 #define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE)
3218 #define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE)
3219 
3220 #define A_TP_CMM_MM_BASE 0x314
3221 
3222 #define S_CMMEMMGRBASE    0
3223 #define M_CMMEMMGRBASE    0xfffffff
3224 #define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE)
3225 #define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE)
3226 
3227 #define A_TP_CMM_TIMER_BASE 0x318
3228 
3229 #define S_CMTIMERBASE    0
3230 #define M_CMTIMERBASE    0xfffffff
3231 #define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE)
3232 #define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE)
3233 
3234 #define S_CMTIMERMAXNUM    28
3235 #define M_CMTIMERMAXNUM    0x3
3236 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
3237 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
3238 
3239 #define A_TP_PMM_SIZE 0x31c
3240 
3241 #define S_PMSIZE    0
3242 #define M_PMSIZE    0xfffffff
3243 #define V_PMSIZE(x) ((x) << S_PMSIZE)
3244 #define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE)
3245 
3246 #define A_TP_PMM_TX_BASE 0x320
3247 #define A_TP_PMM_DEFRAG_BASE 0x324
3248 #define A_TP_PMM_RX_BASE 0x328
3249 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
3250 #define A_TP_PMM_RX_MAX_PAGE 0x330
3251 
3252 #define S_PMRXMAXPAGE    0
3253 #define M_PMRXMAXPAGE    0x1fffff
3254 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
3255 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
3256 
3257 #define A_TP_PMM_TX_PAGE_SIZE 0x334
3258 #define A_TP_PMM_TX_MAX_PAGE 0x338
3259 
3260 #define S_PMTXMAXPAGE    0
3261 #define M_PMTXMAXPAGE    0x1fffff
3262 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
3263 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
3264 
3265 #define A_TP_TCP_OPTIONS 0x340
3266 
3267 #define S_MTUDEFAULT    16
3268 #define M_MTUDEFAULT    0xffff
3269 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
3270 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
3271 
3272 #define S_MTUENABLE    10
3273 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
3274 #define F_MTUENABLE    V_MTUENABLE(1U)
3275 
3276 #define S_SACKTX    9
3277 #define V_SACKTX(x) ((x) << S_SACKTX)
3278 #define F_SACKTX    V_SACKTX(1U)
3279 
3280 #define S_SACKRX    8
3281 #define V_SACKRX(x) ((x) << S_SACKRX)
3282 #define F_SACKRX    V_SACKRX(1U)
3283 
3284 #define S_SACKMODE    4
3285 #define M_SACKMODE    0x3
3286 #define V_SACKMODE(x) ((x) << S_SACKMODE)
3287 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
3288 
3289 #define S_WINDOWSCALEMODE    2
3290 #define M_WINDOWSCALEMODE    0x3
3291 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
3292 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
3293 
3294 #define S_TIMESTAMPSMODE    0
3295 #define M_TIMESTAMPSMODE    0x3
3296 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
3297 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
3298 
3299 #define A_TP_DACK_CONFIG 0x344
3300 
3301 #define S_AUTOSTATE3    30
3302 #define M_AUTOSTATE3    0x3
3303 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
3304 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
3305 
3306 #define S_AUTOSTATE2    28
3307 #define M_AUTOSTATE2    0x3
3308 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
3309 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
3310 
3311 #define S_AUTOSTATE1    26
3312 #define M_AUTOSTATE1    0x3
3313 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
3314 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
3315 
3316 #define S_BYTETHRESHOLD    5
3317 #define M_BYTETHRESHOLD    0xfffff
3318 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
3319 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
3320 
3321 #define S_MSSTHRESHOLD    3
3322 #define M_MSSTHRESHOLD    0x3
3323 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
3324 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
3325 
3326 #define S_AUTOCAREFUL    2
3327 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
3328 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
3329 
3330 #define S_AUTOENABLE    1
3331 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
3332 #define F_AUTOENABLE    V_AUTOENABLE(1U)
3333 
3334 #define S_DACK_MODE    0
3335 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
3336 #define F_DACK_MODE    V_DACK_MODE(1U)
3337 
3338 #define A_TP_PC_CONFIG 0x348
3339 
3340 #define S_TXTOSQUEUEMAPMODE    26
3341 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
3342 #define F_TXTOSQUEUEMAPMODE    V_TXTOSQUEUEMAPMODE(1U)
3343 
3344 #define S_RDDPCONGEN    25
3345 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
3346 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
3347 
3348 #define S_ENABLEONFLYPDU    24
3349 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
3350 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
3351 
3352 #define S_ENABLEEPCMDAFULL    23
3353 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
3354 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
3355 
3356 #define S_MODULATEUNIONMODE    22
3357 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
3358 #define F_MODULATEUNIONMODE    V_MODULATEUNIONMODE(1U)
3359 
3360 #define S_TXDATAACKRATEENABLE    21
3361 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
3362 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
3363 
3364 #define S_TXDEFERENABLE    20
3365 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
3366 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
3367 
3368 #define S_RXCONGESTIONMODE    19
3369 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
3370 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
3371 
3372 #define S_HEARBEATONCEDACK    18
3373 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
3374 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
3375 
3376 #define S_HEARBEATONCEHEAP    17
3377 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
3378 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
3379 
3380 #define S_HEARBEATDACK    16
3381 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
3382 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
3383 
3384 #define S_TXCONGESTIONMODE    15
3385 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
3386 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
3387 
3388 #define S_ACCEPTLATESTRCVADV    14
3389 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
3390 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
3391 
3392 #define S_DISABLESYNDATA    13
3393 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
3394 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
3395 
3396 #define S_DISABLEWINDOWPSH    12
3397 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
3398 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
3399 
3400 #define S_DISABLEFINOLDDATA    11
3401 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
3402 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
3403 
3404 #define S_ENABLEFLMERROR    10
3405 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
3406 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
3407 
3408 #define S_DISABLENEXTMTU    9
3409 #define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU)
3410 #define F_DISABLENEXTMTU    V_DISABLENEXTMTU(1U)
3411 
3412 #define S_FILTERPEERFIN    8
3413 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
3414 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
3415 
3416 #define S_ENABLEFEEDBACKSEND    7
3417 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
3418 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
3419 
3420 #define S_ENABLERDMAERROR    6
3421 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
3422 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
3423 
3424 #define S_ENABLEDDPFLOWCONTROL    5
3425 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
3426 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
3427 
3428 #define S_DISABLEHELDFIN    4
3429 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
3430 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
3431 
3432 #define S_TABLELATENCYDELTA    0
3433 #define M_TABLELATENCYDELTA    0xf
3434 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
3435 #define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
3436 
3437 #define S_CMCACHEDISABLE    31
3438 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
3439 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
3440 
3441 #define S_ENABLEOCSPIFULL    30
3442 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
3443 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
3444 
3445 #define S_ENABLEFLMERRORDDP    29
3446 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
3447 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
3448 
3449 #define S_LOCKTID    28
3450 #define V_LOCKTID(x) ((x) << S_LOCKTID)
3451 #define F_LOCKTID    V_LOCKTID(1U)
3452 
3453 #define S_FIXRCVWND    27
3454 #define V_FIXRCVWND(x) ((x) << S_FIXRCVWND)
3455 #define F_FIXRCVWND    V_FIXRCVWND(1U)
3456 
3457 #define A_TP_PC_CONFIG2 0x34c
3458 
3459 #define S_ENABLEDROPRQEMPTYPKT    10
3460 #define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT)
3461 #define F_ENABLEDROPRQEMPTYPKT    V_ENABLEDROPRQEMPTYPKT(1U)
3462 
3463 #define S_ENABLETXPORTFROMDA2    9
3464 #define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2)
3465 #define F_ENABLETXPORTFROMDA2    V_ENABLETXPORTFROMDA2(1U)
3466 
3467 #define S_ENABLERXPKTTMSTPRSS    8
3468 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
3469 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
3470 
3471 #define S_ENABLESNDUNAINRXDATA    7
3472 #define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA)
3473 #define F_ENABLESNDUNAINRXDATA    V_ENABLESNDUNAINRXDATA(1U)
3474 
3475 #define S_ENABLERXPORTFROMADDR    6
3476 #define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR)
3477 #define F_ENABLERXPORTFROMADDR    V_ENABLERXPORTFROMADDR(1U)
3478 
3479 #define S_ENABLETXPORTFROMDA    5
3480 #define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA)
3481 #define F_ENABLETXPORTFROMDA    V_ENABLETXPORTFROMDA(1U)
3482 
3483 #define S_CHDRAFULL    4
3484 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
3485 #define F_CHDRAFULL    V_CHDRAFULL(1U)
3486 
3487 #define S_ENABLENONOFDSCBBIT    3
3488 #define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT)
3489 #define F_ENABLENONOFDSCBBIT    V_ENABLENONOFDSCBBIT(1U)
3490 
3491 #define S_ENABLENONOFDTIDRSS    2
3492 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
3493 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
3494 
3495 #define S_ENABLENONOFDTCBRSS    1
3496 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
3497 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
3498 
3499 #define S_ENABLEOLDRXFORWARD    0
3500 #define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD)
3501 #define F_ENABLEOLDRXFORWARD    V_ENABLEOLDRXFORWARD(1U)
3502 
3503 #define A_TP_TCP_BACKOFF_REG0 0x350
3504 
3505 #define S_TIMERBACKOFFINDEX3    24
3506 #define M_TIMERBACKOFFINDEX3    0xff
3507 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
3508 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
3509 
3510 #define S_TIMERBACKOFFINDEX2    16
3511 #define M_TIMERBACKOFFINDEX2    0xff
3512 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
3513 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
3514 
3515 #define S_TIMERBACKOFFINDEX1    8
3516 #define M_TIMERBACKOFFINDEX1    0xff
3517 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
3518 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
3519 
3520 #define S_TIMERBACKOFFINDEX0    0
3521 #define M_TIMERBACKOFFINDEX0    0xff
3522 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
3523 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
3524 
3525 #define A_TP_TCP_BACKOFF_REG1 0x354
3526 
3527 #define S_TIMERBACKOFFINDEX7    24
3528 #define M_TIMERBACKOFFINDEX7    0xff
3529 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
3530 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
3531 
3532 #define S_TIMERBACKOFFINDEX6    16
3533 #define M_TIMERBACKOFFINDEX6    0xff
3534 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
3535 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
3536 
3537 #define S_TIMERBACKOFFINDEX5    8
3538 #define M_TIMERBACKOFFINDEX5    0xff
3539 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
3540 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
3541 
3542 #define S_TIMERBACKOFFINDEX4    0
3543 #define M_TIMERBACKOFFINDEX4    0xff
3544 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
3545 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
3546 
3547 #define A_TP_TCP_BACKOFF_REG2 0x358
3548 
3549 #define S_TIMERBACKOFFINDEX11    24
3550 #define M_TIMERBACKOFFINDEX11    0xff
3551 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
3552 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
3553 
3554 #define S_TIMERBACKOFFINDEX10    16
3555 #define M_TIMERBACKOFFINDEX10    0xff
3556 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
3557 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
3558 
3559 #define S_TIMERBACKOFFINDEX9    8
3560 #define M_TIMERBACKOFFINDEX9    0xff
3561 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
3562 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
3563 
3564 #define S_TIMERBACKOFFINDEX8    0
3565 #define M_TIMERBACKOFFINDEX8    0xff
3566 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
3567 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
3568 
3569 #define A_TP_TCP_BACKOFF_REG3 0x35c
3570 
3571 #define S_TIMERBACKOFFINDEX15    24
3572 #define M_TIMERBACKOFFINDEX15    0xff
3573 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
3574 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
3575 
3576 #define S_TIMERBACKOFFINDEX14    16
3577 #define M_TIMERBACKOFFINDEX14    0xff
3578 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
3579 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
3580 
3581 #define S_TIMERBACKOFFINDEX13    8
3582 #define M_TIMERBACKOFFINDEX13    0xff
3583 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
3584 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
3585 
3586 #define S_TIMERBACKOFFINDEX12    0
3587 #define M_TIMERBACKOFFINDEX12    0xff
3588 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
3589 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
3590 
3591 #define A_TP_PARA_REG0 0x360
3592 
3593 #define S_INITCWND    24
3594 #define M_INITCWND    0x7
3595 #define V_INITCWND(x) ((x) << S_INITCWND)
3596 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
3597 
3598 #define S_DUPACKTHRESH    20
3599 #define M_DUPACKTHRESH    0xf
3600 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
3601 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
3602 
3603 #define A_TP_PARA_REG1 0x364
3604 
3605 #define S_INITRWND    16
3606 #define M_INITRWND    0xffff
3607 #define V_INITRWND(x) ((x) << S_INITRWND)
3608 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
3609 
3610 #define S_INITIALSSTHRESH    0
3611 #define M_INITIALSSTHRESH    0xffff
3612 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
3613 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
3614 
3615 #define A_TP_PARA_REG2 0x368
3616 
3617 #define S_MAXRXDATA    16
3618 #define M_MAXRXDATA    0xffff
3619 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
3620 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
3621 
3622 #define S_RXCOALESCESIZE    0
3623 #define M_RXCOALESCESIZE    0xffff
3624 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
3625 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
3626 
3627 #define A_TP_PARA_REG3 0x36c
3628 
3629 #define S_TUNNELCNGDROP1    21
3630 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
3631 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
3632 
3633 #define S_TUNNELCNGDROP0    20
3634 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
3635 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
3636 
3637 #define S_TXDATAACKIDX    16
3638 #define M_TXDATAACKIDX    0xf
3639 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
3640 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
3641 
3642 #define S_RXFRAGENABLE    12
3643 #define M_RXFRAGENABLE    0x7
3644 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
3645 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
3646 
3647 #define S_TXPACEFIXEDSTRICT    11
3648 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
3649 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
3650 
3651 #define S_TXPACEAUTOSTRICT    10
3652 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
3653 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
3654 
3655 #define S_TXPACEFIXED    9
3656 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
3657 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
3658 
3659 #define S_TXPACEAUTO    8
3660 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
3661 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
3662 
3663 #define S_RXURGMODE    5
3664 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
3665 #define F_RXURGMODE    V_RXURGMODE(1U)
3666 
3667 #define S_TXURGMODE    4
3668 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
3669 #define F_TXURGMODE    V_TXURGMODE(1U)
3670 
3671 #define S_CNGCTRLMODE    2
3672 #define M_CNGCTRLMODE    0x3
3673 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
3674 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
3675 
3676 #define S_RXCOALESCEENABLE    1
3677 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
3678 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
3679 
3680 #define S_RXCOALESCEPSHEN    0
3681 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
3682 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
3683 
3684 #define S_RXURGTUNNEL    6
3685 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
3686 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
3687 
3688 #define A_TP_PARA_REG4 0x370
3689 
3690 #define S_HIGHSPEEDCFG    24
3691 #define M_HIGHSPEEDCFG    0xff
3692 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
3693 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
3694 
3695 #define S_NEWRENOCFG    16
3696 #define M_NEWRENOCFG    0xff
3697 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
3698 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
3699 
3700 #define S_TAHOECFG    8
3701 #define M_TAHOECFG    0xff
3702 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
3703 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
3704 
3705 #define S_RENOCFG    0
3706 #define M_RENOCFG    0xff
3707 #define V_RENOCFG(x) ((x) << S_RENOCFG)
3708 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
3709 
3710 #define A_TP_PARA_REG5 0x374
3711 
3712 #define S_INDICATESIZE    16
3713 #define M_INDICATESIZE    0xffff
3714 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
3715 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
3716 
3717 #define S_SCHDENABLE    8
3718 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
3719 #define F_SCHDENABLE    V_SCHDENABLE(1U)
3720 
3721 #define S_ONFLYDDPENABLE    2
3722 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
3723 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
3724 
3725 #define S_DACKTIMERSPIN    1
3726 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
3727 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
3728 
3729 #define S_PUSHTIMERENABLE    0
3730 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
3731 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
3732 
3733 #define A_TP_PARA_REG6 0x378
3734 
3735 #define S_TXPDUSIZEADJ    16
3736 #define M_TXPDUSIZEADJ    0xff
3737 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
3738 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
3739 
3740 #define S_ENABLEEPDU    14
3741 #define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU)
3742 #define F_ENABLEEPDU    V_ENABLEEPDU(1U)
3743 
3744 #define S_T3A_ENABLEESND    13
3745 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
3746 #define F_T3A_ENABLEESND    V_T3A_ENABLEESND(1U)
3747 
3748 #define S_T3A_ENABLECSND    12
3749 #define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND)
3750 #define F_T3A_ENABLECSND    V_T3A_ENABLECSND(1U)
3751 
3752 #define S_T3A_ENABLEDEFERACK    9
3753 #define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK)
3754 #define F_T3A_ENABLEDEFERACK    V_T3A_ENABLEDEFERACK(1U)
3755 
3756 #define S_ENABLEPDUC    8
3757 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
3758 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
3759 
3760 #define S_ENABLEPDUI    7
3761 #define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI)
3762 #define F_ENABLEPDUI    V_ENABLEPDUI(1U)
3763 
3764 #define S_T3A_ENABLEPDUE    6
3765 #define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE)
3766 #define F_T3A_ENABLEPDUE    V_T3A_ENABLEPDUE(1U)
3767 
3768 #define S_ENABLEDEFER    5
3769 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
3770 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
3771 
3772 #define S_ENABLECLEARRXMTOOS    4
3773 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
3774 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
3775 
3776 #define S_DISABLEPDUCNG    3
3777 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
3778 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
3779 
3780 #define S_DISABLEPDUTIMEOUT    2
3781 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
3782 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
3783 
3784 #define S_DISABLEPDURXMT    1
3785 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
3786 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
3787 
3788 #define S_DISABLEPDUXMT    0
3789 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
3790 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
3791 
3792 #define S_ENABLEDEFERACK    12
3793 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
3794 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
3795 
3796 #define S_ENABLEESND    11
3797 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
3798 #define F_ENABLEESND    V_ENABLEESND(1U)
3799 
3800 #define S_ENABLECSND    10
3801 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
3802 #define F_ENABLECSND    V_ENABLECSND(1U)
3803 
3804 #define S_ENABLEPDUE    9
3805 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
3806 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
3807 
3808 #define S_ENABLEBUFI    7
3809 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
3810 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
3811 
3812 #define S_ENABLEBUFE    6
3813 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
3814 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
3815 
3816 #define A_TP_PARA_REG7 0x37c
3817 
3818 #define S_PMMAXXFERLEN1    16
3819 #define M_PMMAXXFERLEN1    0xffff
3820 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
3821 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
3822 
3823 #define S_PMMAXXFERLEN0    0
3824 #define M_PMMAXXFERLEN0    0xffff
3825 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
3826 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
3827 
3828 #define A_TP_TIMER_RESOLUTION 0x390
3829 
3830 #define S_TIMERRESOLUTION    16
3831 #define M_TIMERRESOLUTION    0xff
3832 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
3833 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
3834 
3835 #define S_TIMESTAMPRESOLUTION    8
3836 #define M_TIMESTAMPRESOLUTION    0xff
3837 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
3838 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
3839 
3840 #define S_DELAYEDACKRESOLUTION    0
3841 #define M_DELAYEDACKRESOLUTION    0xff
3842 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
3843 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
3844 
3845 #define A_TP_MSL 0x394
3846 
3847 #define S_MSL    0
3848 #define M_MSL    0x3fffffff
3849 #define V_MSL(x) ((x) << S_MSL)
3850 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
3851 
3852 #define A_TP_RXT_MIN 0x398
3853 
3854 #define S_RXTMIN    0
3855 #define M_RXTMIN    0x3fffffff
3856 #define V_RXTMIN(x) ((x) << S_RXTMIN)
3857 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
3858 
3859 #define A_TP_RXT_MAX 0x39c
3860 
3861 #define S_RXTMAX    0
3862 #define M_RXTMAX    0x3fffffff
3863 #define V_RXTMAX(x) ((x) << S_RXTMAX)
3864 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
3865 
3866 #define A_TP_PERS_MIN 0x3a0
3867 
3868 #define S_PERSMIN    0
3869 #define M_PERSMIN    0x3fffffff
3870 #define V_PERSMIN(x) ((x) << S_PERSMIN)
3871 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
3872 
3873 #define A_TP_PERS_MAX 0x3a4
3874 
3875 #define S_PERSMAX    0
3876 #define M_PERSMAX    0x3fffffff
3877 #define V_PERSMAX(x) ((x) << S_PERSMAX)
3878 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
3879 
3880 #define A_TP_KEEP_IDLE 0x3a8
3881 
3882 #define S_KEEPALIVEIDLE    0
3883 #define M_KEEPALIVEIDLE    0x3fffffff
3884 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
3885 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
3886 
3887 #define A_TP_KEEP_INTVL 0x3ac
3888 
3889 #define S_KEEPALIVEINTVL    0
3890 #define M_KEEPALIVEINTVL    0x3fffffff
3891 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
3892 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
3893 
3894 #define A_TP_INIT_SRTT 0x3b0
3895 
3896 #define S_INITSRTT    0
3897 #define M_INITSRTT    0xffff
3898 #define V_INITSRTT(x) ((x) << S_INITSRTT)
3899 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
3900 
3901 #define A_TP_DACK_TIMER 0x3b4
3902 
3903 #define S_DACKTIME    0
3904 #define M_DACKTIME    0xfff
3905 #define V_DACKTIME(x) ((x) << S_DACKTIME)
3906 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
3907 
3908 #define A_TP_FINWAIT2_TIMER 0x3b8
3909 
3910 #define S_FINWAIT2TIME    0
3911 #define M_FINWAIT2TIME    0x3fffffff
3912 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
3913 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
3914 
3915 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc
3916 
3917 #define S_FASTFINWAIT2TIME    0
3918 #define M_FASTFINWAIT2TIME    0x3fffffff
3919 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
3920 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
3921 
3922 #define A_TP_SHIFT_CNT 0x3c0
3923 
3924 #define S_SYNSHIFTMAX    24
3925 #define M_SYNSHIFTMAX    0xff
3926 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
3927 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
3928 
3929 #define S_RXTSHIFTMAXR1    20
3930 #define M_RXTSHIFTMAXR1    0xf
3931 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
3932 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
3933 
3934 #define S_RXTSHIFTMAXR2    16
3935 #define M_RXTSHIFTMAXR2    0xf
3936 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
3937 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
3938 
3939 #define S_PERSHIFTBACKOFFMAX    12
3940 #define M_PERSHIFTBACKOFFMAX    0xf
3941 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
3942 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
3943 
3944 #define S_PERSHIFTMAX    8
3945 #define M_PERSHIFTMAX    0xf
3946 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
3947 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
3948 
3949 #define S_KEEPALIVEMAX    0
3950 #define M_KEEPALIVEMAX    0xff
3951 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
3952 #define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX)
3953 
3954 #define A_TP_TIME_HI 0x3c8
3955 #define A_TP_TIME_LO 0x3cc
3956 #define A_TP_MTU_PORT_TABLE 0x3d0
3957 
3958 #define S_PORT1MTUVALUE    16
3959 #define M_PORT1MTUVALUE    0xffff
3960 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
3961 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
3962 
3963 #define S_PORT0MTUVALUE    0
3964 #define M_PORT0MTUVALUE    0xffff
3965 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
3966 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
3967 
3968 #define A_TP_ULP_TABLE 0x3d4
3969 
3970 #define S_ULPTYPE7FIELD    28
3971 #define M_ULPTYPE7FIELD    0xf
3972 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
3973 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
3974 
3975 #define S_ULPTYPE6FIELD    24
3976 #define M_ULPTYPE6FIELD    0xf
3977 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
3978 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
3979 
3980 #define S_ULPTYPE5FIELD    20
3981 #define M_ULPTYPE5FIELD    0xf
3982 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
3983 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
3984 
3985 #define S_ULPTYPE4FIELD    16
3986 #define M_ULPTYPE4FIELD    0xf
3987 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
3988 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
3989 
3990 #define S_ULPTYPE3FIELD    12
3991 #define M_ULPTYPE3FIELD    0xf
3992 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
3993 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
3994 
3995 #define S_ULPTYPE2FIELD    8
3996 #define M_ULPTYPE2FIELD    0xf
3997 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
3998 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
3999 
4000 #define S_ULPTYPE1FIELD    4
4001 #define M_ULPTYPE1FIELD    0xf
4002 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
4003 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
4004 
4005 #define S_ULPTYPE0FIELD    0
4006 #define M_ULPTYPE0FIELD    0xf
4007 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
4008 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
4009 
4010 #define A_TP_PACE_TABLE 0x3d8
4011 #define A_TP_CCTRL_TABLE 0x3dc
4012 #define A_TP_TOS_TABLE 0x3e0
4013 #define A_TP_MTU_TABLE 0x3e4
4014 #define A_TP_RSS_MAP_TABLE 0x3e8
4015 #define A_TP_RSS_LKP_TABLE 0x3ec
4016 #define A_TP_RSS_CONFIG 0x3f0
4017 
4018 #define S_TNL4TUPEN    29
4019 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
4020 #define F_TNL4TUPEN    V_TNL4TUPEN(1U)
4021 
4022 #define S_TNL2TUPEN    28
4023 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
4024 #define F_TNL2TUPEN    V_TNL2TUPEN(1U)
4025 
4026 #define S_TNLPRTEN    26
4027 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
4028 #define F_TNLPRTEN    V_TNLPRTEN(1U)
4029 
4030 #define S_TNLMAPEN    25
4031 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
4032 #define F_TNLMAPEN    V_TNLMAPEN(1U)
4033 
4034 #define S_TNLLKPEN    24
4035 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
4036 #define F_TNLLKPEN    V_TNLLKPEN(1U)
4037 
4038 #define S_OFD4TUPEN    21
4039 #define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN)
4040 #define F_OFD4TUPEN    V_OFD4TUPEN(1U)
4041 
4042 #define S_OFD2TUPEN    20
4043 #define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN)
4044 #define F_OFD2TUPEN    V_OFD2TUPEN(1U)
4045 
4046 #define S_OFDMAPEN    17
4047 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
4048 #define F_OFDMAPEN    V_OFDMAPEN(1U)
4049 
4050 #define S_OFDLKPEN    16
4051 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
4052 #define F_OFDLKPEN    V_OFDLKPEN(1U)
4053 
4054 #define S_SYN4TUPEN    13
4055 #define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN)
4056 #define F_SYN4TUPEN    V_SYN4TUPEN(1U)
4057 
4058 #define S_SYN2TUPEN    12
4059 #define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN)
4060 #define F_SYN2TUPEN    V_SYN2TUPEN(1U)
4061 
4062 #define S_SYNMAPEN    9
4063 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
4064 #define F_SYNMAPEN    V_SYNMAPEN(1U)
4065 
4066 #define S_SYNLKPEN    8
4067 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
4068 #define F_SYNLKPEN    V_SYNLKPEN(1U)
4069 
4070 #define S_RRCPLMAPEN    7
4071 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
4072 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
4073 
4074 #define S_RRCPLCPUSIZE    4
4075 #define M_RRCPLCPUSIZE    0x7
4076 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
4077 #define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE)
4078 
4079 #define S_RQFEEDBACKENABLE    3
4080 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
4081 #define F_RQFEEDBACKENABLE    V_RQFEEDBACKENABLE(1U)
4082 
4083 #define S_HASHTOEPLITZ    2
4084 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
4085 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
4086 
4087 #define S_HASHSAVE    1
4088 #define V_HASHSAVE(x) ((x) << S_HASHSAVE)
4089 #define F_HASHSAVE    V_HASHSAVE(1U)
4090 
4091 #define S_DISABLE    0
4092 #define V_DISABLE(x) ((x) << S_DISABLE)
4093 #define F_DISABLE    V_DISABLE(1U)
4094 
4095 #define A_TP_RSS_CONFIG_TNL 0x3f4
4096 
4097 #define S_MASKSIZE    28
4098 #define M_MASKSIZE    0x7
4099 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
4100 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
4101 
4102 #define S_DEFAULTCPUBASE    22
4103 #define M_DEFAULTCPUBASE    0x3f
4104 #define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE)
4105 #define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE)
4106 
4107 #define S_DEFAULTCPU    16
4108 #define M_DEFAULTCPU    0x3f
4109 #define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU)
4110 #define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU)
4111 
4112 #define S_DEFAULTQUEUE    0
4113 #define M_DEFAULTQUEUE    0xffff
4114 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
4115 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
4116 
4117 #define A_TP_RSS_CONFIG_OFD 0x3f8
4118 #define A_TP_RSS_CONFIG_SYN 0x3fc
4119 #define A_TP_RSS_SECRET_KEY0 0x400
4120 #define A_TP_RSS_SECRET_KEY1 0x404
4121 #define A_TP_RSS_SECRET_KEY2 0x408
4122 #define A_TP_RSS_SECRET_KEY3 0x40c
4123 #define A_TP_TM_PIO_ADDR 0x418
4124 #define A_TP_TM_PIO_DATA 0x41c
4125 #define A_TP_TX_MOD_QUE_TABLE 0x420
4126 #define A_TP_TX_RESOURCE_LIMIT 0x424
4127 
4128 #define S_TX_RESOURCE_LIMIT_CH1_PC    24
4129 #define M_TX_RESOURCE_LIMIT_CH1_PC    0xff
4130 #define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC)
4131 #define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC)
4132 
4133 #define S_TX_RESOURCE_LIMIT_CH1_NON_PC    16
4134 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC    0xff
4135 #define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC)
4136 #define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC)
4137 
4138 #define S_TX_RESOURCE_LIMIT_CH0_PC    8
4139 #define M_TX_RESOURCE_LIMIT_CH0_PC    0xff
4140 #define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC)
4141 #define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC)
4142 
4143 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC    0
4144 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC    0xff
4145 #define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC)
4146 #define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC)
4147 
4148 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
4149 
4150 #define S_RX_MOD_WEIGHT    24
4151 #define M_RX_MOD_WEIGHT    0xff
4152 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
4153 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
4154 
4155 #define S_TX_MOD_WEIGHT    16
4156 #define M_TX_MOD_WEIGHT    0xff
4157 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
4158 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
4159 
4160 #define S_TX_MOD_TIMER_MODE    8
4161 #define M_TX_MOD_TIMER_MODE    0xff
4162 #define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE)
4163 #define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE)
4164 
4165 #define S_TX_MOD_QUEUE_REQ_MAP    0
4166 #define M_TX_MOD_QUEUE_REQ_MAP    0xff
4167 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
4168 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
4169 
4170 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
4171 
4172 #define S_TP_TX_MODQ_WGHT7    24
4173 #define M_TP_TX_MODQ_WGHT7    0xff
4174 #define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7)
4175 #define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7)
4176 
4177 #define S_TP_TX_MODQ_WGHT6    16
4178 #define M_TP_TX_MODQ_WGHT6    0xff
4179 #define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6)
4180 #define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6)
4181 
4182 #define S_TP_TX_MODQ_WGHT5    8
4183 #define M_TP_TX_MODQ_WGHT5    0xff
4184 #define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5)
4185 #define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5)
4186 
4187 #define S_TP_TX_MODQ_WGHT4    0
4188 #define M_TP_TX_MODQ_WGHT4    0xff
4189 #define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4)
4190 #define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4)
4191 
4192 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
4193 
4194 #define S_TP_TX_MODQ_WGHT3    24
4195 #define M_TP_TX_MODQ_WGHT3    0xff
4196 #define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3)
4197 #define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3)
4198 
4199 #define S_TP_TX_MODQ_WGHT2    16
4200 #define M_TP_TX_MODQ_WGHT2    0xff
4201 #define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2)
4202 #define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2)
4203 
4204 #define S_TP_TX_MODQ_WGHT1    8
4205 #define M_TP_TX_MODQ_WGHT1    0xff
4206 #define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1)
4207 #define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1)
4208 
4209 #define S_TP_TX_MODQ_WGHT0    0
4210 #define M_TP_TX_MODQ_WGHT0    0xff
4211 #define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0)
4212 #define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0)
4213 
4214 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
4215 
4216 #define S_RX_MOD_CHANNEL_WEIGHT1    24
4217 #define M_RX_MOD_CHANNEL_WEIGHT1    0xff
4218 #define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1)
4219 #define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1)
4220 
4221 #define S_RX_MOD_CHANNEL_WEIGHT0    16
4222 #define M_RX_MOD_CHANNEL_WEIGHT0    0xff
4223 #define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0)
4224 #define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0)
4225 
4226 #define S_TX_MOD_CHANNEL_WEIGHT1    8
4227 #define M_TX_MOD_CHANNEL_WEIGHT1    0xff
4228 #define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1)
4229 #define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1)
4230 
4231 #define S_TX_MOD_CHANNEL_WEIGHT0    0
4232 #define M_TX_MOD_CHANNEL_WEIGHT0    0xff
4233 #define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0)
4234 #define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0)
4235 
4236 #define A_TP_MOD_RATE_LIMIT 0x438
4237 
4238 #define S_RX_MOD_RATE_LIMIT_INC    24
4239 #define M_RX_MOD_RATE_LIMIT_INC    0xff
4240 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
4241 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
4242 
4243 #define S_RX_MOD_RATE_LIMIT_TICK    16
4244 #define M_RX_MOD_RATE_LIMIT_TICK    0xff
4245 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
4246 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
4247 
4248 #define S_TX_MOD_RATE_LIMIT_INC    8
4249 #define M_TX_MOD_RATE_LIMIT_INC    0xff
4250 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
4251 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
4252 
4253 #define S_TX_MOD_RATE_LIMIT_TICK    0
4254 #define M_TX_MOD_RATE_LIMIT_TICK    0xff
4255 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
4256 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
4257 
4258 #define A_TP_PIO_ADDR 0x440
4259 #define A_TP_PIO_DATA 0x444
4260 #define A_TP_RESET 0x44c
4261 
4262 #define S_FLSTINITENABLE    1
4263 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
4264 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
4265 
4266 #define S_TPRESET    0
4267 #define V_TPRESET(x) ((x) << S_TPRESET)
4268 #define F_TPRESET    V_TPRESET(1U)
4269 
4270 #define A_TP_MIB_INDEX 0x450
4271 #define A_TP_MIB_RDATA 0x454
4272 #define A_TP_SYNC_TIME_HI 0x458
4273 #define A_TP_SYNC_TIME_LO 0x45c
4274 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
4275 
4276 #define S_CMRXFLSTBASE    0
4277 #define M_CMRXFLSTBASE    0xfffffff
4278 #define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE)
4279 #define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE)
4280 
4281 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
4282 
4283 #define S_CMTXFLSTBASE    0
4284 #define M_CMTXFLSTBASE    0xfffffff
4285 #define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE)
4286 #define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE)
4287 
4288 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
4289 
4290 #define S_CMPSFLSTBASE    0
4291 #define M_CMPSFLSTBASE    0xfffffff
4292 #define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE)
4293 #define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE)
4294 
4295 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
4296 
4297 #define S_CMMAXPSTRUCT    0
4298 #define M_CMMAXPSTRUCT    0x1fffff
4299 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
4300 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
4301 
4302 #define A_TP_INT_ENABLE 0x470
4303 #define A_TP_INT_CAUSE 0x474
4304 #define A_TP_FLM_FREE_PS_CNT 0x480
4305 
4306 #define S_FREEPSTRUCTCOUNT    0
4307 #define M_FREEPSTRUCTCOUNT    0x1fffff
4308 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
4309 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
4310 
4311 #define A_TP_FLM_FREE_RX_CNT 0x484
4312 
4313 #define S_FREERXPAGECOUNT    0
4314 #define M_FREERXPAGECOUNT    0x1fffff
4315 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
4316 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
4317 
4318 #define A_TP_FLM_FREE_TX_CNT 0x488
4319 
4320 #define S_FREETXPAGECOUNT    0
4321 #define M_FREETXPAGECOUNT    0x1fffff
4322 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
4323 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
4324 
4325 #define A_TP_TM_HEAP_PUSH_CNT 0x48c
4326 #define A_TP_TM_HEAP_POP_CNT 0x490
4327 #define A_TP_TM_DACK_PUSH_CNT 0x494
4328 #define A_TP_TM_DACK_POP_CNT 0x498
4329 #define A_TP_TM_MOD_PUSH_CNT 0x49c
4330 #define A_TP_MOD_POP_CNT 0x4a0
4331 #define A_TP_TIMER_SEPARATOR 0x4a4
4332 #define A_TP_DEBUG_SEL 0x4a8
4333 #define A_TP_DEBUG_FLAGS 0x4ac
4334 
4335 #define S_RXDEBUGFLAGS    16
4336 #define M_RXDEBUGFLAGS    0xffff
4337 #define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS)
4338 #define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS)
4339 
4340 #define S_TXDEBUGFLAGS    0
4341 #define M_TXDEBUGFLAGS    0xffff
4342 #define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS)
4343 #define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS)
4344 
4345 #define S_RXTIMERDACKFIRST    26
4346 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
4347 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
4348 
4349 #define S_RXTIMERDACK    25
4350 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
4351 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
4352 
4353 #define S_RXTIMERHEARTBEAT    24
4354 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
4355 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
4356 
4357 #define S_RXPAWSDROP    23
4358 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
4359 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
4360 
4361 #define S_RXURGDATADROP    22
4362 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
4363 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
4364 
4365 #define S_RXFUTUREDATA    21
4366 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
4367 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
4368 
4369 #define S_RXRCVRXMDATA    20
4370 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
4371 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
4372 
4373 #define S_RXRCVOOODATAFIN    19
4374 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
4375 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
4376 
4377 #define S_RXRCVOOODATA    18
4378 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
4379 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
4380 
4381 #define S_RXRCVWNDZERO    17
4382 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
4383 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
4384 
4385 #define S_RXRCVWNDLTMSS    16
4386 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
4387 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
4388 
4389 #define S_TXDUPACKINC    11
4390 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
4391 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
4392 
4393 #define S_TXRXMURG    10
4394 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
4395 #define F_TXRXMURG    V_TXRXMURG(1U)
4396 
4397 #define S_TXRXMFIN    9
4398 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
4399 #define F_TXRXMFIN    V_TXRXMFIN(1U)
4400 
4401 #define S_TXRXMSYN    8
4402 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
4403 #define F_TXRXMSYN    V_TXRXMSYN(1U)
4404 
4405 #define S_TXRXMNEWRENO    7
4406 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
4407 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
4408 
4409 #define S_TXRXMFAST    6
4410 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
4411 #define F_TXRXMFAST    V_TXRXMFAST(1U)
4412 
4413 #define S_TXRXMTIMER    5
4414 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
4415 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
4416 
4417 #define S_TXRXMTIMERKEEPALIVE    4
4418 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
4419 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
4420 
4421 #define S_TXRXMTIMERPERSIST    3
4422 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
4423 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
4424 
4425 #define S_TXRCVADVSHRUNK    2
4426 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
4427 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
4428 
4429 #define S_TXRCVADVZERO    1
4430 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
4431 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
4432 
4433 #define S_TXRCVADVLTMSS    0
4434 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
4435 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
4436 
4437 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0
4438 
4439 #define S_CMFLOWCACHEDISABLE    0
4440 #define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE)
4441 #define F_CMFLOWCACHEDISABLE    V_CMFLOWCACHEDISABLE(1U)
4442 
4443 #define A_TP_PROXY_FLOW_CNTL 0x4b0
4444 #define A_TP_PC_CONGESTION_CNTL 0x4b4
4445 
4446 #define S_EDROPTUNNEL    19
4447 #define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL)
4448 #define F_EDROPTUNNEL    V_EDROPTUNNEL(1U)
4449 
4450 #define S_CDROPTUNNEL    18
4451 #define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL)
4452 #define F_CDROPTUNNEL    V_CDROPTUNNEL(1U)
4453 
4454 #define S_ETHRESHOLD    12
4455 #define M_ETHRESHOLD    0x3f
4456 #define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD)
4457 #define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD)
4458 
4459 #define S_CTHRESHOLD    6
4460 #define M_CTHRESHOLD    0x3f
4461 #define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD)
4462 #define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD)
4463 
4464 #define S_TXTHRESHOLD    0
4465 #define M_TXTHRESHOLD    0x3f
4466 #define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD)
4467 #define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD)
4468 
4469 #define A_TP_TX_DROP_COUNT 0x4bc
4470 #define A_TP_CLEAR_DEBUG 0x4c0
4471 
4472 #define S_CLRDEBUG    0
4473 #define V_CLRDEBUG(x) ((x) << S_CLRDEBUG)
4474 #define F_CLRDEBUG    V_CLRDEBUG(1U)
4475 
4476 #define A_TP_DEBUG_VEC 0x4c4
4477 #define A_TP_DEBUG_VEC2 0x4c8
4478 #define A_TP_DEBUG_REG_SEL 0x4cc
4479 #define A_TP_DEBUG 0x4d0
4480 #define A_TP_DBG_LA_CONFIG 0x4d4
4481 #define A_TP_DBG_LA_DATAH 0x4d8
4482 #define A_TP_DBG_LA_DATAL 0x4dc
4483 #define A_TP_EMBED_OP_FIELD0 0x4e8
4484 #define A_TP_EMBED_OP_FIELD1 0x4ec
4485 #define A_TP_EMBED_OP_FIELD2 0x4f0
4486 #define A_TP_EMBED_OP_FIELD3 0x4f4
4487 #define A_TP_EMBED_OP_FIELD4 0x4f8
4488 #define A_TP_EMBED_OP_FIELD5 0x4fc
4489 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
4490 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
4491 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
4492 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
4493 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
4494 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
4495 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
4496 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
4497 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
4498 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
4499 #define A_TP_TX_TRC_KEY0 0x20
4500 #define A_TP_TX_TRC_MASK0 0x21
4501 #define A_TP_TX_TRC_KEY1 0x22
4502 #define A_TP_TX_TRC_MASK1 0x23
4503 #define A_TP_TX_TRC_KEY2 0x24
4504 #define A_TP_TX_TRC_MASK2 0x25
4505 #define A_TP_TX_TRC_KEY3 0x26
4506 #define A_TP_TX_TRC_MASK3 0x27
4507 #define A_TP_IPMI_CFG1 0x28
4508 
4509 #define S_VLANENABLE    31
4510 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
4511 #define F_VLANENABLE    V_VLANENABLE(1U)
4512 
4513 #define S_PRIMARYPORTENABLE    30
4514 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
4515 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
4516 
4517 #define S_SECUREPORTENABLE    29
4518 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
4519 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
4520 
4521 #define S_ARPENABLE    28
4522 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
4523 #define F_ARPENABLE    V_ARPENABLE(1U)
4524 
4525 #define S_VLAN    0
4526 #define M_VLAN    0xffff
4527 #define V_VLAN(x) ((x) << S_VLAN)
4528 #define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN)
4529 
4530 #define A_TP_IPMI_CFG2 0x29
4531 
4532 #define S_SECUREPORT    16
4533 #define M_SECUREPORT    0xffff
4534 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
4535 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
4536 
4537 #define S_PRIMARYPORT    0
4538 #define M_PRIMARYPORT    0xffff
4539 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
4540 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
4541 
4542 #define A_TP_RX_TRC_KEY0 0x120
4543 #define A_TP_RX_TRC_MASK0 0x121
4544 #define A_TP_RX_TRC_KEY1 0x122
4545 #define A_TP_RX_TRC_MASK1 0x123
4546 #define A_TP_RX_TRC_KEY2 0x124
4547 #define A_TP_RX_TRC_MASK2 0x125
4548 #define A_TP_RX_TRC_KEY3 0x126
4549 #define A_TP_RX_TRC_MASK3 0x127
4550 #define A_TP_QOS_RX_TOS_MAP_H 0x128
4551 #define A_TP_QOS_RX_TOS_MAP_L 0x129
4552 #define A_TP_QOS_RX_MAP_MODE 0x12a
4553 
4554 #define S_DEFAULTCH    11
4555 #define V_DEFAULTCH(x) ((x) << S_DEFAULTCH)
4556 #define F_DEFAULTCH    V_DEFAULTCH(1U)
4557 
4558 #define S_RXMAPMODE    8
4559 #define M_RXMAPMODE    0x7
4560 #define V_RXMAPMODE(x) ((x) << S_RXMAPMODE)
4561 #define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE)
4562 
4563 #define S_RXVLANMAP    7
4564 #define V_RXVLANMAP(x) ((x) << S_RXVLANMAP)
4565 #define F_RXVLANMAP    V_RXVLANMAP(1U)
4566 
4567 #define A_TP_TX_DROP_CFG_CH0 0x12b
4568 
4569 #define S_TIMERENABLED    31
4570 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
4571 #define F_TIMERENABLED    V_TIMERENABLED(1U)
4572 
4573 #define S_TIMERERRORENABLE    30
4574 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
4575 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
4576 
4577 #define S_TIMERTHRESHOLD    4
4578 #define M_TIMERTHRESHOLD    0x3ffffff
4579 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
4580 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
4581 
4582 #define S_PACKETDROPS    0
4583 #define M_PACKETDROPS    0xf
4584 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
4585 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
4586 
4587 #define A_TP_TX_DROP_CFG_CH1 0x12c
4588 #define A_TP_TX_DROP_CNT_CH0 0x12d
4589 
4590 #define S_TXDROPCNTCH0SENT    16
4591 #define M_TXDROPCNTCH0SENT    0xffff
4592 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
4593 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
4594 
4595 #define S_TXDROPCNTCH0RCVD    0
4596 #define M_TXDROPCNTCH0RCVD    0xffff
4597 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
4598 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
4599 
4600 #define A_TP_TX_DROP_CNT_CH1 0x12e
4601 
4602 #define S_TXDROPCNTCH1SENT    16
4603 #define M_TXDROPCNTCH1SENT    0xffff
4604 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
4605 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
4606 
4607 #define S_TXDROPCNTCH1RCVD    0
4608 #define M_TXDROPCNTCH1RCVD    0xffff
4609 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
4610 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
4611 
4612 #define A_TP_TX_DROP_MODE 0x12f
4613 
4614 #define S_TXDROPMODECH1    1
4615 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
4616 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
4617 
4618 #define S_TXDROPMODECH0    0
4619 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
4620 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
4621 
4622 #define A_TP_VLAN_PRI_MAP 0x137
4623 
4624 #define S_VLANPRIMAP7    14
4625 #define M_VLANPRIMAP7    0x3
4626 #define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7)
4627 #define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7)
4628 
4629 #define S_VLANPRIMAP6    12
4630 #define M_VLANPRIMAP6    0x3
4631 #define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6)
4632 #define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6)
4633 
4634 #define S_VLANPRIMAP5    10
4635 #define M_VLANPRIMAP5    0x3
4636 #define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5)
4637 #define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5)
4638 
4639 #define S_VLANPRIMAP4    8
4640 #define M_VLANPRIMAP4    0x3
4641 #define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4)
4642 #define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4)
4643 
4644 #define S_VLANPRIMAP3    6
4645 #define M_VLANPRIMAP3    0x3
4646 #define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3)
4647 #define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3)
4648 
4649 #define S_VLANPRIMAP2    4
4650 #define M_VLANPRIMAP2    0x3
4651 #define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2)
4652 #define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2)
4653 
4654 #define S_VLANPRIMAP1    2
4655 #define M_VLANPRIMAP1    0x3
4656 #define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1)
4657 #define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1)
4658 
4659 #define S_VLANPRIMAP0    0
4660 #define M_VLANPRIMAP0    0x3
4661 #define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0)
4662 #define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0)
4663 
4664 #define A_TP_MAC_MATCH_MAP0 0x138
4665 
4666 #define S_MACMATCHMAP7    21
4667 #define M_MACMATCHMAP7    0x7
4668 #define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7)
4669 #define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7)
4670 
4671 #define S_MACMATCHMAP6    18
4672 #define M_MACMATCHMAP6    0x7
4673 #define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6)
4674 #define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6)
4675 
4676 #define S_MACMATCHMAP5    15
4677 #define M_MACMATCHMAP5    0x7
4678 #define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5)
4679 #define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5)
4680 
4681 #define S_MACMATCHMAP4    12
4682 #define M_MACMATCHMAP4    0x7
4683 #define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4)
4684 #define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4)
4685 
4686 #define S_MACMATCHMAP3    9
4687 #define M_MACMATCHMAP3    0x7
4688 #define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3)
4689 #define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3)
4690 
4691 #define S_MACMATCHMAP2    6
4692 #define M_MACMATCHMAP2    0x7
4693 #define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2)
4694 #define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2)
4695 
4696 #define S_MACMATCHMAP1    3
4697 #define M_MACMATCHMAP1    0x7
4698 #define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1)
4699 #define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1)
4700 
4701 #define S_MACMATCHMAP0    0
4702 #define M_MACMATCHMAP0    0x7
4703 #define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0)
4704 #define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0)
4705 
4706 #define A_TP_MAC_MATCH_MAP1 0x139
4707 #define A_TP_INGRESS_CONFIG 0x141
4708 
4709 #define S_LOOKUPEVERYPKT    28
4710 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
4711 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
4712 
4713 #define S_ENABLEINSERTIONSFD    27
4714 #define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD)
4715 #define F_ENABLEINSERTIONSFD    V_ENABLEINSERTIONSFD(1U)
4716 
4717 #define S_ENABLEINSERTION    26
4718 #define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION)
4719 #define F_ENABLEINSERTION    V_ENABLEINSERTION(1U)
4720 
4721 #define S_ENABLEEXTRACTIONSFD    25
4722 #define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD)
4723 #define F_ENABLEEXTRACTIONSFD    V_ENABLEEXTRACTIONSFD(1U)
4724 
4725 #define S_ENABLEEXTRACT    24
4726 #define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT)
4727 #define F_ENABLEEXTRACT    V_ENABLEEXTRACT(1U)
4728 
4729 #define S_BITPOS3    18
4730 #define M_BITPOS3    0x3f
4731 #define V_BITPOS3(x) ((x) << S_BITPOS3)
4732 #define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3)
4733 
4734 #define S_BITPOS2    12
4735 #define M_BITPOS2    0x3f
4736 #define V_BITPOS2(x) ((x) << S_BITPOS2)
4737 #define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2)
4738 
4739 #define S_BITPOS1    6
4740 #define M_BITPOS1    0x3f
4741 #define V_BITPOS1(x) ((x) << S_BITPOS1)
4742 #define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1)
4743 
4744 #define S_BITPOS0    0
4745 #define M_BITPOS0    0x3f
4746 #define V_BITPOS0(x) ((x) << S_BITPOS0)
4747 #define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0)
4748 
4749 #define A_TP_PREAMBLE_MSB 0x142
4750 #define A_TP_PREAMBLE_LSB 0x143
4751 #define A_TP_EGRESS_CONFIG 0x145
4752 
4753 #define S_REWRITEFORCETOSIZE    0
4754 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
4755 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
4756 
4757 #define A_TP_INTF_FROM_TX_PKT 0x244
4758 
4759 #define S_INTFFROMTXPKT    0
4760 #define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT)
4761 #define F_INTFFROMTXPKT    V_INTFFROMTXPKT(1U)
4762 
4763 #define A_TP_FIFO_CONFIG 0x8c0
4764 
4765 #define S_RXFIFOCONFIG    10
4766 #define M_RXFIFOCONFIG    0x3f
4767 #define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG)
4768 #define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG)
4769 
4770 #define S_TXFIFOCONFIG    2
4771 #define M_TXFIFOCONFIG    0x3f
4772 #define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG)
4773 #define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG)
4774 
4775 /* registers for module ULP2_RX */
4776 #define ULP2_RX_BASE_ADDR 0x500
4777 
4778 #define A_ULPRX_CTL 0x500
4779 
4780 #define S_PCMD1THRESHOLD    24
4781 #define M_PCMD1THRESHOLD    0xff
4782 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
4783 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
4784 
4785 #define S_PCMD0THRESHOLD    16
4786 #define M_PCMD0THRESHOLD    0xff
4787 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
4788 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
4789 
4790 #define S_ROUND_ROBIN    4
4791 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
4792 #define F_ROUND_ROBIN    V_ROUND_ROBIN(1U)
4793 
4794 #define S_RDMA_PERMISSIVE_MODE    3
4795 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
4796 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
4797 
4798 #define S_PAGEPODME    2
4799 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
4800 #define F_PAGEPODME    V_PAGEPODME(1U)
4801 
4802 #define S_ISCSITAGTCB    1
4803 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
4804 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
4805 
4806 #define S_TDDPTAGTCB    0
4807 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
4808 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
4809 
4810 #define A_ULPRX_INT_ENABLE 0x504
4811 
4812 #define S_PARERR    0
4813 #define V_PARERR(x) ((x) << S_PARERR)
4814 #define F_PARERR    V_PARERR(1U)
4815 
4816 #define A_ULPRX_INT_CAUSE 0x508
4817 #define A_ULPRX_ISCSI_LLIMIT 0x50c
4818 
4819 #define S_ISCSILLIMIT    6
4820 #define M_ISCSILLIMIT    0x3ffffff
4821 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
4822 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
4823 
4824 #define A_ULPRX_ISCSI_ULIMIT 0x510
4825 
4826 #define S_ISCSIULIMIT    6
4827 #define M_ISCSIULIMIT    0x3ffffff
4828 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
4829 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
4830 
4831 #define A_ULPRX_ISCSI_TAGMASK 0x514
4832 
4833 #define S_ISCSITAGMASK    6
4834 #define M_ISCSITAGMASK    0x3ffffff
4835 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
4836 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
4837 
4838 #define A_ULPRX_ISCSI_PSZ 0x518
4839 
4840 #define S_HPZ3    24
4841 #define M_HPZ3    0xf
4842 #define V_HPZ3(x) ((x) << S_HPZ3)
4843 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
4844 
4845 #define S_HPZ2    16
4846 #define M_HPZ2    0xf
4847 #define V_HPZ2(x) ((x) << S_HPZ2)
4848 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
4849 
4850 #define S_HPZ1    8
4851 #define M_HPZ1    0xf
4852 #define V_HPZ1(x) ((x) << S_HPZ1)
4853 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
4854 
4855 #define S_HPZ0    0
4856 #define M_HPZ0    0xf
4857 #define V_HPZ0(x) ((x) << S_HPZ0)
4858 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
4859 
4860 #define A_ULPRX_TDDP_LLIMIT 0x51c
4861 
4862 #define S_TDDPLLIMIT    6
4863 #define M_TDDPLLIMIT    0x3ffffff
4864 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
4865 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
4866 
4867 #define A_ULPRX_TDDP_ULIMIT 0x520
4868 
4869 #define S_TDDPULIMIT    6
4870 #define M_TDDPULIMIT    0x3ffffff
4871 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
4872 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
4873 
4874 #define A_ULPRX_TDDP_TAGMASK 0x524
4875 
4876 #define S_TDDPTAGMASK    6
4877 #define M_TDDPTAGMASK    0x3ffffff
4878 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
4879 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
4880 
4881 #define A_ULPRX_TDDP_PSZ 0x528
4882 #define A_ULPRX_STAG_LLIMIT 0x52c
4883 #define A_ULPRX_STAG_ULIMIT 0x530
4884 #define A_ULPRX_RQ_LLIMIT 0x534
4885 #define A_ULPRX_RQ_ULIMIT 0x538
4886 #define A_ULPRX_PBL_LLIMIT 0x53c
4887 #define A_ULPRX_PBL_ULIMIT 0x540
4888 
4889 /* registers for module ULP2_TX */
4890 #define ULP2_TX_BASE_ADDR 0x580
4891 
4892 #define A_ULPTX_CONFIG 0x580
4893 
4894 #define S_CFG_RR_ARB    0
4895 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
4896 #define F_CFG_RR_ARB    V_CFG_RR_ARB(1U)
4897 
4898 #define A_ULPTX_INT_ENABLE 0x584
4899 
4900 #define S_PBL_BOUND_ERR_CH1    1
4901 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
4902 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
4903 
4904 #define S_PBL_BOUND_ERR_CH0    0
4905 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
4906 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
4907 
4908 #define A_ULPTX_INT_CAUSE 0x588
4909 #define A_ULPTX_TPT_LLIMIT 0x58c
4910 #define A_ULPTX_TPT_ULIMIT 0x590
4911 #define A_ULPTX_PBL_LLIMIT 0x594
4912 #define A_ULPTX_PBL_ULIMIT 0x598
4913 #define A_ULPTX_CPL_ERR_OFFSET 0x59c
4914 #define A_ULPTX_CPL_ERR_MASK 0x5a0
4915 #define A_ULPTX_CPL_ERR_VALUE 0x5a4
4916 #define A_ULPTX_CPL_PACK_SIZE 0x5a8
4917 
4918 #define S_VALUE    24
4919 #define M_VALUE    0xff
4920 #define V_VALUE(x) ((x) << S_VALUE)
4921 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
4922 
4923 #define S_CH1SIZE2    24
4924 #define M_CH1SIZE2    0xff
4925 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
4926 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
4927 
4928 #define S_CH1SIZE1    16
4929 #define M_CH1SIZE1    0xff
4930 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
4931 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
4932 
4933 #define S_CH0SIZE2    8
4934 #define M_CH0SIZE2    0xff
4935 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
4936 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
4937 
4938 #define S_CH0SIZE1    0
4939 #define M_CH0SIZE1    0xff
4940 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
4941 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
4942 
4943 #define A_ULPTX_DMA_WEIGHT 0x5ac
4944 
4945 #define S_D1_WEIGHT    16
4946 #define M_D1_WEIGHT    0xffff
4947 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
4948 #define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT)
4949 
4950 #define S_D0_WEIGHT    0
4951 #define M_D0_WEIGHT    0xffff
4952 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
4953 #define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT)
4954 
4955 /* registers for module PM1_RX */
4956 #define PM1_RX_BASE_ADDR 0x5c0
4957 
4958 #define A_PM1_RX_CFG 0x5c0
4959 #define A_PM1_RX_MODE 0x5c4
4960 
4961 #define S_STAT_CHANNEL    1
4962 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
4963 #define F_STAT_CHANNEL    V_STAT_CHANNEL(1U)
4964 
4965 #define S_PRIORITY_CH    0
4966 #define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH)
4967 #define F_PRIORITY_CH    V_PRIORITY_CH(1U)
4968 
4969 #define A_PM1_RX_STAT_CONFIG 0x5c8
4970 #define A_PM1_RX_STAT_COUNT 0x5cc
4971 #define A_PM1_RX_STAT_MSB 0x5d0
4972 #define A_PM1_RX_STAT_LSB 0x5d4
4973 #define A_PM1_RX_INT_ENABLE 0x5d8
4974 
4975 #define S_ZERO_E_CMD_ERROR    18
4976 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
4977 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
4978 
4979 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    17
4980 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
4981 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
4982 
4983 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    16
4984 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
4985 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
4986 
4987 #define S_IESPI0_RX_FRAMING_ERROR    15
4988 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
4989 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
4990 
4991 #define S_IESPI1_RX_FRAMING_ERROR    14
4992 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
4993 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
4994 
4995 #define S_IESPI0_TX_FRAMING_ERROR    13
4996 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
4997 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
4998 
4999 #define S_IESPI1_TX_FRAMING_ERROR    12
5000 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
5001 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
5002 
5003 #define S_OCSPI0_RX_FRAMING_ERROR    11
5004 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
5005 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
5006 
5007 #define S_OCSPI1_RX_FRAMING_ERROR    10
5008 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
5009 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
5010 
5011 #define S_OCSPI0_TX_FRAMING_ERROR    9
5012 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
5013 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
5014 
5015 #define S_OCSPI1_TX_FRAMING_ERROR    8
5016 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
5017 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
5018 
5019 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    7
5020 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
5021 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5022 
5023 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    6
5024 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
5025 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5026 
5027 #define S_IESPI_PAR_ERROR    3
5028 #define M_IESPI_PAR_ERROR    0x7
5029 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
5030 #define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR)
5031 
5032 #define S_OCSPI_PAR_ERROR    0
5033 #define M_OCSPI_PAR_ERROR    0x7
5034 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
5035 #define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR)
5036 
5037 #define A_PM1_RX_INT_CAUSE 0x5dc
5038 
5039 /* registers for module PM1_TX */
5040 #define PM1_TX_BASE_ADDR 0x5e0
5041 
5042 #define A_PM1_TX_CFG 0x5e0
5043 #define A_PM1_TX_MODE 0x5e4
5044 #define A_PM1_TX_STAT_CONFIG 0x5e8
5045 #define A_PM1_TX_STAT_COUNT 0x5ec
5046 #define A_PM1_TX_STAT_MSB 0x5f0
5047 #define A_PM1_TX_STAT_LSB 0x5f4
5048 #define A_PM1_TX_INT_ENABLE 0x5f8
5049 
5050 #define S_ZERO_C_CMD_ERROR    18
5051 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
5052 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
5053 
5054 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    17
5055 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
5056 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5057 
5058 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    16
5059 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
5060 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5061 
5062 #define S_ICSPI0_RX_FRAMING_ERROR    15
5063 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
5064 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
5065 
5066 #define S_ICSPI1_RX_FRAMING_ERROR    14
5067 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
5068 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
5069 
5070 #define S_ICSPI0_TX_FRAMING_ERROR    13
5071 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
5072 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
5073 
5074 #define S_ICSPI1_TX_FRAMING_ERROR    12
5075 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
5076 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
5077 
5078 #define S_OESPI0_RX_FRAMING_ERROR    11
5079 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
5080 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
5081 
5082 #define S_OESPI1_RX_FRAMING_ERROR    10
5083 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
5084 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
5085 
5086 #define S_OESPI0_TX_FRAMING_ERROR    9
5087 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
5088 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
5089 
5090 #define S_OESPI1_TX_FRAMING_ERROR    8
5091 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
5092 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
5093 
5094 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
5095 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
5096 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5097 
5098 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
5099 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
5100 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5101 
5102 #define S_ICSPI_PAR_ERROR    3
5103 #define M_ICSPI_PAR_ERROR    0x7
5104 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
5105 #define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR)
5106 
5107 #define S_OESPI_PAR_ERROR    0
5108 #define M_OESPI_PAR_ERROR    0x7
5109 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
5110 #define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR)
5111 
5112 #define A_PM1_TX_INT_CAUSE 0x5fc
5113 
5114 /* registers for module MPS0 */
5115 #define MPS0_BASE_ADDR 0x600
5116 
5117 #define A_MPS_CFG 0x600
5118 
5119 #define S_SGETPQID    8
5120 #define M_SGETPQID    0x7
5121 #define V_SGETPQID(x) ((x) << S_SGETPQID)
5122 #define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID)
5123 
5124 #define S_TPRXPORTSIZE    7
5125 #define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE)
5126 #define F_TPRXPORTSIZE    V_TPRXPORTSIZE(1U)
5127 
5128 #define S_TPTXPORT1SIZE    6
5129 #define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE)
5130 #define F_TPTXPORT1SIZE    V_TPTXPORT1SIZE(1U)
5131 
5132 #define S_TPTXPORT0SIZE    5
5133 #define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE)
5134 #define F_TPTXPORT0SIZE    V_TPTXPORT0SIZE(1U)
5135 
5136 #define S_TPRXPORTEN    4
5137 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
5138 #define F_TPRXPORTEN    V_TPRXPORTEN(1U)
5139 
5140 #define S_TPTXPORT1EN    3
5141 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
5142 #define F_TPTXPORT1EN    V_TPTXPORT1EN(1U)
5143 
5144 #define S_TPTXPORT0EN    2
5145 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
5146 #define F_TPTXPORT0EN    V_TPTXPORT0EN(1U)
5147 
5148 #define S_PORT1ACTIVE    1
5149 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
5150 #define F_PORT1ACTIVE    V_PORT1ACTIVE(1U)
5151 
5152 #define S_PORT0ACTIVE    0
5153 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
5154 #define F_PORT0ACTIVE    V_PORT0ACTIVE(1U)
5155 
5156 #define S_ENFORCEPKT    11
5157 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
5158 #define F_ENFORCEPKT    V_ENFORCEPKT(1U)
5159 
5160 #define A_MPS_DRR_CFG1 0x604
5161 
5162 #define S_RLDWTTPD1    11
5163 #define M_RLDWTTPD1    0x7ff
5164 #define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1)
5165 #define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1)
5166 
5167 #define S_RLDWTTPD0    0
5168 #define M_RLDWTTPD0    0x7ff
5169 #define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0)
5170 #define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0)
5171 
5172 #define A_MPS_DRR_CFG2 0x608
5173 
5174 #define S_RLDWTTOTAL    0
5175 #define M_RLDWTTOTAL    0xfff
5176 #define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL)
5177 #define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL)
5178 
5179 #define A_MPS_MCA_STATUS 0x60c
5180 
5181 #define S_MCAPKTCNT    12
5182 #define M_MCAPKTCNT    0xfffff
5183 #define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT)
5184 #define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT)
5185 
5186 #define S_MCADEPTH    0
5187 #define M_MCADEPTH    0xfff
5188 #define V_MCADEPTH(x) ((x) << S_MCADEPTH)
5189 #define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH)
5190 
5191 #define A_MPS_TX0_TP_CNT 0x610
5192 
5193 #define S_TX0TPDISCNT    24
5194 #define M_TX0TPDISCNT    0xff
5195 #define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT)
5196 #define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT)
5197 
5198 #define S_TX0TPCNT    0
5199 #define M_TX0TPCNT    0xffffff
5200 #define V_TX0TPCNT(x) ((x) << S_TX0TPCNT)
5201 #define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT)
5202 
5203 #define A_MPS_TX1_TP_CNT 0x614
5204 
5205 #define S_TX1TPDISCNT    24
5206 #define M_TX1TPDISCNT    0xff
5207 #define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT)
5208 #define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT)
5209 
5210 #define S_TX1TPCNT    0
5211 #define M_TX1TPCNT    0xffffff
5212 #define V_TX1TPCNT(x) ((x) << S_TX1TPCNT)
5213 #define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT)
5214 
5215 #define A_MPS_RX_TP_CNT 0x618
5216 
5217 #define S_RXTPDISCNT    24
5218 #define M_RXTPDISCNT    0xff
5219 #define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT)
5220 #define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT)
5221 
5222 #define S_RXTPCNT    0
5223 #define M_RXTPCNT    0xffffff
5224 #define V_RXTPCNT(x) ((x) << S_RXTPCNT)
5225 #define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT)
5226 
5227 #define A_MPS_INT_ENABLE 0x61c
5228 
5229 #define S_MCAPARERRENB    6
5230 #define M_MCAPARERRENB    0x7
5231 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
5232 #define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB)
5233 
5234 #define S_RXTPPARERRENB    4
5235 #define M_RXTPPARERRENB    0x3
5236 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
5237 #define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB)
5238 
5239 #define S_TX1TPPARERRENB    2
5240 #define M_TX1TPPARERRENB    0x3
5241 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
5242 #define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB)
5243 
5244 #define S_TX0TPPARERRENB    0
5245 #define M_TX0TPPARERRENB    0x3
5246 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
5247 #define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB)
5248 
5249 #define A_MPS_INT_CAUSE 0x620
5250 
5251 #define S_MCAPARERR    6
5252 #define M_MCAPARERR    0x7
5253 #define V_MCAPARERR(x) ((x) << S_MCAPARERR)
5254 #define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR)
5255 
5256 #define S_RXTPPARERR    4
5257 #define M_RXTPPARERR    0x3
5258 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
5259 #define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR)
5260 
5261 #define S_TX1TPPARERR    2
5262 #define M_TX1TPPARERR    0x3
5263 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
5264 #define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR)
5265 
5266 #define S_TX0TPPARERR    0
5267 #define M_TX0TPPARERR    0x3
5268 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
5269 #define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR)
5270 
5271 /* registers for module CPL_SWITCH */
5272 #define CPL_SWITCH_BASE_ADDR 0x640
5273 
5274 #define A_CPL_SWITCH_CNTRL 0x640
5275 
5276 #define S_CPL_PKT_TID    8
5277 #define M_CPL_PKT_TID    0xffffff
5278 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
5279 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
5280 
5281 #define S_CPU_NO_3F_CIM_ENABLE    3
5282 #define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE)
5283 #define F_CPU_NO_3F_CIM_ENABLE    V_CPU_NO_3F_CIM_ENABLE(1U)
5284 
5285 #define S_SWITCH_TABLE_ENABLE    2
5286 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
5287 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
5288 
5289 #define S_SGE_ENABLE    1
5290 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
5291 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
5292 
5293 #define S_CIM_ENABLE    0
5294 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
5295 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
5296 
5297 #define A_CPL_SWITCH_TBL_IDX 0x644
5298 
5299 #define S_SWITCH_TBL_IDX    0
5300 #define M_SWITCH_TBL_IDX    0xf
5301 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
5302 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
5303 
5304 #define A_CPL_SWITCH_TBL_DATA 0x648
5305 #define A_CPL_SWITCH_ZERO_ERROR 0x64c
5306 
5307 #define S_ZERO_CMD    0
5308 #define M_ZERO_CMD    0xff
5309 #define V_ZERO_CMD(x) ((x) << S_ZERO_CMD)
5310 #define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD)
5311 
5312 #define A_CPL_INTR_ENABLE 0x650
5313 
5314 #define S_CIM_OVFL_ERROR    4
5315 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
5316 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
5317 
5318 #define S_TP_FRAMING_ERROR    3
5319 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
5320 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
5321 
5322 #define S_SGE_FRAMING_ERROR    2
5323 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
5324 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
5325 
5326 #define S_CIM_FRAMING_ERROR    1
5327 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
5328 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
5329 
5330 #define S_ZERO_SWITCH_ERROR    0
5331 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
5332 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
5333 
5334 #define A_CPL_INTR_CAUSE 0x654
5335 #define A_CPL_MAP_TBL_IDX 0x658
5336 
5337 #define S_CPL_MAP_TBL_IDX    0
5338 #define M_CPL_MAP_TBL_IDX    0xff
5339 #define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX)
5340 #define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX)
5341 
5342 #define A_CPL_MAP_TBL_DATA 0x65c
5343 
5344 #define S_CPL_MAP_TBL_DATA    0
5345 #define M_CPL_MAP_TBL_DATA    0xff
5346 #define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA)
5347 #define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA)
5348 
5349 /* registers for module SMB0 */
5350 #define SMB0_BASE_ADDR 0x660
5351 
5352 #define A_SMB_GLOBAL_TIME_CFG 0x660
5353 
5354 #define S_LADBGWRPTR    24
5355 #define M_LADBGWRPTR    0xff
5356 #define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR)
5357 #define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR)
5358 
5359 #define S_LADBGRDPTR    16
5360 #define M_LADBGRDPTR    0xff
5361 #define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR)
5362 #define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR)
5363 
5364 #define S_LADBGEN    13
5365 #define V_LADBGEN(x) ((x) << S_LADBGEN)
5366 #define F_LADBGEN    V_LADBGEN(1U)
5367 
5368 #define S_MACROCNTCFG    8
5369 #define M_MACROCNTCFG    0x1f
5370 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
5371 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
5372 
5373 #define S_MICROCNTCFG    0
5374 #define M_MICROCNTCFG    0xff
5375 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
5376 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
5377 
5378 #define A_SMB_MST_TIMEOUT_CFG 0x664
5379 
5380 #define S_DEBUGSELH    28
5381 #define M_DEBUGSELH    0xf
5382 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
5383 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
5384 
5385 #define S_DEBUGSELL    24
5386 #define M_DEBUGSELL    0xf
5387 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
5388 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
5389 
5390 #define S_MSTTIMEOUTCFG    0
5391 #define M_MSTTIMEOUTCFG    0xffffff
5392 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
5393 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
5394 
5395 #define A_SMB_MST_CTL_CFG 0x668
5396 
5397 #define S_MSTFIFODBG    31
5398 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
5399 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
5400 
5401 #define S_MSTFIFODBGCLR    30
5402 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
5403 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
5404 
5405 #define S_MSTRXBYTECFG    12
5406 #define M_MSTRXBYTECFG    0x3f
5407 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
5408 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
5409 
5410 #define S_MSTTXBYTECFG    6
5411 #define M_MSTTXBYTECFG    0x3f
5412 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
5413 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
5414 
5415 #define S_MSTRESET    1
5416 #define V_MSTRESET(x) ((x) << S_MSTRESET)
5417 #define F_MSTRESET    V_MSTRESET(1U)
5418 
5419 #define S_MSTCTLEN    0
5420 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
5421 #define F_MSTCTLEN    V_MSTCTLEN(1U)
5422 
5423 #define A_SMB_MST_CTL_STS 0x66c
5424 
5425 #define S_MSTRXBYTECNT    12
5426 #define M_MSTRXBYTECNT    0x3f
5427 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
5428 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
5429 
5430 #define S_MSTTXBYTECNT    6
5431 #define M_MSTTXBYTECNT    0x3f
5432 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
5433 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
5434 
5435 #define S_MSTBUSYSTS    0
5436 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
5437 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
5438 
5439 #define A_SMB_MST_TX_FIFO_RDWR 0x670
5440 #define A_SMB_MST_RX_FIFO_RDWR 0x674
5441 #define A_SMB_SLV_TIMEOUT_CFG 0x678
5442 
5443 #define S_SLVTIMEOUTCFG    0
5444 #define M_SLVTIMEOUTCFG    0xffffff
5445 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
5446 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
5447 
5448 #define A_SMB_SLV_CTL_CFG 0x67c
5449 
5450 #define S_SLVFIFODBG    31
5451 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
5452 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
5453 
5454 #define S_SLVFIFODBGCLR    30
5455 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
5456 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
5457 
5458 #define S_SLVADDRCFG    4
5459 #define M_SLVADDRCFG    0x7f
5460 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
5461 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
5462 
5463 #define S_SLVALRTSET    2
5464 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
5465 #define F_SLVALRTSET    V_SLVALRTSET(1U)
5466 
5467 #define S_SLVRESET    1
5468 #define V_SLVRESET(x) ((x) << S_SLVRESET)
5469 #define F_SLVRESET    V_SLVRESET(1U)
5470 
5471 #define S_SLVCTLEN    0
5472 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
5473 #define F_SLVCTLEN    V_SLVCTLEN(1U)
5474 
5475 #define A_SMB_SLV_CTL_STS 0x680
5476 
5477 #define S_SLVFIFOTXCNT    12
5478 #define M_SLVFIFOTXCNT    0x3f
5479 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
5480 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
5481 
5482 #define S_SLVFIFOCNT    6
5483 #define M_SLVFIFOCNT    0x3f
5484 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
5485 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
5486 
5487 #define S_SLVALRTSTS    2
5488 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
5489 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
5490 
5491 #define S_SLVBUSYSTS    0
5492 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
5493 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
5494 
5495 #define A_SMB_SLV_FIFO_RDWR 0x684
5496 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688
5497 #define A_SMB_INT_ENABLE 0x68c
5498 
5499 #define S_SLVTIMEOUTINTEN    7
5500 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
5501 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
5502 
5503 #define S_SLVERRINTEN    6
5504 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
5505 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
5506 
5507 #define S_SLVDONEINTEN    5
5508 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
5509 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
5510 
5511 #define S_SLVRXRDYINTEN    4
5512 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
5513 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
5514 
5515 #define S_MSTTIMEOUTINTEN    3
5516 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
5517 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
5518 
5519 #define S_MSTNACKINTEN    2
5520 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
5521 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
5522 
5523 #define S_MSTLOSTARBINTEN    1
5524 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
5525 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
5526 
5527 #define S_MSTDONEINTEN    0
5528 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
5529 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
5530 
5531 #define A_SMB_INT_CAUSE 0x690
5532 
5533 #define S_SLVTIMEOUTINT    7
5534 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
5535 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
5536 
5537 #define S_SLVERRINT    6
5538 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
5539 #define F_SLVERRINT    V_SLVERRINT(1U)
5540 
5541 #define S_SLVDONEINT    5
5542 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
5543 #define F_SLVDONEINT    V_SLVDONEINT(1U)
5544 
5545 #define S_SLVRXRDYINT    4
5546 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
5547 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
5548 
5549 #define S_MSTTIMEOUTINT    3
5550 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
5551 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
5552 
5553 #define S_MSTNACKINT    2
5554 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
5555 #define F_MSTNACKINT    V_MSTNACKINT(1U)
5556 
5557 #define S_MSTLOSTARBINT    1
5558 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
5559 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
5560 
5561 #define S_MSTDONEINT    0
5562 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
5563 #define F_MSTDONEINT    V_MSTDONEINT(1U)
5564 
5565 #define A_SMB_DEBUG_DATA 0x694
5566 
5567 #define S_DEBUGDATAH    16
5568 #define M_DEBUGDATAH    0xffff
5569 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
5570 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
5571 
5572 #define S_DEBUGDATAL    0
5573 #define M_DEBUGDATAL    0xffff
5574 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
5575 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
5576 
5577 #define A_SMB_DEBUG_LA 0x69c
5578 
5579 #define S_DEBUGLAREQADDR    0
5580 #define M_DEBUGLAREQADDR    0x3ff
5581 #define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR)
5582 #define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR)
5583 
5584 /* registers for module I2CM0 */
5585 #define I2CM0_BASE_ADDR 0x6a0
5586 
5587 #define A_I2C_CFG 0x6a0
5588 
5589 #define S_I2C_CLKDIV    0
5590 #define M_I2C_CLKDIV    0xfff
5591 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
5592 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
5593 
5594 #define A_I2C_DATA 0x6a4
5595 #define A_I2C_OP 0x6a8
5596 
5597 #define S_ACK    30
5598 #define V_ACK(x) ((x) << S_ACK)
5599 #define F_ACK    V_ACK(1U)
5600 
5601 #define S_I2C_CONT    1
5602 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
5603 #define F_I2C_CONT    V_I2C_CONT(1U)
5604 
5605 /* registers for module MI1 */
5606 #define MI1_BASE_ADDR 0x6b0
5607 
5608 #define A_MI1_CFG 0x6b0
5609 
5610 #define S_CLKDIV    5
5611 #define M_CLKDIV    0xff
5612 #define V_CLKDIV(x) ((x) << S_CLKDIV)
5613 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
5614 
5615 #define S_ST    3
5616 #define M_ST    0x3
5617 #define V_ST(x) ((x) << S_ST)
5618 #define G_ST(x) (((x) >> S_ST) & M_ST)
5619 
5620 #define S_PREEN    2
5621 #define V_PREEN(x) ((x) << S_PREEN)
5622 #define F_PREEN    V_PREEN(1U)
5623 
5624 #define S_MDIINV    1
5625 #define V_MDIINV(x) ((x) << S_MDIINV)
5626 #define F_MDIINV    V_MDIINV(1U)
5627 
5628 #define S_MDIEN    0
5629 #define V_MDIEN(x) ((x) << S_MDIEN)
5630 #define F_MDIEN    V_MDIEN(1U)
5631 
5632 #define A_MI1_ADDR 0x6b4
5633 
5634 #define S_PHYADDR    5
5635 #define M_PHYADDR    0x1f
5636 #define V_PHYADDR(x) ((x) << S_PHYADDR)
5637 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
5638 
5639 #define S_REGADDR    0
5640 #define M_REGADDR    0x1f
5641 #define V_REGADDR(x) ((x) << S_REGADDR)
5642 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
5643 
5644 #define A_MI1_DATA 0x6b8
5645 
5646 #define S_MDI_DATA    0
5647 #define M_MDI_DATA    0xffff
5648 #define V_MDI_DATA(x) ((x) << S_MDI_DATA)
5649 #define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA)
5650 
5651 #define A_MI1_OP 0x6bc
5652 
5653 #define S_INC    2
5654 #define V_INC(x) ((x) << S_INC)
5655 #define F_INC    V_INC(1U)
5656 
5657 #define S_MDI_OP    0
5658 #define M_MDI_OP    0x3
5659 #define V_MDI_OP(x) ((x) << S_MDI_OP)
5660 #define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP)
5661 
5662 /* registers for module JM1 */
5663 #define JM1_BASE_ADDR 0x6c0
5664 
5665 #define A_JM_CFG 0x6c0
5666 
5667 #define S_JM_CLKDIV    2
5668 #define M_JM_CLKDIV    0xff
5669 #define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV)
5670 #define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV)
5671 
5672 #define S_TRST    1
5673 #define V_TRST(x) ((x) << S_TRST)
5674 #define F_TRST    V_TRST(1U)
5675 
5676 #define S_EN    0
5677 #define V_EN(x) ((x) << S_EN)
5678 #define F_EN    V_EN(1U)
5679 
5680 #define A_JM_MODE 0x6c4
5681 #define A_JM_DATA 0x6c8
5682 #define A_JM_OP 0x6cc
5683 
5684 #define S_CNT    0
5685 #define M_CNT    0x1f
5686 #define V_CNT(x) ((x) << S_CNT)
5687 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
5688 
5689 /* registers for module SF1 */
5690 #define SF1_BASE_ADDR 0x6d8
5691 
5692 #define A_SF_DATA 0x6d8
5693 #define A_SF_OP 0x6dc
5694 
5695 #define S_BYTECNT    1
5696 #define M_BYTECNT    0x3
5697 #define V_BYTECNT(x) ((x) << S_BYTECNT)
5698 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
5699 
5700 /* registers for module PL3 */
5701 #define PL3_BASE_ADDR 0x6e0
5702 
5703 #define A_PL_INT_ENABLE0 0x6e0
5704 
5705 #define S_EXT    24
5706 #define V_EXT(x) ((x) << S_EXT)
5707 #define F_EXT    V_EXT(1U)
5708 
5709 #define S_T3DBG    23
5710 #define V_T3DBG(x) ((x) << S_T3DBG)
5711 #define F_T3DBG    V_T3DBG(1U)
5712 
5713 #define S_XGMAC0_1    20
5714 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
5715 #define F_XGMAC0_1    V_XGMAC0_1(1U)
5716 
5717 #define S_XGMAC0_0    19
5718 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
5719 #define F_XGMAC0_0    V_XGMAC0_0(1U)
5720 
5721 #define S_MC5A    18
5722 #define V_MC5A(x) ((x) << S_MC5A)
5723 #define F_MC5A    V_MC5A(1U)
5724 
5725 #define S_SF1    17
5726 #define V_SF1(x) ((x) << S_SF1)
5727 #define F_SF1    V_SF1(1U)
5728 
5729 #define S_SMB0    15
5730 #define V_SMB0(x) ((x) << S_SMB0)
5731 #define F_SMB0    V_SMB0(1U)
5732 
5733 #define S_I2CM0    14
5734 #define V_I2CM0(x) ((x) << S_I2CM0)
5735 #define F_I2CM0    V_I2CM0(1U)
5736 
5737 #define S_MI1    13
5738 #define V_MI1(x) ((x) << S_MI1)
5739 #define F_MI1    V_MI1(1U)
5740 
5741 #define S_CPL_SWITCH    12
5742 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
5743 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
5744 
5745 #define S_MPS0    11
5746 #define V_MPS0(x) ((x) << S_MPS0)
5747 #define F_MPS0    V_MPS0(1U)
5748 
5749 #define S_PM1_TX    10
5750 #define V_PM1_TX(x) ((x) << S_PM1_TX)
5751 #define F_PM1_TX    V_PM1_TX(1U)
5752 
5753 #define S_PM1_RX    9
5754 #define V_PM1_RX(x) ((x) << S_PM1_RX)
5755 #define F_PM1_RX    V_PM1_RX(1U)
5756 
5757 #define S_ULP2_TX    8
5758 #define V_ULP2_TX(x) ((x) << S_ULP2_TX)
5759 #define F_ULP2_TX    V_ULP2_TX(1U)
5760 
5761 #define S_ULP2_RX    7
5762 #define V_ULP2_RX(x) ((x) << S_ULP2_RX)
5763 #define F_ULP2_RX    V_ULP2_RX(1U)
5764 
5765 #define S_TP1    6
5766 #define V_TP1(x) ((x) << S_TP1)
5767 #define F_TP1    V_TP1(1U)
5768 
5769 #define S_CIM    5
5770 #define V_CIM(x) ((x) << S_CIM)
5771 #define F_CIM    V_CIM(1U)
5772 
5773 #define S_MC7_CM    4
5774 #define V_MC7_CM(x) ((x) << S_MC7_CM)
5775 #define F_MC7_CM    V_MC7_CM(1U)
5776 
5777 #define S_MC7_PMTX    3
5778 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
5779 #define F_MC7_PMTX    V_MC7_PMTX(1U)
5780 
5781 #define S_MC7_PMRX    2
5782 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
5783 #define F_MC7_PMRX    V_MC7_PMRX(1U)
5784 
5785 #define S_PCIM0    1
5786 #define V_PCIM0(x) ((x) << S_PCIM0)
5787 #define F_PCIM0    V_PCIM0(1U)
5788 
5789 #define S_SGE3    0
5790 #define V_SGE3(x) ((x) << S_SGE3)
5791 #define F_SGE3    V_SGE3(1U)
5792 
5793 #define S_SW    25
5794 #define V_SW(x) ((x) << S_SW)
5795 #define F_SW    V_SW(1U)
5796 
5797 #define A_PL_INT_CAUSE0 0x6e4
5798 #define A_PL_INT_ENABLE1 0x6e8
5799 #define A_PL_INT_CAUSE1 0x6ec
5800 #define A_PL_RST 0x6f0
5801 
5802 #define S_CRSTWRM    1
5803 #define V_CRSTWRM(x) ((x) << S_CRSTWRM)
5804 #define F_CRSTWRM    V_CRSTWRM(1U)
5805 
5806 #define S_SWINT1    3
5807 #define V_SWINT1(x) ((x) << S_SWINT1)
5808 #define F_SWINT1    V_SWINT1(1U)
5809 
5810 #define S_SWINT0    2
5811 #define V_SWINT0(x) ((x) << S_SWINT0)
5812 #define F_SWINT0    V_SWINT0(1U)
5813 
5814 #define A_PL_REV 0x6f4
5815 
5816 #define S_REV    0
5817 #define M_REV    0xf
5818 #define V_REV(x) ((x) << S_REV)
5819 #define G_REV(x) (((x) >> S_REV) & M_REV)
5820 
5821 #define A_PL_CLI 0x6f8
5822 #define A_PL_LCK 0x6fc
5823 
5824 #define S_LCK    0
5825 #define M_LCK    0x3
5826 #define V_LCK(x) ((x) << S_LCK)
5827 #define G_LCK(x) (((x) >> S_LCK) & M_LCK)
5828 
5829 /* registers for module MC5A */
5830 #define MC5A_BASE_ADDR 0x700
5831 
5832 #define A_MC5_BUF_CONFIG 0x700
5833 
5834 #define S_TERM300_240    31
5835 #define V_TERM300_240(x) ((x) << S_TERM300_240)
5836 #define F_TERM300_240    V_TERM300_240(1U)
5837 
5838 #define S_MC5_TERM150    30
5839 #define V_MC5_TERM150(x) ((x) << S_MC5_TERM150)
5840 #define F_MC5_TERM150    V_MC5_TERM150(1U)
5841 
5842 #define S_TERM60    29
5843 #define V_TERM60(x) ((x) << S_TERM60)
5844 #define F_TERM60    V_TERM60(1U)
5845 
5846 #define S_GDDRIII    28
5847 #define V_GDDRIII(x) ((x) << S_GDDRIII)
5848 #define F_GDDRIII    V_GDDRIII(1U)
5849 
5850 #define S_GDDRII    27
5851 #define V_GDDRII(x) ((x) << S_GDDRII)
5852 #define F_GDDRII    V_GDDRII(1U)
5853 
5854 #define S_GDDRI    26
5855 #define V_GDDRI(x) ((x) << S_GDDRI)
5856 #define F_GDDRI    V_GDDRI(1U)
5857 
5858 #define S_READ    25
5859 #define V_READ(x) ((x) << S_READ)
5860 #define F_READ    V_READ(1U)
5861 
5862 #define S_CAL_IMP_UPD    23
5863 #define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD)
5864 #define F_CAL_IMP_UPD    V_CAL_IMP_UPD(1U)
5865 
5866 #define S_CAL_BUSY    22
5867 #define V_CAL_BUSY(x) ((x) << S_CAL_BUSY)
5868 #define F_CAL_BUSY    V_CAL_BUSY(1U)
5869 
5870 #define S_CAL_ERROR    21
5871 #define V_CAL_ERROR(x) ((x) << S_CAL_ERROR)
5872 #define F_CAL_ERROR    V_CAL_ERROR(1U)
5873 
5874 #define S_SGL_CAL_EN    20
5875 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
5876 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
5877 
5878 #define S_IMP_UPD_MODE    19
5879 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
5880 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
5881 
5882 #define S_IMP_SEL    18
5883 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
5884 #define F_IMP_SEL    V_IMP_SEL(1U)
5885 
5886 #define S_MAN_PU    15
5887 #define M_MAN_PU    0x7
5888 #define V_MAN_PU(x) ((x) << S_MAN_PU)
5889 #define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU)
5890 
5891 #define S_MAN_PD    12
5892 #define M_MAN_PD    0x7
5893 #define V_MAN_PD(x) ((x) << S_MAN_PD)
5894 #define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD)
5895 
5896 #define S_CAL_PU    9
5897 #define M_CAL_PU    0x7
5898 #define V_CAL_PU(x) ((x) << S_CAL_PU)
5899 #define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU)
5900 
5901 #define S_CAL_PD    6
5902 #define M_CAL_PD    0x7
5903 #define V_CAL_PD(x) ((x) << S_CAL_PD)
5904 #define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD)
5905 
5906 #define S_SET_PU    3
5907 #define M_SET_PU    0x7
5908 #define V_SET_PU(x) ((x) << S_SET_PU)
5909 #define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU)
5910 
5911 #define S_SET_PD    0
5912 #define M_SET_PD    0x7
5913 #define V_SET_PD(x) ((x) << S_SET_PD)
5914 #define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD)
5915 
5916 #define S_IMP_SET_UPDATE    24
5917 #define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE)
5918 #define F_IMP_SET_UPDATE    V_IMP_SET_UPDATE(1U)
5919 
5920 #define S_CAL_UPDATE    23
5921 #define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE)
5922 #define F_CAL_UPDATE    V_CAL_UPDATE(1U)
5923 
5924 #define A_MC5_DB_CONFIG 0x704
5925 
5926 #define S_TMCFGWRLOCK    31
5927 #define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK)
5928 #define F_TMCFGWRLOCK    V_TMCFGWRLOCK(1U)
5929 
5930 #define S_TMTYPEHI    30
5931 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
5932 #define F_TMTYPEHI    V_TMTYPEHI(1U)
5933 
5934 #define S_TMPARTSIZE    28
5935 #define M_TMPARTSIZE    0x3
5936 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
5937 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
5938 
5939 #define S_TMTYPE    26
5940 #define M_TMTYPE    0x3
5941 #define V_TMTYPE(x) ((x) << S_TMTYPE)
5942 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
5943 
5944 #define S_TMPARTCOUNT    24
5945 #define M_TMPARTCOUNT    0x3
5946 #define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT)
5947 #define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT)
5948 
5949 #define S_NLIP    18
5950 #define M_NLIP    0x3f
5951 #define V_NLIP(x) ((x) << S_NLIP)
5952 #define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP)
5953 
5954 #define S_COMPEN    17
5955 #define V_COMPEN(x) ((x) << S_COMPEN)
5956 #define F_COMPEN    V_COMPEN(1U)
5957 
5958 #define S_BUILD    16
5959 #define V_BUILD(x) ((x) << S_BUILD)
5960 #define F_BUILD    V_BUILD(1U)
5961 
5962 #define S_TM_IO_PDOWN    9
5963 #define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN)
5964 #define F_TM_IO_PDOWN    V_TM_IO_PDOWN(1U)
5965 
5966 #define S_SYNMODE    7
5967 #define M_SYNMODE    0x3
5968 #define V_SYNMODE(x) ((x) << S_SYNMODE)
5969 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
5970 
5971 #define S_PRTYEN    6
5972 #define V_PRTYEN(x) ((x) << S_PRTYEN)
5973 #define F_PRTYEN    V_PRTYEN(1U)
5974 
5975 #define S_MBUSEN    5
5976 #define V_MBUSEN(x) ((x) << S_MBUSEN)
5977 #define F_MBUSEN    V_MBUSEN(1U)
5978 
5979 #define S_DBGIEN    4
5980 #define V_DBGIEN(x) ((x) << S_DBGIEN)
5981 #define F_DBGIEN    V_DBGIEN(1U)
5982 
5983 #define S_TMRDY    2
5984 #define V_TMRDY(x) ((x) << S_TMRDY)
5985 #define F_TMRDY    V_TMRDY(1U)
5986 
5987 #define S_TMRST    1
5988 #define V_TMRST(x) ((x) << S_TMRST)
5989 #define F_TMRST    V_TMRST(1U)
5990 
5991 #define S_TMMODE    0
5992 #define V_TMMODE(x) ((x) << S_TMMODE)
5993 #define F_TMMODE    V_TMMODE(1U)
5994 
5995 #define S_FILTEREN    11
5996 #define V_FILTEREN(x) ((x) << S_FILTEREN)
5997 #define F_FILTEREN    V_FILTEREN(1U)
5998 
5999 #define S_CLIPUPDATE    10
6000 #define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE)
6001 #define F_CLIPUPDATE    V_CLIPUPDATE(1U)
6002 
6003 #define S_TCMCFGOVR    3
6004 #define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR)
6005 #define F_TCMCFGOVR    V_TCMCFGOVR(1U)
6006 
6007 #define A_MC5_MISC 0x708
6008 
6009 #define S_LIP_CMP_UNAVAILABLE    0
6010 #define M_LIP_CMP_UNAVAILABLE    0xf
6011 #define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE)
6012 #define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE)
6013 
6014 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
6015 
6016 #define S_RTINDX    0
6017 #define M_RTINDX    0x3fffff
6018 #define V_RTINDX(x) ((x) << S_RTINDX)
6019 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
6020 
6021 #define A_MC5_DB_FILTER_TABLE 0x710
6022 #define A_MC5_DB_SERVER_INDEX 0x714
6023 
6024 #define S_SRINDX    0
6025 #define M_SRINDX    0x3fffff
6026 #define V_SRINDX(x) ((x) << S_SRINDX)
6027 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
6028 
6029 #define A_MC5_DB_LIP_RAM_ADDR 0x718
6030 
6031 #define S_RAMWR    8
6032 #define V_RAMWR(x) ((x) << S_RAMWR)
6033 #define F_RAMWR    V_RAMWR(1U)
6034 
6035 #define S_RAMADDR    0
6036 #define M_RAMADDR    0x3f
6037 #define V_RAMADDR(x) ((x) << S_RAMADDR)
6038 #define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR)
6039 
6040 #define A_MC5_DB_LIP_RAM_DATA 0x71c
6041 #define A_MC5_DB_RSP_LATENCY 0x720
6042 
6043 #define S_RDLAT    16
6044 #define M_RDLAT    0x1f
6045 #define V_RDLAT(x) ((x) << S_RDLAT)
6046 #define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT)
6047 
6048 #define S_LRNLAT    8
6049 #define M_LRNLAT    0x1f
6050 #define V_LRNLAT(x) ((x) << S_LRNLAT)
6051 #define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT)
6052 
6053 #define S_SRCHLAT    0
6054 #define M_SRCHLAT    0x1f
6055 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
6056 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
6057 
6058 #define A_MC5_DB_PARITY_LATENCY 0x724
6059 
6060 #define S_PARLAT    0
6061 #define M_PARLAT    0xf
6062 #define V_PARLAT(x) ((x) << S_PARLAT)
6063 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
6064 
6065 #define A_MC5_DB_WR_LRN_VERIFY 0x728
6066 
6067 #define S_VWVEREN    2
6068 #define V_VWVEREN(x) ((x) << S_VWVEREN)
6069 #define F_VWVEREN    V_VWVEREN(1U)
6070 
6071 #define S_LRNVEREN    1
6072 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
6073 #define F_LRNVEREN    V_LRNVEREN(1U)
6074 
6075 #define S_POVEREN    0
6076 #define V_POVEREN(x) ((x) << S_POVEREN)
6077 #define F_POVEREN    V_POVEREN(1U)
6078 
6079 #define A_MC5_DB_PART_ID_INDEX 0x72c
6080 
6081 #define S_IDINDEX    0
6082 #define M_IDINDEX    0xf
6083 #define V_IDINDEX(x) ((x) << S_IDINDEX)
6084 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
6085 
6086 #define A_MC5_DB_RESET_MAX 0x730
6087 
6088 #define S_RSTMAX    0
6089 #define M_RSTMAX    0xf
6090 #define V_RSTMAX(x) ((x) << S_RSTMAX)
6091 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
6092 
6093 #define A_MC5_DB_ACT_CNT 0x734
6094 
6095 #define S_ACTCNT    0
6096 #define M_ACTCNT    0xfffff
6097 #define V_ACTCNT(x) ((x) << S_ACTCNT)
6098 #define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT)
6099 
6100 #define A_MC5_DB_CLIP_MAP 0x738
6101 
6102 #define S_CLIPMAPOP    31
6103 #define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP)
6104 #define F_CLIPMAPOP    V_CLIPMAPOP(1U)
6105 
6106 #define S_CLIPMAPVAL    16
6107 #define M_CLIPMAPVAL    0x3f
6108 #define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL)
6109 #define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL)
6110 
6111 #define S_CLIPMAPADDR    0
6112 #define M_CLIPMAPADDR    0x3f
6113 #define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR)
6114 #define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR)
6115 
6116 #define A_MC5_DB_INT_ENABLE 0x740
6117 
6118 #define S_MSGSEL    28
6119 #define M_MSGSEL    0xf
6120 #define V_MSGSEL(x) ((x) << S_MSGSEL)
6121 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
6122 
6123 #define S_DELACTEMPTY    18
6124 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
6125 #define F_DELACTEMPTY    V_DELACTEMPTY(1U)
6126 
6127 #define S_DISPQPARERR    17
6128 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
6129 #define F_DISPQPARERR    V_DISPQPARERR(1U)
6130 
6131 #define S_REQQPARERR    16
6132 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
6133 #define F_REQQPARERR    V_REQQPARERR(1U)
6134 
6135 #define S_UNKNOWNCMD    15
6136 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
6137 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
6138 
6139 #define S_SYNCOOKIEOFF    11
6140 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
6141 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
6142 
6143 #define S_SYNCOOKIEBAD    10
6144 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
6145 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
6146 
6147 #define S_SYNCOOKIE    9
6148 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
6149 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
6150 
6151 #define S_NFASRCHFAIL    8
6152 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
6153 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
6154 
6155 #define S_ACTRGNFULL    7
6156 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
6157 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
6158 
6159 #define S_PARITYERR    6
6160 #define V_PARITYERR(x) ((x) << S_PARITYERR)
6161 #define F_PARITYERR    V_PARITYERR(1U)
6162 
6163 #define S_LIPMISS    5
6164 #define V_LIPMISS(x) ((x) << S_LIPMISS)
6165 #define F_LIPMISS    V_LIPMISS(1U)
6166 
6167 #define S_LIP0    4
6168 #define V_LIP0(x) ((x) << S_LIP0)
6169 #define F_LIP0    V_LIP0(1U)
6170 
6171 #define S_MISS    3
6172 #define V_MISS(x) ((x) << S_MISS)
6173 #define F_MISS    V_MISS(1U)
6174 
6175 #define S_ROUTINGHIT    2
6176 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
6177 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
6178 
6179 #define S_ACTIVEHIT    1
6180 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
6181 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
6182 
6183 #define S_ACTIVEOUTHIT    0
6184 #define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT)
6185 #define F_ACTIVEOUTHIT    V_ACTIVEOUTHIT(1U)
6186 
6187 #define A_MC5_DB_INT_CAUSE 0x744
6188 #define A_MC5_DB_INT_TID 0x748
6189 
6190 #define S_INTTID    0
6191 #define M_INTTID    0xfffff
6192 #define V_INTTID(x) ((x) << S_INTTID)
6193 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
6194 
6195 #define A_MC5_DB_INT_PTID 0x74c
6196 
6197 #define S_INTPTID    0
6198 #define M_INTPTID    0xfffff
6199 #define V_INTPTID(x) ((x) << S_INTPTID)
6200 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
6201 
6202 #define A_MC5_DB_DBGI_CONFIG 0x774
6203 
6204 #define S_WRREQSIZE    22
6205 #define M_WRREQSIZE    0x3ff
6206 #define V_WRREQSIZE(x) ((x) << S_WRREQSIZE)
6207 #define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE)
6208 
6209 #define S_SADRSEL    4
6210 #define V_SADRSEL(x) ((x) << S_SADRSEL)
6211 #define F_SADRSEL    V_SADRSEL(1U)
6212 
6213 #define S_CMDMODE    0
6214 #define M_CMDMODE    0x7
6215 #define V_CMDMODE(x) ((x) << S_CMDMODE)
6216 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
6217 
6218 #define A_MC5_DB_DBGI_REQ_CMD 0x778
6219 
6220 #define S_MBUSCMD    0
6221 #define M_MBUSCMD    0xf
6222 #define V_MBUSCMD(x) ((x) << S_MBUSCMD)
6223 #define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD)
6224 
6225 #define S_IDTCMDHI    11
6226 #define M_IDTCMDHI    0x7
6227 #define V_IDTCMDHI(x) ((x) << S_IDTCMDHI)
6228 #define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI)
6229 
6230 #define S_IDTCMDLO    0
6231 #define M_IDTCMDLO    0xf
6232 #define V_IDTCMDLO(x) ((x) << S_IDTCMDLO)
6233 #define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO)
6234 
6235 #define S_IDTCMD    0
6236 #define M_IDTCMD    0xfffff
6237 #define V_IDTCMD(x) ((x) << S_IDTCMD)
6238 #define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD)
6239 
6240 #define S_LCMDB    16
6241 #define M_LCMDB    0x7ff
6242 #define V_LCMDB(x) ((x) << S_LCMDB)
6243 #define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB)
6244 
6245 #define S_LCMDA    0
6246 #define M_LCMDA    0x7ff
6247 #define V_LCMDA(x) ((x) << S_LCMDA)
6248 #define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA)
6249 
6250 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
6251 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
6252 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
6253 
6254 #define S_DBGIREQADRHI    0
6255 #define M_DBGIREQADRHI    0xff
6256 #define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI)
6257 #define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI)
6258 
6259 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
6260 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
6261 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
6262 #define A_MC5_DB_DBGI_REQ_DATA3 0x794
6263 #define A_MC5_DB_DBGI_REQ_DATA4 0x798
6264 
6265 #define S_DBGIREQDATA4    0
6266 #define M_DBGIREQDATA4    0xffff
6267 #define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4)
6268 #define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4)
6269 
6270 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c
6271 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0
6272 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4
6273 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8
6274 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac
6275 
6276 #define S_DBGIREQMSK4    0
6277 #define M_DBGIREQMSK4    0xffff
6278 #define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4)
6279 #define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4)
6280 
6281 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
6282 
6283 #define S_DBGIRSPMSG    8
6284 #define M_DBGIRSPMSG    0xf
6285 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
6286 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
6287 
6288 #define S_DBGIRSPMSGVLD    2
6289 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
6290 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
6291 
6292 #define S_DBGIRSPHIT    1
6293 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
6294 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
6295 
6296 #define S_DBGIRSPVALID    0
6297 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
6298 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
6299 
6300 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
6301 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
6302 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
6303 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0
6304 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4
6305 
6306 #define S_DBGIRSPDATA3    0
6307 #define M_DBGIRSPDATA3    0xffff
6308 #define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3)
6309 #define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3)
6310 
6311 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8
6312 
6313 #define S_LASTCMDB    16
6314 #define M_LASTCMDB    0x7ff
6315 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
6316 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
6317 
6318 #define S_LASTCMDA    0
6319 #define M_LASTCMDA    0x7ff
6320 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
6321 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
6322 
6323 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
6324 
6325 #define S_PO_DWR    0
6326 #define M_PO_DWR    0xfffff
6327 #define V_PO_DWR(x) ((x) << S_PO_DWR)
6328 #define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR)
6329 
6330 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
6331 
6332 #define S_PO_MWR    0
6333 #define M_PO_MWR    0xfffff
6334 #define V_PO_MWR(x) ((x) << S_PO_MWR)
6335 #define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR)
6336 
6337 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
6338 
6339 #define S_AO_SRCH    0
6340 #define M_AO_SRCH    0xfffff
6341 #define V_AO_SRCH(x) ((x) << S_AO_SRCH)
6342 #define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH)
6343 
6344 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
6345 
6346 #define S_AO_LRN    0
6347 #define M_AO_LRN    0xfffff
6348 #define V_AO_LRN(x) ((x) << S_AO_LRN)
6349 #define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN)
6350 
6351 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
6352 
6353 #define S_SYN_SRCH    0
6354 #define M_SYN_SRCH    0xfffff
6355 #define V_SYN_SRCH(x) ((x) << S_SYN_SRCH)
6356 #define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH)
6357 
6358 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
6359 
6360 #define S_SYN_LRN    0
6361 #define M_SYN_LRN    0xfffff
6362 #define V_SYN_LRN(x) ((x) << S_SYN_LRN)
6363 #define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN)
6364 
6365 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
6366 
6367 #define S_ACK_SRCH    0
6368 #define M_ACK_SRCH    0xfffff
6369 #define V_ACK_SRCH(x) ((x) << S_ACK_SRCH)
6370 #define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH)
6371 
6372 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
6373 
6374 #define S_ACK_LRN    0
6375 #define M_ACK_LRN    0xfffff
6376 #define V_ACK_LRN(x) ((x) << S_ACK_LRN)
6377 #define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN)
6378 
6379 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
6380 
6381 #define S_I_SRCH    0
6382 #define M_I_SRCH    0xfffff
6383 #define V_I_SRCH(x) ((x) << S_I_SRCH)
6384 #define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH)
6385 
6386 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
6387 
6388 #define S_E_SRCH    0
6389 #define M_E_SRCH    0xfffff
6390 #define V_E_SRCH(x) ((x) << S_E_SRCH)
6391 #define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH)
6392 
6393 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
6394 
6395 #define S_WRITE    0
6396 #define M_WRITE    0xfffff
6397 #define V_WRITE(x) ((x) << S_WRITE)
6398 #define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE)
6399 
6400 #define A_MC5_DB_DATA_READ_CMD 0x7f8
6401 
6402 #define S_READCMD    0
6403 #define M_READCMD    0xfffff
6404 #define V_READCMD(x) ((x) << S_READCMD)
6405 #define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD)
6406 
6407 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc
6408 
6409 #define S_MASKWR    0
6410 #define M_MASKWR    0xffff
6411 #define V_MASKWR(x) ((x) << S_MASKWR)
6412 #define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR)
6413 
6414 /* registers for module XGMAC0_0 */
6415 #define XGMAC0_0_BASE_ADDR 0x800
6416 
6417 #define A_XGM_TX_CTRL 0x800
6418 
6419 #define S_SENDPAUSE    2
6420 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
6421 #define F_SENDPAUSE    V_SENDPAUSE(1U)
6422 
6423 #define S_SENDZEROPAUSE    1
6424 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
6425 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
6426 
6427 #define S_TXEN    0
6428 #define V_TXEN(x) ((x) << S_TXEN)
6429 #define F_TXEN    V_TXEN(1U)
6430 
6431 #define A_XGM_TX_CFG 0x804
6432 
6433 #define S_CFGCLKSPEED    2
6434 #define M_CFGCLKSPEED    0x7
6435 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
6436 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
6437 
6438 #define S_STRETCHMODE    1
6439 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
6440 #define F_STRETCHMODE    V_STRETCHMODE(1U)
6441 
6442 #define S_TXPAUSEEN    0
6443 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
6444 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
6445 
6446 #define A_XGM_TX_PAUSE_QUANTA 0x808
6447 
6448 #define S_TXPAUSEQUANTA    0
6449 #define M_TXPAUSEQUANTA    0xffff
6450 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
6451 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
6452 
6453 #define A_XGM_RX_CTRL 0x80c
6454 
6455 #define S_RXEN    0
6456 #define V_RXEN(x) ((x) << S_RXEN)
6457 #define F_RXEN    V_RXEN(1U)
6458 
6459 #define A_XGM_RX_CFG 0x810
6460 
6461 #define S_CON802_3PREAMBLE    12
6462 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
6463 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
6464 
6465 #define S_ENNON802_3PREAMBLE    11
6466 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
6467 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
6468 
6469 #define S_COPYPREAMBLE    10
6470 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
6471 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
6472 
6473 #define S_DISPAUSEFRAMES    9
6474 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
6475 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
6476 
6477 #define S_EN1536BFRAMES    8
6478 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
6479 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
6480 
6481 #define S_ENJUMBO    7
6482 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
6483 #define F_ENJUMBO    V_ENJUMBO(1U)
6484 
6485 #define S_RMFCS    6
6486 #define V_RMFCS(x) ((x) << S_RMFCS)
6487 #define F_RMFCS    V_RMFCS(1U)
6488 
6489 #define S_DISNONVLAN    5
6490 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
6491 #define F_DISNONVLAN    V_DISNONVLAN(1U)
6492 
6493 #define S_ENEXTMATCH    4
6494 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
6495 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
6496 
6497 #define S_ENHASHUCAST    3
6498 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
6499 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
6500 
6501 #define S_ENHASHMCAST    2
6502 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
6503 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
6504 
6505 #define S_DISBCAST    1
6506 #define V_DISBCAST(x) ((x) << S_DISBCAST)
6507 #define F_DISBCAST    V_DISBCAST(1U)
6508 
6509 #define S_COPYALLFRAMES    0
6510 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
6511 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
6512 
6513 #define A_XGM_RX_HASH_LOW 0x814
6514 #define A_XGM_RX_HASH_HIGH 0x818
6515 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
6516 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
6517 
6518 #define S_ADDRESS_HIGH    0
6519 #define M_ADDRESS_HIGH    0xffff
6520 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
6521 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
6522 
6523 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
6524 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828
6525 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
6526 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830
6527 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
6528 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838
6529 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
6530 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840
6531 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
6532 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848
6533 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
6534 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850
6535 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
6536 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858
6537 #define A_XGM_RX_TYPE_MATCH_1 0x85c
6538 
6539 #define S_ENTYPEMATCH    31
6540 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
6541 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
6542 
6543 #define S_TYPE    0
6544 #define M_TYPE    0xffff
6545 #define V_TYPE(x) ((x) << S_TYPE)
6546 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
6547 
6548 #define A_XGM_RX_TYPE_MATCH_2 0x860
6549 #define A_XGM_RX_TYPE_MATCH_3 0x864
6550 #define A_XGM_RX_TYPE_MATCH_4 0x868
6551 #define A_XGM_INT_STATUS 0x86c
6552 
6553 #define S_XGMIIEXTINT    10
6554 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
6555 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
6556 
6557 #define S_LINKFAULTCHANGE    9
6558 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
6559 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
6560 
6561 #define S_PHYFRAMECOMPLETE    8
6562 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
6563 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
6564 
6565 #define S_PAUSEFRAMETXMT    7
6566 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
6567 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
6568 
6569 #define S_PAUSECNTRTIMEOUT    6
6570 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
6571 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
6572 
6573 #define S_NON0PAUSERCVD    5
6574 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
6575 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
6576 
6577 #define S_STATOFLOW    4
6578 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
6579 #define F_STATOFLOW    V_STATOFLOW(1U)
6580 
6581 #define S_TXERRFIFO    3
6582 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
6583 #define F_TXERRFIFO    V_TXERRFIFO(1U)
6584 
6585 #define S_TXUFLOW    2
6586 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
6587 #define F_TXUFLOW    V_TXUFLOW(1U)
6588 
6589 #define S_FRAMETXMT    1
6590 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
6591 #define F_FRAMETXMT    V_FRAMETXMT(1U)
6592 
6593 #define S_FRAMERCVD    0
6594 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
6595 #define F_FRAMERCVD    V_FRAMERCVD(1U)
6596 
6597 #define A_XGM_XGM_INT_MASK 0x870
6598 #define A_XGM_XGM_INT_ENABLE 0x874
6599 #define A_XGM_XGM_INT_DISABLE 0x878
6600 #define A_XGM_TX_PAUSE_TIMER 0x87c
6601 
6602 #define S_CURPAUSETIMER    0
6603 #define M_CURPAUSETIMER    0xffff
6604 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
6605 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
6606 
6607 #define A_XGM_STAT_CTRL 0x880
6608 
6609 #define S_READSNPSHOT    4
6610 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
6611 #define F_READSNPSHOT    V_READSNPSHOT(1U)
6612 
6613 #define S_TAKESNPSHOT    3
6614 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
6615 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
6616 
6617 #define S_CLRSTATS    2
6618 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
6619 #define F_CLRSTATS    V_CLRSTATS(1U)
6620 
6621 #define S_INCRSTATS    1
6622 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
6623 #define F_INCRSTATS    V_INCRSTATS(1U)
6624 
6625 #define S_ENTESTMODEWR    0
6626 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
6627 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
6628 
6629 #define A_XGM_RXFIFO_CFG 0x884
6630 
6631 #define S_RXFIFOPAUSEHWM    17
6632 #define M_RXFIFOPAUSEHWM    0xfff
6633 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
6634 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
6635 
6636 #define S_RXFIFOPAUSELWM    5
6637 #define M_RXFIFOPAUSELWM    0xfff
6638 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
6639 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
6640 
6641 #define S_FORCEDPAUSE    4
6642 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
6643 #define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
6644 
6645 #define S_EXTERNLOOPBACK    3
6646 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
6647 #define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
6648 
6649 #define S_RXBYTESWAP    2
6650 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
6651 #define F_RXBYTESWAP    V_RXBYTESWAP(1U)
6652 
6653 #define S_RXSTRFRWRD    1
6654 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
6655 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
6656 
6657 #define S_DISERRFRAMES    0
6658 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
6659 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
6660 
6661 #define A_XGM_TXFIFO_CFG 0x888
6662 
6663 #define S_TXIPG    13
6664 #define M_TXIPG    0xff
6665 #define V_TXIPG(x) ((x) << S_TXIPG)
6666 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
6667 
6668 #define S_TXFIFOTHRESH    4
6669 #define M_TXFIFOTHRESH    0x1ff
6670 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
6671 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
6672 
6673 #define S_INTERNLOOPBACK    3
6674 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
6675 #define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
6676 
6677 #define S_TXBYTESWAP    2
6678 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
6679 #define F_TXBYTESWAP    V_TXBYTESWAP(1U)
6680 
6681 #define S_DISCRC    1
6682 #define V_DISCRC(x) ((x) << S_DISCRC)
6683 #define F_DISCRC    V_DISCRC(1U)
6684 
6685 #define S_DISPREAMBLE    0
6686 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
6687 #define F_DISPREAMBLE    V_DISPREAMBLE(1U)
6688 
6689 #define S_ENDROPPKT    21
6690 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
6691 #define F_ENDROPPKT    V_ENDROPPKT(1U)
6692 
6693 #define A_XGM_SLOW_TIMER 0x88c
6694 
6695 #define S_PAUSESLOWTIMEREN    31
6696 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
6697 #define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
6698 
6699 #define S_PAUSESLOWTIMER    0
6700 #define M_PAUSESLOWTIMER    0xfffff
6701 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
6702 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
6703 
6704 #define A_XGM_SERDES_CTRL 0x890
6705 
6706 #define S_SERDESEN    25
6707 #define V_SERDESEN(x) ((x) << S_SERDESEN)
6708 #define F_SERDESEN    V_SERDESEN(1U)
6709 
6710 #define S_SERDESRESET_    24
6711 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
6712 #define F_SERDESRESET_    V_SERDESRESET_(1U)
6713 
6714 #define S_CMURANGE    21
6715 #define M_CMURANGE    0x7
6716 #define V_CMURANGE(x) ((x) << S_CMURANGE)
6717 #define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE)
6718 
6719 #define S_BGENB    20
6720 #define V_BGENB(x) ((x) << S_BGENB)
6721 #define F_BGENB    V_BGENB(1U)
6722 
6723 #define S_ENSKPDROP    19
6724 #define V_ENSKPDROP(x) ((x) << S_ENSKPDROP)
6725 #define F_ENSKPDROP    V_ENSKPDROP(1U)
6726 
6727 #define S_ENCOMMA    18
6728 #define V_ENCOMMA(x) ((x) << S_ENCOMMA)
6729 #define F_ENCOMMA    V_ENCOMMA(1U)
6730 
6731 #define S_EN8B10B    17
6732 #define V_EN8B10B(x) ((x) << S_EN8B10B)
6733 #define F_EN8B10B    V_EN8B10B(1U)
6734 
6735 #define S_ENELBUF    16
6736 #define V_ENELBUF(x) ((x) << S_ENELBUF)
6737 #define F_ENELBUF    V_ENELBUF(1U)
6738 
6739 #define S_GAIN    11
6740 #define M_GAIN    0x1f
6741 #define V_GAIN(x) ((x) << S_GAIN)
6742 #define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN)
6743 
6744 #define S_BANDGAP    7
6745 #define M_BANDGAP    0xf
6746 #define V_BANDGAP(x) ((x) << S_BANDGAP)
6747 #define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP)
6748 
6749 #define S_LPBKEN    5
6750 #define M_LPBKEN    0x3
6751 #define V_LPBKEN(x) ((x) << S_LPBKEN)
6752 #define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN)
6753 
6754 #define S_RXENABLE    4
6755 #define V_RXENABLE(x) ((x) << S_RXENABLE)
6756 #define F_RXENABLE    V_RXENABLE(1U)
6757 
6758 #define S_TXENABLE    3
6759 #define V_TXENABLE(x) ((x) << S_TXENABLE)
6760 #define F_TXENABLE    V_TXENABLE(1U)
6761 
6762 #define A_XGM_PAUSE_TIMER 0x890
6763 
6764 #define S_PAUSETIMER    0
6765 #define M_PAUSETIMER    0xfffff
6766 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
6767 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
6768 
6769 #define A_XGM_XAUI_PCS_TEST 0x894
6770 
6771 #define S_TESTPATTERN    1
6772 #define M_TESTPATTERN    0x3
6773 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
6774 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
6775 
6776 #define S_ENTEST    0
6777 #define V_ENTEST(x) ((x) << S_ENTEST)
6778 #define F_ENTEST    V_ENTEST(1U)
6779 
6780 #define A_XGM_RGMII_CTRL 0x898
6781 
6782 #define S_PHALIGNFIFOTHRESH    1
6783 #define M_PHALIGNFIFOTHRESH    0x3
6784 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
6785 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
6786 
6787 #define S_TXCLK90SHIFT    0
6788 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
6789 #define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
6790 
6791 #define A_XGM_RGMII_IMP 0x89c
6792 
6793 #define S_XGM_IMPSETUPDATE    6
6794 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
6795 #define F_XGM_IMPSETUPDATE    V_XGM_IMPSETUPDATE(1U)
6796 
6797 #define S_RGMIIIMPPD    3
6798 #define M_RGMIIIMPPD    0x7
6799 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
6800 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
6801 
6802 #define S_RGMIIIMPPU    0
6803 #define M_RGMIIIMPPU    0x7
6804 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
6805 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
6806 
6807 #define S_CALRESET    8
6808 #define V_CALRESET(x) ((x) << S_CALRESET)
6809 #define F_CALRESET    V_CALRESET(1U)
6810 
6811 #define S_CALUPDATE    7
6812 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
6813 #define F_CALUPDATE    V_CALUPDATE(1U)
6814 
6815 #define A_XGM_XAUI_IMP 0x8a0
6816 
6817 #define S_XGM_CALFAULT    29
6818 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
6819 #define F_XGM_CALFAULT    V_XGM_CALFAULT(1U)
6820 
6821 #define S_CALIMP    24
6822 #define M_CALIMP    0x1f
6823 #define V_CALIMP(x) ((x) << S_CALIMP)
6824 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
6825 
6826 #define S_XAUIIMP    0
6827 #define M_XAUIIMP    0x7
6828 #define V_XAUIIMP(x) ((x) << S_XAUIIMP)
6829 #define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP)
6830 
6831 #define A_XGM_SERDES_BIST 0x8a4
6832 
6833 #define S_BISTDONE    28
6834 #define M_BISTDONE    0xf
6835 #define V_BISTDONE(x) ((x) << S_BISTDONE)
6836 #define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE)
6837 
6838 #define S_BISTCYCLETHRESH    3
6839 #define M_BISTCYCLETHRESH    0x1ffff
6840 #define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH)
6841 #define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH)
6842 
6843 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
6844 
6845 #define S_RXMAXPKTSIZE    0
6846 #define M_RXMAXPKTSIZE    0x3fff
6847 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
6848 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
6849 
6850 #define A_XGM_RESET_CTRL 0x8ac
6851 
6852 #define S_XG2G_RESET_    3
6853 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
6854 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
6855 
6856 #define S_RGMII_RESET_    2
6857 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
6858 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
6859 
6860 #define S_PCS_RESET_    1
6861 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
6862 #define F_PCS_RESET_    V_PCS_RESET_(1U)
6863 
6864 #define S_MAC_RESET_    0
6865 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
6866 #define F_MAC_RESET_    V_MAC_RESET_(1U)
6867 
6868 #define A_XGM_XAUI1G_CTRL 0x8b0
6869 
6870 #define S_XAUI1GLINKID    0
6871 #define M_XAUI1GLINKID    0x3
6872 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
6873 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
6874 
6875 #define A_XGM_SERDES_LANE_CTRL 0x8b4
6876 
6877 #define S_LANEREVERSAL    8
6878 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
6879 #define F_LANEREVERSAL    V_LANEREVERSAL(1U)
6880 
6881 #define S_TXPOLARITY    4
6882 #define M_TXPOLARITY    0xf
6883 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
6884 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
6885 
6886 #define S_RXPOLARITY    0
6887 #define M_RXPOLARITY    0xf
6888 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
6889 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
6890 
6891 #define A_XGM_PORT_CFG 0x8b8
6892 
6893 #define S_SAFESPEEDCHANGE    4
6894 #define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE)
6895 #define F_SAFESPEEDCHANGE    V_SAFESPEEDCHANGE(1U)
6896 
6897 #define S_CLKDIVRESET_    3
6898 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
6899 #define F_CLKDIVRESET_    V_CLKDIVRESET_(1U)
6900 
6901 #define S_PORTSPEED    1
6902 #define M_PORTSPEED    0x3
6903 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
6904 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
6905 
6906 #define S_ENRGMII    0
6907 #define V_ENRGMII(x) ((x) << S_ENRGMII)
6908 #define F_ENRGMII    V_ENRGMII(1U)
6909 
6910 #define A_XGM_EPIO_DATA0 0x8c0
6911 #define A_XGM_EPIO_DATA1 0x8c4
6912 #define A_XGM_EPIO_DATA2 0x8c8
6913 #define A_XGM_EPIO_DATA3 0x8cc
6914 #define A_XGM_EPIO_OP 0x8d0
6915 
6916 #define S_PIO_READY    31
6917 #define V_PIO_READY(x) ((x) << S_PIO_READY)
6918 #define F_PIO_READY    V_PIO_READY(1U)
6919 
6920 #define S_PIO_WRRD    24
6921 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
6922 #define F_PIO_WRRD    V_PIO_WRRD(1U)
6923 
6924 #define S_PIO_ADDRESS    0
6925 #define M_PIO_ADDRESS    0xff
6926 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
6927 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
6928 
6929 #define A_XGM_INT_ENABLE 0x8d4
6930 
6931 #define S_SERDESCMULOCK_LOSS    24
6932 #define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS)
6933 #define F_SERDESCMULOCK_LOSS    V_SERDESCMULOCK_LOSS(1U)
6934 
6935 #define S_RGMIIRXFIFOOVERFLOW    23
6936 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
6937 #define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
6938 
6939 #define S_RGMIIRXFIFOUNDERFLOW    22
6940 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
6941 #define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
6942 
6943 #define S_RXPKTSIZEERROR    21
6944 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
6945 #define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
6946 
6947 #define S_WOLPATDETECTED    20
6948 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
6949 #define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
6950 
6951 #define S_TXFIFO_PRTY_ERR    17
6952 #define M_TXFIFO_PRTY_ERR    0x7
6953 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
6954 #define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR)
6955 
6956 #define S_RXFIFO_PRTY_ERR    14
6957 #define M_RXFIFO_PRTY_ERR    0x7
6958 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
6959 #define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR)
6960 
6961 #define S_TXFIFO_UNDERRUN    13
6962 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
6963 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
6964 
6965 #define S_RXFIFO_OVERFLOW    12
6966 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
6967 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
6968 
6969 #define S_SERDESBIST_ERR    8
6970 #define M_SERDESBIST_ERR    0xf
6971 #define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR)
6972 #define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR)
6973 
6974 #define S_SERDES_LOS    4
6975 #define M_SERDES_LOS    0xf
6976 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
6977 #define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS)
6978 
6979 #define S_XAUIPCSCTCERR    3
6980 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
6981 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
6982 
6983 #define S_XAUIPCSALIGNCHANGE    2
6984 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
6985 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
6986 
6987 #define S_RGMIILINKSTSCHANGE    1
6988 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
6989 #define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
6990 
6991 #define S_XGM_INT    0
6992 #define V_XGM_INT(x) ((x) << S_XGM_INT)
6993 #define F_XGM_INT    V_XGM_INT(1U)
6994 
6995 #define S_SERDESBISTERR    8
6996 #define M_SERDESBISTERR    0xf
6997 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
6998 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
6999 
7000 #define S_SERDESLOWSIGCHANGE    4
7001 #define M_SERDESLOWSIGCHANGE    0xf
7002 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
7003 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
7004 
7005 #define A_XGM_INT_CAUSE 0x8d8
7006 #define A_XGM_XAUI_ACT_CTRL 0x8dc
7007 
7008 #define S_TXACTENABLE    1
7009 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
7010 #define F_TXACTENABLE    V_TXACTENABLE(1U)
7011 
7012 #define A_XGM_SERDES_CTRL0 0x8e0
7013 
7014 #define S_INTSERLPBK3    27
7015 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
7016 #define F_INTSERLPBK3    V_INTSERLPBK3(1U)
7017 
7018 #define S_INTSERLPBK2    26
7019 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
7020 #define F_INTSERLPBK2    V_INTSERLPBK2(1U)
7021 
7022 #define S_INTSERLPBK1    25
7023 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
7024 #define F_INTSERLPBK1    V_INTSERLPBK1(1U)
7025 
7026 #define S_INTSERLPBK0    24
7027 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
7028 #define F_INTSERLPBK0    V_INTSERLPBK0(1U)
7029 
7030 #define S_RESET3    23
7031 #define V_RESET3(x) ((x) << S_RESET3)
7032 #define F_RESET3    V_RESET3(1U)
7033 
7034 #define S_RESET2    22
7035 #define V_RESET2(x) ((x) << S_RESET2)
7036 #define F_RESET2    V_RESET2(1U)
7037 
7038 #define S_RESET1    21
7039 #define V_RESET1(x) ((x) << S_RESET1)
7040 #define F_RESET1    V_RESET1(1U)
7041 
7042 #define S_RESET0    20
7043 #define V_RESET0(x) ((x) << S_RESET0)
7044 #define F_RESET0    V_RESET0(1U)
7045 
7046 #define S_PWRDN3    19
7047 #define V_PWRDN3(x) ((x) << S_PWRDN3)
7048 #define F_PWRDN3    V_PWRDN3(1U)
7049 
7050 #define S_PWRDN2    18
7051 #define V_PWRDN2(x) ((x) << S_PWRDN2)
7052 #define F_PWRDN2    V_PWRDN2(1U)
7053 
7054 #define S_PWRDN1    17
7055 #define V_PWRDN1(x) ((x) << S_PWRDN1)
7056 #define F_PWRDN1    V_PWRDN1(1U)
7057 
7058 #define S_PWRDN0    16
7059 #define V_PWRDN0(x) ((x) << S_PWRDN0)
7060 #define F_PWRDN0    V_PWRDN0(1U)
7061 
7062 #define S_RESETPLL23    15
7063 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
7064 #define F_RESETPLL23    V_RESETPLL23(1U)
7065 
7066 #define S_RESETPLL01    14
7067 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
7068 #define F_RESETPLL01    V_RESETPLL01(1U)
7069 
7070 #define S_PW23    12
7071 #define M_PW23    0x3
7072 #define V_PW23(x) ((x) << S_PW23)
7073 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
7074 
7075 #define S_PW01    10
7076 #define M_PW01    0x3
7077 #define V_PW01(x) ((x) << S_PW01)
7078 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
7079 
7080 #define S_XGM_DEQ    6
7081 #define M_XGM_DEQ    0xf
7082 #define V_XGM_DEQ(x) ((x) << S_XGM_DEQ)
7083 #define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ)
7084 
7085 #define S_XGM_DTX    2
7086 #define M_XGM_DTX    0xf
7087 #define V_XGM_DTX(x) ((x) << S_XGM_DTX)
7088 #define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX)
7089 
7090 #define S_XGM_LODRV    1
7091 #define V_XGM_LODRV(x) ((x) << S_XGM_LODRV)
7092 #define F_XGM_LODRV    V_XGM_LODRV(1U)
7093 
7094 #define S_XGM_HIDRV    0
7095 #define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV)
7096 #define F_XGM_HIDRV    V_XGM_HIDRV(1U)
7097 
7098 #define A_XGM_SERDES_CTRL1 0x8e4
7099 
7100 #define S_FMOFFSET3    19
7101 #define M_FMOFFSET3    0x1f
7102 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
7103 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
7104 
7105 #define S_FMOFFSETEN3    18
7106 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
7107 #define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
7108 
7109 #define S_FMOFFSET2    13
7110 #define M_FMOFFSET2    0x1f
7111 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
7112 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
7113 
7114 #define S_FMOFFSETEN2    12
7115 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
7116 #define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
7117 
7118 #define S_FMOFFSET1    7
7119 #define M_FMOFFSET1    0x1f
7120 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
7121 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
7122 
7123 #define S_FMOFFSETEN1    6
7124 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
7125 #define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
7126 
7127 #define S_FMOFFSET0    1
7128 #define M_FMOFFSET0    0x1f
7129 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
7130 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
7131 
7132 #define S_FMOFFSETEN0    0
7133 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
7134 #define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
7135 
7136 #define A_XGM_SERDES_CTRL2 0x8e8
7137 
7138 #define S_DNIN3    11
7139 #define V_DNIN3(x) ((x) << S_DNIN3)
7140 #define F_DNIN3    V_DNIN3(1U)
7141 
7142 #define S_UPIN3    10
7143 #define V_UPIN3(x) ((x) << S_UPIN3)
7144 #define F_UPIN3    V_UPIN3(1U)
7145 
7146 #define S_RXSLAVE3    9
7147 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
7148 #define F_RXSLAVE3    V_RXSLAVE3(1U)
7149 
7150 #define S_DNIN2    8
7151 #define V_DNIN2(x) ((x) << S_DNIN2)
7152 #define F_DNIN2    V_DNIN2(1U)
7153 
7154 #define S_UPIN2    7
7155 #define V_UPIN2(x) ((x) << S_UPIN2)
7156 #define F_UPIN2    V_UPIN2(1U)
7157 
7158 #define S_RXSLAVE2    6
7159 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
7160 #define F_RXSLAVE2    V_RXSLAVE2(1U)
7161 
7162 #define S_DNIN1    5
7163 #define V_DNIN1(x) ((x) << S_DNIN1)
7164 #define F_DNIN1    V_DNIN1(1U)
7165 
7166 #define S_UPIN1    4
7167 #define V_UPIN1(x) ((x) << S_UPIN1)
7168 #define F_UPIN1    V_UPIN1(1U)
7169 
7170 #define S_RXSLAVE1    3
7171 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
7172 #define F_RXSLAVE1    V_RXSLAVE1(1U)
7173 
7174 #define S_DNIN0    2
7175 #define V_DNIN0(x) ((x) << S_DNIN0)
7176 #define F_DNIN0    V_DNIN0(1U)
7177 
7178 #define S_UPIN0    1
7179 #define V_UPIN0(x) ((x) << S_UPIN0)
7180 #define F_UPIN0    V_UPIN0(1U)
7181 
7182 #define S_RXSLAVE0    0
7183 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
7184 #define F_RXSLAVE0    V_RXSLAVE0(1U)
7185 
7186 #define A_XGM_SERDES_CTRL3 0x8ec
7187 
7188 #define S_EXTBISTCHKERRCLR3    31
7189 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
7190 #define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
7191 
7192 #define S_EXTBISTCHKEN3    30
7193 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
7194 #define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
7195 
7196 #define S_EXTBISTGENEN3    29
7197 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
7198 #define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
7199 
7200 #define S_EXTBISTPAT3    26
7201 #define M_EXTBISTPAT3    0x7
7202 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
7203 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
7204 
7205 #define S_EXTPARRESET3    25
7206 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
7207 #define F_EXTPARRESET3    V_EXTPARRESET3(1U)
7208 
7209 #define S_EXTPARLPBK3    24
7210 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
7211 #define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
7212 
7213 #define S_EXTBISTCHKERRCLR2    23
7214 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
7215 #define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
7216 
7217 #define S_EXTBISTCHKEN2    22
7218 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
7219 #define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
7220 
7221 #define S_EXTBISTGENEN2    21
7222 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
7223 #define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
7224 
7225 #define S_EXTBISTPAT2    18
7226 #define M_EXTBISTPAT2    0x7
7227 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
7228 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
7229 
7230 #define S_EXTPARRESET2    17
7231 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
7232 #define F_EXTPARRESET2    V_EXTPARRESET2(1U)
7233 
7234 #define S_EXTPARLPBK2    16
7235 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
7236 #define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
7237 
7238 #define S_EXTBISTCHKERRCLR1    15
7239 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
7240 #define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
7241 
7242 #define S_EXTBISTCHKEN1    14
7243 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
7244 #define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
7245 
7246 #define S_EXTBISTGENEN1    13
7247 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
7248 #define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
7249 
7250 #define S_EXTBISTPAT1    10
7251 #define M_EXTBISTPAT1    0x7
7252 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
7253 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
7254 
7255 #define S_EXTPARRESET1    9
7256 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
7257 #define F_EXTPARRESET1    V_EXTPARRESET1(1U)
7258 
7259 #define S_EXTPARLPBK1    8
7260 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
7261 #define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
7262 
7263 #define S_EXTBISTCHKERRCLR0    7
7264 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
7265 #define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
7266 
7267 #define S_EXTBISTCHKEN0    6
7268 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
7269 #define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
7270 
7271 #define S_EXTBISTGENEN0    5
7272 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
7273 #define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
7274 
7275 #define S_EXTBISTPAT0    2
7276 #define M_EXTBISTPAT0    0x7
7277 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
7278 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
7279 
7280 #define S_EXTPARRESET0    1
7281 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
7282 #define F_EXTPARRESET0    V_EXTPARRESET0(1U)
7283 
7284 #define S_EXTPARLPBK0    0
7285 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
7286 #define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
7287 
7288 #define A_XGM_SERDES_STAT0 0x8f0
7289 
7290 #define S_EXTBISTCHKERRCNT0    4
7291 #define M_EXTBISTCHKERRCNT0    0xffffff
7292 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
7293 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
7294 
7295 #define S_EXTBISTCHKFMD0    3
7296 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
7297 #define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
7298 
7299 #define S_LOWSIG0    0
7300 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
7301 #define F_LOWSIG0    V_LOWSIG0(1U)
7302 
7303 #define A_XGM_SERDES_STAT1 0x8f4
7304 
7305 #define S_EXTBISTCHKERRCNT1    4
7306 #define M_EXTBISTCHKERRCNT1    0xffffff
7307 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
7308 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
7309 
7310 #define S_EXTBISTCHKFMD1    3
7311 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
7312 #define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
7313 
7314 #define S_LOWSIG1    0
7315 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
7316 #define F_LOWSIG1    V_LOWSIG1(1U)
7317 
7318 #define A_XGM_SERDES_STAT2 0x8f8
7319 
7320 #define S_EXTBISTCHKERRCNT2    4
7321 #define M_EXTBISTCHKERRCNT2    0xffffff
7322 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
7323 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
7324 
7325 #define S_EXTBISTCHKFMD2    3
7326 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
7327 #define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
7328 
7329 #define S_LOWSIG2    0
7330 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
7331 #define F_LOWSIG2    V_LOWSIG2(1U)
7332 
7333 #define A_XGM_SERDES_STAT3 0x8fc
7334 
7335 #define S_EXTBISTCHKERRCNT3    4
7336 #define M_EXTBISTCHKERRCNT3    0xffffff
7337 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
7338 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
7339 
7340 #define S_EXTBISTCHKFMD3    3
7341 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
7342 #define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
7343 
7344 #define S_LOWSIG3    0
7345 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
7346 #define F_LOWSIG3    V_LOWSIG3(1U)
7347 
7348 #define A_XGM_STAT_TX_BYTE_LOW 0x900
7349 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
7350 
7351 #define S_TXBYTES_HIGH    0
7352 #define M_TXBYTES_HIGH    0x1fff
7353 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
7354 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
7355 
7356 #define A_XGM_STAT_TX_FRAME_LOW 0x908
7357 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
7358 
7359 #define S_TXFRAMES_HIGH    0
7360 #define M_TXFRAMES_HIGH    0xf
7361 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
7362 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
7363 
7364 #define A_XGM_STAT_TX_BCAST 0x910
7365 #define A_XGM_STAT_TX_MCAST 0x914
7366 #define A_XGM_STAT_TX_PAUSE 0x918
7367 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
7368 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
7369 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
7370 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
7371 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
7372 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
7373 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
7374 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
7375 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
7376 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
7377 
7378 #define S_RXBYTES_HIGH    0
7379 #define M_RXBYTES_HIGH    0x1fff
7380 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
7381 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
7382 
7383 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
7384 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
7385 
7386 #define S_RXFRAMES_HIGH    0
7387 #define M_RXFRAMES_HIGH    0xf
7388 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
7389 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
7390 
7391 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
7392 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
7393 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
7394 
7395 #define S_RXPAUSEFRAMES    0
7396 #define M_RXPAUSEFRAMES    0xffff
7397 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
7398 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
7399 
7400 #define A_XGM_STAT_RX_64B_FRAMES 0x958
7401 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
7402 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
7403 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
7404 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
7405 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
7406 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
7407 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
7408 
7409 #define S_RXSHORTFRAMES    0
7410 #define M_RXSHORTFRAMES    0xffff
7411 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
7412 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
7413 
7414 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
7415 
7416 #define S_RXOVERSIZEFRAMES    0
7417 #define M_RXOVERSIZEFRAMES    0xffff
7418 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
7419 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
7420 
7421 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
7422 
7423 #define S_RXJABBERFRAMES    0
7424 #define M_RXJABBERFRAMES    0xffff
7425 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
7426 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
7427 
7428 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
7429 
7430 #define S_RXCRCERRFRAMES    0
7431 #define M_RXCRCERRFRAMES    0xffff
7432 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
7433 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
7434 
7435 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
7436 
7437 #define S_RXLENGTHERRFRAMES    0
7438 #define M_RXLENGTHERRFRAMES    0xffff
7439 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
7440 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
7441 
7442 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
7443 
7444 #define S_RXSYMCODEERRFRAMES    0
7445 #define M_RXSYMCODEERRFRAMES    0xffff
7446 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
7447 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
7448 
7449 #define A_XGM_SERDES_STATUS0 0x98c
7450 
7451 #define S_RXERRLANE3    9
7452 #define M_RXERRLANE3    0x7
7453 #define V_RXERRLANE3(x) ((x) << S_RXERRLANE3)
7454 #define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3)
7455 
7456 #define S_RXERRLANE2    6
7457 #define M_RXERRLANE2    0x7
7458 #define V_RXERRLANE2(x) ((x) << S_RXERRLANE2)
7459 #define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2)
7460 
7461 #define S_RXERRLANE1    3
7462 #define M_RXERRLANE1    0x7
7463 #define V_RXERRLANE1(x) ((x) << S_RXERRLANE1)
7464 #define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1)
7465 
7466 #define S_RXERRLANE0    0
7467 #define M_RXERRLANE0    0x7
7468 #define V_RXERRLANE0(x) ((x) << S_RXERRLANE0)
7469 #define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0)
7470 
7471 #define A_XGM_SERDES_STATUS1 0x990
7472 
7473 #define S_RXKLOCKLANE3    11
7474 #define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3)
7475 #define F_RXKLOCKLANE3    V_RXKLOCKLANE3(1U)
7476 
7477 #define S_RXKLOCKLANE2    10
7478 #define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2)
7479 #define F_RXKLOCKLANE2    V_RXKLOCKLANE2(1U)
7480 
7481 #define S_RXKLOCKLANE1    9
7482 #define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1)
7483 #define F_RXKLOCKLANE1    V_RXKLOCKLANE1(1U)
7484 
7485 #define S_RXKLOCKLANE0    8
7486 #define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0)
7487 #define F_RXKLOCKLANE0    V_RXKLOCKLANE0(1U)
7488 
7489 #define S_RXUFLOWLANE3    7
7490 #define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3)
7491 #define F_RXUFLOWLANE3    V_RXUFLOWLANE3(1U)
7492 
7493 #define S_RXUFLOWLANE2    6
7494 #define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2)
7495 #define F_RXUFLOWLANE2    V_RXUFLOWLANE2(1U)
7496 
7497 #define S_RXUFLOWLANE1    5
7498 #define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1)
7499 #define F_RXUFLOWLANE1    V_RXUFLOWLANE1(1U)
7500 
7501 #define S_RXUFLOWLANE0    4
7502 #define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0)
7503 #define F_RXUFLOWLANE0    V_RXUFLOWLANE0(1U)
7504 
7505 #define S_RXOFLOWLANE3    3
7506 #define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3)
7507 #define F_RXOFLOWLANE3    V_RXOFLOWLANE3(1U)
7508 
7509 #define S_RXOFLOWLANE2    2
7510 #define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2)
7511 #define F_RXOFLOWLANE2    V_RXOFLOWLANE2(1U)
7512 
7513 #define S_RXOFLOWLANE1    1
7514 #define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1)
7515 #define F_RXOFLOWLANE1    V_RXOFLOWLANE1(1U)
7516 
7517 #define S_RXOFLOWLANE0    0
7518 #define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0)
7519 #define F_RXOFLOWLANE0    V_RXOFLOWLANE0(1U)
7520 
7521 #define A_XGM_SERDES_STATUS2 0x994
7522 
7523 #define S_XGM_RXEIDLANE3    11
7524 #define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3)
7525 #define F_XGM_RXEIDLANE3    V_XGM_RXEIDLANE3(1U)
7526 
7527 #define S_XGM_RXEIDLANE2    10
7528 #define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2)
7529 #define F_XGM_RXEIDLANE2    V_XGM_RXEIDLANE2(1U)
7530 
7531 #define S_XGM_RXEIDLANE1    9
7532 #define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1)
7533 #define F_XGM_RXEIDLANE1    V_XGM_RXEIDLANE1(1U)
7534 
7535 #define S_XGM_RXEIDLANE0    8
7536 #define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0)
7537 #define F_XGM_RXEIDLANE0    V_XGM_RXEIDLANE0(1U)
7538 
7539 #define S_RXREMSKIPLANE3    7
7540 #define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3)
7541 #define F_RXREMSKIPLANE3    V_RXREMSKIPLANE3(1U)
7542 
7543 #define S_RXREMSKIPLANE2    6
7544 #define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2)
7545 #define F_RXREMSKIPLANE2    V_RXREMSKIPLANE2(1U)
7546 
7547 #define S_RXREMSKIPLANE1    5
7548 #define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1)
7549 #define F_RXREMSKIPLANE1    V_RXREMSKIPLANE1(1U)
7550 
7551 #define S_RXREMSKIPLANE0    4
7552 #define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0)
7553 #define F_RXREMSKIPLANE0    V_RXREMSKIPLANE0(1U)
7554 
7555 #define S_RXADDSKIPLANE3    3
7556 #define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3)
7557 #define F_RXADDSKIPLANE3    V_RXADDSKIPLANE3(1U)
7558 
7559 #define S_RXADDSKIPLANE2    2
7560 #define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2)
7561 #define F_RXADDSKIPLANE2    V_RXADDSKIPLANE2(1U)
7562 
7563 #define S_RXADDSKIPLANE1    1
7564 #define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1)
7565 #define F_RXADDSKIPLANE1    V_RXADDSKIPLANE1(1U)
7566 
7567 #define S_RXADDSKIPLANE0    0
7568 #define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0)
7569 #define F_RXADDSKIPLANE0    V_RXADDSKIPLANE0(1U)
7570 
7571 #define A_XGM_XAUI_PCS_ERR 0x998
7572 
7573 #define S_PCS_SYNCSTATUS    5
7574 #define M_PCS_SYNCSTATUS    0xf
7575 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
7576 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
7577 
7578 #define S_PCS_CTCFIFOERR    1
7579 #define M_PCS_CTCFIFOERR    0xf
7580 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
7581 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
7582 
7583 #define S_PCS_NOTALIGNED    0
7584 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
7585 #define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
7586 
7587 #define A_XGM_RGMII_STATUS 0x99c
7588 
7589 #define S_GMIIDUPLEX    3
7590 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
7591 #define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
7592 
7593 #define S_GMIISPEED    1
7594 #define M_GMIISPEED    0x3
7595 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
7596 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
7597 
7598 #define S_GMIILINKSTATUS    0
7599 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
7600 #define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
7601 
7602 #define A_XGM_WOL_STATUS 0x9a0
7603 
7604 #define S_PATDETECTED    31
7605 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
7606 #define F_PATDETECTED    V_PATDETECTED(1U)
7607 
7608 #define S_MATCHEDFILTER    0
7609 #define M_MATCHEDFILTER    0x7
7610 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
7611 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
7612 
7613 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
7614 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
7615 
7616 #define S_TXSPI4SOPCNT    16
7617 #define M_TXSPI4SOPCNT    0xffff
7618 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
7619 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
7620 
7621 #define S_TXSPI4EOPCNT    0
7622 #define M_TXSPI4EOPCNT    0xffff
7623 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
7624 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
7625 
7626 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
7627 
7628 #define S_RXSPI4SOPCNT    16
7629 #define M_RXSPI4SOPCNT    0xffff
7630 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
7631 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
7632 
7633 #define S_RXSPI4EOPCNT    0
7634 #define M_RXSPI4EOPCNT    0xffff
7635 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
7636 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
7637 
7638 /* registers for module XGMAC0_1 */
7639 #define XGMAC0_1_BASE_ADDR 0xa00
7640