1 /* $OpenBSD: if_wbreg.h,v 1.9 2012/10/18 21:44:21 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_wbreg.h,v 1.4 1999/07/11 00:56:07 wpaul Exp $ 35 */ 36 37 /* 38 * Winbond register definitions. 39 */ 40 41 #define WB_BUSCTL 0x00 /* bus control */ 42 #define WB_TXSTART 0x04 /* tx start demand */ 43 #define WB_RXSTART 0x08 /* rx start demand */ 44 #define WB_RXADDR 0x0C /* rx descriptor list start addr */ 45 #define WB_TXADDR 0x10 /* tx descriptor list start addr */ 46 #define WB_ISR 0x14 /* interrupt status register */ 47 #define WB_NETCFG 0x18 /* network config register */ 48 #define WB_IMR 0x1C /* interrupt mask */ 49 #define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */ 50 #define WB_SIO 0x24 /* MII and ROM/EEPROM access */ 51 #define WB_BOOTROMADDR 0x28 52 #define WB_TIMER 0x2C /* general timer */ 53 #define WB_CURRXCTL 0x30 /* current RX descriptor */ 54 #define WB_CURRXBUF 0x34 /* current RX buffer */ 55 #define WB_MAR0 0x38 /* multicast filter 0 */ 56 #define WB_MAR1 0x3C /* multicast filter 1 */ 57 #define WB_NODE0 0x40 /* station address 0 */ 58 #define WB_NODE1 0x44 /* station address 1 */ 59 #define WB_BOOTROMSIZE 0x48 /* boot ROM size */ 60 #define WB_CURTXCTL 0x4C /* current TX descriptor */ 61 #define WB_CURTXBUF 0x50 /* current TX buffer */ 62 63 /* 64 * Bus control bits. 65 */ 66 #define WB_BUSCTL_RESET 0x00000001 67 #define WB_BUSCTL_ARBITRATION 0x00000002 68 #define WB_BUSCTL_SKIPLEN 0x0000007C 69 #define WB_BUSCTL_BUF_BIGENDIAN 0x00000080 70 #define WB_BUSCTL_BURSTLEN 0x00003F00 71 #define WB_BUSCTL_CACHEALIGN 0x0000C000 72 #define WB_BUSCTL_DES_BIGENDIAN 0x00100000 73 #define WB_BUSCTL_WAIT 0x00200000 74 #define WB_BUSCTL_MUSTBEONE 0x00400000 75 76 #define WB_SKIPLEN_1LONG 0x00000004 77 #define WB_SKIPLEN_2LONG 0x00000008 78 #define WB_SKIPLEN_3LONG 0x00000010 79 #define WB_SKIPLEN_4LONG 0x00000020 80 #define WB_SKIPLEN_5LONG 0x00000040 81 82 #define WB_CACHEALIGN_NONE 0x00000000 83 #define WB_CACHEALIGN_8LONG 0x00004000 84 #define WB_CACHEALIGN_16LONG 0x00008000 85 #define WB_CACHEALIGN_32LONG 0x0000C000 86 87 #define WB_BURSTLEN_USECA 0x00000000 88 #define WB_BURSTLEN_1LONG 0x00000100 89 #define WB_BURSTLEN_2LONG 0x00000200 90 #define WB_BURSTLEN_4LONG 0x00000400 91 #define WB_BURSTLEN_8LONG 0x00000800 92 #define WB_BURSTLEN_16LONG 0x00001000 93 #define WB_BURSTLEN_32LONG 0x00002000 94 95 #define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \ 96 WB_BURSTLEN_8LONG) 97 98 /* 99 * Interrupt status bits. 100 */ 101 #define WB_ISR_TX_OK 0x00000001 102 #define WB_ISR_TX_IDLE 0x00000002 103 #define WB_ISR_TX_NOBUF 0x00000004 104 #define WB_ISR_RX_EARLY 0x00000008 105 #define WB_ISR_RX_ERR 0x00000010 106 #define WB_ISR_TX_UNDERRUN 0x00000020 107 #define WB_ISR_RX_OK 0x00000040 108 #define WB_ISR_RX_NOBUF 0x00000080 109 #define WB_ISR_RX_IDLE 0x00000100 110 #define WB_ISR_TX_EARLY 0x00000400 111 #define WB_ISR_TIMER_EXPIRED 0x00000800 112 #define WB_ISR_BUS_ERR 0x00002000 113 #define WB_ISR_ABNORMAL 0x00008000 114 #define WB_ISR_NORMAL 0x00010000 115 #define WB_ISR_RX_STATE 0x000E0000 116 #define WB_ISR_TX_STATE 0x00700000 117 #define WB_ISR_BUSERRTYPE 0x03800000 118 119 /* 120 * The RX_STATE and TX_STATE fields are not described anywhere in the 121 * Winbond datasheet, however it appears that the Winbond chip is an 122 * attempt at a DEC 'tulip' clone, hence the ISR register is identical 123 * to that of the tulip chip and we can steal the bit definitions from 124 * the tulip documentation. 125 */ 126 #define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 127 #define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 128 #define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 129 #define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 130 #define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 131 #define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 132 #define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 133 #define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 134 135 #define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */ 136 #define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 137 #define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 138 #define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 139 #define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 140 #define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 141 #define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 142 #define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 143 144 /* 145 * Network config bits. 146 */ 147 #define WB_NETCFG_RX_ON 0x00000002 148 #define WB_NETCFG_RX_ALLPHYS 0x00000008 149 #define WB_NETCFG_RX_MULTI 0x00000010 150 #define WB_NETCFG_RX_BROAD 0x00000020 151 #define WB_NETCFG_RX_RUNT 0x00000040 152 #define WB_NETCFG_RX_ERR 0x00000080 153 #define WB_NETCFG_FULLDUPLEX 0x00000200 154 #define WB_NETCFG_LOOPBACK 0x00000C00 155 #define WB_NETCFG_TX_ON 0x00002000 156 #define WB_NETCFG_TX_THRESH 0x001FC000 157 #define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000 158 #define WB_NETCFG_100MBPS 0x20000000 159 #define WB_NETCFG_TX_EARLY_ON 0x40000000 160 #define WB_NETCFG_RX_EARLY_ON 0x80000000 161 162 /* 163 * The tx threshold can be adjusted in increments of 32 bytes. 164 */ 165 #define WB_TXTHRESH(x) ((x >> 5) << 14) 166 #define WB_TXTHRESH_CHUNK 32 167 #define WB_TXTHRESH_INIT 0 /*72*/ 168 169 /* 170 * Interrupt mask bits. 171 */ 172 #define WB_IMR_TX_OK 0x00000001 173 #define WB_IMR_TX_IDLE 0x00000002 174 #define WB_IMR_TX_NOBUF 0x00000004 175 #define WB_IMR_RX_EARLY 0x00000008 176 #define WB_IMR_RX_ERR 0x00000010 177 #define WB_IMR_TX_UNDERRUN 0x00000020 178 #define WB_IMR_RX_OK 0x00000040 179 #define WB_IMR_RX_NOBUF 0x00000080 180 #define WB_IMR_RX_IDLE 0x00000100 181 #define WB_IMR_TX_EARLY 0x00000400 182 #define WB_IMR_TIMER_EXPIRED 0x00000800 183 #define WB_IMR_BUS_ERR 0x00002000 184 #define WB_IMR_ABNORMAL 0x00008000 185 #define WB_IMR_NORMAL 0x00010000 186 187 #define WB_INTRS \ 188 (WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \ 189 WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \ 190 WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY) 191 /* 192 * Serial I/O (EEPROM/ROM) bits. 193 */ 194 #define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 195 #define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 196 #define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 197 #define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 198 #define WB_SIO_ROMDATA4 0x00000010 199 #define WB_SIO_ROMDATA5 0x00000020 200 #define WB_SIO_ROMDATA6 0x00000040 201 #define WB_SIO_ROMDATA7 0x00000080 202 #define WB_SIO_ROMCTL_WRITE 0x00000200 203 #define WB_SIO_ROMCTL_READ 0x00000400 204 #define WB_SIO_EESEL 0x00000800 205 #define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */ 206 #define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */ 207 #define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */ 208 #define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */ 209 210 #define WB_EECMD_WRITE 0x140 211 #define WB_EECMD_READ 0x180 212 #define WB_EECMD_ERASE 0x1c0 213 214 /* 215 * Winbond TX/RX descriptor structure. 216 */ 217 218 struct wb_desc { 219 u_int32_t wb_status; 220 u_int32_t wb_ctl; 221 u_int32_t wb_ptr1; 222 u_int32_t wb_ptr2; 223 }; 224 225 #define wb_data wb_ptr1 226 #define wb_next wb_ptr2 227 228 #define WB_RXSTAT_CRCERR 0x00000002 229 #define WB_RXSTAT_DRIBBLE 0x00000004 230 #define WB_RXSTAT_MIIERR 0x00000008 231 #define WB_RXSTAT_LATEEVENT 0x00000040 232 #define WB_RXSTAT_GIANT 0x00000080 233 #define WB_RXSTAT_LASTFRAG 0x00000100 234 #define WB_RXSTAT_FIRSTFRAG 0x00000200 235 #define WB_RXSTAT_MULTICAST 0x00000400 236 #define WB_RXSTAT_RUNT 0x00000800 237 #define WB_RXSTAT_RXTYPE 0x00003000 238 #define WB_RXSTAT_RXERR 0x00008000 239 #define WB_RXSTAT_RXLEN 0x3FFF0000 240 #define WB_RXSTAT_RXCMP 0x40000000 241 #define WB_RXSTAT_OWN 0x80000000 242 243 #define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16) 244 #define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN) 245 246 #define WB_RXCTL_BUFLEN1 0x00000FFF 247 #define WB_RXCTL_BUFLEN2 0x00FFF000 248 #define WB_RXCTL_RLINK 0x01000000 249 #define WB_RXCTL_RLAST 0x02000000 250 251 #define WB_TXSTAT_DEFER 0x00000001 252 #define WB_TXSTAT_UNDERRUN 0x00000002 253 #define WB_TXSTAT_COLLCNT 0x00000078 254 #define WB_TXSTAT_SQE 0x00000080 255 #define WB_TXSTAT_ABORT 0x00000100 256 #define WB_TXSTAT_LATECOLL 0x00000200 257 #define WB_TXSTAT_NOCARRIER 0x00000400 258 #define WB_TXSTAT_CARRLOST 0x00000800 259 #define WB_TXSTAT_TXERR 0x00001000 260 #define WB_TXSTAT_OWN 0x80000000 261 262 #define WB_TXCTL_BUFLEN1 0x000007FF 263 #define WB_TXCTL_BUFLEN2 0x003FF800 264 #define WB_TXCTL_PAD 0x00800000 265 #define WB_TXCTL_TLINK 0x01000000 266 #define WB_TXCTL_TLAST 0x02000000 267 #define WB_TXCTL_NOCRC 0x08000000 268 #define WB_TXCTL_FIRSTFRAG 0x20000000 269 #define WB_TXCTL_LASTFRAG 0x40000000 270 #define WB_TXCTL_FINT 0x80000000 271 272 #define WB_MAXFRAGS 16 273 #define WB_RX_LIST_CNT 64 274 #define WB_TX_LIST_CNT 64 275 #define WB_MIN_FRAMELEN 60 276 277 /* 278 * A transmit 'super descriptor' is actually WB_MAXFRAGS regular 279 * descriptors clumped together. The idea here is to emulate the 280 * multi-fragment descriptor layout found in devices such as the 281 * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips. 282 * The advantage to using this scheme is that it avoids buffer copies. 283 * The disadvantage is that there's a certain amount of overhead due 284 * to the fact that each 'fragment' is 16 bytes long. In my tests, 285 * this limits top speed to about 10.5MB/sec. It should be more like 286 * 11.5MB/sec. However, the upshot is that you can achieve better 287 * results on slower machines: a Pentium 200 can pump out packets at 288 * same speed as a PII 400. 289 */ 290 struct wb_txdesc { 291 struct wb_desc wb_frag[WB_MAXFRAGS]; 292 }; 293 294 #define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next 295 #define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status 296 #define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl 297 #define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data 298 299 #define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status 300 301 #define WB_UNSENT 0x1234 302 303 #define WB_BUFBYTES (1024 * sizeof(u_int32_t)) 304 305 struct wb_buf { 306 u_int32_t wb_data[1024]; 307 }; 308 309 struct wb_list_data { 310 struct wb_buf wb_rxbufs[WB_RX_LIST_CNT]; 311 struct wb_desc wb_rx_list[WB_RX_LIST_CNT]; 312 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT]; 313 }; 314 315 struct wb_chain { 316 struct wb_txdesc *wb_ptr; 317 struct mbuf *wb_mbuf; 318 struct wb_chain *wb_nextdesc; 319 u_int8_t wb_lastdesc; 320 }; 321 322 struct wb_chain_onefrag { 323 struct wb_desc *wb_ptr; 324 struct mbuf *wb_mbuf; 325 void *wb_buf; 326 struct wb_chain_onefrag *wb_nextdesc; 327 u_int8_t wb_rlast; 328 }; 329 330 struct wb_chain_data { 331 u_int8_t wb_pad[WB_MIN_FRAMELEN]; 332 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT]; 333 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT]; 334 335 struct wb_chain_onefrag *wb_rx_head; 336 337 struct wb_chain *wb_tx_head; 338 struct wb_chain *wb_tx_tail; 339 struct wb_chain *wb_tx_free; 340 }; 341 342 struct wb_type { 343 u_int16_t wb_vid; 344 u_int16_t wb_did; 345 char *wb_name; 346 }; 347 348 struct wb_mii_frame { 349 u_int8_t mii_stdelim; 350 u_int8_t mii_opcode; 351 u_int8_t mii_phyaddr; 352 u_int8_t mii_regaddr; 353 u_int8_t mii_turnaround; 354 u_int16_t mii_data; 355 }; 356 357 /* 358 * MII constants 359 */ 360 #define WB_MII_STARTDELIM 0x01 361 #define WB_MII_READOP 0x02 362 #define WB_MII_WRITEOP 0x01 363 #define WB_MII_TURNAROUND 0x02 364 365 struct wb_softc { 366 struct device sc_dev; /* generic device structure */ 367 void * sc_ih; /* interrupt handler cookie */ 368 struct arpcom arpcom; /* interface info */ 369 struct timeout wb_tick_tmo; 370 mii_data_t sc_mii; 371 bus_space_handle_t wb_bhandle; 372 bus_space_tag_t wb_btag; 373 struct wb_type *wb_info; /* 3Com adapter info */ 374 u_int8_t wb_type; 375 u_int16_t wb_txthresh; 376 int wb_cachesize; 377 caddr_t wb_ldata_ptr; 378 struct wb_list_data *wb_ldata; 379 struct wb_chain_data wb_cdata; 380 }; 381 382 /* 383 * register space access macros 384 */ 385 #define CSR_WRITE_4(sc, reg, val) \ 386 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val) 387 #define CSR_WRITE_2(sc, reg, val) \ 388 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val) 389 #define CSR_WRITE_1(sc, reg, val) \ 390 bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val) 391 392 #define CSR_READ_4(sc, reg) \ 393 bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg) 394 #define CSR_READ_2(sc, reg) \ 395 bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg) 396 #define CSR_READ_1(sc, reg) \ 397 bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg) 398 399 #define WB_TIMEOUT 1000 400 401 /* 402 * General constants that are fun to know. 403 * 404 * Winbond PCI vendor ID 405 */ 406 #define WB_VENDORID 0x1050 407 408 /* 409 * Winbond device IDs. 410 */ 411 #define WB_DEVICEID_840F 0x0840 412 413 /* 414 * Compex vendor ID. 415 */ 416 #define CP_VENDORID 0x11F6 417 418 /* 419 * Compex device IDs. 420 */ 421 #define CP_DEVICEID_RL100 0x2011 422 423 /* 424 * PCI low memory base and low I/O base register, and 425 * other PCI registers. 426 */ 427 428 #define WB_PCI_VENDOR_ID 0x00 429 #define WB_PCI_DEVICE_ID 0x02 430 #define WB_PCI_COMMAND 0x04 431 #define WB_PCI_STATUS 0x06 432 #define WB_PCI_CLASSCODE 0x09 433 #define WB_PCI_CACHELEN 0x0C 434 #define WB_PCI_LATENCY_TIMER 0x0D 435 #define WB_PCI_HEADER_TYPE 0x0E 436 #define WB_PCI_LOIO 0x10 437 #define WB_PCI_LOMEM 0x14 438 #define WB_PCI_BIOSROM 0x30 439 #define WB_PCI_INTLINE 0x3C 440 #define WB_PCI_INTPIN 0x3D 441 #define WB_PCI_MINGNT 0x3E 442 #define WB_PCI_MINLAT 0x0F 443 #define WB_PCI_RESETOPT 0x48 444 #define WB_PCI_EEPROM_DATA 0x4C 445 446 /* power management registers */ 447 #define WB_PCI_CAPID 0xDC /* 8 bits */ 448 #define WB_PCI_NEXTPTR 0xDD /* 8 bits */ 449 #define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 450 #define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 451 452 #define WB_PME_EN 0x0010 453 #define WB_PME_STATUS 0x8000 454 455 #ifdef __alpha__ 456 #undef vtophys 457 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)va) 458 #endif 459