1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8998_MASK \ 25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 26 27 #define VIG_SDM845_MASK \ 28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 29 30 #define VIG_SDM845_MASK_SDMA \ 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 33 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 34 35 #define DMA_MSM8998_MASK \ 36 (BIT(DPU_SSPP_QOS) |\ 37 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 38 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 39 40 #define VIG_SC7280_MASK \ 41 (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 42 43 #define VIG_SC7280_MASK_SDMA \ 44 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 45 46 #define DMA_SDM845_MASK \ 47 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 48 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 49 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 50 51 #define DMA_CURSOR_SDM845_MASK \ 52 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 53 54 #define DMA_SDM845_MASK_SDMA \ 55 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 56 57 #define DMA_CURSOR_SDM845_MASK_SDMA \ 58 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 59 60 #define DMA_CURSOR_MSM8998_MASK \ 61 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 62 63 #define MIXER_MSM8998_MASK \ 64 (BIT(DPU_MIXER_SOURCESPLIT)) 65 66 #define MIXER_SDM845_MASK \ 67 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 68 69 #define MIXER_QCM2290_MASK \ 70 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 71 72 #define PINGPONG_SDM845_MASK \ 73 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 74 75 #define PINGPONG_SDM845_TE2_MASK \ 76 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 77 78 #define PINGPONG_SM8150_MASK \ 79 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 80 81 #define CTL_SC7280_MASK \ 82 (BIT(DPU_CTL_ACTIVE_CFG) | \ 83 BIT(DPU_CTL_FETCH_ACTIVE) | \ 84 BIT(DPU_CTL_VM_CFG) | \ 85 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 86 87 #define CTL_SM8550_MASK \ 88 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 89 90 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 91 92 #define INTF_SC7180_MASK \ 93 (BIT(DPU_INTF_INPUT_CTRL) | \ 94 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 95 BIT(DPU_DATA_HCTL_EN)) 96 97 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 98 99 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 100 BIT(DPU_WB_UBWC) | \ 101 BIT(DPU_WB_YUV_CONFIG) | \ 102 BIT(DPU_WB_PIPE_ALPHA) | \ 103 BIT(DPU_WB_XY_ROI_OFFSET) | \ 104 BIT(DPU_WB_QOS) | \ 105 BIT(DPU_WB_QOS_8LVL) | \ 106 BIT(DPU_WB_CDP) | \ 107 BIT(DPU_WB_INPUT_CTRL)) 108 109 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 110 #define DEFAULT_DPU_LINE_WIDTH 2048 111 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 112 113 #define MAX_HORZ_DECIMATION 4 114 #define MAX_VERT_DECIMATION 4 115 116 #define MAX_UPSCALE_RATIO 20 117 #define MAX_DOWNSCALE_RATIO 4 118 #define SSPP_UNITY_SCALE 1 119 120 #define STRCAT(X, Y) (X Y) 121 122 static const uint32_t plane_formats[] = { 123 DRM_FORMAT_ARGB8888, 124 DRM_FORMAT_ABGR8888, 125 DRM_FORMAT_RGBA8888, 126 DRM_FORMAT_BGRA8888, 127 DRM_FORMAT_XRGB8888, 128 DRM_FORMAT_RGBX8888, 129 DRM_FORMAT_BGRX8888, 130 DRM_FORMAT_XBGR8888, 131 DRM_FORMAT_ARGB2101010, 132 DRM_FORMAT_XRGB2101010, 133 DRM_FORMAT_RGB888, 134 DRM_FORMAT_BGR888, 135 DRM_FORMAT_RGB565, 136 DRM_FORMAT_BGR565, 137 DRM_FORMAT_ARGB1555, 138 DRM_FORMAT_ABGR1555, 139 DRM_FORMAT_RGBA5551, 140 DRM_FORMAT_BGRA5551, 141 DRM_FORMAT_XRGB1555, 142 DRM_FORMAT_XBGR1555, 143 DRM_FORMAT_RGBX5551, 144 DRM_FORMAT_BGRX5551, 145 DRM_FORMAT_ARGB4444, 146 DRM_FORMAT_ABGR4444, 147 DRM_FORMAT_RGBA4444, 148 DRM_FORMAT_BGRA4444, 149 DRM_FORMAT_XRGB4444, 150 DRM_FORMAT_XBGR4444, 151 DRM_FORMAT_RGBX4444, 152 DRM_FORMAT_BGRX4444, 153 }; 154 155 static const uint32_t plane_formats_yuv[] = { 156 DRM_FORMAT_ARGB8888, 157 DRM_FORMAT_ABGR8888, 158 DRM_FORMAT_RGBA8888, 159 DRM_FORMAT_BGRX8888, 160 DRM_FORMAT_BGRA8888, 161 DRM_FORMAT_ARGB2101010, 162 DRM_FORMAT_XRGB2101010, 163 DRM_FORMAT_XRGB8888, 164 DRM_FORMAT_XBGR8888, 165 DRM_FORMAT_RGBX8888, 166 DRM_FORMAT_RGB888, 167 DRM_FORMAT_BGR888, 168 DRM_FORMAT_RGB565, 169 DRM_FORMAT_BGR565, 170 DRM_FORMAT_ARGB1555, 171 DRM_FORMAT_ABGR1555, 172 DRM_FORMAT_RGBA5551, 173 DRM_FORMAT_BGRA5551, 174 DRM_FORMAT_XRGB1555, 175 DRM_FORMAT_XBGR1555, 176 DRM_FORMAT_RGBX5551, 177 DRM_FORMAT_BGRX5551, 178 DRM_FORMAT_ARGB4444, 179 DRM_FORMAT_ABGR4444, 180 DRM_FORMAT_RGBA4444, 181 DRM_FORMAT_BGRA4444, 182 DRM_FORMAT_XRGB4444, 183 DRM_FORMAT_XBGR4444, 184 DRM_FORMAT_RGBX4444, 185 DRM_FORMAT_BGRX4444, 186 187 DRM_FORMAT_P010, 188 DRM_FORMAT_NV12, 189 DRM_FORMAT_NV21, 190 DRM_FORMAT_NV16, 191 DRM_FORMAT_NV61, 192 DRM_FORMAT_VYUY, 193 DRM_FORMAT_UYVY, 194 DRM_FORMAT_YUYV, 195 DRM_FORMAT_YVYU, 196 DRM_FORMAT_YUV420, 197 DRM_FORMAT_YVU420, 198 }; 199 200 static const u32 rotation_v2_formats[] = { 201 DRM_FORMAT_NV12, 202 /* TODO add formats after validation */ 203 }; 204 205 static const u32 wb2_formats_rgb[] = { 206 DRM_FORMAT_RGB565, 207 DRM_FORMAT_BGR565, 208 DRM_FORMAT_RGB888, 209 DRM_FORMAT_ARGB8888, 210 DRM_FORMAT_RGBA8888, 211 DRM_FORMAT_ABGR8888, 212 DRM_FORMAT_XRGB8888, 213 DRM_FORMAT_RGBX8888, 214 DRM_FORMAT_XBGR8888, 215 DRM_FORMAT_ARGB1555, 216 DRM_FORMAT_RGBA5551, 217 DRM_FORMAT_XRGB1555, 218 DRM_FORMAT_RGBX5551, 219 DRM_FORMAT_ARGB4444, 220 DRM_FORMAT_RGBA4444, 221 DRM_FORMAT_RGBX4444, 222 DRM_FORMAT_XRGB4444, 223 DRM_FORMAT_BGR565, 224 DRM_FORMAT_BGR888, 225 DRM_FORMAT_ABGR8888, 226 DRM_FORMAT_BGRA8888, 227 DRM_FORMAT_BGRX8888, 228 DRM_FORMAT_XBGR8888, 229 DRM_FORMAT_ABGR1555, 230 DRM_FORMAT_BGRA5551, 231 DRM_FORMAT_XBGR1555, 232 DRM_FORMAT_BGRX5551, 233 DRM_FORMAT_ABGR4444, 234 DRM_FORMAT_BGRA4444, 235 DRM_FORMAT_BGRX4444, 236 DRM_FORMAT_XBGR4444, 237 }; 238 239 static const u32 wb2_formats_rgb_yuv[] = { 240 DRM_FORMAT_RGB565, 241 DRM_FORMAT_BGR565, 242 DRM_FORMAT_RGB888, 243 DRM_FORMAT_ARGB8888, 244 DRM_FORMAT_RGBA8888, 245 DRM_FORMAT_ABGR8888, 246 DRM_FORMAT_XRGB8888, 247 DRM_FORMAT_RGBX8888, 248 DRM_FORMAT_XBGR8888, 249 DRM_FORMAT_ARGB1555, 250 DRM_FORMAT_RGBA5551, 251 DRM_FORMAT_XRGB1555, 252 DRM_FORMAT_RGBX5551, 253 DRM_FORMAT_ARGB4444, 254 DRM_FORMAT_RGBA4444, 255 DRM_FORMAT_RGBX4444, 256 DRM_FORMAT_XRGB4444, 257 DRM_FORMAT_BGR565, 258 DRM_FORMAT_BGR888, 259 DRM_FORMAT_ABGR8888, 260 DRM_FORMAT_BGRA8888, 261 DRM_FORMAT_BGRX8888, 262 DRM_FORMAT_XBGR8888, 263 DRM_FORMAT_ABGR1555, 264 DRM_FORMAT_BGRA5551, 265 DRM_FORMAT_XBGR1555, 266 DRM_FORMAT_BGRX5551, 267 DRM_FORMAT_ABGR4444, 268 DRM_FORMAT_BGRA4444, 269 DRM_FORMAT_BGRX4444, 270 DRM_FORMAT_XBGR4444, 271 DRM_FORMAT_NV12, 272 }; 273 274 /************************************************************* 275 * SSPP sub blocks config 276 *************************************************************/ 277 278 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) 279 280 /* SSPP common configuration */ 281 #define _VIG_SBLK(scaler_ver) \ 282 { \ 283 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 284 .maxupscale = MAX_UPSCALE_RATIO, \ 285 .scaler_blk = {.name = "scaler", \ 286 .version = scaler_ver, \ 287 .base = 0xa00, .len = 0xa0,}, \ 288 .csc_blk = {.name = "csc", \ 289 .base = 0x1a00, .len = 0x100,}, \ 290 .format_list = plane_formats_yuv, \ 291 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 292 .virt_format_list = plane_formats, \ 293 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 294 .rotation_cfg = NULL, \ 295 } 296 297 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 298 { \ 299 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 300 .maxupscale = MAX_UPSCALE_RATIO, \ 301 .scaler_blk = {.name = "scaler", \ 302 .version = scaler_ver, \ 303 .base = 0xa00, .len = 0xa0,}, \ 304 .csc_blk = {.name = "csc", \ 305 .base = 0x1a00, .len = 0x100,}, \ 306 .format_list = plane_formats_yuv, \ 307 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 308 .virt_format_list = plane_formats, \ 309 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 310 .rotation_cfg = rot_cfg, \ 311 } 312 313 #define _VIG_SBLK_NOSCALE() \ 314 { \ 315 .maxdwnscale = SSPP_UNITY_SCALE, \ 316 .maxupscale = SSPP_UNITY_SCALE, \ 317 .format_list = plane_formats_yuv, \ 318 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 319 .virt_format_list = plane_formats, \ 320 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 321 } 322 323 #define _DMA_SBLK() \ 324 { \ 325 .maxdwnscale = SSPP_UNITY_SCALE, \ 326 .maxupscale = SSPP_UNITY_SCALE, \ 327 .format_list = plane_formats, \ 328 .num_formats = ARRAY_SIZE(plane_formats), \ 329 .virt_format_list = plane_formats, \ 330 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 331 } 332 333 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 334 .rot_maxheight = 1088, 335 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 336 .rot_format_list = rotation_v2_formats, 337 }; 338 339 static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale = 340 _VIG_SBLK_NOSCALE(); 341 342 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 = 343 _VIG_SBLK(SSPP_SCALER_VER(1, 2)); 344 345 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 = 346 _VIG_SBLK(SSPP_SCALER_VER(1, 3)); 347 348 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 = 349 _VIG_SBLK(SSPP_SCALER_VER(1, 4)); 350 351 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 = 352 _VIG_SBLK(SSPP_SCALER_VER(2, 4)); 353 354 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 = 355 _VIG_SBLK(SSPP_SCALER_VER(3, 0)); 356 357 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 = 358 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0), 359 &dpu_rot_sc7280_cfg_v2); 360 361 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 = 362 _VIG_SBLK(SSPP_SCALER_VER(3, 1)); 363 364 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 = 365 _VIG_SBLK(SSPP_SCALER_VER(3, 2)); 366 367 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 = 368 _VIG_SBLK(SSPP_SCALER_VER(3, 3)); 369 370 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK(); 371 372 /************************************************************* 373 * MIXER sub blocks config 374 *************************************************************/ 375 376 /* MSM8998 */ 377 378 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 379 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 380 .maxblendstages = 7, /* excluding base layer */ 381 .blendstage_base = { /* offsets relative to mixer base */ 382 0x20, 0x50, 0x80, 0xb0, 0x230, 383 0x260, 0x290 384 }, 385 }; 386 387 /* SDM845 */ 388 389 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 390 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 391 .maxblendstages = 11, /* excluding base layer */ 392 .blendstage_base = { /* offsets relative to mixer base */ 393 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 394 0xb0, 0xc8, 0xe0, 0xf8, 0x110 395 }, 396 }; 397 398 /* SC7180 */ 399 400 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 401 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 402 .maxblendstages = 7, /* excluding base layer */ 403 .blendstage_base = { /* offsets relative to mixer base */ 404 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 405 }, 406 }; 407 408 /* QCM2290 */ 409 410 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 411 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 412 .maxblendstages = 4, /* excluding base layer */ 413 .blendstage_base = { /* offsets relative to mixer base */ 414 0x20, 0x38, 0x50, 0x68 415 }, 416 }; 417 418 /************************************************************* 419 * DSPP sub blocks config 420 *************************************************************/ 421 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 422 .pcc = {.name = "pcc", .base = 0x1700, 423 .len = 0x90, .version = 0x10007}, 424 }; 425 426 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 427 .pcc = {.name = "pcc", .base = 0x1700, 428 .len = 0x90, .version = 0x40000}, 429 }; 430 431 /************************************************************* 432 * PINGPONG sub blocks config 433 *************************************************************/ 434 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 435 .te2 = {.name = "te2", .base = 0x2000, .len = 0x0, 436 .version = 0x1}, 437 .dither = {.name = "dither", .base = 0x30e0, 438 .len = 0x20, .version = 0x10000}, 439 }; 440 441 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 442 .dither = {.name = "dither", .base = 0x30e0, 443 .len = 0x20, .version = 0x10000}, 444 }; 445 446 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 447 .dither = {.name = "dither", .base = 0xe0, 448 .len = 0x20, .version = 0x20000}, 449 }; 450 451 /************************************************************* 452 * DSC sub blocks config 453 *************************************************************/ 454 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 455 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 456 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 457 }; 458 459 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 460 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 461 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 462 }; 463 464 /************************************************************* 465 * CDM block config 466 *************************************************************/ 467 static const struct dpu_cdm_cfg sc7280_cdm = { 468 .name = "cdm_0", 469 .id = CDM_0, 470 .len = 0x228, 471 .base = 0x79200, 472 }; 473 474 /************************************************************* 475 * VBIF sub blocks config 476 *************************************************************/ 477 /* VBIF QOS remap */ 478 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 479 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 480 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 481 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 482 static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6}; 483 484 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 485 { 486 .pps = 1920 * 1080 * 30, 487 .ot_limit = 2, 488 }, 489 { 490 .pps = 1920 * 1080 * 60, 491 .ot_limit = 4, 492 }, 493 { 494 .pps = 3840 * 2160 * 30, 495 .ot_limit = 16, 496 }, 497 }; 498 499 static const struct dpu_vbif_cfg msm8998_vbif[] = { 500 { 501 .name = "vbif_rt", .id = VBIF_RT, 502 .base = 0, .len = 0x1040, 503 .default_ot_rd_limit = 32, 504 .default_ot_wr_limit = 32, 505 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 506 .xin_halt_timeout = 0x4000, 507 .qos_rp_remap_size = 0x20, 508 .dynamic_ot_rd_tbl = { 509 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 510 .cfg = msm8998_ot_rdwr_cfg, 511 }, 512 .dynamic_ot_wr_tbl = { 513 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 514 .cfg = msm8998_ot_rdwr_cfg, 515 }, 516 .qos_rt_tbl = { 517 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 518 .priority_lvl = msm8998_rt_pri_lvl, 519 }, 520 .qos_nrt_tbl = { 521 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 522 .priority_lvl = msm8998_nrt_pri_lvl, 523 }, 524 .memtype_count = 14, 525 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 526 }, 527 }; 528 529 static const struct dpu_vbif_cfg sdm845_vbif[] = { 530 { 531 .name = "vbif_rt", .id = VBIF_RT, 532 .base = 0, .len = 0x1040, 533 .features = BIT(DPU_VBIF_QOS_REMAP), 534 .xin_halt_timeout = 0x4000, 535 .qos_rp_remap_size = 0x40, 536 .qos_rt_tbl = { 537 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 538 .priority_lvl = sdm845_rt_pri_lvl, 539 }, 540 .qos_nrt_tbl = { 541 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 542 .priority_lvl = sdm845_nrt_pri_lvl, 543 }, 544 .memtype_count = 14, 545 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 546 }, 547 }; 548 549 static const struct dpu_vbif_cfg sm8550_vbif[] = { 550 { 551 .name = "vbif_rt", .id = VBIF_RT, 552 .base = 0, .len = 0x1040, 553 .features = BIT(DPU_VBIF_QOS_REMAP), 554 .xin_halt_timeout = 0x4000, 555 .qos_rp_remap_size = 0x40, 556 .qos_rt_tbl = { 557 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 558 .priority_lvl = sdm845_rt_pri_lvl, 559 }, 560 .qos_nrt_tbl = { 561 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 562 .priority_lvl = sdm845_nrt_pri_lvl, 563 }, 564 .memtype_count = 16, 565 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 566 }, 567 }; 568 569 static const struct dpu_vbif_cfg sm8650_vbif[] = { 570 { 571 .name = "vbif_rt", .id = VBIF_RT, 572 .base = 0, .len = 0x1074, 573 .features = BIT(DPU_VBIF_QOS_REMAP), 574 .xin_halt_timeout = 0x4000, 575 .qos_rp_remap_size = 0x40, 576 .qos_rt_tbl = { 577 .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl), 578 .priority_lvl = sm8650_rt_pri_lvl, 579 }, 580 .qos_nrt_tbl = { 581 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 582 .priority_lvl = sdm845_nrt_pri_lvl, 583 }, 584 .memtype_count = 16, 585 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 586 }, 587 }; 588 589 /************************************************************* 590 * PERF data config 591 *************************************************************/ 592 593 /* SSPP QOS LUTs */ 594 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 595 {.fl = 4, .lut = 0x1b}, 596 {.fl = 5, .lut = 0x5b}, 597 {.fl = 6, .lut = 0x15b}, 598 {.fl = 7, .lut = 0x55b}, 599 {.fl = 8, .lut = 0x155b}, 600 {.fl = 9, .lut = 0x555b}, 601 {.fl = 10, .lut = 0x1555b}, 602 {.fl = 11, .lut = 0x5555b}, 603 {.fl = 12, .lut = 0x15555b}, 604 {.fl = 0, .lut = 0x55555b} 605 }; 606 607 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 608 {.fl = 4, .lut = 0x357}, 609 {.fl = 5, .lut = 0x3357}, 610 {.fl = 6, .lut = 0x23357}, 611 {.fl = 7, .lut = 0x223357}, 612 {.fl = 8, .lut = 0x2223357}, 613 {.fl = 9, .lut = 0x22223357}, 614 {.fl = 10, .lut = 0x222223357}, 615 {.fl = 11, .lut = 0x2222223357}, 616 {.fl = 12, .lut = 0x22222223357}, 617 {.fl = 13, .lut = 0x222222223357}, 618 {.fl = 14, .lut = 0x1222222223357}, 619 {.fl = 0, .lut = 0x11222222223357} 620 }; 621 622 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 623 {.fl = 10, .lut = 0x1aaff}, 624 {.fl = 11, .lut = 0x5aaff}, 625 {.fl = 12, .lut = 0x15aaff}, 626 {.fl = 0, .lut = 0x55aaff}, 627 }; 628 629 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 630 {.fl = 0, .lut = 0x0011222222335777}, 631 }; 632 633 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 634 {.fl = 0, .lut = 0x0011223445566777 }, 635 }; 636 637 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 638 {.fl = 0, .lut = 0x0011222222223357 }, 639 }; 640 641 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 642 {.fl = 4, .lut = 0x0000000000000357 }, 643 }; 644 645 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 646 {.fl = 0, .lut = 0x0011222222335777}, 647 }; 648 649 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 650 {.fl = 10, .lut = 0x344556677}, 651 {.fl = 11, .lut = 0x3344556677}, 652 {.fl = 12, .lut = 0x23344556677}, 653 {.fl = 13, .lut = 0x223344556677}, 654 {.fl = 14, .lut = 0x1223344556677}, 655 {.fl = 0, .lut = 0x112233344556677}, 656 }; 657 658 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 659 {.fl = 0, .lut = 0x0011223344556677}, 660 }; 661 662 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 663 {.fl = 10, .lut = 0x0000000344556677}, 664 }; 665 666 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 667 {.fl = 0, .lut = 0x0}, 668 }; 669 670 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 671 {.fl = 0, .lut = 0x0}, 672 }; 673 674 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 675 {.fl = 0, .lut = 0x0}, 676 }; 677 678 /************************************************************* 679 * Hardware catalog 680 *************************************************************/ 681 682 #include "catalog/dpu_3_0_msm8998.h" 683 #include "catalog/dpu_3_2_sdm660.h" 684 #include "catalog/dpu_3_3_sdm630.h" 685 686 #include "catalog/dpu_4_0_sdm845.h" 687 #include "catalog/dpu_4_1_sdm670.h" 688 689 #include "catalog/dpu_5_0_sm8150.h" 690 #include "catalog/dpu_5_1_sc8180x.h" 691 #include "catalog/dpu_5_4_sm6125.h" 692 693 #include "catalog/dpu_6_0_sm8250.h" 694 #include "catalog/dpu_6_2_sc7180.h" 695 #include "catalog/dpu_6_3_sm6115.h" 696 #include "catalog/dpu_6_4_sm6350.h" 697 #include "catalog/dpu_6_5_qcm2290.h" 698 #include "catalog/dpu_6_9_sm6375.h" 699 700 #include "catalog/dpu_7_0_sm8350.h" 701 #include "catalog/dpu_7_2_sc7280.h" 702 703 #include "catalog/dpu_8_0_sc8280xp.h" 704 #include "catalog/dpu_8_1_sm8450.h" 705 706 #include "catalog/dpu_9_0_sm8550.h" 707 708 #include "catalog/dpu_9_2_x1e80100.h" 709 710 #include "catalog/dpu_10_0_sm8650.h" 711