1 /* $OpenBSD: if_wereg.h,v 1.4 2022/01/09 05:42:44 jsg Exp $ */ 2 /* $NetBSD: if_wereg.h,v 1.1 1997/11/03 21:22:50 thorpej Exp $ */ 3 4 /* 5 * National Semiconductor DS8390 NIC register definitions. 6 * 7 * Copyright (C) 1993, David Greenman. This software may be used, modified, 8 * copied, distributed, and sold, in both source and binary form provided that 9 * the above copyright and these terms are retained. Under no circumstances is 10 * the author responsible for the proper functioning of this software, nor does 11 * the author assume any responsibility for damages incurred with its use. 12 */ 13 14 /* 15 * Compile-time config flags 16 */ 17 /* 18 * This sets the default for enabling/disabling the transceiver. 19 */ 20 #define WE_FLAGS_DISABLE_TRANSCEIVER 0x0001 21 22 /* 23 * This forces the board to be used in 8/16-bit mode even if it autoconfigs 24 * differently. 25 */ 26 #define WE_FLAGS_FORCE_8BIT_MODE 0x0002 27 #define WE_FLAGS_FORCE_16BIT_MODE 0x0004 28 29 /* 30 * This disables the use of double transmit buffers. 31 */ 32 #define WE_FLAGS_NO_MULTI_BUFFERING 0x0008 33 34 /* 35 * Definitions for Western digital/SMC WD80x3 series ASIC 36 */ 37 38 /* 39 * Memory Select Register (MSR) 40 */ 41 #define WE_MSR 0 42 43 /* next three definitions for Toshiba */ 44 #define WE_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 45 #define WE_MSR_BSY 0x04 /* gate array busy (R) */ 46 #define WE_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */ 47 48 #define WE_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 49 #define WE_MSR_MENB 0x40 /* Memory enable */ 50 #define WE_MSR_RST 0x80 /* Reset board */ 51 52 /* 53 * Interface Configuration Register (ICR) 54 */ 55 #define WE_ICR 1 56 57 #define WE_ICR_16BIT 0x01 /* 16-bit interface */ 58 #define WE_ICR_OAR 0x02 /* select register (0=BIO 1=EAR) */ 59 #define WE_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 60 #define WE_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 61 #define WE_ICR_RLA 0x10 /* recall LAN address */ 62 #define WE_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 63 #define WE_ICR_RIO 0x40 /* recall i/o address */ 64 #define WE_ICR_STO 0x80 /* store to non-volatile memory */ 65 #ifdef TOSH_ETHER 66 #define WE_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 67 #define WE_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 68 0x02 = 16K, 0x01 = 8K */ 69 /* 64K can only be used if mem address 70 above 1MB */ 71 /* IAR holds address A23-A16 (R/W) */ 72 #endif 73 74 /* 75 * IO Address Register (IAR) 76 */ 77 #define WE_IAR 2 78 79 /* 80 * EEROM Address Register 81 */ 82 #define WE_EAR 3 83 84 /* 85 * Interrupt Request Register (IRR) 86 */ 87 #define WE_IRR 4 88 89 #define WE_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 90 #define WE_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 91 #define WE_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 92 #define WE_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 93 #define WE_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 94 95 /* 96 * The three bits of the encoded IRQ are decoded as follows: 97 * 98 * IR2 IR1 IR0 IRQ 99 * 0 0 0 2/9 100 * 0 0 1 3 101 * 0 1 0 5 102 * 0 1 1 7 103 * 1 0 0 10 104 * 1 0 1 11 105 * 1 1 0 15 106 * 1 1 1 4 107 */ 108 #define WE_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 109 #define WE_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 110 #define WE_IRR_IEN 0x80 /* Interrupt enable */ 111 112 /* 113 * LA Address Register (LAAR) 114 */ 115 #define WE_LAAR 5 116 117 #define WE_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 118 #define WE_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 119 #define WE_LAAR_L16EN 0x40 /* enable 16-bit operation */ 120 #define WE_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 121 122 /* i/o base offset to station address/card-ID PROM */ 123 #define WE_PROM 8 124 125 /* 126 * 83C790 specific registers 127 */ 128 /* 129 * Hardware Support Register (HWR) ('790) 130 */ 131 #define WE790_HWR 4 132 133 #define WE790_HWR_RST 0x10 /* hardware reset */ 134 #define WE790_HWR_LPRM 0x40 /* LAN PROM select */ 135 #define WE790_HWR_SWH 0x80 /* switch register set */ 136 137 /* 138 * ICR790 Interrupt Control Register for the 83C790 139 */ 140 #define WE790_ICR 6 141 142 #define WE790_ICR_EIL 0x01 /* enable interrupts */ 143 144 /* 145 * REV/IOPA Revision / I/O Pipe register for the 83C79X 146 */ 147 #define WE790_REV 7 148 149 #define WE790_REV_790 0x20 150 #define WE790_REV_795 0x40 151 152 /* 153 * 79X RAM Address Register (RAR) 154 * Enabled with SWH bit=1 in HWR register 155 */ 156 157 #define WE790_RAR 0x0b 158 159 #define WE790_RAR_SZ8 0x00 /* 8k memory buffer */ 160 #define WE790_RAR_SZ16 0x10 /* 16k memory buffer */ 161 #define WE790_RAR_SZ32 0x20 /* 32k memory buffer */ 162 #define WE790_RAR_SZ64 0x30 /* 64k memory buffer */ 163 164 /* 165 * General Control Register (GCR) 166 * Enabled with SWH bit == 1 in HWR register 167 */ 168 #define WE790_GCR 0x0d 169 170 #define WE790_GCR_LIT 0x01 /* on for UTP */ 171 #define WE790_GCR_GPOUT 0x02 /* if BNC is enabled */ 172 #define WE790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 173 #define WE790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 174 #define WE790_GCR_ZWSEN 0x20 /* zero wait state enable */ 175 #define WE790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 176 /* 177 * The three bits of the encoded IRQ are decoded as follows: 178 * 179 * IR2 IR1 IR0 IRQ 180 * 0 0 0 none 181 * 0 0 1 9 182 * 0 1 0 3 183 * 0 1 1 5 184 * 1 0 0 7 185 * 1 0 1 10 186 * 1 1 0 11 187 * 1 1 1 15 188 */ 189 190 /* i/o base offset to CARD ID */ 191 #define WE_CARD_ID WE_PROM+6 192 193 /* Board type codes in card ID */ 194 #define WE_TYPE_WD8003S 0x02 195 #define WE_TYPE_WD8003E 0x03 196 #define WE_TYPE_WD8013EBT 0x05 197 #define WE_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 198 #define WE_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 199 #define WE_TYPE_TOSHIBA3 0x13 /* named PCETB */ 200 #define WE_TYPE_TOSHIBA4 0x14 /* named PCETC */ 201 #define WE_TYPE_WD8003W 0x24 202 #define WE_TYPE_WD8003EB 0x25 203 #define WE_TYPE_WD8013W 0x26 204 #define WE_TYPE_WD8013EP 0x27 205 #define WE_TYPE_WD8013WC 0x28 206 #define WE_TYPE_WD8013EPC 0x29 207 #define WE_TYPE_SMC8216T 0x2a 208 #define WE_TYPE_SMC8216C 0x2b 209 #define WE_TYPE_WD8013EBP 0x2c 210 211 /* Bit definitions in card ID */ 212 #define WE_REV_MASK 0x1f /* Revision mask */ 213 #define WE_SOFTCONFIG 0x20 /* Soft config */ 214 #define WE_LARGERAM 0x40 /* Large RAM */ 215 #define WE_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 216 217 /* 218 * Checksum total. All 8 bytes in station address PROM will add up to this. 219 */ 220 #ifdef TOSH_ETHER 221 #define WE_ROM_CHECKSUM_TOTAL 0xA5 222 #else 223 #define WE_ROM_CHECKSUM_TOTAL 0xFF 224 #endif 225 226 #define WE_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 227 #define WE_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 228 #define WE_NIC_NPORTS 16 229 #define WE_ASIC_NPORTS 16 230 #define WE_NPORTS (WE_NIC_NPORTS + WE_ASIC_NPORTS) 231 232 #define WE_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 233