1 // Copyright 2008 Dolphin Emulator Project
2 // Licensed under GPLv2+
3 // Refer to the license.txt file included.
4 
5 #pragma once
6 
7 #include "Common/CommonTypes.h"
8 
9 class PointerWrap;
10 namespace MMIO
11 {
12 class Mapping;
13 }
14 
15 namespace CommandProcessor
16 {
17 struct SCPFifoStruct
18 {
19   // fifo registers
20   volatile u32 CPBase;
21   volatile u32 CPEnd;
22   u32 CPHiWatermark;
23   u32 CPLoWatermark;
24   volatile u32 CPReadWriteDistance;
25   volatile u32 CPWritePointer;
26   volatile u32 CPReadPointer;
27   volatile u32 CPBreakpoint;
28   volatile u32 SafeCPReadPointer;
29 
30   volatile u32 bFF_GPLinkEnable;
31   volatile u32 bFF_GPReadEnable;
32   volatile u32 bFF_BPEnable;
33   volatile u32 bFF_BPInt;
34   volatile u32 bFF_Breakpoint;
35 
36   volatile u32 bFF_LoWatermarkInt;
37   volatile u32 bFF_HiWatermarkInt;
38 
39   volatile u32 bFF_LoWatermark;
40   volatile u32 bFF_HiWatermark;
41 
42   void DoState(PointerWrap& p);
43 };
44 
45 // This one is shared between gfx thread and emulator thread.
46 // It is only used by the Fifo and by the CommandProcessor.
47 extern SCPFifoStruct fifo;
48 
49 // internal hardware addresses
50 enum
51 {
52   STATUS_REGISTER = 0x00,
53   CTRL_REGISTER = 0x02,
54   CLEAR_REGISTER = 0x04,
55   PERF_SELECT = 0x06,
56   FIFO_TOKEN_REGISTER = 0x0E,
57   FIFO_BOUNDING_BOX_LEFT = 0x10,
58   FIFO_BOUNDING_BOX_RIGHT = 0x12,
59   FIFO_BOUNDING_BOX_TOP = 0x14,
60   FIFO_BOUNDING_BOX_BOTTOM = 0x16,
61   FIFO_BASE_LO = 0x20,
62   FIFO_BASE_HI = 0x22,
63   FIFO_END_LO = 0x24,
64   FIFO_END_HI = 0x26,
65   FIFO_HI_WATERMARK_LO = 0x28,
66   FIFO_HI_WATERMARK_HI = 0x2a,
67   FIFO_LO_WATERMARK_LO = 0x2c,
68   FIFO_LO_WATERMARK_HI = 0x2e,
69   FIFO_RW_DISTANCE_LO = 0x30,
70   FIFO_RW_DISTANCE_HI = 0x32,
71   FIFO_WRITE_POINTER_LO = 0x34,
72   FIFO_WRITE_POINTER_HI = 0x36,
73   FIFO_READ_POINTER_LO = 0x38,
74   FIFO_READ_POINTER_HI = 0x3A,
75   FIFO_BP_LO = 0x3C,
76   FIFO_BP_HI = 0x3E,
77   XF_RASBUSY_L = 0x40,
78   XF_RASBUSY_H = 0x42,
79   XF_CLKS_L = 0x44,
80   XF_CLKS_H = 0x46,
81   XF_WAIT_IN_L = 0x48,
82   XF_WAIT_IN_H = 0x4a,
83   XF_WAIT_OUT_L = 0x4c,
84   XF_WAIT_OUT_H = 0x4e,
85   VCACHE_METRIC_CHECK_L = 0x50,
86   VCACHE_METRIC_CHECK_H = 0x52,
87   VCACHE_METRIC_MISS_L = 0x54,
88   VCACHE_METRIC_MISS_H = 0x56,
89   VCACHE_METRIC_STALL_L = 0x58,
90   VCACHE_METRIC_STALL_H = 0x5A,
91   CLKS_PER_VTX_IN_L = 0x60,
92   CLKS_PER_VTX_IN_H = 0x62,
93   CLKS_PER_VTX_OUT = 0x64,
94 };
95 
96 enum
97 {
98   GATHER_PIPE_SIZE = 32,
99   INT_CAUSE_CP = 0x800
100 };
101 
102 // Fifo Status Register
103 union UCPStatusReg
104 {
105   struct
106   {
107     u16 OverflowHiWatermark : 1;
108     u16 UnderflowLoWatermark : 1;
109     u16 ReadIdle : 1;
110     u16 CommandIdle : 1;
111     u16 Breakpoint : 1;
112     u16 : 11;
113   };
114   u16 Hex;
UCPStatusReg()115   UCPStatusReg() { Hex = 0; }
UCPStatusReg(u16 _hex)116   UCPStatusReg(u16 _hex) { Hex = _hex; }
117 };
118 
119 // Fifo Control Register
120 union UCPCtrlReg
121 {
122   struct
123   {
124     u16 GPReadEnable : 1;
125     u16 BPEnable : 1;
126     u16 FifoOverflowIntEnable : 1;
127     u16 FifoUnderflowIntEnable : 1;
128     u16 GPLinkEnable : 1;
129     u16 BPInt : 1;
130     u16 : 10;
131   };
132   u16 Hex;
UCPCtrlReg()133   UCPCtrlReg() { Hex = 0; }
UCPCtrlReg(u16 _hex)134   UCPCtrlReg(u16 _hex) { Hex = _hex; }
135 };
136 
137 // Fifo Clear Register
138 union UCPClearReg
139 {
140   struct
141   {
142     u16 ClearFifoOverflow : 1;
143     u16 ClearFifoUnderflow : 1;
144     u16 ClearMetrices : 1;
145     u16 : 13;
146   };
147   u16 Hex;
UCPClearReg()148   UCPClearReg() { Hex = 0; }
UCPClearReg(u16 _hex)149   UCPClearReg(u16 _hex) { Hex = _hex; }
150 };
151 
152 // Init
153 void Init();
154 void DoState(PointerWrap& p);
155 
156 void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
157 
158 void SetCPStatusFromGPU();
159 void SetCPStatusFromCPU();
160 void GatherPipeBursted();
161 void UpdateInterrupts(u64 userdata);
162 void UpdateInterruptsFromVideoBackend(u64 userdata);
163 
164 bool IsInterruptWaiting();
165 
166 void SetCpClearRegister();
167 void SetCpControlRegister();
168 void SetCpStatusRegister();
169 
170 void HandleUnknownOpcode(u8 cmd_byte, void* buffer, bool preprocess);
171 
172 u32 GetPhysicalAddressMask();
173 
174 }  // namespace CommandProcessor
175