1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * The Mach Operating System project at Carnegie-Mellon University, 7 * Ralph Campbell and Rick Macklem. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)maxine.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* 15 * Mach Operating System 16 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 17 * All Rights Reserved. 18 * 19 * Permission to use, copy, modify and distribute this software and 20 * its documentation is hereby granted, provided that both the copyright 21 * notice and this permission notice appear in all copies of the 22 * software, derivative works or modified versions, and any portions 23 * thereof, and that both notices appear in supporting documentation. 24 * 25 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 26 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 27 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 28 * 29 * Carnegie Mellon requests users of this software to return to 30 * 31 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 32 * School of Computer Science 33 * Carnegie Mellon University 34 * Pittsburgh PA 15213-3890 35 * 36 * any improvements or extensions that they make and grant Carnegie the 37 * rights to redistribute these changes. 38 */ 39 /* 40 * HISTORY 41 * $Log: maxine.h,v $ 42 * Revision 2.3 92/04/01 15:14:52 rpd 43 * Defined pseudo slot for mappable timer. 44 * [92/03/11 02:37:41 af] 45 * 46 * Revision 2.2 92/03/02 18:34:28 rpd 47 * Created, from the DEC specs: 48 * "MAXine System Module Functional Specification" Revision 1.2 49 * Workstation Systems Engineering, Palo Alto, CA. July 15, 1991. 50 * [92/01/17 af] 51 * 52 */ 53 /* 54 * File: maxine.h 55 * Author: Alessandro Forin, Carnegie Mellon University 56 * Date: 1/92 57 * 58 * Definitions specific to the MAXine system module (54-21325-01) 59 * and compatible processors (KN02BA). 60 */ 61 62 #ifndef MIPS_XINE_H 63 #define MIPS_XINE_H 1 64 65 /* 66 * MAXine's Physical address space 67 */ 68 69 #define XINE_PHYS_MIN 0x00000000 /* 512 Meg */ 70 #define XINE_PHYS_MAX 0x1fffffff 71 72 /* 73 * Memory map 74 */ 75 76 #define XINE_PHYS_MEMORY_START 0x00000000 77 #define XINE_PHYS_MEMORY_END 0x027fffff /* 40 Meg in 2 slots 78 and baseboard */ 79 80 /* 81 * I/O map 82 */ 83 84 #define XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */ 85 #define XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */ 86 87 #define XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ 88 #define XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ 89 #define XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ 90 #define XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ 91 92 #define XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ 93 #define XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ 94 95 #define XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ 96 #define XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ 97 98 #define XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */ 99 /* 64 Meg */ 100 101 #define XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ 102 #define XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ 103 104 #define XINE_PHYS_TC_START XINE_PHYS_TC_0_START 105 #define XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */ 106 107 #define XINE_TC_NSLOTS 4 108 #define XINE_TC_MIN 0 109 #define XINE_TC_MAX 1 /* only option slots */ 110 111 /* Pseudo-TCslots */ 112 #define XINE_FLOPPY_SLOT 2 113 #define XINE_SCSI_SLOT 3 114 #define XINE_LANCE_SLOT 4 115 #define XINE_SCC0_SLOT 5 116 #define XINE_DTOP_SLOT 6 117 #define XINE_ISDN_SLOT 7 118 #define XINE_CFB_SLOT 8 119 #define XINE_ASIC_SLOT 9 120 #define XINE_FRC_SLOT 10 121 122 /* 123 * System module space 124 */ 125 126 #define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) 127 128 #define XINE_SYS_ROM_START (XINE_SYS_ASIC + ASIC_SLOT_0_START) 129 130 #define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + ASIC_SLOT_1_START) 131 132 #define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + ASIC_SLOT_2_START) 133 134 #define XINE_SYS_LANCE (XINE_SYS_ASIC + ASIC_SLOT_3_START) 135 136 #define XINE_SYS_SCC_0 (XINE_SYS_ASIC + ASIC_SLOT_4_START) 137 138 #define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + ASIC_SLOT_5_START) 139 140 #define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + ASIC_SLOT_7_START) 141 142 #define XINE_SYS_CLOCK (XINE_SYS_ASIC + ASIC_SLOT_8_START) 143 144 #define XINE_SYS_ISDN (XINE_SYS_ASIC + ASIC_SLOT_9_START) 145 146 #define XINE_SYS_DTOP (XINE_SYS_ASIC + ASIC_SLOT_10_START) 147 148 #define XINE_SYS_FLOPPY (XINE_SYS_ASIC + ASIC_SLOT_11_START) 149 150 #define XINE_SYS_SCSI (XINE_SYS_ASIC + ASIC_SLOT_12_START) 151 152 #define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + ASIC_SLOT_13_START) 153 154 #define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + ASIC_SLOT_14_START) 155 156 #define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) 157 #define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) 158 159 /* 160 * Interrupts 161 */ 162 163 #define XINE_INT_FPA IP_LEV7 /* Floating Point coproc */ 164 #define XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */ 165 #define XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */ 166 #define XINE_INT_TIMEOUT IP_LEV4 /* Timeout on I/O write */ 167 #define XINE_INT_TOY IP_LEV3 /* Clock chip */ 168 #define XINE_INT_1_10_MS IP_LEV2 /* Periodic interrupt */ 169 170 /* 171 * System registers addresses (MREG and CREG space, and IO Control ASIC) 172 */ 173 174 #define XINE_REG_CMR 0x0c000000 /* Color mask register */ 175 #define XINE_REG_MER 0x0c400000 /* Memory error register */ 176 #define XINE_REG_MSR 0x0c800000 /* Memory size register */ 177 #define XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */ 178 #define XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */ 179 180 #define XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */ 181 #define XINE_REG_AER 0x0e000004 /* Address error register */ 182 #define XINE_REG_TIMEOUT 0x0e00000c /* I/O write timeout reg */ 183 184 185 #define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + ASIC_SCSI_DMAPTR ) 186 #define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + ASIC_SCSI_NEXTPTR ) 187 #define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + ASIC_LANCE_DMAPTR ) 188 #define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + ASIC_SCC_T1_DMAPTR ) 189 #define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + ASIC_SCC_R1_DMAPTR ) 190 #define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + ASIC_SCC_T2_DMAPTR ) 191 #define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + ASIC_SCC_R2_DMAPTR ) 192 #define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + ASIC_FLOPPY_DMAPTR ) 193 #define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + ASIC_ISDN_X_DMAPTR ) 194 #define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + ASIC_ISDN_X_NEXTPTR ) 195 #define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + ASIC_ISDN_R_DMAPTR ) 196 #define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + ASIC_ISDN_R_NEXTPTR ) 197 #define XINE_REG_CSR ( XINE_SYS_ASIC + ASIC_CSR ) 198 #define XINE_REG_INTR ( XINE_SYS_ASIC + ASIC_INTR ) 199 #define XINE_REG_IMSK ( XINE_SYS_ASIC + ASIC_IMSK ) 200 #define XINE_REG_CURADDR ( XINE_SYS_ASIC + ASIC_CURADDR ) 201 #define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + ASIC_ISDN_X_DATA ) 202 #define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + ASIC_ISDN_R_DATA ) 203 204 #define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + ASIC_LANCE_DECODE ) 205 #define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + ASIC_SCSI_DECODE ) 206 #define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + ASIC_SCC0_DECODE ) 207 #define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + ASIC_SCC1_DECODE ) 208 #define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + ASIC_FLOPPY_DECODE ) 209 # define XINE_LANCE_CONFIG 3 210 # define XINE_SCSI_CONFIG 14 211 # define XINE_SCC0_CONFIG (0x10|4) 212 # define XINE_DTOP_CONFIG 10 213 # define XINE_FLOPPY_CONFIG 13 214 215 #define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + ASIC_SCSI_SCR ) 216 #define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + ASIC_SCSI_SDR0 ) 217 #define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + ASIC_SCSI_SDR1 ) 218 219 /* 220 * System registers defines (MREG and CREG) 221 */ 222 223 /* Memory error register */ 224 225 #define XINE_MER_xxx 0xf7fe30ff /* undefined */ 226 #define XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */ 227 #define XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ 228 #define XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */ 229 #define XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ 230 #define XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ 231 # define XINE_LASTB31 0x00000800 /* upper byte of word */ 232 # define XINE_LASTB23 0x00000400 /* .. through .. */ 233 # define XINE_LASTB15 0x00000200 /* .. the .. */ 234 # define XINE_LASTB07 0x00000100 /* .. lower byte */ 235 236 /* Memory size register */ 237 238 #define XINE_MSR_xxx 0xffffdfff /* undefined */ 239 #define XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */ 240 #define XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */ 241 #define XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */ 242 #define XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */ 243 #define XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */ 244 # define XINE_BANK_0 0x00020000 /* .. at bank 0, .. */ 245 # define XINE_BANK_1 0x00040000 /* .. at bank 1, .. */ 246 # define XINE_BANK_2 0x00080000 /* .. or at bank 2 */ 247 #define XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ 248 249 /* FI register */ 250 251 #define XINE_FI_VALUE 0x00001000 252 253 /* NOTES 254 255 Memory access priority is, from higher to lower: 256 - VRAM/DRAM refresh 257 - IO DMA (IO Control ASIC) 258 - Slot 0 DMA 259 - Processor 260 - Slot 1 DMA 261 262 Memory performance is (with 80ns mem cycles) 263 - single word read 5 cyc 10.0 Mb/s 264 - word write 3 cyc 16.7 Mb/s 265 - single byte write 3 cyc 4.2 Mb/s 266 - 64w DMA read 68 cyc 47.1 Mb/s 267 - 64w DMA write 66 cyc 48.5 Mb/s 268 - Refresh 5 cyc N/A 269 */ 270 271 /* Timeout config register */ 272 273 #define XINE_CNFG_VALUE 121 274 275 /* Address error register */ 276 277 #define XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ 278 279 /* Memory access timeout interrupt register */ 280 281 #define XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */ 282 283 /* 284 * More system registers defines (IO Control ASIC) 285 */ 286 287 /* (re)defines for the system Status and Control register (SSR) */ 288 289 #define XINE_CSR_DMAEN_T1 ASIC_CSR_DMAEN_T1 290 #define XINE_CSR_DMAEN_R1 ASIC_CSR_DMAEN_R1 291 #define XINE_CSR_DMAEN_DTOP_T ASIC_CSR_DMAEN_T2 292 #define XINE_CSR_DMAEN_DTOP_R ASIC_CSR_DMAEN_R2 293 #define XINE_CSR_FLOPPY_DIR ASIC_CSR_FLOPPY_DIR 294 #define XINE_CSR_DMAEN_FLOPPY ASIC_CSR_DMAEN_FLOPPY 295 #define XINE_CSR_DMAEN_ISDN_T ASIC_CSR_DMAEN_ISDN_T 296 #define XINE_CSR_DMAEN_ISDN_R ASIC_CSR_DMAEN_ISDN_R 297 #define XINE_CSR_SCSI_DIR ASIC_CSR_SCSI_DIR 298 #define XINE_CSR_DMAEN_SCSI ASIC_CSR_DMAEN_SCSI 299 #define XINE_CSR_DMAEN_LANCE ASIC_CSR_DMAEN_LANCE 300 #define XINE_CSR_DIAGDN 0x00008000 /* rw */ 301 #define XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */ 302 #define XINE_CSR_SCC_ENABLE 0x00000800 /* rw */ 303 #define XINE_CSR_RTC_ENABLE 0x00000400 /* rw */ 304 #define XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */ 305 #define XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */ 306 #define XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */ 307 #define XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */ 308 #define XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */ 309 #define XINE_CSR_LED 0x00000001 /* rw */ 310 311 /* (re)defines for the System Interrupt and Mask Registers */ 312 313 #define XINE_INTR_T1_PAGE_END ASIC_INTR_T1_PAGE_END 314 #define XINE_INTR_T1_READ_E ASIC_INTR_T1_READ_E 315 #define XINE_INTR_R1_HALF_PAGE ASIC_INTR_R1_HALF_PAGE 316 #define XINE_INTR_R1_DMA_OVRUN ASIC_INTR_R1_DMA_OVRUN 317 #define XINE_INTR_DT_PAGE_END ASIC_INTR_T2_PAGE_END 318 #define XINE_INTR_DT_READ_E ASIC_INTR_T2_READ_E 319 #define XINE_INTR_DT_HALF_PAGE ASIC_INTR_R2_HALF_PAGE 320 #define XINE_INTR_DT_DMA_OVRUN ASIC_INTR_R2_DMA_OVRUN 321 #define XINE_INTR_FLOPPY_DMA_E ASIC_INTR_FLOPPY_DMA_E 322 #define XINE_INTR_ISDN_PTR_LOAD ASIC_INTR_ISDN_PTR_LOAD 323 #define XINE_INTR_ISDN_OVRUN ASIC_INTR_ISDN_OVRUN 324 #define XINE_INTR_ISDN_READ_E ASIC_INTR_ISDN_READ_E 325 #define XINE_INTR_SCSI_PTR_LOAD ASIC_INTR_SCSI_PTR_LOAD 326 #define XINE_INTR_SCSI_OVRUN ASIC_INTR_SCSI_OVRUN 327 #define XINE_INTR_SCSI_READ_E ASIC_INTR_SCSI_READ_E 328 #define XINE_INTR_LANCE_READ_E ASIC_INTR_LANCE_READ_E 329 #define XINE_INTR_xxxx 0x00002808 /* ro */ 330 #define XINE_INTR_FLOPPY 0x00008000 /* ro */ 331 #define XINE_INTR_NVR_JUMPER 0x00004000 /* ro */ 332 #define XINE_INTR_POWERUP 0x00002000 /* ro */ 333 #define XINE_INTR_TC_0 0x00001000 /* ro */ 334 #define XINE_INTR_ISDN 0x00000800 /* ro */ 335 #define XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 336 #define XINE_INTR_SCSI 0x00000200 /* ro */ 337 #define XINE_INTR_LANCE 0x00000100 /* ro */ 338 #define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */ 339 #define XINE_INTR_SCC_0 0x00000040 /* ro */ 340 #define XINE_INTR_TC_1 0x00000020 /* ro */ 341 #define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */ 342 #define XINE_INTR_VINT 0x00000008 /* ro */ 343 #define XINE_INTR_N_VINT 0x00000004 /* ro */ 344 #define XINE_INTR_DTOP_TX 0x00000002 /* ro */ 345 #define XINE_INTR_DTOP_RX 0x00000001 /* ro */ 346 #define XINE_INTR_ASIC 0xffff0000 347 #define XINE_INTR_DTOP 0x00000003 348 #define XINE_IM0 0xffff9b6b /* all good ones enabled */ 349 350 #endif /* MIPS_XINE_H */ 351