1 /////////////////////////////////////////////////////////////////////////
2 // $Id: logical16.cc 13573 2019-10-14 14:54:07Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (C) 2001-2019 The Bochs Project
6 //
7 // This library is free software; you can redistribute it and/or
8 // modify it under the terms of the GNU Lesser General Public
9 // License as published by the Free Software Foundation; either
10 // version 2 of the License, or (at your option) any later version.
11 //
12 // This library is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 // Lesser General Public License for more details.
16 //
17 // You should have received a copy of the GNU Lesser General Public
18 // License along with this library; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
20 /////////////////////////////////////////////////////////////////////////
21
22 #define NEED_CPU_REG_SHORTCUTS 1
23 #include "bochs.h"
24 #include "cpu.h"
25 #define LOG_THIS BX_CPU_THIS_PTR
26
ZERO_IDIOM_GwR(bxInstruction_c * i)27 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ZERO_IDIOM_GwR(bxInstruction_c *i)
28 {
29 BX_WRITE_16BIT_REG(i->dst(), 0);
30 SET_FLAGS_OSZAPC_LOGIC_16(0);
31 BX_NEXT_INSTR(i);
32 }
33
XOR_EwGwM(bxInstruction_c * i)34 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwGwM(bxInstruction_c *i)
35 {
36 Bit16u op1_16, op2_16;
37
38 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
39
40 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
41 op2_16 = BX_READ_16BIT_REG(i->src());
42 op1_16 ^= op2_16;
43 write_RMW_linear_word(op1_16);
44
45 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
46
47 BX_NEXT_INSTR(i);
48 }
49
XOR_GwEwR(bxInstruction_c * i)50 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwR(bxInstruction_c *i)
51 {
52 Bit16u op1_16, op2_16;
53
54 op1_16 = BX_READ_16BIT_REG(i->dst());
55 op2_16 = BX_READ_16BIT_REG(i->src());
56 op1_16 ^= op2_16;
57 BX_WRITE_16BIT_REG(i->dst(), op1_16);
58
59 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
60
61 BX_NEXT_INSTR(i);
62 }
63
XOR_GwEwM(bxInstruction_c * i)64 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_GwEwM(bxInstruction_c *i)
65 {
66 Bit16u op1_16, op2_16;
67
68 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
69
70 op1_16 = BX_READ_16BIT_REG(i->dst());
71 op2_16 = read_virtual_word(i->seg(), eaddr);
72 op1_16 ^= op2_16;
73 BX_WRITE_16BIT_REG(i->dst(), op1_16);
74
75 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
76
77 BX_NEXT_INSTR(i);
78 }
79
XOR_EwIwM(bxInstruction_c * i)80 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwM(bxInstruction_c *i)
81 {
82 Bit16u op1_16;
83
84 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
85
86 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
87 op1_16 ^= i->Iw();
88 write_RMW_linear_word(op1_16);
89
90 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
91
92 BX_NEXT_INSTR(i);
93 }
94
XOR_EwIwR(bxInstruction_c * i)95 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EwIwR(bxInstruction_c *i)
96 {
97 Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
98 op1_16 ^= i->Iw();
99 BX_WRITE_16BIT_REG(i->dst(), op1_16);
100
101 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
102
103 BX_NEXT_INSTR(i);
104 }
105
OR_EwIwM(bxInstruction_c * i)106 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwM(bxInstruction_c *i)
107 {
108 Bit16u op1_16;
109
110 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
111
112 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
113 op1_16 |= i->Iw();
114 write_RMW_linear_word(op1_16);
115
116 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
117
118 BX_NEXT_INSTR(i);
119 }
120
OR_EwIwR(bxInstruction_c * i)121 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwIwR(bxInstruction_c *i)
122 {
123 Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
124 op1_16 |= i->Iw();
125 BX_WRITE_16BIT_REG(i->dst(), op1_16);
126
127 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
128
129 BX_NEXT_INSTR(i);
130 }
131
NOT_EwM(bxInstruction_c * i)132 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwM(bxInstruction_c *i)
133 {
134 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
135
136 Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
137 op1_16 = ~op1_16;
138 write_RMW_linear_word(op1_16);
139
140 BX_NEXT_INSTR(i);
141 }
142
NOT_EwR(bxInstruction_c * i)143 void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EwR(bxInstruction_c *i)
144 {
145 Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
146 op1_16 = ~op1_16;
147 BX_WRITE_16BIT_REG(i->dst(), op1_16);
148
149 BX_NEXT_INSTR(i);
150 }
151
OR_EwGwM(bxInstruction_c * i)152 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EwGwM(bxInstruction_c *i)
153 {
154 Bit16u op1_16, op2_16;
155
156 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
157
158 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
159 op2_16 = BX_READ_16BIT_REG(i->src());
160 op1_16 |= op2_16;
161 write_RMW_linear_word(op1_16);
162
163 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
164
165 BX_NEXT_INSTR(i);
166 }
167
OR_GwEwR(bxInstruction_c * i)168 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwR(bxInstruction_c *i)
169 {
170 Bit16u op1_16, op2_16;
171
172 op1_16 = BX_READ_16BIT_REG(i->dst());
173 op2_16 = BX_READ_16BIT_REG(i->src());
174 op1_16 |= op2_16;
175 BX_WRITE_16BIT_REG(i->dst(), op1_16);
176
177 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
178
179 BX_NEXT_INSTR(i);
180 }
181
OR_GwEwM(bxInstruction_c * i)182 void BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_GwEwM(bxInstruction_c *i)
183 {
184 Bit16u op1_16, op2_16;
185
186 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
187
188 op1_16 = BX_READ_16BIT_REG(i->dst());
189 op2_16 = read_virtual_word(i->seg(), eaddr);
190 op1_16 |= op2_16;
191 BX_WRITE_16BIT_REG(i->dst(), op1_16);
192
193 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
194
195 BX_NEXT_INSTR(i);
196 }
197
AND_EwGwM(bxInstruction_c * i)198 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwGwM(bxInstruction_c *i)
199 {
200 Bit16u op1_16, op2_16;
201
202 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
203
204 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
205 op2_16 = BX_READ_16BIT_REG(i->src());
206 op1_16 &= op2_16;
207 write_RMW_linear_word(op1_16);
208
209 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
210
211 BX_NEXT_INSTR(i);
212 }
213
AND_GwEwR(bxInstruction_c * i)214 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwR(bxInstruction_c *i)
215 {
216 Bit16u op1_16, op2_16;
217
218 op1_16 = BX_READ_16BIT_REG(i->dst());
219 op2_16 = BX_READ_16BIT_REG(i->src());
220 op1_16 &= op2_16;
221 BX_WRITE_16BIT_REG(i->dst(), op1_16);
222
223 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
224
225 BX_NEXT_INSTR(i);
226 }
227
AND_GwEwM(bxInstruction_c * i)228 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_GwEwM(bxInstruction_c *i)
229 {
230 Bit16u op1_16, op2_16;
231
232 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
233
234 op1_16 = BX_READ_16BIT_REG(i->dst());
235 op2_16 = read_virtual_word(i->seg(), eaddr);
236 op1_16 &= op2_16;
237 BX_WRITE_16BIT_REG(i->dst(), op1_16);
238
239 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
240
241 BX_NEXT_INSTR(i);
242 }
243
AND_EwIwM(bxInstruction_c * i)244 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwM(bxInstruction_c *i)
245 {
246 Bit16u op1_16;
247
248 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
249
250 op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
251 op1_16 &= i->Iw();
252 write_RMW_linear_word(op1_16);
253
254 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
255
256 BX_NEXT_INSTR(i);
257 }
258
AND_EwIwR(bxInstruction_c * i)259 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AND_EwIwR(bxInstruction_c *i)
260 {
261 Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
262 op1_16 &= i->Iw();
263 BX_WRITE_16BIT_REG(i->dst(), op1_16);
264
265 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
266
267 BX_NEXT_INSTR(i);
268 }
269
TEST_EwGwR(bxInstruction_c * i)270 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwR(bxInstruction_c *i)
271 {
272 Bit16u op1_16, op2_16;
273
274 op1_16 = BX_READ_16BIT_REG(i->dst());
275 op2_16 = BX_READ_16BIT_REG(i->src());
276 op1_16 &= op2_16;
277 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
278
279 BX_NEXT_INSTR(i);
280 }
281
TEST_EwGwM(bxInstruction_c * i)282 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwGwM(bxInstruction_c *i)
283 {
284 Bit16u op1_16, op2_16;
285
286 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
287
288 op1_16 = read_virtual_word(i->seg(), eaddr);
289 op2_16 = BX_READ_16BIT_REG(i->src());
290 op1_16 &= op2_16;
291 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
292
293 BX_NEXT_INSTR(i);
294 }
295
TEST_EwIwR(bxInstruction_c * i)296 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwR(bxInstruction_c *i)
297 {
298 Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
299 op1_16 &= i->Iw();
300 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
301
302 BX_NEXT_INSTR(i);
303 }
304
TEST_EwIwM(bxInstruction_c * i)305 void BX_CPP_AttrRegparmN(1) BX_CPU_C::TEST_EwIwM(bxInstruction_c *i)
306 {
307 bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
308
309 Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
310 op1_16 &= i->Iw();
311 SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
312
313 BX_NEXT_INSTR(i);
314 }
315