1 /*
2 * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include "qemu/osdep.h"
29 #include "qemu/log.h"
30 #include "qemu/qemu-print.h"
31 #include "qemu/units.h"
32 #include "cpu.h"
33 #include "exec/helper-proto.h"
34 #include "qemu/host-utils.h"
35 #include "exec/exec-all.h"
36 #include "exec/page-protection.h"
37
38 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f
39 #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
40 #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8
41 #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000
42 #define XTENSA_MPU_MEM_TYPE_SHIFT 12
43 #define XTENSA_MPU_ATTR_MASK 0x001fff00
44
45 #define XTENSA_MPU_PROBE_B 0x40000000
46 #define XTENSA_MPU_PROBE_V 0x80000000
47
48 #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001
49 #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002
50 #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003
51 #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003
52
53 #define XTENSA_MPU_TYPE_SYS_C 0x0010
54 #define XTENSA_MPU_TYPE_SYS_W 0x0020
55 #define XTENSA_MPU_TYPE_SYS_R 0x0040
56 #define XTENSA_MPU_TYPE_CPU_C 0x0100
57 #define XTENSA_MPU_TYPE_CPU_W 0x0200
58 #define XTENSA_MPU_TYPE_CPU_R 0x0400
59 #define XTENSA_MPU_TYPE_CPU_CACHE 0x0800
60 #define XTENSA_MPU_TYPE_B 0x1000
61 #define XTENSA_MPU_TYPE_INT 0x2000
62
HELPER(itlb_hit_test)63 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
64 {
65 /*
66 * Probe the memory; we don't care about the result but
67 * only the side-effects (ie any MMU or other exception)
68 */
69 probe_access(env, vaddr, 1, MMU_INST_FETCH,
70 cpu_mmu_index(env_cpu(env), true), GETPC());
71 }
72
HELPER(wsr_rasid)73 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
74 {
75 v = (v & 0xffffff00) | 0x1;
76 if (v != env->sregs[RASID]) {
77 env->sregs[RASID] = v;
78 tlb_flush(env_cpu(env));
79 }
80 }
81
get_page_size(const CPUXtensaState * env,bool dtlb,uint32_t way)82 static uint32_t get_page_size(const CPUXtensaState *env,
83 bool dtlb, uint32_t way)
84 {
85 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
86
87 switch (way) {
88 case 4:
89 return (tlbcfg >> 16) & 0x3;
90
91 case 5:
92 return (tlbcfg >> 20) & 0x1;
93
94 case 6:
95 return (tlbcfg >> 24) & 0x1;
96
97 default:
98 return 0;
99 }
100 }
101
102 /*!
103 * Get bit mask for the virtual address bits translated by the TLB way
104 */
xtensa_tlb_get_addr_mask(const CPUXtensaState * env,bool dtlb,uint32_t way)105 static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
106 bool dtlb, uint32_t way)
107 {
108 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
109 bool varway56 = dtlb ?
110 env->config->dtlb.varway56 :
111 env->config->itlb.varway56;
112
113 switch (way) {
114 case 4:
115 return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
116
117 case 5:
118 if (varway56) {
119 return 0xf8000000 << get_page_size(env, dtlb, way);
120 } else {
121 return 0xf8000000;
122 }
123
124 case 6:
125 if (varway56) {
126 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
127 } else {
128 return 0xf0000000;
129 }
130
131 default:
132 return 0xfffff000;
133 }
134 } else {
135 return REGION_PAGE_MASK;
136 }
137 }
138
139 /*!
140 * Get bit mask for the 'VPN without index' field.
141 * See ISA, 4.6.5.6, data format for RxTLB0
142 */
get_vpn_mask(const CPUXtensaState * env,bool dtlb,uint32_t way)143 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
144 {
145 if (way < 4) {
146 bool is32 = (dtlb ?
147 env->config->dtlb.nrefillentries :
148 env->config->itlb.nrefillentries) == 32;
149 return is32 ? 0xffff8000 : 0xffffc000;
150 } else if (way == 4) {
151 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
152 } else if (way <= 6) {
153 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
154 bool varway56 = dtlb ?
155 env->config->dtlb.varway56 :
156 env->config->itlb.varway56;
157
158 if (varway56) {
159 return mask << (way == 5 ? 2 : 3);
160 } else {
161 return mask << 1;
162 }
163 } else {
164 return 0xfffff000;
165 }
166 }
167
168 /*!
169 * Split virtual address into VPN (with index) and entry index
170 * for the given TLB way
171 */
split_tlb_entry_spec_way(const CPUXtensaState * env,uint32_t v,bool dtlb,uint32_t * vpn,uint32_t wi,uint32_t * ei)172 static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
173 bool dtlb, uint32_t *vpn,
174 uint32_t wi, uint32_t *ei)
175 {
176 bool varway56 = dtlb ?
177 env->config->dtlb.varway56 :
178 env->config->itlb.varway56;
179
180 if (!dtlb) {
181 wi &= 7;
182 }
183
184 if (wi < 4) {
185 bool is32 = (dtlb ?
186 env->config->dtlb.nrefillentries :
187 env->config->itlb.nrefillentries) == 32;
188 *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
189 } else {
190 switch (wi) {
191 case 4:
192 {
193 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
194 *ei = (v >> eibase) & 0x3;
195 }
196 break;
197
198 case 5:
199 if (varway56) {
200 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
201 *ei = (v >> eibase) & 0x3;
202 } else {
203 *ei = (v >> 27) & 0x1;
204 }
205 break;
206
207 case 6:
208 if (varway56) {
209 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
210 *ei = (v >> eibase) & 0x7;
211 } else {
212 *ei = (v >> 28) & 0x1;
213 }
214 break;
215
216 default:
217 *ei = 0;
218 break;
219 }
220 }
221 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
222 }
223
224 /*!
225 * Split TLB address into TLB way, entry index and VPN (with index).
226 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
227 */
split_tlb_entry_spec(CPUXtensaState * env,uint32_t v,bool dtlb,uint32_t * vpn,uint32_t * wi,uint32_t * ei)228 static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
229 uint32_t *vpn, uint32_t *wi, uint32_t *ei)
230 {
231 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
232 *wi = v & (dtlb ? 0xf : 0x7);
233 if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
234 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
235 return true;
236 } else {
237 return false;
238 }
239 } else {
240 *vpn = v & REGION_PAGE_MASK;
241 *wi = 0;
242 *ei = (v >> 29) & 0x7;
243 return true;
244 }
245 }
246
xtensa_tlb_get_entry(CPUXtensaState * env,bool dtlb,unsigned wi,unsigned ei)247 static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
248 unsigned wi, unsigned ei)
249 {
250 const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb;
251
252 assert(wi < tlb->nways && ei < tlb->way_size[wi]);
253 return dtlb ?
254 env->dtlb[wi] + ei :
255 env->itlb[wi] + ei;
256 }
257
get_tlb_entry(CPUXtensaState * env,uint32_t v,bool dtlb,uint32_t * pwi)258 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
259 uint32_t v, bool dtlb, uint32_t *pwi)
260 {
261 uint32_t vpn;
262 uint32_t wi;
263 uint32_t ei;
264
265 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
266 if (pwi) {
267 *pwi = wi;
268 }
269 return xtensa_tlb_get_entry(env, dtlb, wi, ei);
270 } else {
271 return NULL;
272 }
273 }
274
xtensa_tlb_set_entry_mmu(const CPUXtensaState * env,xtensa_tlb_entry * entry,bool dtlb,unsigned wi,unsigned ei,uint32_t vpn,uint32_t pte)275 static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
276 xtensa_tlb_entry *entry, bool dtlb,
277 unsigned wi, unsigned ei, uint32_t vpn,
278 uint32_t pte)
279 {
280 entry->vaddr = vpn;
281 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
282 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
283 entry->attr = pte & 0xf;
284 }
285
xtensa_tlb_set_entry(CPUXtensaState * env,bool dtlb,unsigned wi,unsigned ei,uint32_t vpn,uint32_t pte)286 static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
287 unsigned wi, unsigned ei,
288 uint32_t vpn, uint32_t pte)
289 {
290 CPUState *cs = env_cpu(env);
291 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
292
293 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
294 if (entry->variable) {
295 if (entry->asid) {
296 tlb_flush_page(cs, entry->vaddr);
297 }
298 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
299 tlb_flush_page(cs, entry->vaddr);
300 } else {
301 qemu_log_mask(LOG_GUEST_ERROR,
302 "%s %d, %d, %d trying to set immutable entry\n",
303 __func__, dtlb, wi, ei);
304 }
305 } else {
306 tlb_flush_page(cs, entry->vaddr);
307 if (xtensa_option_enabled(env->config,
308 XTENSA_OPTION_REGION_TRANSLATION)) {
309 entry->paddr = pte & REGION_PAGE_MASK;
310 }
311 entry->attr = pte & 0xf;
312 }
313 }
314
xtensa_cpu_get_phys_page_debug(CPUState * cs,vaddr addr)315 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
316 {
317 XtensaCPU *cpu = XTENSA_CPU(cs);
318 uint32_t paddr;
319 uint32_t page_size;
320 unsigned access;
321
322 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
323 &paddr, &page_size, &access) == 0) {
324 return paddr;
325 }
326 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
327 &paddr, &page_size, &access) == 0) {
328 return paddr;
329 }
330 return ~0;
331 }
332
reset_tlb_mmu_all_ways(CPUXtensaState * env,const xtensa_tlb * tlb,xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])333 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
334 const xtensa_tlb *tlb,
335 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
336 {
337 unsigned wi, ei;
338
339 for (wi = 0; wi < tlb->nways; ++wi) {
340 for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
341 entry[wi][ei].asid = 0;
342 entry[wi][ei].variable = true;
343 }
344 }
345 }
346
reset_tlb_mmu_ways56(CPUXtensaState * env,const xtensa_tlb * tlb,xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])347 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
348 const xtensa_tlb *tlb,
349 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
350 {
351 if (!tlb->varway56) {
352 static const xtensa_tlb_entry way5[] = {
353 {
354 .vaddr = 0xd0000000,
355 .paddr = 0,
356 .asid = 1,
357 .attr = 7,
358 .variable = false,
359 }, {
360 .vaddr = 0xd8000000,
361 .paddr = 0,
362 .asid = 1,
363 .attr = 3,
364 .variable = false,
365 }
366 };
367 static const xtensa_tlb_entry way6[] = {
368 {
369 .vaddr = 0xe0000000,
370 .paddr = 0xf0000000,
371 .asid = 1,
372 .attr = 7,
373 .variable = false,
374 }, {
375 .vaddr = 0xf0000000,
376 .paddr = 0xf0000000,
377 .asid = 1,
378 .attr = 3,
379 .variable = false,
380 }
381 };
382 memcpy(entry[5], way5, sizeof(way5));
383 memcpy(entry[6], way6, sizeof(way6));
384 } else {
385 uint32_t ei;
386 for (ei = 0; ei < 8; ++ei) {
387 entry[6][ei].vaddr = ei << 29;
388 entry[6][ei].paddr = ei << 29;
389 entry[6][ei].asid = 1;
390 entry[6][ei].attr = 3;
391 }
392 }
393 }
394
reset_tlb_region_way0(CPUXtensaState * env,xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])395 static void reset_tlb_region_way0(CPUXtensaState *env,
396 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
397 {
398 unsigned ei;
399
400 for (ei = 0; ei < 8; ++ei) {
401 entry[0][ei].vaddr = ei << 29;
402 entry[0][ei].paddr = ei << 29;
403 entry[0][ei].asid = 1;
404 entry[0][ei].attr = 2;
405 entry[0][ei].variable = true;
406 }
407 }
408
reset_mmu(CPUXtensaState * env)409 void reset_mmu(CPUXtensaState *env)
410 {
411 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
412 env->sregs[RASID] = 0x04030201;
413 env->sregs[ITLBCFG] = 0;
414 env->sregs[DTLBCFG] = 0;
415 env->autorefill_idx = 0;
416 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
417 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
418 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
419 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
420 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
421 unsigned i;
422
423 env->sregs[MPUENB] = 0;
424 env->sregs[MPUCFG] = env->config->n_mpu_fg_segments;
425 env->sregs[CACHEADRDIS] = 0;
426 assert(env->config->n_mpu_bg_segments > 0 &&
427 env->config->mpu_bg[0].vaddr == 0);
428 for (i = 1; i < env->config->n_mpu_bg_segments; ++i) {
429 assert(env->config->mpu_bg[i].vaddr >=
430 env->config->mpu_bg[i - 1].vaddr);
431 }
432 } else {
433 env->sregs[CACHEATTR] = 0x22222222;
434 reset_tlb_region_way0(env, env->itlb);
435 reset_tlb_region_way0(env, env->dtlb);
436 }
437 }
438
get_ring(const CPUXtensaState * env,uint8_t asid)439 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
440 {
441 unsigned i;
442 for (i = 0; i < 4; ++i) {
443 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
444 return i;
445 }
446 }
447 return 0xff;
448 }
449
450 /*!
451 * Lookup xtensa TLB for the given virtual address.
452 * See ISA, 4.6.2.2
453 *
454 * \param pwi: [out] way index
455 * \param pei: [out] entry index
456 * \param pring: [out] access ring
457 * \return 0 if ok, exception cause code otherwise
458 */
xtensa_tlb_lookup(const CPUXtensaState * env,uint32_t addr,bool dtlb,uint32_t * pwi,uint32_t * pei,uint8_t * pring)459 static int xtensa_tlb_lookup(const CPUXtensaState *env,
460 uint32_t addr, bool dtlb,
461 uint32_t *pwi, uint32_t *pei, uint8_t *pring)
462 {
463 const xtensa_tlb *tlb = dtlb ?
464 &env->config->dtlb : &env->config->itlb;
465 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
466 env->dtlb : env->itlb;
467
468 int nhits = 0;
469 unsigned wi;
470
471 for (wi = 0; wi < tlb->nways; ++wi) {
472 uint32_t vpn;
473 uint32_t ei;
474 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
475 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
476 unsigned ring = get_ring(env, entry[wi][ei].asid);
477 if (ring < 4) {
478 if (++nhits > 1) {
479 return dtlb ?
480 LOAD_STORE_TLB_MULTI_HIT_CAUSE :
481 INST_TLB_MULTI_HIT_CAUSE;
482 }
483 *pwi = wi;
484 *pei = ei;
485 *pring = ring;
486 }
487 }
488 }
489 return nhits ? 0 :
490 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
491 }
492
HELPER(rtlb0)493 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
494 {
495 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
496 uint32_t wi;
497 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
498
499 if (entry) {
500 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
501 } else {
502 return 0;
503 }
504 } else {
505 return v & REGION_PAGE_MASK;
506 }
507 }
508
HELPER(rtlb1)509 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
510 {
511 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
512
513 if (entry) {
514 return entry->paddr | entry->attr;
515 } else {
516 return 0;
517 }
518 }
519
HELPER(itlb)520 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
521 {
522 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
523 uint32_t wi;
524 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
525 if (entry && entry->variable && entry->asid) {
526 tlb_flush_page(env_cpu(env), entry->vaddr);
527 entry->asid = 0;
528 }
529 }
530 }
531
HELPER(ptlb)532 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
533 {
534 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
535 uint32_t wi;
536 uint32_t ei;
537 uint8_t ring;
538 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
539
540 switch (res) {
541 case 0:
542 if (ring >= xtensa_get_ring(env)) {
543 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
544 }
545 break;
546
547 case INST_TLB_MULTI_HIT_CAUSE:
548 case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
549 HELPER(exception_cause_vaddr)(env, env->pc, res, v);
550 break;
551 }
552 return 0;
553 } else {
554 return (v & REGION_PAGE_MASK) | 0x1;
555 }
556 }
557
HELPER(wtlb)558 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
559 {
560 uint32_t vpn;
561 uint32_t wi;
562 uint32_t ei;
563 if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
564 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
565 }
566 }
567
568 /*!
569 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
570 * See ISA, 4.6.5.10
571 */
mmu_attr_to_access(uint32_t attr)572 static unsigned mmu_attr_to_access(uint32_t attr)
573 {
574 unsigned access = 0;
575
576 if (attr < 12) {
577 access |= PAGE_READ;
578 if (attr & 0x1) {
579 access |= PAGE_EXEC;
580 }
581 if (attr & 0x2) {
582 access |= PAGE_WRITE;
583 }
584
585 switch (attr & 0xc) {
586 case 0:
587 access |= PAGE_CACHE_BYPASS;
588 break;
589
590 case 4:
591 access |= PAGE_CACHE_WB;
592 break;
593
594 case 8:
595 access |= PAGE_CACHE_WT;
596 break;
597 }
598 } else if (attr == 13) {
599 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
600 }
601 return access;
602 }
603
604 /*!
605 * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
606 * See ISA, 4.6.3.3
607 */
region_attr_to_access(uint32_t attr)608 static unsigned region_attr_to_access(uint32_t attr)
609 {
610 static const unsigned access[16] = {
611 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
612 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
613 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
614 [3] = PAGE_EXEC | PAGE_CACHE_WB,
615 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
616 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
617 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
618 };
619
620 return access[attr & 0xf];
621 }
622
623 /*!
624 * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
625 * See ISA, A.2.14 The Cache Attribute Register
626 */
cacheattr_attr_to_access(uint32_t attr)627 static unsigned cacheattr_attr_to_access(uint32_t attr)
628 {
629 static const unsigned access[16] = {
630 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
631 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
632 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
633 [3] = PAGE_EXEC | PAGE_CACHE_WB,
634 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
635 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
636 };
637
638 return access[attr & 0xf];
639 }
640
641 struct attr_pattern {
642 uint32_t mask;
643 uint32_t value;
644 };
645
attr_pattern_match(uint32_t attr,const struct attr_pattern * pattern,size_t n)646 static int attr_pattern_match(uint32_t attr,
647 const struct attr_pattern *pattern,
648 size_t n)
649 {
650 size_t i;
651
652 for (i = 0; i < n; ++i) {
653 if ((attr & pattern[i].mask) == pattern[i].value) {
654 return 1;
655 }
656 }
657 return 0;
658 }
659
mpu_attr_to_cpu_cache(uint32_t attr)660 static unsigned mpu_attr_to_cpu_cache(uint32_t attr)
661 {
662 static const struct attr_pattern cpu_c[] = {
663 { .mask = 0x18f, .value = 0x089 },
664 { .mask = 0x188, .value = 0x080 },
665 { .mask = 0x180, .value = 0x180 },
666 };
667
668 unsigned type = 0;
669
670 if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) {
671 type |= XTENSA_MPU_TYPE_CPU_CACHE;
672 if (attr & 0x10) {
673 type |= XTENSA_MPU_TYPE_CPU_C;
674 }
675 if (attr & 0x20) {
676 type |= XTENSA_MPU_TYPE_CPU_W;
677 }
678 if (attr & 0x40) {
679 type |= XTENSA_MPU_TYPE_CPU_R;
680 }
681 }
682 return type;
683 }
684
mpu_attr_to_type(uint32_t attr)685 static unsigned mpu_attr_to_type(uint32_t attr)
686 {
687 static const struct attr_pattern device_type[] = {
688 { .mask = 0x1f6, .value = 0x000 },
689 { .mask = 0x1f6, .value = 0x006 },
690 };
691 static const struct attr_pattern sys_nc_type[] = {
692 { .mask = 0x1fe, .value = 0x018 },
693 { .mask = 0x1fe, .value = 0x01e },
694 { .mask = 0x18f, .value = 0x089 },
695 };
696 static const struct attr_pattern sys_c_type[] = {
697 { .mask = 0x1f8, .value = 0x010 },
698 { .mask = 0x188, .value = 0x080 },
699 { .mask = 0x1f0, .value = 0x030 },
700 { .mask = 0x180, .value = 0x180 },
701 };
702 static const struct attr_pattern b[] = {
703 { .mask = 0x1f7, .value = 0x001 },
704 { .mask = 0x1f7, .value = 0x007 },
705 { .mask = 0x1ff, .value = 0x019 },
706 { .mask = 0x1ff, .value = 0x01f },
707 };
708
709 unsigned type = 0;
710
711 attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT;
712 if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) {
713 type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE;
714 if (attr & 0x80) {
715 type |= XTENSA_MPU_TYPE_INT;
716 }
717 }
718 if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) {
719 type |= XTENSA_MPU_SYSTEM_TYPE_NC;
720 }
721 if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) {
722 type |= XTENSA_MPU_SYSTEM_TYPE_C;
723 if (attr & 0x1) {
724 type |= XTENSA_MPU_TYPE_SYS_C;
725 }
726 if (attr & 0x2) {
727 type |= XTENSA_MPU_TYPE_SYS_W;
728 }
729 if (attr & 0x4) {
730 type |= XTENSA_MPU_TYPE_SYS_R;
731 }
732 }
733 if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) {
734 type |= XTENSA_MPU_TYPE_B;
735 }
736 type |= mpu_attr_to_cpu_cache(attr);
737
738 return type;
739 }
740
mpu_attr_to_access(uint32_t attr,unsigned ring)741 static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring)
742 {
743 static const unsigned access[2][16] = {
744 [0] = {
745 [4] = PAGE_READ,
746 [5] = PAGE_READ | PAGE_EXEC,
747 [6] = PAGE_READ | PAGE_WRITE,
748 [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
749 [8] = PAGE_WRITE,
750 [9] = PAGE_READ | PAGE_WRITE,
751 [10] = PAGE_READ | PAGE_WRITE,
752 [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
753 [12] = PAGE_READ,
754 [13] = PAGE_READ | PAGE_EXEC,
755 [14] = PAGE_READ | PAGE_WRITE,
756 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
757 },
758 [1] = {
759 [8] = PAGE_WRITE,
760 [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
761 [10] = PAGE_READ,
762 [11] = PAGE_READ | PAGE_EXEC,
763 [12] = PAGE_READ,
764 [13] = PAGE_READ | PAGE_EXEC,
765 [14] = PAGE_READ | PAGE_WRITE,
766 [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC,
767 },
768 };
769 unsigned rv;
770 unsigned type;
771
772 type = mpu_attr_to_cpu_cache(attr);
773 rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >>
774 XTENSA_MPU_ACC_RIGHTS_SHIFT];
775
776 if (type & XTENSA_MPU_TYPE_CPU_CACHE) {
777 rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT;
778 } else {
779 rv |= PAGE_CACHE_BYPASS;
780 }
781 return rv;
782 }
783
is_access_granted(unsigned access,int is_write)784 static bool is_access_granted(unsigned access, int is_write)
785 {
786 switch (is_write) {
787 case 0:
788 return access & PAGE_READ;
789
790 case 1:
791 return access & PAGE_WRITE;
792
793 case 2:
794 return access & PAGE_EXEC;
795
796 default:
797 return 0;
798 }
799 }
800
801 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
802
get_physical_addr_mmu(CPUXtensaState * env,bool update_tlb,uint32_t vaddr,int is_write,int mmu_idx,uint32_t * paddr,uint32_t * page_size,unsigned * access,bool may_lookup_pt)803 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
804 uint32_t vaddr, int is_write, int mmu_idx,
805 uint32_t *paddr, uint32_t *page_size,
806 unsigned *access, bool may_lookup_pt)
807 {
808 bool dtlb = is_write != 2;
809 uint32_t wi;
810 uint32_t ei;
811 uint8_t ring;
812 uint32_t vpn;
813 uint32_t pte;
814 const xtensa_tlb_entry *entry = NULL;
815 xtensa_tlb_entry tmp_entry;
816 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
817
818 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
819 may_lookup_pt && get_pte(env, vaddr, &pte)) {
820 ring = (pte >> 4) & 0x3;
821 wi = 0;
822 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
823
824 if (update_tlb) {
825 wi = ++env->autorefill_idx & 0x3;
826 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
827 env->sregs[EXCVADDR] = vaddr;
828 qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n",
829 __func__, vaddr, vpn, pte);
830 } else {
831 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
832 entry = &tmp_entry;
833 }
834 ret = 0;
835 }
836 if (ret != 0) {
837 return ret;
838 }
839
840 if (entry == NULL) {
841 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
842 }
843
844 if (ring < mmu_idx) {
845 return dtlb ?
846 LOAD_STORE_PRIVILEGE_CAUSE :
847 INST_FETCH_PRIVILEGE_CAUSE;
848 }
849
850 *access = mmu_attr_to_access(entry->attr) &
851 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
852 if (!is_access_granted(*access, is_write)) {
853 return dtlb ?
854 (is_write ?
855 STORE_PROHIBITED_CAUSE :
856 LOAD_PROHIBITED_CAUSE) :
857 INST_FETCH_PROHIBITED_CAUSE;
858 }
859
860 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
861 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
862
863 return 0;
864 }
865
get_pte(CPUXtensaState * env,uint32_t vaddr,uint32_t * pte)866 static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
867 {
868 CPUState *cs = env_cpu(env);
869 uint32_t paddr;
870 uint32_t page_size;
871 unsigned access;
872 uint32_t pt_vaddr =
873 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
874 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
875 &paddr, &page_size, &access, false);
876
877 if (ret == 0) {
878 qemu_log_mask(CPU_LOG_MMU,
879 "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
880 __func__, vaddr, pt_vaddr, paddr);
881 } else {
882 qemu_log_mask(CPU_LOG_MMU,
883 "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
884 __func__, vaddr, pt_vaddr, ret);
885 }
886
887 if (ret == 0) {
888 MemTxResult result;
889
890 *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
891 &result);
892 if (result != MEMTX_OK) {
893 qemu_log_mask(CPU_LOG_MMU,
894 "%s: couldn't load PTE: transaction failed (%u)\n",
895 __func__, (unsigned)result);
896 ret = 1;
897 }
898 }
899 return ret == 0;
900 }
901
get_physical_addr_region(CPUXtensaState * env,uint32_t vaddr,int is_write,int mmu_idx,uint32_t * paddr,uint32_t * page_size,unsigned * access)902 static int get_physical_addr_region(CPUXtensaState *env,
903 uint32_t vaddr, int is_write, int mmu_idx,
904 uint32_t *paddr, uint32_t *page_size,
905 unsigned *access)
906 {
907 bool dtlb = is_write != 2;
908 uint32_t wi = 0;
909 uint32_t ei = (vaddr >> 29) & 0x7;
910 const xtensa_tlb_entry *entry =
911 xtensa_tlb_get_entry(env, dtlb, wi, ei);
912
913 *access = region_attr_to_access(entry->attr);
914 if (!is_access_granted(*access, is_write)) {
915 return dtlb ?
916 (is_write ?
917 STORE_PROHIBITED_CAUSE :
918 LOAD_PROHIBITED_CAUSE) :
919 INST_FETCH_PROHIBITED_CAUSE;
920 }
921
922 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
923 *page_size = ~REGION_PAGE_MASK + 1;
924
925 return 0;
926 }
927
xtensa_mpu_lookup(const xtensa_mpu_entry * entry,unsigned n,uint32_t vaddr,unsigned * segment)928 static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n,
929 uint32_t vaddr, unsigned *segment)
930 {
931 unsigned nhits = 0;
932 unsigned i;
933
934 for (i = 0; i < n; ++i) {
935 if (vaddr >= entry[i].vaddr &&
936 (i == n - 1 || vaddr < entry[i + 1].vaddr)) {
937 if (nhits++) {
938 break;
939 }
940 *segment = i;
941 }
942 }
943 return nhits;
944 }
945
HELPER(wsr_mpuenb)946 void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v)
947 {
948 v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1;
949
950 if (v != env->sregs[MPUENB]) {
951 env->sregs[MPUENB] = v;
952 tlb_flush(env_cpu(env));
953 }
954 }
955
HELPER(wptlb)956 void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v)
957 {
958 unsigned segment = p & XTENSA_MPU_SEGMENT_MASK;
959
960 if (segment < env->config->n_mpu_fg_segments) {
961 env->mpu_fg[segment].vaddr = v & -env->config->mpu_align;
962 env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
963 env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v);
964 tlb_flush(env_cpu(env));
965 }
966 }
967
HELPER(rptlb0)968 uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s)
969 {
970 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK;
971
972 if (segment < env->config->n_mpu_fg_segments) {
973 return env->mpu_fg[segment].vaddr |
974 extract32(env->sregs[MPUENB], segment, 1);
975 } else {
976 return 0;
977 }
978 }
979
HELPER(rptlb1)980 uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s)
981 {
982 unsigned segment = s & XTENSA_MPU_SEGMENT_MASK;
983
984 if (segment < env->config->n_mpu_fg_segments) {
985 return env->mpu_fg[segment].attr;
986 } else {
987 return 0;
988 }
989 }
990
HELPER(pptlb)991 uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v)
992 {
993 unsigned nhits;
994 unsigned segment = XTENSA_MPU_PROBE_B;
995 unsigned bg_segment;
996
997 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments,
998 v, &segment);
999 if (nhits > 1) {
1000 HELPER(exception_cause_vaddr)(env, env->pc,
1001 LOAD_STORE_TLB_MULTI_HIT_CAUSE, v);
1002 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) {
1003 return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V;
1004 } else {
1005 xtensa_mpu_lookup(env->config->mpu_bg,
1006 env->config->n_mpu_bg_segments,
1007 v, &bg_segment);
1008 return env->config->mpu_bg[bg_segment].attr | segment;
1009 }
1010 }
1011
get_physical_addr_mpu(CPUXtensaState * env,uint32_t vaddr,int is_write,int mmu_idx,uint32_t * paddr,uint32_t * page_size,unsigned * access)1012 static int get_physical_addr_mpu(CPUXtensaState *env,
1013 uint32_t vaddr, int is_write, int mmu_idx,
1014 uint32_t *paddr, uint32_t *page_size,
1015 unsigned *access)
1016 {
1017 unsigned nhits;
1018 unsigned segment;
1019 uint32_t attr;
1020
1021 nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments,
1022 vaddr, &segment);
1023 if (nhits > 1) {
1024 return is_write < 2 ?
1025 LOAD_STORE_TLB_MULTI_HIT_CAUSE :
1026 INST_TLB_MULTI_HIT_CAUSE;
1027 } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) {
1028 attr = env->mpu_fg[segment].attr;
1029 } else {
1030 xtensa_mpu_lookup(env->config->mpu_bg,
1031 env->config->n_mpu_bg_segments,
1032 vaddr, &segment);
1033 attr = env->config->mpu_bg[segment].attr;
1034 }
1035
1036 *access = mpu_attr_to_access(attr, mmu_idx);
1037 if (!is_access_granted(*access, is_write)) {
1038 return is_write < 2 ?
1039 (is_write ?
1040 STORE_PROHIBITED_CAUSE :
1041 LOAD_PROHIBITED_CAUSE) :
1042 INST_FETCH_PROHIBITED_CAUSE;
1043 }
1044 *paddr = vaddr;
1045 *page_size = env->config->mpu_align;
1046 return 0;
1047 }
1048
1049 /*!
1050 * Convert virtual address to physical addr.
1051 * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
1052 *
1053 * \return 0 if ok, exception cause code otherwise
1054 */
xtensa_get_physical_addr(CPUXtensaState * env,bool update_tlb,uint32_t vaddr,int is_write,int mmu_idx,uint32_t * paddr,uint32_t * page_size,unsigned * access)1055 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
1056 uint32_t vaddr, int is_write, int mmu_idx,
1057 uint32_t *paddr, uint32_t *page_size,
1058 unsigned *access)
1059 {
1060 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
1061 return get_physical_addr_mmu(env, update_tlb,
1062 vaddr, is_write, mmu_idx, paddr,
1063 page_size, access, true);
1064 } else if (xtensa_option_bits_enabled(env->config,
1065 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1066 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
1067 return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
1068 paddr, page_size, access);
1069 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
1070 return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx,
1071 paddr, page_size, access);
1072 } else {
1073 *paddr = vaddr;
1074 *page_size = TARGET_PAGE_SIZE;
1075 *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >>
1076 ((vaddr & 0xe0000000) >> 27));
1077 return 0;
1078 }
1079 }
1080
dump_tlb(CPUXtensaState * env,bool dtlb)1081 static void dump_tlb(CPUXtensaState *env, bool dtlb)
1082 {
1083 unsigned wi, ei;
1084 const xtensa_tlb *conf =
1085 dtlb ? &env->config->dtlb : &env->config->itlb;
1086 unsigned (*attr_to_access)(uint32_t) =
1087 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
1088 mmu_attr_to_access : region_attr_to_access;
1089
1090 for (wi = 0; wi < conf->nways; ++wi) {
1091 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
1092 const char *sz_text;
1093 bool print_header = true;
1094
1095 if (sz >= 0x100000) {
1096 sz /= MiB;
1097 sz_text = "MB";
1098 } else {
1099 sz /= KiB;
1100 sz_text = "KB";
1101 }
1102
1103 for (ei = 0; ei < conf->way_size[wi]; ++ei) {
1104 const xtensa_tlb_entry *entry =
1105 xtensa_tlb_get_entry(env, dtlb, wi, ei);
1106
1107 if (entry->asid) {
1108 static const char * const cache_text[8] = {
1109 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
1110 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
1111 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
1112 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
1113 };
1114 unsigned access = attr_to_access(entry->attr);
1115 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
1116 PAGE_CACHE_SHIFT;
1117
1118 if (print_header) {
1119 print_header = false;
1120 qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text);
1121 qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n"
1122 "\t---------- ---------- ---- ---- --- -------\n");
1123 }
1124 qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n",
1125 entry->vaddr,
1126 entry->paddr,
1127 entry->asid,
1128 entry->attr,
1129 (access & PAGE_READ) ? 'R' : '-',
1130 (access & PAGE_WRITE) ? 'W' : '-',
1131 (access & PAGE_EXEC) ? 'X' : '-',
1132 cache_text[cache_idx] ?
1133 cache_text[cache_idx] : "Invalid");
1134 }
1135 }
1136 }
1137 }
1138
dump_mpu(CPUXtensaState * env,const xtensa_mpu_entry * entry,unsigned n)1139 static void dump_mpu(CPUXtensaState *env,
1140 const xtensa_mpu_entry *entry, unsigned n)
1141 {
1142 unsigned i;
1143
1144 qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n"
1145 "\t%s ---------- ---------- ----- ----- ------------- ---------\n",
1146 env ? "En" : " ",
1147 env ? "--" : " ");
1148
1149 for (i = 0; i < n; ++i) {
1150 uint32_t attr = entry[i].attr;
1151 unsigned access0 = mpu_attr_to_access(attr, 0);
1152 unsigned access1 = mpu_attr_to_access(attr, 1);
1153 unsigned type = mpu_attr_to_type(attr);
1154 char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' ';
1155
1156 qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ",
1157 env ?
1158 ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ',
1159 entry[i].vaddr, attr,
1160 (access0 & PAGE_READ) ? 'R' : '-',
1161 (access0 & PAGE_WRITE) ? 'W' : '-',
1162 (access0 & PAGE_EXEC) ? 'X' : '-',
1163 (access1 & PAGE_READ) ? 'R' : '-',
1164 (access1 & PAGE_WRITE) ? 'W' : '-',
1165 (access1 & PAGE_EXEC) ? 'X' : '-');
1166
1167 switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) {
1168 case XTENSA_MPU_SYSTEM_TYPE_DEVICE:
1169 qemu_printf("Device %cB %3s\n",
1170 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
1171 (type & XTENSA_MPU_TYPE_INT) ? "int" : "");
1172 break;
1173 case XTENSA_MPU_SYSTEM_TYPE_NC:
1174 qemu_printf("Sys NC %cB %c%c%c\n",
1175 (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n',
1176 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
1177 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
1178 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
1179 break;
1180 case XTENSA_MPU_SYSTEM_TYPE_C:
1181 qemu_printf("Sys C %c%c%c %c%c%c\n",
1182 (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-',
1183 (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-',
1184 (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-',
1185 (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache,
1186 (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache,
1187 (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache);
1188 break;
1189 default:
1190 qemu_printf("Unknown\n");
1191 break;
1192 }
1193 }
1194 }
1195
dump_mmu(CPUXtensaState * env)1196 void dump_mmu(CPUXtensaState *env)
1197 {
1198 if (xtensa_option_bits_enabled(env->config,
1199 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1200 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
1201 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
1202
1203 qemu_printf("ITLB:\n");
1204 dump_tlb(env, false);
1205 qemu_printf("\nDTLB:\n");
1206 dump_tlb(env, true);
1207 } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) {
1208 qemu_printf("Foreground map:\n");
1209 dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments);
1210 qemu_printf("\nBackground map:\n");
1211 dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments);
1212 } else {
1213 qemu_printf("No TLB for this CPU core\n");
1214 }
1215 }
1216