1 /* sds_defs.h: SDS 940 simulator definitions 2 3 Copyright (c) 2001-2010, Robert M. Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 22-May-10 RMS Added check for 64b definitions 27 25-Apr-03 RMS Revised for extended file support 28 */ 29 30 #ifndef _SDS_DEFS_H_ 31 #define _SDS_DEFS_H_ 0 32 33 #include "sim_defs.h" /* simulator defns */ 34 35 #if defined(USE_INT64) || defined(USE_ADDR64) 36 #error "SDS 940 does not support 64b values!" 37 #endif 38 39 /* Simulator stop codes */ 40 41 #define STOP_IONRDY 1 /* I/O dev not ready */ 42 #define STOP_HALT 2 /* HALT */ 43 #define STOP_IBKPT 3 /* breakpoint */ 44 #define STOP_INVDEV 4 /* invalid dev */ 45 #define STOP_INVINS 5 /* invalid instr */ 46 #define STOP_INVIOP 6 /* invalid I/O op */ 47 #define STOP_INDLIM 7 /* indirect limit */ 48 #define STOP_EXULIM 8 /* EXU limit */ 49 #define STOP_MMINT 9 /* mm in intr */ 50 #define STOP_MMTRP 10 /* mm in trap */ 51 #define STOP_TRPINS 11 /* trap inst not BRM */ 52 #define STOP_RTCINS 12 /* rtc inst not MIN/SKR */ 53 #define STOP_ILLVEC 13 /* zero vector */ 54 #define STOP_CCT 14 /* runaway CCT */ 55 56 /* Trap codes */ 57 58 #define MM_PRVINS -040 /* privileged */ 59 #define MM_NOACC -041 /* no access */ 60 #define MM_WRITE -043 /* write protect */ 61 #define MM_MONUSR -044 /* mon to user */ 62 63 /* Conditional error returns */ 64 65 #define CRETINS return ((stop_invins)? STOP_INVINS: SCPE_OK) 66 #define CRETDEV return ((stop_invdev)? STOP_INVDEV: SCPE_OK) 67 #define CRETIOP return ((stop_inviop)? STOP_INVIOP: SCPE_OK) 68 #define CRETIOE(f,c) return ((f)? c: SCPE_OK) 69 70 /* Architectural constants */ 71 72 #define SIGN 040000000 /* sign */ 73 #define DMASK 077777777 /* data mask */ 74 #define EXPS 0400 /* exp sign */ 75 #define EXPMASK 0777 /* exp mask */ 76 #define SXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): \ 77 ((x) & DMASK))) 78 #define SXT_EXP(x) ((int32) (((x) & EXPS)? ((x) | ~EXPMASK): \ 79 ((x) & EXPMASK))) 80 81 /* Memory */ 82 83 #define MAXMEMSIZE (1 << 16) /* max memory size */ 84 #define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */ 85 #define MEMSIZE (cpu_unit.capac) /* actual memory size */ 86 #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) 87 #define ReadP(x) M[x] 88 #define WriteP(x,y) if (MEM_ADDR_OK (x)) M[x] = y 89 90 /* Virtual addressing */ 91 92 #define VA_SIZE (1 << 14) /* virtual addr size */ 93 #define VA_MASK (VA_SIZE - 1) /* virtual addr mask */ 94 #define VA_V_PN 11 /* page number */ 95 #define VA_M_PN 07 96 #define VA_GETPN(x) (((x) >> VA_V_PN) & VA_M_PN) 97 #define VA_POFF ((1 << VA_V_PN) - 1) /* offset */ 98 #define VA_USR (I_USR) /* user flag in addr */ 99 #define XVA_MASK (VA_USR | VA_MASK) 100 101 /* Arithmetic */ 102 103 #define TSTS(x) ((x) & SIGN) 104 #define NEG(x) (-((int32) (x)) & DMASK) 105 #define ABS(x) (TSTS (x)? NEG(x): (x)) 106 107 /* Memory map */ 108 109 #define MAP_PROT (040 << VA_V_PN) /* protected */ 110 #define MAP_PAGE (037 << VA_V_PN) /* phys page number */ 111 112 /* Instruction format */ 113 114 #define I_USR (1 << 23) /* user */ 115 #define I_IDX (1 << 22) /* indexed */ 116 #define I_POP (1 << 21) /* programmed op */ 117 #define I_V_TAG 21 /* tag */ 118 #define I_V_OP 15 /* opcode */ 119 #define I_M_OP 077 120 #define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP) 121 #define I_IND (1 << 14) /* indirect */ 122 #define I_V_SHFOP 11 /* shift op */ 123 #define I_M_SHFOP 07 124 #define I_GETSHFOP(x) (((x) >> I_V_SHFOP) & I_M_SHFOP) 125 #define I_SHFMSK 0777 /* shift count */ 126 #define I_V_IOMD 12 /* IO inst mode */ 127 #define I_M_IOMD 03 128 #define I_GETIOMD(x) (((x) >> I_V_IOMD) & I_M_IOMD) 129 #define I_V_SKCND 7 /* SKS skip cond */ 130 #define I_M_SKCND 037 131 #define I_GETSKCND(x) (((x) >> I_V_SKCND) & I_M_SKCND) 132 #define I_EOB2 000400000 /* chan# bit 2 */ 133 #define I_SKB2 000040000 /* skschan# bit 2 */ 134 #define I_EOB1 020000000 /* chan# bit 1 */ 135 #define I_EOB0 000000100 /* chan# bit 0 */ 136 #define I_GETEOCH(x) ((((x) & I_EOB2)? 4: 0) | \ 137 (((x) & I_EOB1)? 2: 0) | \ 138 (((x) & I_EOB0)? 1: 0)) 139 #define I_SETEOCH(x) ((((x) & 4)? I_EOB2: 0) | \ 140 (((x) & 2)? I_EOB1: 0) | \ 141 (((x) & 1)? I_EOB0: 0)) 142 #define I_GETSKCH(x) ((((x) & I_SKB2)? 4: 0) | \ 143 (((x) & I_EOB1)? 2: 0) | \ 144 (((x) & I_EOB0)? 1: 0)) 145 #define I_SETSKCH(x) ((((x) & 4)? I_SKB2: 0) | \ 146 (((x) & 2)? I_EOB1: 0) | \ 147 (((x) & 1)? I_EOB0: 0)) 148 149 /* Globally visible flags */ 150 151 #define UNIT_V_GENIE (UNIT_V_UF + 0) 152 #define UNIT_GENIE (1 << UNIT_V_GENIE) 153 154 /* Timers */ 155 156 #define TMR_RTC 0 /* clock */ 157 #define TMR_MUX 1 /* mux */ 158 159 /* I/O routine functions */ 160 161 #define IO_CONN 0 /* connect */ 162 #define IO_EOM1 1 /* EOM mode 1 */ 163 #define IO_DISC 2 /* disconnect */ 164 #define IO_READ 3 /* read */ 165 #define IO_WRITE 4 /* write */ 166 #define IO_WREOR 5 /* write eor */ 167 #define IO_SKS 6 /* skip signal */ 168 169 /* Dispatch template */ 170 171 struct sdsdspt { 172 uint32 num; /* # entries */ 173 uint32 off; /* offset from base */ 174 }; 175 176 typedef struct sdsdspt DSPT; 177 178 /* Device information block */ 179 180 struct sdsdib { 181 int32 chan; /* channel */ 182 int32 dev; /* base dev no */ 183 int32 xfr; /* xfer flag */ 184 DSPT *tplt; /* dispatch templates */ 185 t_stat (*iop) (uint32 fnc, uint32 dev, uint32 *dat); 186 }; 187 188 typedef struct sdsdib DIB; 189 190 /* Channels */ 191 192 #define NUM_CHAN 8 /* max num chan */ 193 #define CHAN_W 0 /* TMCC */ 194 #define CHAN_Y 1 195 #define CHAN_C 2 196 #define CHAN_D 3 197 #define CHAN_E 4 /* DACC */ 198 #define CHAN_F 5 199 #define CHAN_G 6 200 #define CHAN_H 7 201 202 /* I/O control EOM */ 203 204 #define CHC_REV 04000 /* reverse */ 205 #define CHC_NLDR 02000 /* no leader */ 206 #define CHC_BIN 01000 /* binary */ 207 #define CHC_V_CPW 7 /* char/word */ 208 #define CHC_M_CPW 03 209 #define CHC_GETCPW(x) (((x) >> CHC_V_CPW) & CHC_M_CPW) 210 211 /* Buffer control (extended) EOM */ 212 213 #define CHM_CE 04000 /* compat/ext */ 214 #define CHM_ER 02000 /* end rec int */ 215 #define CHM_ZC 01000 /* zero wc int */ 216 #define CHM_V_FNC 7 /* term func */ 217 #define CHM_M_FNC 03 218 #define CHM_GETFNC(x) (((x) & CHM_CE)? (((x) >> CHM_V_FNC) & CHM_M_FNC): CHM_COMP) 219 #define CHM_IORD 0 /* record, disc */ 220 #define CHM_IOSD 1 /* signal, disc */ 221 #define CHM_IORP 2 /* record, proc */ 222 #define CHM_IOSP 3 /* signal, proc */ 223 #define CHM_COMP 5 /* compatible */ 224 #define CHM_SGNL 1 /* signal bit */ 225 #define CHM_PROC 2 /* proceed bit */ 226 #define CHM_V_HMA 5 /* hi mem addr */ 227 #define CHM_M_HMA 03 228 #define CHM_GETHMA(x) (((x) >> CHM_V_HMA) & CHM_M_HMA) 229 #define CHM_V_HWC 0 /* hi word count */ 230 #define CHM_M_HWC 037 231 #define CHM_GETHWC(x) (((x) >> CHM_V_HWC) & CHM_M_HWC) 232 233 /* Channel flags word */ 234 235 #define CHF_ERR 00001 /* error */ 236 #define CHF_IREC 00002 /* interrecord */ 237 #define CHF_ILCE 00004 /* interlace */ 238 #define CHF_DCHN 00010 /* data chain */ 239 #define CHF_EOR 00020 /* end of record */ 240 #define CHF_12B 00040 /* 12 bit mode */ 241 #define CHF_24B 00100 /* 24 bit mode */ 242 #define CHF_OWAK 00200 /* output wake */ 243 #define CHF_SCAN 00400 /* scan */ 244 #define CHF_TOP 01000 /* TOP pending */ 245 #define CHF_N_FLG 9 /* <= 16 */ 246 247 /* Interrupts and vectors (0 is reserved), highest bit is highest priority */ 248 249 #define INT_V_PWRO 31 /* power on */ 250 #define INT_V_PWRF 30 /* power off */ 251 #define INT_V_CPAR 29 /* CPU parity err */ 252 #define INT_V_IPAR 28 /* IO parity err */ 253 #define INT_V_RTCS 27 /* clock sync */ 254 #define INT_V_RTCP 26 /* clock pulse */ 255 #define INT_V_YZWC 25 /* chan Y zero wc */ 256 #define INT_V_WZWC 24 /* chan W zero wc */ 257 #define INT_V_YEOR 23 /* chan Y end rec */ 258 #define INT_V_WEOR 22 /* chan W end rec */ 259 #define INT_V_CZWC 21 /* chan C */ 260 #define INT_V_CEOR 20 261 #define INT_V_DZWC 19 /* chan D */ 262 #define INT_V_DEOR 18 263 #define INT_V_EZWC 17 /* chan E */ 264 #define INT_V_EEOR 16 265 #define INT_V_FZWC 15 /* chan F */ 266 #define INT_V_FEOR 14 267 #define INT_V_GZWC 13 /* chan G */ 268 #define INT_V_GEOR 12 269 #define INT_V_HZWC 11 /* chan H */ 270 #define INT_V_HEOR 10 271 #define INT_V_MUXR 9 /* mux receive */ 272 #define INT_V_MUXT 8 /* mux transmit */ 273 #define INT_V_MUXCO 7 /* SDS carrier on */ 274 #define INT_V_MUXCF 6 /* SDS carrier off */ 275 #define INT_V_DRM 5 /* Genie drum */ 276 #define INT_V_FORK 4 /* fork */ 277 278 #define INT_PWRO (1 << INT_V_PWRO) 279 #define INT_PWRF (1 << INT_V_PWRF) 280 #define INT_CPAR (1 << INT_V_CPAR) 281 #define INT_IPAR (1 << INT_V_IPAR) 282 #define INT_RTCS (1 << INT_V_RTCS) 283 #define INT_RTCP (1 << INT_V_RTCP) 284 #define INT_YZWC (1 << INT_V_YZWC) 285 #define INT_WZWC (1 << INT_V_WZWC) 286 #define INT_YEOR (1 << INT_V_YEOR) 287 #define INT_WEOR (1 << INT_V_WEOR) 288 #define INT_CZWC (1 << INT_V_CZWC) 289 #define INT_CEOR (1 << INT_V_CEOR) 290 #define INT_DZWC (1 << INT_V_DZWC) 291 #define INT_DEOR (1 << INT_V_DEOR) 292 #define INT_EZWC (1 << INT_V_EZWC) 293 #define INT_EEOR (1 << INT_V_EEOR) 294 #define INT_FZWC (1 << INT_V_FZWC) 295 #define INT_FEOR (1 << INT_V_FEOR) 296 #define INT_GZWC (1 << INT_V_GZWC) 297 #define INT_GEOR (1 << INT_V_GEOR) 298 #define INT_HZWC (1 << INT_V_HZWC) 299 #define INT_HEOR (1 << INT_V_HEOR) 300 #define INT_MUXR (1 << INT_V_MUXR) 301 #define INT_MUXT (1 << INT_V_MUXT) 302 #define INT_MUXCO (1 << INT_V_MUXCO) 303 #define INT_MUXCF (1 << INT_V_MUXCF) 304 #define INT_DRM (1 << INT_V_DRM) 305 #define INT_FORK (1 << INT_V_FORK) 306 307 #define VEC_PWRO 0036 308 #define VEC_PWRF 0037 309 #define VEC_CPAR 0056 310 #define VEC_IPAR 0057 311 #define VEC_RTCS 0074 312 #define VEC_RTCP 0075 313 #define VEC_YZWC 0030 314 #define VEC_WZWC 0031 315 #define VEC_YEOR 0032 316 #define VEC_WEOR 0033 317 #define VEC_CZWC 0060 318 #define VEC_CEOR 0061 319 #define VEC_DZWC 0062 320 #define VEC_DEOR 0063 321 #define VEC_EZWC 0064 322 #define VEC_EEOR 0065 323 #define VEC_FZWC 0066 324 #define VEC_FEOR 0067 325 #define VEC_GZWC 0070 326 #define VEC_GEOR 0071 327 #define VEC_HZWC 0072 328 #define VEC_HEOR 0073 329 #define VEC_MUXR 0200 /* term mux rcv */ 330 #define VEC_MUXT 0201 /* term mux xmt */ 331 #define VEC_MUXCO 0202 /* SDS: mux carrier on */ 332 #define VEC_MUXCF 0203 /* SDS: mux carrier off */ 333 #define VEC_DRM 0202 /* Genie: drum */ 334 #define VEC_FORK 0216 /* "fork" */ 335 336 /* Device constants */ 337 338 #define DEV_MASK 077 /* device mask */ 339 #define DEV_TTI 001 /* teletype */ 340 #define DEV_PTR 004 /* paper tape rdr */ 341 #define DEV_MT 010 /* magtape */ 342 #define DEV_RAD 026 /* fixed head disk */ 343 #define DEV_DSK 026 /* moving head disk */ 344 #define DEV_TTO 041 /* teletype */ 345 #define DEV_PTP 044 /* paper tape punch */ 346 #define DEV_LPT 060 /* line printer */ 347 #define DEV_MTS 020 /* MT scan/erase */ 348 #define DEV_OUT 040 /* output flag */ 349 #define DEV3_GDRM 004 /* Genie drum */ 350 #define DEV3_GMUX 001 /* Genie mux */ 351 #define DEV3_SMUX (DEV_MASK) /* standard mux */ 352 353 #define LPT_WIDTH 132 /* line print width */ 354 #define CCT_LNT 132 /* car ctrl length */ 355 356 /* Transfer request flags for devices (0 is reserved) */ 357 358 #define XFR_V_TTI 1 /* console */ 359 #define XFR_V_TTO 2 360 #define XFR_V_PTR 3 /* paper tape */ 361 #define XFR_V_PTP 4 362 #define XFR_V_LPT 5 /* line printer */ 363 #define XFR_V_RAD 6 /* fixed hd disk */ 364 #define XFR_V_DSK 7 /* mving hd disk */ 365 #define XFR_V_MT0 8 /* magtape */ 366 367 #define XFR_TTI (1 << XFR_V_TTI) 368 #define XFR_TTO (1 << XFR_V_TTO) 369 #define XFR_PTR (1 << XFR_V_PTR) 370 #define XFR_PTP (1 << XFR_V_PTP) 371 #define XFR_LPT (1 << XFR_V_LPT) 372 #define XFR_RAD (1 << XFR_V_RAD) 373 #define XFR_DSK (1 << XFR_V_DSK) 374 #define XFR_MT0 (1 << XFR_V_MT0) 375 376 /* PIN/POT ordinals (0 is reserved) */ 377 378 #define POT_ILCY 1 /* interlace */ 379 #define POT_DCRY (POT_ILCY + NUM_CHAN) /* data chain */ 380 #define POT_ADRY (POT_DCRY + NUM_CHAN) /* address reg */ 381 #define POT_RL1 (POT_ADRY + NUM_CHAN) /* RL1 */ 382 #define POT_RL2 (POT_RL1 + 1) /* RL2 */ 383 #define POT_RL4 (POT_RL2 + 1) /* RL4 */ 384 #define POT_RADS (POT_RL4 + 1) /* fhd sector */ 385 #define POT_RADA (POT_RADS + 1) /* fhd addr */ 386 #define POT_DSK (POT_RADA + 1) /* mhd sec/addr */ 387 #define POT_SYSI (POT_DSK + 1) /* sys intr */ 388 #define POT_MUX (POT_SYSI + 1) /* multiplexor */ 389 390 /* Opcodes */ 391 392 enum opcodes { 393 HLT, BRU, EOM, EOD = 006, 394 MIY = 010, BRI, MIW, POT, ETR, MRG = 016, EOR, 395 NOP, OVF = 022, EXU, 396 YIM = 030, WIM = 032, PIN, STA = 035, STB, STX, 397 SKS, BRX, BRM = 043, RCH = 046, 398 SKE = 050, BRR, SKB, SKN, SUB, ADD, SUC, ADC, 399 SKR, MIN, XMA, ADM, MUL, DIV, RSH, LSH, 400 SKM, LDX, SKA, SKG, SKD, LDB, LDA, EAX 401 }; 402 403 /* Channel function prototypes */ 404 405 void chan_set_flag (int32 ch, uint32 fl); 406 void chan_set_ordy (int32 ch); 407 void chan_disc (int32 ch); 408 void chan_set_uar (int32 ch, uint32 dev); 409 t_stat set_chan (UNIT *uptr, int32 val, char *cptr, void *desc); 410 t_stat show_chan (FILE *st, UNIT *uptr, int32 val, void *desc); 411 t_stat chan_process (void); 412 t_bool chan_testact (void); 413 414 #endif 415