1/* 2 * yosys -- Yosys Open SYnthesis Suite 3 * 4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * --- 19 * 20 * The internal logic cell simulation library. 21 * 22 * This Verilog library contains simple simulation models for the internal 23 * logic cells (_NOT_, _AND_, ...) that are generated by the default technology 24 * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. 25 * 26 */ 27 28module _NOT_(A, Y); 29input A; 30output Y; 31assign Y = ~A; 32endmodule 33 34module _AND_(A, B, Y); 35input A, B; 36output Y; 37assign Y = A & B; 38endmodule 39 40module _OR_(A, B, Y); 41input A, B; 42output Y; 43assign Y = A | B; 44endmodule 45 46module _XOR_(A, B, Y); 47input A, B; 48output Y; 49assign Y = A ^ B; 50endmodule 51 52module _MUX_(A, B, S, Y); 53input A, B, S; 54output reg Y; 55always @* begin 56 if (S) 57 Y = B; 58 else 59 Y = A; 60end 61endmodule 62 63module _DFF_N_(D, Q, C); 64input D, C; 65output reg Q; 66always @(negedge C) begin 67 Q <= D; 68end 69endmodule 70 71module _DFF_P_(D, Q, C); 72input D, C; 73output reg Q; 74always @(posedge C) begin 75 Q <= D; 76end 77endmodule 78 79module _DFF_NN0_(D, Q, C, R); 80input D, C, R; 81output reg Q; 82always @(negedge C or negedge R) begin 83 if (R == 0) 84 Q <= 0; 85 else 86 Q <= D; 87end 88endmodule 89 90module _DFF_NN1_(D, Q, C, R); 91input D, C, R; 92output reg Q; 93always @(negedge C or negedge R) begin 94 if (R == 0) 95 Q <= 1; 96 else 97 Q <= D; 98end 99endmodule 100 101module _DFF_NP0_(D, Q, C, R); 102input D, C, R; 103output reg Q; 104always @(negedge C or posedge R) begin 105 if (R == 1) 106 Q <= 0; 107 else 108 Q <= D; 109end 110endmodule 111 112module _DFF_NP1_(D, Q, C, R); 113input D, C, R; 114output reg Q; 115always @(negedge C or posedge R) begin 116 if (R == 1) 117 Q <= 1; 118 else 119 Q <= D; 120end 121endmodule 122 123module _DFF_PN0_(D, Q, C, R); 124input D, C, R; 125output reg Q; 126always @(posedge C or negedge R) begin 127 if (R == 0) 128 Q <= 0; 129 else 130 Q <= D; 131end 132endmodule 133 134module _DFF_PN1_(D, Q, C, R); 135input D, C, R; 136output reg Q; 137always @(posedge C or negedge R) begin 138 if (R == 0) 139 Q <= 1; 140 else 141 Q <= D; 142end 143endmodule 144 145module _DFF_PP0_(D, Q, C, R); 146input D, C, R; 147output reg Q; 148always @(posedge C or posedge R) begin 149 if (R == 1) 150 Q <= 0; 151 else 152 Q <= D; 153end 154endmodule 155 156module _DFF_PP1_(D, Q, C, R); 157input D, C, R; 158output reg Q; 159always @(posedge C or posedge R) begin 160 if (R == 1) 161 Q <= 1; 162 else 163 Q <= D; 164end 165endmodule 166 167