1 /* $NetBSD: intr.h,v 1.21 2023/07/11 11:46:38 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2001 Matt Fredette.
5 * Copyright (c) 1998 Matt Thomas.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the company nor the names of the authors may be used to
17 * endorse or promote products derived from this software without specific
18 * prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #ifndef _SUN68K_INTR_H_
34 #define _SUN68K_INTR_H_
35
36 #include <sys/queue.h>
37 #include <m68k/psl.h>
38
39 /*
40 * Interrupt levels.
41 */
42 #define IPL_NONE 0
43 #define IPL_SOFTCLOCK 1
44 #define IPL_SOFTBIO 2
45 #define IPL_SOFTNET 3
46 #define IPL_SOFTSERIAL 4
47 #define IPL_VM 5
48 #define IPL_SCHED 6
49 #define IPL_HIGH 7
50 #define NIPL 8
51
52 #define _IPL_SOFT_LEVEL1 1
53 #define _IPL_SOFT_LEVEL2 2
54 #define _IPL_SOFT_LEVEL3 3
55 #define _IPL_SOFT_LEVEL_MIN 1
56 #define _IPL_SOFT_LEVEL_MAX 3
57
58 #if defined(_KERNEL) || defined(_KMEMUSER)
59 typedef struct {
60 uint16_t _psl;
61 } ipl_cookie_t;
62 #endif
63
64 #ifdef _KERNEL
65
66 extern int idepth;
67
68 static inline bool
cpu_intr_p(void)69 cpu_intr_p(void)
70 {
71
72 return idepth != 0;
73 }
74
75 extern const uint16_t ipl2psl_table[NIPL];
76
77 typedef int ipl_t;
78
79 static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)80 makeiplcookie(ipl_t ipl)
81 {
82
83 return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
84 }
85
86 static inline int
splraiseipl(ipl_cookie_t icookie)87 splraiseipl(ipl_cookie_t icookie)
88 {
89
90 return _splraise(icookie._psl);
91 }
92
93 /* These connect interrupt handlers. */
94 typedef int (*isr_func_t)(void *);
95 void isr_add_autovect(isr_func_t, void *, int);
96 void isr_add_vectored(isr_func_t, void *, int, int);
97 void isr_add_custom(int, void *);
98
99 /*
100 * Define inline functions for PSL manipulation.
101 * These are as close to macros as one can get.
102 * When not optimizing gcc will call the locore.s
103 * functions by the same names, so breakpoints on
104 * these functions will work normally, etc.
105 * (See the GCC extensions info document.)
106 */
107
108 static __inline int _getsr(void);
109
110 /* Get current sr value. */
111 static __inline int
_getsr(void)112 _getsr(void)
113 {
114 int rv;
115
116 __asm volatile ("clrl %0; movew %%sr,%0" : "=&d" (rv));
117 return (rv);
118 }
119
120 /*
121 * The rest of this is sun68k specific, because other ports may
122 * need to do special things in spl0() (i.e. simulate SIR).
123 * Suns have a REAL interrupt register, so spl0() and splx(s)
124 * have no need to check for any simulated interrupts, etc.
125 */
126
127 #define spl0() _spl0() /* we have real software interrupts */
128 #define splx(x) _spl(x)
129
130 /* IPL used by soft interrupts: netintr(), softclock() */
131 #define splsoftclock() splraise1()
132 #define splsoftbio() splraise1()
133 #define splsoftnet() splraise1()
134 #define splsoftserial() splraise3()
135
136 /*
137 * Note that the VM code runs at spl7 during kernel
138 * initialization, and later at spl0, so we have to
139 * use splraise to avoid enabling interrupts early.
140 */
141 #define splvm() splraise4()
142
143 /* Zilog Serial hardware interrupts (hard-wired at 6) */
144 #define splzs() splserial()
145 #define IPL_ZS IPL_SERIAL
146
147 /* Block out all interrupts (except NMI of course). */
148 #define splhigh() spl7()
149 #define splsched() spl7()
150
151 /* This returns true iff the spl given is spl0. */
152 #define is_spl0(s) (((s) & PSL_IPL7) == 0)
153
154 #endif /* _KERNEL */
155
156 #endif /* _SUN68K_INTR_H */
157