1 /* $NetBSD: mcontext.h,v 1.18 2019/12/27 00:32:17 kamil Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Klaus Klein.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _SPARC_MCONTEXT_H_
33 #define _SPARC_MCONTEXT_H_
34
35 #define _UC_SETSTACK 0x00010000
36 #define _UC_CLRSTACK 0x00020000
37 #define _UC_TLSBASE 0x00080000
38
39 /*
40 * Layout of mcontext_t according the System V Application Binary Interface,
41 * Edition 4.1, SPARC Processor ABI Supplement and updated for SPARC v9.
42 */
43
44 #ifdef __arch64__
45 #define _NGREG 21 /* %ccr, pc, npc, %g1-7, %o0-7, %asi, %fprs */
46 #else
47 #define _NGREG 19 /* %psr, pc, npc, %g1-7, %o0-7 */
48 #endif
49 typedef long int __greg_t;
50 typedef __greg_t __gregset_t[_NGREG];
51
52 /* Offsets into gregset_t, for convenience. */
53 #define _REG_CCR 0 /* 64 bit only */
54 #define _REG_PSR 0 /* 32 bit only */
55 #define _REG_PC 1
56 #define _REG_nPC 2
57 #define _REG_Y 3
58 #define _REG_G1 4
59 #define _REG_G2 5
60 #define _REG_G3 6
61 #define _REG_G4 7
62 #define _REG_G5 8
63 #define _REG_G6 9
64 #define _REG_G7 10
65 #define _REG_O0 11
66 #define _REG_O1 12
67 #define _REG_O2 13
68 #define _REG_O3 14
69 #define _REG_O4 15
70 #define _REG_O5 16
71 #define _REG_O6 17
72 #define _REG_O7 18
73 #define _REG_ASI 19 /* 64 bit only */
74 #define _REG_FPRS 20 /* 64 bit only */
75
76
77 #define _SPARC_MAXREGWINDOW 31
78
79 /* Layout of a register window. */
80 typedef struct {
81 __greg_t __rw_local[8]; /* %l0-7 */
82 __greg_t __rw_in[8]; /* %i0-7 */
83 } __rwindow_t;
84
85 /* Description of available register windows. */
86 typedef struct {
87 int __wbcnt;
88 __greg_t * __spbuf[_SPARC_MAXREGWINDOW];
89 __rwindow_t __wbuf[_SPARC_MAXREGWINDOW];
90 } __gwindows_t;
91
92 /* FPU address queue */
93 struct __fpq {
94 unsigned int * __fpq_addr; /* address */
95 unsigned int __fpq_instr; /* instruction */
96 };
97
98 struct __fq {
99 union {
100 double __whole;
101 struct __fpq __fpq;
102 } _FQu;
103 };
104
105 /* FPU state description */
106 typedef struct {
107 union {
108 unsigned int __fpu_regs[32];
109 #ifdef __arch64__
110 double __fpu_dregs[32];
111 long double __fpu_qregs[16];
112 #else
113 double __fpu_dregs[16];
114 #endif
115 } __fpu_fr; /* FPR contents */
116 struct __fq * __fpu_q; /* pointer to FPU insn queue */
117 unsigned long __fpu_fsr; /* %fsr */
118 unsigned char __fpu_qcnt; /* # entries in __fpu_q */
119 unsigned char __fpu_q_entrysize; /* size of a __fpu_q entry */
120 unsigned char __fpu_en; /* this context valid? */
121 } __fpregset_t;
122
123 /* `Extra Register State'(?) */
124 typedef struct {
125 unsigned int __xrs_id; /* See below */
126 char * __xrs_ptr; /* points into filler area */
127 } __xrs_t;
128
129 #define _XRS_ID 0x78727300 /* 'xrs\0' */
130
131 #ifdef __arch64__
132 /* Ancillary State Registers, 16-31 are available to user programs */
133 typedef long __asrset_t[16]; /* %asr16-31 */
134 #endif
135
136 typedef struct {
137 __gregset_t __gregs; /* GPR state */
138 __gwindows_t * __gwins; /* may point to register windows */
139 __fpregset_t __fpregs; /* FPU state, if any */
140 __xrs_t __xrs; /* may indicate extra reg state */
141 #ifdef __arch64__
142 __asrset_t __asrs; /* ASR state */
143 #endif
144 } mcontext_t;
145
146 #ifdef __arch64__
147 #define _UC_MACHINE_PAD 8 /* Padding appended to ucontext_t */
148 #define _UC_MACHINE_SP(uc) (((uc)->uc_mcontext.__gregs[_REG_O6]) + 0x7ff)
149 #define _UC_MACHINE_FP(uc) (((__greg_t *)_UC_MACHINE_SP(uc))[15])
150 #else
151 #define _UC_MACHINE_PAD 43 /* Padding appended to ucontext_t */
152 #define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_O6])
153 #define _UC_MACHINE_FP(uc) (((__greg_t *)_UC_MACHINE_SP(uc))[15])
154 #endif
155 #define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_PC])
156 #define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_O0])
157
158 #define _UC_MACHINE_SET_PC(uc, pc) \
159 do { \
160 (uc)->uc_mcontext.__gregs[_REG_PC] = (pc); \
161 (uc)->uc_mcontext.__gregs[_REG_nPC] = (pc) + 4; \
162 } while (/*CONSTCOND*/0)
163
164 #if defined(_RTLD_SOURCE) || defined(_LIBC_SOURCE) || \
165 defined(__LIBPTHREAD_SOURCE__)
166 #include <sys/tls.h>
167
168 __BEGIN_DECLS
169 static __inline void *
__lwp_getprivate_fast(void)170 __lwp_getprivate_fast(void)
171 {
172 register void *__tmp;
173
174 __asm volatile("mov %%g7, %0" : "=r" (__tmp));
175
176 return __tmp;
177 }
178 __END_DECLS
179
180 #endif
181
182 #endif /* !_SPARC_MCONTEXT_H_ */
183