1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include <drm/drm_device.h>
7 #include <linux/sysfs.h>
8 #include <linux/printk.h>
9
10 #include "i915_drv.h"
11 #include "i915_reg.h"
12 #include "i915_sysfs.h"
13 #include "intel_gt.h"
14 #include "intel_gt_print.h"
15 #include "intel_gt_regs.h"
16 #include "intel_gt_sysfs.h"
17 #include "intel_gt_sysfs_pm.h"
18 #include "intel_pcode.h"
19 #include "intel_rc6.h"
20 #include "intel_rps.h"
21
22 #ifdef notyet
23
24 enum intel_gt_sysfs_op {
25 INTEL_GT_SYSFS_MIN = 0,
26 INTEL_GT_SYSFS_MAX,
27 };
28
29 static int
sysfs_gt_attribute_w_func(struct kobject * kobj,struct attribute * attr,int (func)(struct intel_gt * gt,u32 val),u32 val)30 sysfs_gt_attribute_w_func(struct kobject *kobj, struct attribute *attr,
31 int (func)(struct intel_gt *gt, u32 val), u32 val)
32 {
33 struct intel_gt *gt;
34 int ret;
35
36 if (!is_object_gt(kobj)) {
37 int i;
38 struct device *dev = kobj_to_dev(kobj);
39 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
40
41 for_each_gt(gt, i915, i) {
42 ret = func(gt, val);
43 if (ret)
44 break;
45 }
46 } else {
47 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
48 ret = func(gt, val);
49 }
50
51 return ret;
52 }
53
54 static u32
sysfs_gt_attribute_r_func(struct kobject * kobj,struct attribute * attr,u32 (func)(struct intel_gt * gt),enum intel_gt_sysfs_op op)55 sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
56 u32 (func)(struct intel_gt *gt),
57 enum intel_gt_sysfs_op op)
58 {
59 struct intel_gt *gt;
60 u32 ret;
61
62 ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
63
64 if (!is_object_gt(kobj)) {
65 int i;
66 struct device *dev = kobj_to_dev(kobj);
67 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
68
69 for_each_gt(gt, i915, i) {
70 u32 val = func(gt);
71
72 switch (op) {
73 case INTEL_GT_SYSFS_MIN:
74 if (val < ret)
75 ret = val;
76 break;
77
78 case INTEL_GT_SYSFS_MAX:
79 if (val > ret)
80 ret = val;
81 break;
82 }
83 }
84 } else {
85 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
86 ret = func(gt);
87 }
88
89 return ret;
90 }
91
92 /* RC6 interfaces will show the minimum RC6 residency value */
93 #define sysfs_gt_attribute_r_min_func(d, a, f) \
94 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
95
96 /* Frequency interfaces will show the maximum frequency value */
97 #define sysfs_gt_attribute_r_max_func(d, a, f) \
98 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
99
100 #define INTEL_GT_SYSFS_SHOW(_name, _attr_type) \
101 static ssize_t _name##_show_common(struct kobject *kobj, \
102 struct attribute *attr, char *buff) \
103 { \
104 u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
105 __##_name##_show); \
106 \
107 return sysfs_emit(buff, "%u\n", val); \
108 } \
109 static ssize_t _name##_show(struct kobject *kobj, \
110 struct kobj_attribute *attr, char *buff) \
111 { \
112 return _name ##_show_common(kobj, &attr->attr, buff); \
113 } \
114 static ssize_t _name##_dev_show(struct device *dev, \
115 struct device_attribute *attr, char *buff) \
116 { \
117 return _name##_show_common(&dev->kobj, &attr->attr, buff); \
118 }
119
120 #define INTEL_GT_SYSFS_STORE(_name, _func) \
121 static ssize_t _name##_store_common(struct kobject *kobj, \
122 struct attribute *attr, \
123 const char *buff, size_t count) \
124 { \
125 int ret; \
126 u32 val; \
127 \
128 ret = kstrtou32(buff, 0, &val); \
129 if (ret) \
130 return ret; \
131 \
132 ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
133 \
134 return ret ?: count; \
135 } \
136 static ssize_t _name##_store(struct kobject *kobj, \
137 struct kobj_attribute *attr, const char *buff, \
138 size_t count) \
139 { \
140 return _name##_store_common(kobj, &attr->attr, buff, count); \
141 } \
142 static ssize_t _name##_dev_store(struct device *dev, \
143 struct device_attribute *attr, \
144 const char *buff, size_t count) \
145 { \
146 return _name##_store_common(&dev->kobj, &attr->attr, buff, count); \
147 }
148
149 #define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max)
150 #define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min)
151
152 #define INTEL_GT_ATTR_RW(_name) \
153 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
154
155 #define INTEL_GT_ATTR_RO(_name) \
156 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
157
158 #define INTEL_GT_DUAL_ATTR_RW(_name) \
159 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
160 _name##_dev_show, \
161 _name##_dev_store); \
162 INTEL_GT_ATTR_RW(_name)
163
164 #define INTEL_GT_DUAL_ATTR_RO(_name) \
165 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
166 _name##_dev_show, \
167 NULL); \
168 INTEL_GT_ATTR_RO(_name)
169
get_residency(struct intel_gt * gt,enum intel_rc6_res_type id)170 static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
171 {
172 intel_wakeref_t wakeref;
173 u64 res = 0;
174
175 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
176 res = intel_rc6_residency_us(>->rc6, id);
177
178 return DIV_ROUND_CLOSEST_ULL(res, 1000);
179 }
180
get_rc6_mask(struct intel_gt * gt)181 static u8 get_rc6_mask(struct intel_gt *gt)
182 {
183 u8 mask = 0;
184
185 if (HAS_RC6(gt->i915))
186 mask |= BIT(0);
187 if (HAS_RC6p(gt->i915))
188 mask |= BIT(1);
189 if (HAS_RC6pp(gt->i915))
190 mask |= BIT(2);
191
192 return mask;
193 }
194
rc6_enable_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)195 static ssize_t rc6_enable_show(struct kobject *kobj,
196 struct kobj_attribute *attr,
197 char *buff)
198 {
199 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
200
201 return sysfs_emit(buff, "%x\n", get_rc6_mask(gt));
202 }
203
rc6_enable_dev_show(struct device * dev,struct device_attribute * attr,char * buff)204 static ssize_t rc6_enable_dev_show(struct device *dev,
205 struct device_attribute *attr,
206 char *buff)
207 {
208 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(&dev->kobj, attr->attr.name);
209
210 return sysfs_emit(buff, "%x\n", get_rc6_mask(gt));
211 }
212
__rc6_residency_ms_show(struct intel_gt * gt)213 static u32 __rc6_residency_ms_show(struct intel_gt *gt)
214 {
215 return get_residency(gt, INTEL_RC6_RES_RC6);
216 }
217
__rc6p_residency_ms_show(struct intel_gt * gt)218 static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
219 {
220 return get_residency(gt, INTEL_RC6_RES_RC6p);
221 }
222
__rc6pp_residency_ms_show(struct intel_gt * gt)223 static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
224 {
225 return get_residency(gt, INTEL_RC6_RES_RC6pp);
226 }
227
__media_rc6_residency_ms_show(struct intel_gt * gt)228 static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
229 {
230 return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
231 }
232
233 INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);
234 INTEL_GT_SYSFS_SHOW_MIN(rc6p_residency_ms);
235 INTEL_GT_SYSFS_SHOW_MIN(rc6pp_residency_ms);
236 INTEL_GT_SYSFS_SHOW_MIN(media_rc6_residency_ms);
237
238 INTEL_GT_DUAL_ATTR_RO(rc6_enable);
239 INTEL_GT_DUAL_ATTR_RO(rc6_residency_ms);
240 INTEL_GT_DUAL_ATTR_RO(rc6p_residency_ms);
241 INTEL_GT_DUAL_ATTR_RO(rc6pp_residency_ms);
242 INTEL_GT_DUAL_ATTR_RO(media_rc6_residency_ms);
243
244 static struct attribute *rc6_attrs[] = {
245 &attr_rc6_enable.attr,
246 &attr_rc6_residency_ms.attr,
247 NULL
248 };
249
250 static struct attribute *rc6p_attrs[] = {
251 &attr_rc6p_residency_ms.attr,
252 &attr_rc6pp_residency_ms.attr,
253 NULL
254 };
255
256 static struct attribute *media_rc6_attrs[] = {
257 &attr_media_rc6_residency_ms.attr,
258 NULL
259 };
260
261 static struct attribute *rc6_dev_attrs[] = {
262 &dev_attr_rc6_enable.attr,
263 &dev_attr_rc6_residency_ms.attr,
264 NULL
265 };
266
267 static struct attribute *rc6p_dev_attrs[] = {
268 &dev_attr_rc6p_residency_ms.attr,
269 &dev_attr_rc6pp_residency_ms.attr,
270 NULL
271 };
272
273 static struct attribute *media_rc6_dev_attrs[] = {
274 &dev_attr_media_rc6_residency_ms.attr,
275 NULL
276 };
277
278 static const struct attribute_group rc6_attr_group[] = {
279 { .attrs = rc6_attrs, },
280 { .name = power_group_name, .attrs = rc6_dev_attrs, },
281 };
282
283 static const struct attribute_group rc6p_attr_group[] = {
284 { .attrs = rc6p_attrs, },
285 { .name = power_group_name, .attrs = rc6p_dev_attrs, },
286 };
287
288 static const struct attribute_group media_rc6_attr_group[] = {
289 { .attrs = media_rc6_attrs, },
290 { .name = power_group_name, .attrs = media_rc6_dev_attrs, },
291 };
292
__intel_gt_sysfs_create_group(struct kobject * kobj,const struct attribute_group * grp)293 static int __intel_gt_sysfs_create_group(struct kobject *kobj,
294 const struct attribute_group *grp)
295 {
296 return is_object_gt(kobj) ?
297 sysfs_create_group(kobj, &grp[0]) :
298 sysfs_merge_group(kobj, &grp[1]);
299 }
300
intel_sysfs_rc6_init(struct intel_gt * gt,struct kobject * kobj)301 static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
302 {
303 int ret;
304
305 if (!IS_ENABLED(CONFIG_PM) || !HAS_RC6(gt->i915))
306 return;
307
308 ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
309 if (ret)
310 gt_warn(gt, "failed to create RC6 sysfs files (%pe)\n", ERR_PTR(ret));
311
312 /*
313 * cannot use the is_visible() attribute because
314 * the upper object inherits from the parent group.
315 */
316 if (HAS_RC6p(gt->i915)) {
317 ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
318 if (ret)
319 gt_warn(gt, "failed to create RC6p sysfs files (%pe)\n", ERR_PTR(ret));
320 }
321
322 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
323 ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
324 if (ret)
325 gt_warn(gt, "failed to create media RC6 sysfs files (%pe)\n", ERR_PTR(ret));
326 }
327 }
328
__act_freq_mhz_show(struct intel_gt * gt)329 static u32 __act_freq_mhz_show(struct intel_gt *gt)
330 {
331 return intel_rps_read_actual_frequency(>->rps);
332 }
333
__cur_freq_mhz_show(struct intel_gt * gt)334 static u32 __cur_freq_mhz_show(struct intel_gt *gt)
335 {
336 return intel_rps_get_requested_frequency(>->rps);
337 }
338
__boost_freq_mhz_show(struct intel_gt * gt)339 static u32 __boost_freq_mhz_show(struct intel_gt *gt)
340 {
341 return intel_rps_get_boost_frequency(>->rps);
342 }
343
__boost_freq_mhz_store(struct intel_gt * gt,u32 val)344 static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
345 {
346 return intel_rps_set_boost_frequency(>->rps, val);
347 }
348
__RP0_freq_mhz_show(struct intel_gt * gt)349 static u32 __RP0_freq_mhz_show(struct intel_gt *gt)
350 {
351 return intel_rps_get_rp0_frequency(>->rps);
352 }
353
__RPn_freq_mhz_show(struct intel_gt * gt)354 static u32 __RPn_freq_mhz_show(struct intel_gt *gt)
355 {
356 return intel_rps_get_rpn_frequency(>->rps);
357 }
358
__RP1_freq_mhz_show(struct intel_gt * gt)359 static u32 __RP1_freq_mhz_show(struct intel_gt *gt)
360 {
361 return intel_rps_get_rp1_frequency(>->rps);
362 }
363
__max_freq_mhz_show(struct intel_gt * gt)364 static u32 __max_freq_mhz_show(struct intel_gt *gt)
365 {
366 return intel_rps_get_max_frequency(>->rps);
367 }
368
__set_max_freq(struct intel_gt * gt,u32 val)369 static int __set_max_freq(struct intel_gt *gt, u32 val)
370 {
371 return intel_rps_set_max_frequency(>->rps, val);
372 }
373
__min_freq_mhz_show(struct intel_gt * gt)374 static u32 __min_freq_mhz_show(struct intel_gt *gt)
375 {
376 return intel_rps_get_min_frequency(>->rps);
377 }
378
__set_min_freq(struct intel_gt * gt,u32 val)379 static int __set_min_freq(struct intel_gt *gt, u32 val)
380 {
381 return intel_rps_set_min_frequency(>->rps, val);
382 }
383
__vlv_rpe_freq_mhz_show(struct intel_gt * gt)384 static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
385 {
386 struct intel_rps *rps = >->rps;
387
388 return intel_gpu_freq(rps, rps->efficient_freq);
389 }
390
391 INTEL_GT_SYSFS_SHOW_MAX(act_freq_mhz);
392 INTEL_GT_SYSFS_SHOW_MAX(boost_freq_mhz);
393 INTEL_GT_SYSFS_SHOW_MAX(cur_freq_mhz);
394 INTEL_GT_SYSFS_SHOW_MAX(RP0_freq_mhz);
395 INTEL_GT_SYSFS_SHOW_MAX(RP1_freq_mhz);
396 INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);
397 INTEL_GT_SYSFS_SHOW_MAX(max_freq_mhz);
398 INTEL_GT_SYSFS_SHOW_MIN(min_freq_mhz);
399 INTEL_GT_SYSFS_SHOW_MAX(vlv_rpe_freq_mhz);
400 INTEL_GT_SYSFS_STORE(boost_freq_mhz, __boost_freq_mhz_store);
401 INTEL_GT_SYSFS_STORE(max_freq_mhz, __set_max_freq);
402 INTEL_GT_SYSFS_STORE(min_freq_mhz, __set_min_freq);
403
404 #define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, _store_dev) \
405 static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, \
406 _show_dev, _store_dev); \
407 static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, _mode, \
408 _show, _store)
409
410 #define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
411 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
412 _name##_dev_show, NULL)
413 #define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
414 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
415 _name##_dev_show, _name##_dev_store)
416
417 /* The below macros generate static structures */
418 INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
419 INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
420 INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
421 INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
422 INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
423 INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
424 INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
425 INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
426 INTEL_GT_RPS_SYSFS_ATTR_RO(vlv_rpe_freq_mhz);
427
428 #define GEN6_ATTR(p, s) { \
429 &p##attr_##s##_act_freq_mhz.attr, \
430 &p##attr_##s##_cur_freq_mhz.attr, \
431 &p##attr_##s##_boost_freq_mhz.attr, \
432 &p##attr_##s##_max_freq_mhz.attr, \
433 &p##attr_##s##_min_freq_mhz.attr, \
434 &p##attr_##s##_RP0_freq_mhz.attr, \
435 &p##attr_##s##_RP1_freq_mhz.attr, \
436 &p##attr_##s##_RPn_freq_mhz.attr, \
437 NULL, \
438 }
439
440 #define GEN6_RPS_ATTR GEN6_ATTR(, rps)
441 #define GEN6_GT_ATTR GEN6_ATTR(dev_, gt)
442
443 static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
444 static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
445
punit_req_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)446 static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
447 struct kobj_attribute *attr,
448 char *buff)
449 {
450 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
451 u32 preq = intel_rps_read_punit_req_frequency(>->rps);
452
453 return sysfs_emit(buff, "%u\n", preq);
454 }
455
slpc_ignore_eff_freq_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)456 static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
457 struct kobj_attribute *attr,
458 char *buff)
459 {
460 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
461 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
462
463 return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
464 }
465
slpc_ignore_eff_freq_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buff,size_t count)466 static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
467 struct kobj_attribute *attr,
468 const char *buff, size_t count)
469 {
470 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
471 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
472 int err;
473 u32 val;
474
475 err = kstrtou32(buff, 0, &val);
476 if (err)
477 return err;
478
479 err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
480 return err ?: count;
481 }
482
483 struct intel_gt_bool_throttle_attr {
484 struct attribute attr;
485 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
486 char *buf);
487 i915_reg_t (*reg32)(struct intel_gt *gt);
488 u32 mask;
489 };
490
throttle_reason_bool_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)491 static ssize_t throttle_reason_bool_show(struct kobject *kobj,
492 struct kobj_attribute *attr,
493 char *buff)
494 {
495 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
496 struct intel_gt_bool_throttle_attr *t_attr =
497 (struct intel_gt_bool_throttle_attr *) attr;
498 bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask);
499
500 return sysfs_emit(buff, "%u\n", val);
501 }
502
503 #define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
504 struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
505 .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
506 .show = throttle_reason_bool_show, \
507 .reg32 = intel_gt_perf_limit_reasons_reg, \
508 .mask = mask__, \
509 }
510
511 INTEL_GT_ATTR_RO(punit_req_freq_mhz);
512 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
513 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
514 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
515 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
516 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
517 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
518 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
519 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
520 static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
521
522 static const struct attribute *throttle_reason_attrs[] = {
523 &attr_throttle_reason_status.attr,
524 &attr_throttle_reason_pl1.attr,
525 &attr_throttle_reason_pl2.attr,
526 &attr_throttle_reason_pl4.attr,
527 &attr_throttle_reason_thermal.attr,
528 &attr_throttle_reason_prochot.attr,
529 &attr_throttle_reason_ratl.attr,
530 &attr_throttle_reason_vr_thermalert.attr,
531 &attr_throttle_reason_vr_tdc.attr,
532 NULL
533 };
534
535 /*
536 * Scaling for multipliers (aka frequency factors).
537 * The format of the value in the register is u8.8.
538 *
539 * The presentation to userspace is inspired by the perf event framework.
540 * See:
541 * Documentation/ABI/testing/sysfs-bus-event_source-devices-events
542 * for description of:
543 * /sys/bus/event_source/devices/<pmu>/events/<event>.scale
544 *
545 * Summary: Expose two sysfs files for each multiplier.
546 *
547 * 1. File <attr> contains a raw hardware value.
548 * 2. File <attr>.scale contains the multiplicative scale factor to be
549 * used by userspace to compute the actual value.
550 *
551 * So userspace knows that to get the frequency_factor it multiplies the
552 * provided value by the specified scale factor and vice-versa.
553 *
554 * That way there is no precision loss in the kernel interface and API
555 * is future proof should one day the hardware register change to u16.u16,
556 * on some platform. (Or any other fixed point representation.)
557 *
558 * Example:
559 * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
560 * is comprised of:
561 * - an integer part of 2
562 * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
563 * File <attr>.scale contains a string representation of floating point
564 * value 0.00390625 (which is (1 / 256)).
565 * Userspace computes the actual value:
566 * 0x0280 * 0.00390625 -> 2.5
567 * or converts an actual value to the value to be written into <attr>:
568 * 2.5 / 0.00390625 -> 0x0280
569 */
570
571 #define U8_8_VAL_MASK 0xffff
572 #define U8_8_SCALE_TO_VALUE "0.00390625"
573
freq_factor_scale_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)574 static ssize_t freq_factor_scale_show(struct kobject *kobj,
575 struct kobj_attribute *attr,
576 char *buff)
577 {
578 return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
579 }
580
media_ratio_mode_to_factor(u32 mode)581 static u32 media_ratio_mode_to_factor(u32 mode)
582 {
583 /* 0 -> 0, 1 -> 256, 2 -> 128 */
584 return !mode ? mode : 256 / mode;
585 }
586
media_freq_factor_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)587 static ssize_t media_freq_factor_show(struct kobject *kobj,
588 struct kobj_attribute *attr,
589 char *buff)
590 {
591 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
592 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
593 intel_wakeref_t wakeref;
594 u32 mode;
595
596 /*
597 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
598 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
599 */
600 if (IS_XEHPSDV(gt->i915) &&
601 slpc->media_ratio_mode == SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL) {
602 /*
603 * For XEHPSDV dynamic mode GEN6_RPNSWREQ:13 does not contain
604 * the media_ratio_mode, just return the cached media ratio
605 */
606 mode = slpc->media_ratio_mode;
607 } else {
608 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
609 mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
610 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
611 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
612 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
613 }
614
615 return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
616 }
617
media_freq_factor_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buff,size_t count)618 static ssize_t media_freq_factor_store(struct kobject *kobj,
619 struct kobj_attribute *attr,
620 const char *buff, size_t count)
621 {
622 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
623 struct intel_guc_slpc *slpc = >->uc.guc.slpc;
624 u32 factor, mode;
625 int err;
626
627 err = kstrtou32(buff, 0, &factor);
628 if (err)
629 return err;
630
631 for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
632 mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
633 if (factor == media_ratio_mode_to_factor(mode))
634 break;
635
636 if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
637 return -EINVAL;
638
639 err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
640 if (!err) {
641 slpc->media_ratio_mode = mode;
642 DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
643 }
644 return err ?: count;
645 }
646
media_RP0_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)647 static ssize_t media_RP0_freq_mhz_show(struct kobject *kobj,
648 struct kobj_attribute *attr,
649 char *buff)
650 {
651 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
652 u32 val;
653 int err;
654
655 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
656 PCODE_MBOX_FC_SC_READ_FUSED_P0,
657 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
658
659 if (err)
660 return err;
661
662 /* Fused media RP0 read from pcode is in units of 50 MHz */
663 val *= GT_FREQUENCY_MULTIPLIER;
664
665 return sysfs_emit(buff, "%u\n", val);
666 }
667
media_RPn_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buff)668 static ssize_t media_RPn_freq_mhz_show(struct kobject *kobj,
669 struct kobj_attribute *attr,
670 char *buff)
671 {
672 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
673 u32 val;
674 int err;
675
676 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
677 PCODE_MBOX_FC_SC_READ_FUSED_PN,
678 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
679
680 if (err)
681 return err;
682
683 /* Fused media RPn read from pcode is in units of 50 MHz */
684 val *= GT_FREQUENCY_MULTIPLIER;
685
686 return sysfs_emit(buff, "%u\n", val);
687 }
688
689 INTEL_GT_ATTR_RW(media_freq_factor);
690 static struct kobj_attribute attr_media_freq_factor_scale =
691 __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
692 INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
693 INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
694
695 INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
696
697 static const struct attribute *media_perf_power_attrs[] = {
698 &attr_media_freq_factor.attr,
699 &attr_media_freq_factor_scale.attr,
700 &attr_media_RP0_freq_mhz.attr,
701 &attr_media_RPn_freq_mhz.attr,
702 NULL
703 };
704
705 static ssize_t
rps_up_threshold_pct_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)706 rps_up_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
707 char *buf)
708 {
709 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
710 struct intel_rps *rps = >->rps;
711
712 return sysfs_emit(buf, "%u\n", intel_rps_get_up_threshold(rps));
713 }
714
715 static ssize_t
rps_up_threshold_pct_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)716 rps_up_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
717 const char *buf, size_t count)
718 {
719 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
720 struct intel_rps *rps = >->rps;
721 int ret;
722 u8 val;
723
724 ret = kstrtou8(buf, 10, &val);
725 if (ret)
726 return ret;
727
728 ret = intel_rps_set_up_threshold(rps, val);
729
730 return ret == 0 ? count : ret;
731 }
732
733 static struct kobj_attribute rps_up_threshold_pct =
734 __ATTR(rps_up_threshold_pct,
735 0664,
736 rps_up_threshold_pct_show,
737 rps_up_threshold_pct_store);
738
739 static ssize_t
rps_down_threshold_pct_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)740 rps_down_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
741 char *buf)
742 {
743 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
744 struct intel_rps *rps = >->rps;
745
746 return sysfs_emit(buf, "%u\n", intel_rps_get_down_threshold(rps));
747 }
748
749 static ssize_t
rps_down_threshold_pct_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)750 rps_down_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
751 const char *buf, size_t count)
752 {
753 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
754 struct intel_rps *rps = >->rps;
755 int ret;
756 u8 val;
757
758 ret = kstrtou8(buf, 10, &val);
759 if (ret)
760 return ret;
761
762 ret = intel_rps_set_down_threshold(rps, val);
763
764 return ret == 0 ? count : ret;
765 }
766
767 static struct kobj_attribute rps_down_threshold_pct =
768 __ATTR(rps_down_threshold_pct,
769 0664,
770 rps_down_threshold_pct_show,
771 rps_down_threshold_pct_store);
772
773 static const struct attribute * const gen6_gt_rps_attrs[] = {
774 &rps_up_threshold_pct.attr,
775 &rps_down_threshold_pct.attr,
776 NULL
777 };
778
779 static ssize_t
default_min_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)780 default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
781 {
782 struct intel_gt *gt = kobj_to_gt(kobj->parent);
783
784 return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
785 }
786
787 static struct kobj_attribute default_min_freq_mhz =
788 __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
789
790 static ssize_t
default_max_freq_mhz_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)791 default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
792 {
793 struct intel_gt *gt = kobj_to_gt(kobj->parent);
794
795 return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
796 }
797
798 static struct kobj_attribute default_max_freq_mhz =
799 __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
800
801 static ssize_t
default_rps_up_threshold_pct_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)802 default_rps_up_threshold_pct_show(struct kobject *kobj,
803 struct kobj_attribute *attr,
804 char *buf)
805 {
806 struct intel_gt *gt = kobj_to_gt(kobj->parent);
807
808 return sysfs_emit(buf, "%u\n", gt->defaults.rps_up_threshold);
809 }
810
811 static struct kobj_attribute default_rps_up_threshold_pct =
812 __ATTR(rps_up_threshold_pct, 0444, default_rps_up_threshold_pct_show, NULL);
813
814 static ssize_t
default_rps_down_threshold_pct_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)815 default_rps_down_threshold_pct_show(struct kobject *kobj,
816 struct kobj_attribute *attr,
817 char *buf)
818 {
819 struct intel_gt *gt = kobj_to_gt(kobj->parent);
820
821 return sysfs_emit(buf, "%u\n", gt->defaults.rps_down_threshold);
822 }
823
824 static struct kobj_attribute default_rps_down_threshold_pct =
825 __ATTR(rps_down_threshold_pct, 0444, default_rps_down_threshold_pct_show, NULL);
826
827 static const struct attribute * const rps_defaults_attrs[] = {
828 &default_min_freq_mhz.attr,
829 &default_max_freq_mhz.attr,
830 &default_rps_up_threshold_pct.attr,
831 &default_rps_down_threshold_pct.attr,
832 NULL
833 };
834
intel_sysfs_rps_init(struct intel_gt * gt,struct kobject * kobj)835 static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
836 {
837 const struct attribute * const *attrs;
838 struct attribute *vlv_attr;
839 int ret;
840
841 if (GRAPHICS_VER(gt->i915) < 6)
842 return 0;
843
844 if (is_object_gt(kobj)) {
845 attrs = gen6_rps_attrs;
846 vlv_attr = &attr_rps_vlv_rpe_freq_mhz.attr;
847 } else {
848 attrs = gen6_gt_attrs;
849 vlv_attr = &dev_attr_gt_vlv_rpe_freq_mhz.attr;
850 }
851
852 ret = sysfs_create_files(kobj, attrs);
853 if (ret)
854 return ret;
855
856 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
857 ret = sysfs_create_file(kobj, vlv_attr);
858
859 if (is_object_gt(kobj) && !intel_uc_uses_guc_slpc(>->uc)) {
860 ret = sysfs_create_files(kobj, gen6_gt_rps_attrs);
861 if (ret)
862 return ret;
863 }
864
865 return ret;
866 }
867
868 #endif /* notyet */
869
intel_gt_sysfs_pm_init(struct intel_gt * gt,struct kobject * kobj)870 void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
871 {
872 STUB();
873 #ifdef notyet
874 int ret;
875
876 intel_sysfs_rc6_init(gt, kobj);
877
878 ret = intel_sysfs_rps_init(gt, kobj);
879 if (ret)
880 gt_warn(gt, "failed to create RPS sysfs files (%pe)", ERR_PTR(ret));
881
882 /* end of the legacy interfaces */
883 if (!is_object_gt(kobj))
884 return;
885
886 ret = sysfs_create_file(kobj, &attr_punit_req_freq_mhz.attr);
887 if (ret)
888 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
889
890 if (intel_uc_uses_guc_slpc(>->uc)) {
891 ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
892 if (ret)
893 gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
894 }
895
896 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
897 ret = sysfs_create_files(kobj, throttle_reason_attrs);
898 if (ret)
899 gt_warn(gt, "failed to create throttle sysfs files (%pe)", ERR_PTR(ret));
900 }
901
902 if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(>->uc)) {
903 ret = sysfs_create_files(kobj, media_perf_power_attrs);
904 if (ret)
905 gt_warn(gt, "failed to create media_perf_power_attrs sysfs (%pe)\n",
906 ERR_PTR(ret));
907 }
908
909 ret = sysfs_create_files(gt->sysfs_defaults, rps_defaults_attrs);
910 if (ret)
911 gt_warn(gt, "failed to add rps defaults (%pe)\n", ERR_PTR(ret));
912 #endif
913 }
914